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Since all clocks in the driver are now registered via devm_ variants, the remove callback 'ipq_cmn_pll_clk_remove()' and the manual 'unregister_fixed_clk' error-path loop are no longer needed and are removed. Reviewed-by: Konrad Dybcio Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 39 +++++++++------------------------------ 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index dafe8c1738df..4fdf78f6829e 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -390,13 +390,14 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 /* Register the fixed rate output clocks. */ for (i =3D 0; i < num_clks; i++) { - hw =3D clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, - cmn_pll_hw, 0, - fixed_clk[i].rate); - if (IS_ERR(hw)) { - ret =3D PTR_ERR(hw); - goto unregister_fixed_clk; - } + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + + hw =3D devm_clk_hw_register_fixed_rate_parent_data(dev, + fixed_clk[i].name, + &pdata, 0, + fixed_clk[i].rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); =20 hw_data->hws[fixed_clk[i].id] =3D hw; } @@ -410,17 +411,11 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); 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The IPQ5210 CMN PLL supplies configurable clocks to the NSS (network subsystem), PPE (packet process engine), and PON (passive optical network) hardware blocks. It also supplies a raw EPHY output clock for the integrated Ethernet PHY and several gated fixed-rate outputs to Ethernet PHY and switch devices. Acked-by: Rob Herring (Arm) Signed-off-by: Luo Jie --- .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h | 30 ++++++++++++++++++= ++++ 2 files changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.y= aml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index a4f9af8fa187..91e17f126a9b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -25,6 +25,7 @@ properties: compatible: enum: - qcom,ipq5018-cmn-pll + - qcom,ipq5210-cmn-pll - qcom,ipq5332-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq6018-cmn-pll diff --git a/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h b/include/dt-= bindings/clock/qcom,ipq5210-cmn-pll.h new file mode 100644 index 000000000000..9201d1e1062c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H + +/* Parent clock */ +#define IPQ5210_CMN_PLL_CLK 0 + +/* Fixed-rate clocks */ +#define IPQ5210_XO_24MHZ_CLK 1 +#define IPQ5210_SLEEP_32KHZ_CLK 2 + +/* Configurable divider clocks */ +#define IPQ5210_NSS_CLK 3 +#define IPQ5210_PPE_CLK 4 +#define IPQ5210_PON_CLK 5 +#define IPQ5210_EPHY_RAW_CLK 6 + +/* Gate clocks */ +#define IPQ5210_PCS_31P25MHZ_CLK 7 +#define IPQ5210_ETH0_50MHZ_CLK 8 +#define IPQ5210_ETH1_50MHZ_CLK 9 +#define IPQ5210_ETH2_50MHZ_CLK 10 +#define IPQ5210_EPHY_50MHZ_CLK 11 +#define IPQ5210_ETH_25MHZ_CLK 12 + +#endif --=20 2.43.0 From nobody Fri Aug 14 15:51:39 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D31F645517F for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8517d26726bsm405934b3a.54.2026.08.14.05.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 05:48:18 -0700 (PDT) From: Luo Jie Date: Fri, 14 Aug 2026 05:48:13 -0700 Subject: [PATCH v3 03/12] clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260814-qcom_ipq5210_cmnpll-v3-3-21c3db378611@oss.qualcomm.com> References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> In-Reply-To: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786711693; l=3107; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=NtUxYOq5wA+7fchoBStjIVzIpRQFswrF2uRB4I6rFcg=; b=Fy18cu2veV33m5V/4BkPSyg8ppzCODvyKpLif05iN9IIs23ueifEoSD0yq/fEFhOYQ3PNZ217 bPSGRhSyDfQDwJ+VZKsA22+6fayfb4dK0hU3mpAH/cp4NgIzd1rNdXV X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Info: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfXwsym8WIhu0oQ OCkjA6d7GyLwfJ/usz7fnPI2+VtIC/0s4zlsiXa3O5lOIGx6E3cjNtDownAf+zXhw34wFM0fzzq g0SzZ7DtC5SVntY7bcC/cXB7bVnwbmY= X-Authority-Analysis: v=2.4 cv=eqzvCIpX c=1 sm=1 tr=0 ts=6a7f0e94 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=vx7U0BMSOfWHh9VQJyQA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: 9A2ySU7Je0qGOYGIbtGQzMVKwp3B_gQi X-Proofpoint-ORIG-GUID: 9A2ySU7Je0qGOYGIbtGQzMVKwp3B_gQi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfX8OhGGV698Jf4 WD58MuUxHpWCURj4BP3psRhd0ZPIY46RrQ1OsXEII3VdBoKAKo83bYNBgzu3FRgCii1vHDlm47F 3nr3brRdc8eFvNmjGk1Rwg7bnxdQoWb9mGOEtrTWHZaX8hszE7Iey6snxYH6Opn7P6Dp/CuWo0g hI50l/MIUc37vlWb6I3WHrhHj4uffVRRbtSaMiZY/W4+FwnGb9aY6S7c+XrPydlWioGsBVKPKn+ 90EXw+P+EDCostYblCzn3huvFTNl0s4GFemin/brrj1nyxdeVIQhp1eS7Yy4MZw5zyuqsrIyekn 5QmBuxKHWAqAhii52aBQhs5pFfNuowH8gVkSJG1UK8PjZ2tuqp0CTzaEZwok7VzknZYFRU+Uesh 6lAobz9HCdhUzGSMLfLoHib655ltMr/+oGysXokiBW+5+kGV42ZbvheJqDSi1UDzW08Bvu9Ull4 y4kRDFR6x7tX7DkOHyQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-14_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608140097 Add a flags field to struct clk_regmap_div and OR it into the CLK_DIVIDER_ROUND_CLOSEST flag passed to divider_determine_rate(), divider_ro_determine_rate(), divider_get_val(), and divider_recalc_rate(), so that qcom drivers can opt into CLK_DIVIDER_* behavior variants such as CLK_DIVIDER_ONE_BASED. This is additive and backward compatible: existing clk_regmap_div users don't initialize .flags, so it defaults to 0, and CLK_DIVIDER_ROUND_CLOSEST | 0 is identical to current behavior. Signed-off-by: Luo Jie --- drivers/clk/qcom/clk-regmap-divider.c | 16 ++++++++++------ drivers/clk/qcom/clk-regmap-divider.h | 1 + 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-r= egmap-divider.c index 672e82caf205..6e12aebf14b6 100644 --- a/drivers/clk/qcom/clk-regmap-divider.c +++ b/drivers/clk/qcom/clk-regmap-divider.c @@ -27,7 +27,8 @@ static int div_ro_determine_rate(struct clk_hw *hw, val &=3D BIT(divider->width) - 1; =20 return divider_ro_determine_rate(hw, req, NULL, divider->width, - CLK_DIVIDER_ROUND_CLOSEST, val); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags, + val); } =20 static int div_determine_rate(struct clk_hw *hw, struct clk_rate_request *= req) @@ -35,7 +36,7 @@ static int div_determine_rate(struct clk_hw *hw, struct c= lk_rate_request *req) struct clk_regmap_div *divider =3D to_clk_regmap_div(hw); =20 return divider_determine_rate(hw, req, NULL, divider->width, - CLK_DIVIDER_ROUND_CLOSEST); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags); } =20 static int div_set_rate(struct clk_hw *hw, unsigned long rate, @@ -43,14 +44,16 @@ static int div_set_rate(struct clk_hw *hw, unsigned lon= g rate, { struct clk_regmap_div *divider =3D to_clk_regmap_div(hw); struct clk_regmap *clkr =3D ÷r->clkr; - u32 div; + int div; =20 div =3D divider_get_val(rate, parent_rate, NULL, divider->width, - CLK_DIVIDER_ROUND_CLOSEST); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags); + if (div < 0) + return div; =20 return regmap_update_bits(clkr->regmap, divider->reg, (BIT(divider->width) - 1) << divider->shift, - div << divider->shift); + (u32)div << divider->shift); } =20 static unsigned long div_recalc_rate(struct clk_hw *hw, @@ -65,7 +68,8 @@ static unsigned long div_recalc_rate(struct clk_hw *hw, div &=3D BIT(divider->width) - 1; =20 return divider_recalc_rate(hw, parent_rate, div, NULL, - CLK_DIVIDER_ROUND_CLOSEST, divider->width); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags, + divider->width); } =20 const struct clk_ops clk_regmap_div_ops =3D { diff --git a/drivers/clk/qcom/clk-regmap-divider.h b/drivers/clk/qcom/clk-r= egmap-divider.h index e75a65c3839c..4fde766b2633 100644 --- a/drivers/clk/qcom/clk-regmap-divider.h +++ b/drivers/clk/qcom/clk-regmap-divider.h @@ -13,6 +13,7 @@ struct clk_regmap_div { u32 reg; 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This /2 stage is present in the CMN PLL block on every SoC supported by this driver, not just IPQ5210. Register this /2 stage once as a fixed-factor clock, "cmn_pll_div2", and store it on struct clk_cmn_pll so the output clock types added by later patches can parent on it. The two plain fixed-rate outputs, xo-24mhz and sleep-32khz, are the exception on IPQ5210 SoC: they stay parented directly on the main PLL clock. On SoCs other than IPQ5210, every output clock is a plain fixed-rate clock (CMN_PLL_CLK_FIXED_RATE) whose rate is a hardcoded absolute value rather than one computed from the parent rate, so this /2 clock is registered there but currently has no consumers; IPQ5210 is simply the first SoC in this driver whose output clocks are modeled as depending on parent_rate, which is what makes the /2 stage significant. This patch only registers the clock; later patches wire it in as the effective parent for the output clock types that sit downstream of it. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 4fdf78f6829e..bcb51a5f559a 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -96,10 +96,17 @@ struct cmn_pll_fixed_output_clk { * struct clk_cmn_pll - CMN PLL hardware specific data * @regmap: hardware regmap. * @hw: handle between common and hardware-specific interfaces + * @div2_hw: fixed /2 clock derived from the CMN PLL output; present on + * every supported SoC, but only IPQ5210 currently parents + * any output clock on it (every output clock except the + * plain fixed-rate xo/sleep clocks, which stay on the main + * PLL); other SoCs' output clocks use hardcoded rates that + * never depend on a parent */ struct clk_cmn_pll { struct regmap *regmap; struct clk_hw hw; + struct clk_hw *div2_hw; }; =20 #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ @@ -362,6 +369,7 @@ static int ipq_cmn_pll_register_clks(struct platform_de= vice *pdev) const struct cmn_pll_fixed_output_clk *p, *fixed_clk; struct clk_hw_onecell_data *hw_data; struct device *dev =3D &pdev->dev; + struct clk_cmn_pll *cmn_pll; struct clk_hw *cmn_pll_hw; unsigned int num_clks; struct clk_hw *hw; @@ -388,6 +396,20 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) if (IS_ERR(cmn_pll_hw)) return PTR_ERR(cmn_pll_hw); =20 + cmn_pll =3D to_clk_cmn_pll(cmn_pll_hw); + + /* + * The CMN PLL output feeds a shared, physical /2 stage ahead of + * any further per-clock processing (a gated fixed rate, a + * configurable divider, or a rate-select bit). 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Register the NSS clock through a new ipq_cmn_pll_regmap_div_register() helper, built as a plain struct clk_regmap_div instance instead of hand-rolling recalc_rate/set_rate. The helper takes the register field mask and clock name as parameters so that the upcoming PPE clock, which shares the same register with a different field, can reuse it. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 84 ++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 79 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index bcb51a5f559a..59978789f493 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -60,12 +60,18 @@ #include #include =20 +#include "clk-regmap.h" +#include "clk-regmap-divider.h" + #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 #define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) =20 #define CMN_PLL_LOCKED 0x64 #define CMN_PLL_CLKS_LOCKED BIT(8) =20 +#define CMN_PLL_NSS_PPE_FREQ_CTRL 0x98 +#define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) + #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) =20 @@ -80,15 +86,27 @@ #define CMN_PLL_DIVIDER_CTRL 0x794 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) =20 +/** + * enum cmn_pll_clk_type - CMN PLL output clock registration type + * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock + * @CMN_PLL_CLK_NSS: NSS clock with configurable divider + */ +enum cmn_pll_clk_type { + CMN_PLL_CLK_FIXED_RATE, + CMN_PLL_CLK_NSS, +}; + /** * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information * @id: Clock specifier to be supplied * @name: Clock name to be registered + * @type: Clock registration type * @rate: Clock rate */ struct cmn_pll_fixed_output_clk { unsigned int id; const char *name; + enum cmn_pll_clk_type type; unsigned long rate; }; =20 @@ -112,6 +130,7 @@ struct clk_cmn_pll { #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ .id =3D _id, \ .name =3D _name, \ + .type =3D CMN_PLL_CLK_FIXED_RATE, \ .rate =3D _rate, \ } =20 @@ -364,6 +383,47 @@ static struct clk_hw *ipq_cmn_pll_clk_hw_register(stru= ct platform_device *pdev) return &cmn_pll->hw; } =20 +static struct clk_hw *ipq_cmn_pll_regmap_div_register(struct platform_devi= ce *pdev, + struct regmap *regmap, + struct clk_hw *parent_hw, + const char *name, + u32 field_mask) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct device *dev =3D &pdev->dev; + struct clk_regmap_div *div_clk; + int ret; + + div_clk =3D devm_kzalloc(dev, sizeof(*div_clk), GFP_KERNEL); + if (!div_clk) + return ERR_PTR(-ENOMEM); + + div_clk->reg =3D CMN_PLL_NSS_PPE_FREQ_CTRL; + div_clk->shift =3D __ffs(field_mask); + div_clk->width =3D hweight32(field_mask); + /* + * CMN_PLL_NSS_CLK_SEL / CMN_PLL_PPE_CLK_SEL reset to a valid, non-zero + * divider in hardware. CLK_DIVIDER_ALLOW_ZERO is deliberately not set: + * a divider field read back as 0 is genuinely invalid and should trip + * the core clk-divider's zero-divisor WARN rather than be silently + * tolerated. + */ + div_clk->flags =3D CLK_DIVIDER_ONE_BASED; + div_clk->clkr.regmap =3D regmap; + div_clk->clkr.hw.init =3D &(struct clk_init_data){ + .name =3D name, + .parent_data =3D &pdata, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ops, + }; + + ret =3D devm_clk_register_regmap(dev, &div_clk->clkr); + if (ret) + return ERR_PTR(ret); + + return &div_clk->clkr.hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -412,12 +472,26 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 /* Register the fixed rate output clocks. */ for (i =3D 0; i < num_clks; i++) { - struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + hw =3D ERR_PTR(-EINVAL); + + switch (fixed_clk[i].type) { + case CMN_PLL_CLK_FIXED_RATE: { + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8517d26726bsm405934b3a.54.2026.08.14.05.48.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 05:48:22 -0700 (PDT) From: Luo Jie Date: Fri, 14 Aug 2026 05:48:16 -0700 Subject: [PATCH v3 06/12] clk: qcom: ipq-cmn-pll: Add PPE clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260814-qcom_ipq5210_cmnpll-v3-6-21c3db378611@oss.qualcomm.com> References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> In-Reply-To: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786711693; l=1832; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=lr6+NNmr4NsXc4/LaBfiY5NRMqq+fb2nCdq1JFVlFhw=; b=keqbc3eq5HyDZ3AiMpGWUIP0BGqRZMGcXsQGivYTRNfEPjqj1Sc4gmlYZWKoaFi+F/Qi0PQvV m9388r/9QhMBlmJoHrSCxEPMA190eWOFm1zPBcG39HEZkowRBk2vCx5 X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfXxsvNna+/bxnz vwnk9JPhfwvZnfsXjnfNbOKVSrehgC/TRAVYsqsSF7Yq+R/IvP6IgcWp9R91GhDysNLTAMSBFPs QIOxLxhGE12onEhFtNxf0tZgS0boa2wldBFt0b/6eluIT7fB2BYU8Jm3WeCo4ewSVATrkJrfj/v xzyb6+NosgamRBz66jkAHpBh6B0NK1wwfRS5ES/4wZMO+WrkajDQu92Hbui3knxTWnqbbbbvSjn w/zuMYiyPhIw7BR/8Bw2O6SoZT5t91n64Py9R8JJsgLclLBlOsLOn6XLlMz4tBUdYKmUt8hfGW8 hDo+sUVVX1TlkzaWYPXv6m44qWhzwJUD2CCZvAnpy5II3BIcpMXn5i4Ad1PwKO8SDgpGNsdSeaN hMQ+T5RjChGQsZRKTBPxmXSh8p5EPLxMBUbOc8SKXj6daS/qFZVeZlz3e/FaayDkCPX/JbKhbjG hDLNqlxvYeV088R/L1Q== X-Authority-Analysis: v=2.4 cv=AaSB2XXG c=1 sm=1 tr=0 ts=6a7f0e98 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=mAYwyletAeVdbrWGRpcA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: wclnTkZngOOvueBA2hoAW-O4-tdxY7lp X-Proofpoint-GUID: wclnTkZngOOvueBA2hoAW-O4-tdxY7lp X-Proofpoint-Spam-Info: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfX1QUO33bSnk4N Gb9xpnCT4Pm5JzfbLuU9pTQ3+ZEg2msnZux2AYlBYF18yXkQL0PP6AlalrnOGErnQVOvE4x+Sax +lGDnLWaexXLzmVYo57zWLx/XO/dbj4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-14_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608140097 The PPE (packet process engine) clock is derived from the CMN PLL output divided by 2 and then further divided by a configurable 6-bit divider. It shares the CMN_PLL_NSS_PPE_FREQ_CTRL register with the NSS clock but uses a different field (bits [5:0]). Register the PPE clock through the ipq_cmn_pll_regmap_div_register() helper introduced for the NSS clock, passing the PPE-specific field mask and reusing the same cmn_pll_div2 parent selection as NSS. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 59978789f493..a5c2224ff22e 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -71,6 +71,7 @@ =20 #define CMN_PLL_NSS_PPE_FREQ_CTRL 0x98 #define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) +#define CMN_PLL_PPE_CLK_SEL GENMASK(5, 0) =20 #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) @@ -90,10 +91,12 @@ * enum cmn_pll_clk_type - CMN PLL output clock registration type * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock * @CMN_PLL_CLK_NSS: NSS clock with configurable divider + * @CMN_PLL_CLK_PPE: PPE clock with configurable divider */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, CMN_PLL_CLK_NSS, + CMN_PLL_CLK_PPE, }; =20 /** @@ -490,6 +493,12 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) fixed_clk[i].name, CMN_PLL_NSS_CLK_SEL); break; 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The clock supports two modes: - UNIPHY mode (CMN_PLL_PON_MODE_SEL =3D 0): fixed 31.25 MHz output - PON mode (CMN_PLL_PON_MODE_SEL =3D 1): parent_rate / divider The clock output can be independently enabled and disabled via the CMN_PLL_PON_EN bit. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 182 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 182 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index a5c2224ff22e..8987e0ff7dea 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -73,6 +73,11 @@ #define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) #define CMN_PLL_PPE_CLK_SEL GENMASK(5, 0) =20 +#define CMN_PLL_PON_CONFIG 0x42c +#define CMN_PLL_PON_MODE_SEL BIT(9) +#define CMN_PLL_PON_EN BIT(8) +#define CMN_PLL_PON_DIV_CTRL GENMASK(7, 0) + #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) =20 @@ -92,11 +97,13 @@ * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock * @CMN_PLL_CLK_NSS: NSS clock with configurable divider * @CMN_PLL_CLK_PPE: PPE clock with configurable divider + * @CMN_PLL_CLK_PON: PON reference clock */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, CMN_PLL_CLK_NSS, CMN_PLL_CLK_PPE, + CMN_PLL_CLK_PON, }; =20 /** @@ -427,6 +434,175 @@ static struct clk_hw *ipq_cmn_pll_regmap_div_register= (struct platform_device *pd return &div_clk->clkr.hw; } =20 +/* + * PON (Passive Optical Network) reference clock operations. + * The PON refclk's parent is cmn_pll_div2 (CMN PLL rate / 2); it is + * then divided by a configurable 8-bit divider (1-255). + */ +static int clk_pon_clk_enable(struct clk_hw *hw) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + + return regmap_set_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_EN); +} + +static void clk_pon_clk_disable(struct clk_hw *hw) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + + regmap_clear_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_EN); +} + +static int clk_pon_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + + return regmap_test_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_EN); +} + +static unsigned long clk_pon_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + u32 val, div; + int ret; + + ret =3D regmap_read(pon_clk->regmap, CMN_PLL_PON_CONFIG, &val); + if (ret) + return 0; + + /* Check if in UNIPHY mode (bit 9 =3D 0) - fixed 31.25 MHz */ + if (!(val & CMN_PLL_PON_MODE_SEL)) + return 31250000UL; + + /* PON mode: calculate from divider */ + div =3D FIELD_GET(CMN_PLL_PON_DIV_CTRL, val); + if (!div) + return 0; + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, div); +} + +static int clk_pon_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long div, pon_rate, uniphy_rate =3D 31250000UL; + bool uniphy_rate_valid, pon_rate_valid; + + if (!req->rate) + return -EINVAL; + + div =3D DIV64_U64_ROUND_CLOSEST((u64)req->best_parent_rate, req->rate); + + /* Clamp to valid range (1-255) */ + div =3D clamp_t(unsigned long, div, 1, 255); + + pon_rate =3D DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, div); + + uniphy_rate_valid =3D uniphy_rate >=3D req->min_rate && + uniphy_rate <=3D req->max_rate; + pon_rate_valid =3D pon_rate >=3D req->min_rate && + pon_rate <=3D req->max_rate; + + if (!uniphy_rate_valid && !pon_rate_valid) + return -EINVAL; + + /* Pick whichever mode gets closer to the requested rate */ + if (uniphy_rate_valid && pon_rate_valid) { + unsigned long diff_uniphy, diff_pon; + + diff_uniphy =3D abs_diff(req->rate, uniphy_rate); + diff_pon =3D abs_diff(req->rate, pon_rate); + req->rate =3D diff_uniphy < diff_pon ? uniphy_rate : pon_rate; + } else { + req->rate =3D uniphy_rate_valid ? uniphy_rate : pon_rate; + } + + return 0; +} + +static int clk_pon_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + unsigned long div; + + if (rate =3D=3D 0) + return -EINVAL; + + /* + * An exact request for 31.25 MHz is always satisfiable by UNIPHY + * mode, even though PON mode with a suitable divider can produce + * the same frequency for some parent rates. Preferring UNIPHY here + * is safe: this function is only ever called with a rate produced + * by clk_pon_clk_determine_rate() through the standard + * clk_set_rate() path, and either mode yields the identical output + * rate for this value. + */ + if (rate =3D=3D 31250000UL) + return regmap_clear_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_MODE_SEL); + + div =3D DIV64_U64_ROUND_CLOSEST((u64)parent_rate, rate); + if (div =3D=3D 0 || div > 255) + return -EINVAL; + + /* Switch to PON mode and program the divider in a single write */ + return regmap_update_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_MODE_SEL | CMN_PLL_PON_DIV_CTRL, + CMN_PLL_PON_MODE_SEL | + FIELD_PREP(CMN_PLL_PON_DIV_CTRL, div)); +} + +static const struct clk_ops clk_pon_clk_ops =3D { + .enable =3D clk_pon_clk_enable, + .disable =3D clk_pon_clk_disable, + .is_enabled =3D clk_pon_clk_is_enabled, + .recalc_rate =3D clk_pon_clk_recalc_rate, + .determine_rate =3D clk_pon_clk_determine_rate, + .set_rate =3D clk_pon_clk_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_pon_clk_register(struct platform_device = *pdev, + struct regmap *regmap, + struct clk_hw *parent_hw, + const char *name) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; + struct clk_cmn_pll *pon_clk; + int ret; + + pon_clk =3D devm_kzalloc(dev, sizeof(*pon_clk), GFP_KERNEL); + if (!pon_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_pon_clk_ops; + /* + * The PON reference clock may already be enabled by bootloader + * or consumed by hardware without an in-kernel client driver. + * Add CLK_IGNORE_UNUSED so the clock framework does not disable + * it when no consumer has claimed it. + */ + init.flags =3D CLK_IGNORE_UNUSED; + + pon_clk->hw.init =3D &init; + pon_clk->regmap =3D regmap; + + ret =3D devm_clk_hw_register(dev, &pon_clk->hw); + if (ret) + return ERR_PTR(ret); + + return &pon_clk->hw; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8517d26726bsm405934b3a.54.2026.08.14.05.48.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 05:48:24 -0700 (PDT) From: Luo Jie Date: Fri, 14 Aug 2026 05:48:18 -0700 Subject: [PATCH v3 08/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260814-qcom_ipq5210_cmnpll-v3-8-21c3db378611@oss.qualcomm.com> References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> In-Reply-To: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786711693; l=5324; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=LpInDpEUWJ19GKOJD8F8/rInbWot2Uwo7fiFfk68V/I=; b=51L3vF8gZU9WaaBShZE79eYH24pp+FlPFfVKqsb6F1z7ZDAlD4/vtI8srQ4AAiua/uW3ZEFtN HpwgxNPAjw0BNGxyzYFs+9z3K9DvqjCLQmD8udkq+onu9PQ9+FMl4/d X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfXwtMUNSy3PuPV xs2INap7cSDY2i36njKsIUQOYyQJNUGuitVKOBcY6krBIu3E0hI9qFAimU/BicI/d93Z3JMZyL+ Makn69Jvh0X9xsgnRDzJo7Dia1z36EnP3Wn7g1+n81kk9rzDfvG0ebdy1PB8CWAsWpXJOd14vVL Ci+MGoSs+mkmqCBkDoh9n8mNQARdqYHcMXYLyJYttRiuzMbHssnLE5CTCYMocjfDbRcmk2lpfw8 JoVGlr0ejOjZDSsLLANF9GtMrcEsMkjmPpYPh0O2eeBpCojKLX75HQducoHmKOi2484rv1RgvpU 0c5UpKYIaD+Qf4j9BBJ0BWV3Tx16ptLptFBPwcnCX27Ws459wTe2cd4+oWVwXhDWNtwSs21Xf3i S5+vDGsnuXh8LRbExS2anAGhKdLxgXb67JKOlMIXhBhXL2m5vnxfwHzYOolfEVlCgLt4wxd4dA+ EKcY6E02fhFB6m5CNvQ== X-Authority-Analysis: v=2.4 cv=DdMnbPtW c=1 sm=1 tr=0 ts=6a7f0e9a cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=nVjtjxfPRRi5vZi_wFUA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfX5z5YCPU5a5Ir JexRtDTKJrUmAI9jTibVhaYfCNrlpaMC8dtUMZNMOh3ledeHcRtPnBF9ja1FR0anjFbSM4+qhHZ S7o1BK0qkXvQtxKtW/53FQAHPfr+WTE= X-Proofpoint-GUID: 7qEAmzUdoYSKOQxW7NJDSzz5qNspLQNC X-Proofpoint-ORIG-GUID: 7qEAmzUdoYSKOQxW7NJDSzz5qNspLQNC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-14_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 phishscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608140097 The EPHY-RAW clock is an IPQ5210-specific output from the CMN PLL that provides the raw reference clock to the SoC-integrated Ethernet PHY (EPHY), which supports up to 2.5G link speed. The output frequency is selected via bit 10 (CMN_PLL_GEPHY_312P5M_125M_SEL) of the CMN_PLL_PON_CONFIG register: - 0: 125 MHz - for 1G/100M/10M link speed - 1: 312.5 MHz - for 2.5G link speed Parent it on cmn_pll_div2, like the rest of IPQ5210's output clocks, for clock-tree consistency. This is functionally identical: the output rate is purely register-bit-selected and never depends on the parent rate. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 114 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 114 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 8987e0ff7dea..eadbf6482aa4 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -77,6 +77,7 @@ #define CMN_PLL_PON_MODE_SEL BIT(9) #define CMN_PLL_PON_EN BIT(8) #define CMN_PLL_PON_DIV_CTRL GENMASK(7, 0) +#define CMN_PLL_GEPHY_312P5M_125M_SEL BIT(10) =20 #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) @@ -98,12 +99,14 @@ * @CMN_PLL_CLK_NSS: NSS clock with configurable divider * @CMN_PLL_CLK_PPE: PPE clock with configurable divider * @CMN_PLL_CLK_PON: PON reference clock + * @CMN_PLL_CLK_EPHY_RAW: EPHY-RAW clock */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, CMN_PLL_CLK_NSS, CMN_PLL_CLK_PPE, CMN_PLL_CLK_PON, + CMN_PLL_CLK_EPHY_RAW, }; =20 /** @@ -603,6 +606,111 @@ static struct clk_hw *ipq_cmn_pll_pon_clk_register(st= ruct platform_device *pdev, return &pon_clk->hw; } =20 +/* + * EPHY-RAW clock operations for IPQ5210. + * The output clock rate is selected via bit 10 of CMN_PLL_PON_CONFIG: + * 0: 125 MHz (for 1G link speed) + * 1: 312.5 MHz (for 2.5G link speed) + */ +static unsigned long clk_ephy_raw_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cmn_pll *ephy_raw_clk =3D to_clk_cmn_pll(hw); + u32 val; + int ret; + + ret =3D regmap_read(ephy_raw_clk->regmap, CMN_PLL_PON_CONFIG, &val); + if (WARN_ON_ONCE(ret)) + return 0; + + if (val & CMN_PLL_GEPHY_312P5M_125M_SEL) + return 312500000UL; + + return 125000000UL; +} + +static int clk_ephy_raw_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long rate_125m =3D 125000000UL, rate_312p5m =3D 312500000UL; + bool rate_125m_valid, rate_312p5m_valid; + + rate_125m_valid =3D rate_125m >=3D req->min_rate && + rate_125m <=3D req->max_rate; + rate_312p5m_valid =3D rate_312p5m >=3D req->min_rate && + rate_312p5m <=3D req->max_rate; + + if (!rate_125m_valid && !rate_312p5m_valid) + return -EINVAL; + + /* Pick whichever of the two supported rates is closer to the request */ + if (rate_125m_valid && rate_312p5m_valid) { + unsigned long diff_125m, diff_312p5m; + + diff_125m =3D abs_diff(req->rate, rate_125m); + diff_312p5m =3D abs_diff(req->rate, rate_312p5m); + req->rate =3D diff_125m < diff_312p5m ? rate_125m : rate_312p5m; + } else { + req->rate =3D rate_125m_valid ? rate_125m : rate_312p5m; + } + + return 0; +} + +static int clk_ephy_raw_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cmn_pll *ephy_raw_clk =3D to_clk_cmn_pll(hw); + + if (rate =3D=3D 125000000UL) + return regmap_clear_bits(ephy_raw_clk->regmap, + CMN_PLL_PON_CONFIG, + CMN_PLL_GEPHY_312P5M_125M_SEL); + + if (rate =3D=3D 312500000UL) + return regmap_set_bits(ephy_raw_clk->regmap, + CMN_PLL_PON_CONFIG, + CMN_PLL_GEPHY_312P5M_125M_SEL); + + return -EINVAL; +} + +static const struct clk_ops clk_ephy_raw_ops =3D { + .recalc_rate =3D clk_ephy_raw_recalc_rate, + .determine_rate =3D clk_ephy_raw_determine_rate, + .set_rate =3D clk_ephy_raw_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_ephy_raw_register(struct platform_device= *pdev, + struct regmap *regmap, + struct clk_hw *parent_hw, + const char *name) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct clk_cmn_pll *ephy_raw_clk; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; + int ret; + + ephy_raw_clk =3D devm_kzalloc(dev, sizeof(*ephy_raw_clk), GFP_KERNEL); + if (!ephy_raw_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_ephy_raw_ops; + + ephy_raw_clk->hw.init =3D &init; + ephy_raw_clk->regmap =3D regmap; + + ret =3D devm_clk_hw_register(dev, &ephy_raw_clk->hw); + if (ret) + return ERR_PTR(ret); + + return &ephy_raw_clk->hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -681,6 +789,12 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) cmn_pll->div2_hw, fixed_clk[i].name); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8517d26726bsm405934b3a.54.2026.08.14.05.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 05:48:26 -0700 (PDT) From: Luo Jie Date: Fri, 14 Aug 2026 05:48:19 -0700 Subject: [PATCH v3 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260814-qcom_ipq5210_cmnpll-v3-9-21c3db378611@oss.qualcomm.com> References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> In-Reply-To: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786711693; l=7664; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=pUoIbUSL+f38DPS2zkKlmAHQL0qngovWZZsCPqhx2Tg=; b=In+v8/zFLi2JIHz9JCYovxykSH0TiHi2kXfMkSCaWBK+L7eJvUYTIuQBxkS0ToazzM9u4EdMR XXrtLGKgIssB4qwd+uy9hKLcxigpAqgNIyJx9ZlZfH+3ZbZZZn8R8V9 X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfX/sRN52NTF/io btLVkWkb5H5hWY4S6hCdlTILa+4t4DKiLWycxcQx1+GxfjyONSv2EmWmnhhS8KmPVFcay3CzYyq 70qTtmKeYrV46CvKVrYH5CBA2SYUN5U7a2MHFnj9lRRkpBn7Ud5lY9k8l8FPKG/ttKysw+9zQAN v4irje+9QI1Fhr1glCSgCdtMIShcgNm7gncQ+HnFu39Gtnf4bR/4YjH+v/6z95Oig8DAwbj86NA yA6LhkQRZ4I0ijyNbIlQERAwRdEBXGkA6FCro4zyJEfCgaxpN9kqvm9zq+s9axiXEor6K/R1gu9 rs31nMsnHg5x92c13nWfoiUZcS4zuNhHsnFvaQKxv4o+8OMhzBDnUmSkCj7O5pJi8I088tyNY5r r4VscCpVZgxHp1fEEmGaUoc6gyLl6sB8XZchpqZn6KjIFVJRsuAUgik3Tksb/Qazt+J4yJVZ5ej jBUopdoe/cBf3Hs1fnQ== X-Authority-Analysis: v=2.4 cv=AaSB2XXG c=1 sm=1 tr=0 ts=6a7f0e9c cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=iNkdjwxjGt8fguHhLfQA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: CSBtmoJhEVCuhUJMnStet0zjzl1L8wzM X-Proofpoint-GUID: CSBtmoJhEVCuhUJMnStet0zjzl1L8wzM X-Proofpoint-Spam-Info: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfX8PkVZ6/Qj8IA U7Ftx3+d7IxHzNgcs3cnAMHOODZhUNSbFYCYzg3noT42XvF9barkT0+1PuLUER82eLJEEbeGnW+ np9a3FMiPwXSZaeeHvkp/VjpUYU7rJo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-14_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608140097 Some CMN PLL output clocks require a hardware gate in addition to a fixed rate. The gate control bits reside in the register CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered via a new struct clk_fixed_gate and clk_fixed_gate_ops, combining a fixed rate with enable/disable/is_enabled gate control through the shared regmap for CMN_PLL_OUTPUT_RELATED_1. The enable_bit field is added to struct cmn_pll_fixed_output_clk (set to -1 for non-gated clocks). The CLK_PLL_OUTPUT_RAW() and CLK_PLL_GATE() helper macros are introduced alongside the existing CLK_PLL_OUTPUT(). Parent these gated fixed-rate clocks on cmn_pll_div2, like the rest of IPQ5210's output clocks, for clock-tree consistency. This is functionally identical: clk_fixed_gate_recalc_rate() returns a fixed constant rate and never depends on the parent rate. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 141 +++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 136 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index eadbf6482aa4..d5eddedd01ed 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -93,9 +93,19 @@ #define CMN_PLL_DIVIDER_CTRL 0x794 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) =20 +/* Clock gate enable bits. */ +#define CMN_PLL_OUTPUT_RELATED_1 0x79c +#define CLK25M_EN_BIT 15 +#define CLK50M_EN_BIT3_BIT 14 +#define CLK250M_EN_BIT 13 +#define CLK31P25M_EN_BIT 12 +#define CLK50M_EN_BIT 11 +#define CLK50M_EN_BIT2_BIT 10 + /** * enum cmn_pll_clk_type - CMN PLL output clock registration type * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock + * @CMN_PLL_CLK_FIXED_GATE: fixed rate clock with a hardware gate * @CMN_PLL_CLK_NSS: NSS clock with configurable divider * @CMN_PLL_CLK_PPE: PPE clock with configurable divider * @CMN_PLL_CLK_PON: PON reference clock @@ -103,6 +113,7 @@ */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, + CMN_PLL_CLK_FIXED_GATE, CMN_PLL_CLK_NSS, CMN_PLL_CLK_PPE, CMN_PLL_CLK_PON, @@ -115,12 +126,15 @@ enum cmn_pll_clk_type { * @name: Clock name to be registered * @type: Clock registration type * @rate: Clock rate + * @enable_bit: Enable bit in CMN_PLL_OUTPUT_RELATED_1 for gate clock, + * -1 for non-gated clocks. */ struct cmn_pll_fixed_output_clk { unsigned int id; const char *name; enum cmn_pll_clk_type type; unsigned long rate; + int enable_bit; }; =20 /** @@ -133,6 +147,10 @@ struct cmn_pll_fixed_output_clk { * plain fixed-rate xo/sleep clocks, which stay on the main * PLL); other SoCs' output clocks use hardcoded rates that * never depend on a parent + * + * This structure is used for all CMN PLL-derived clocks including + * the main PLL, NSS clock, PPE clock, PON reference clock, and + * EPHY-RAW clock. */ struct clk_cmn_pll { struct regmap *regmap; @@ -140,15 +158,41 @@ struct clk_cmn_pll { struct clk_hw *div2_hw; }; =20 -#define CLK_PLL_OUTPUT(_id, _name, _rate) { \ - .id =3D _id, \ - .name =3D _name, \ - .type =3D CMN_PLL_CLK_FIXED_RATE, \ - .rate =3D _rate, \ +/** + * struct clk_fixed_gate - fixed rate clock with a hardware gate + * @regmap: hardware regmap. + * @hw: handle between common and hardware-specific interfaces + * @rate: fixed clock rate. + * @enable_bit: enable bit in CMN_PLL_OUTPUT_RELATED_1, which is shared + * across multiple gate clocks, but regmap already serializes + * read-modify-write access to a given register, so no + * additional locking is needed here. + */ +struct clk_fixed_gate { + struct regmap *regmap; + struct clk_hw hw; + unsigned long rate; + int enable_bit; +}; + +#define CLK_PLL_OUTPUT_RAW(_id, _name, _type, _rate, _bit) { \ + .id =3D _id, \ + .name =3D _name, \ + .type =3D _type, \ + .rate =3D _rate, \ + .enable_bit =3D _bit, \ } =20 +#define CLK_PLL_OUTPUT(_id, _name, _rate) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_RATE, _rate, -1) + +#define CLK_PLL_GATE(_id, _name, _rate, _bit) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_GATE, _rate, _bit) + #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) =20 +#define to_clk_fixed_gate(_hw) container_of(_hw, struct clk_fixed_gate, hw) + static const struct regmap_config ipq_cmn_pll_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -711,6 +755,85 @@ static struct clk_hw *ipq_cmn_pll_ephy_raw_register(st= ruct platform_device *pdev return &ephy_raw_clk->hw; } =20 +static int clk_fixed_gate_enable(struct clk_hw *hw) +{ + struct clk_fixed_gate *gate_clk =3D to_clk_fixed_gate(hw); + + return regmap_set_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, + BIT(gate_clk->enable_bit)); +} + +static void clk_fixed_gate_disable(struct clk_hw *hw) +{ + struct clk_fixed_gate *gate_clk =3D to_clk_fixed_gate(hw); + + regmap_clear_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, + BIT(gate_clk->enable_bit)); +} + +static int clk_fixed_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_fixed_gate *gate_clk =3D to_clk_fixed_gate(hw); + + return regmap_test_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, + BIT(gate_clk->enable_bit)); +} + +static unsigned long clk_fixed_gate_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_fixed_gate *gate_clk =3D to_clk_fixed_gate(hw); + + return gate_clk->rate; +} + +static const struct clk_ops clk_fixed_gate_ops =3D { + .enable =3D clk_fixed_gate_enable, + .disable =3D clk_fixed_gate_disable, + .is_enabled =3D clk_fixed_gate_is_enabled, + .recalc_rate =3D clk_fixed_gate_recalc_rate, +}; + +static struct clk_hw *ipq_cmn_pll_register_fixed_gate(struct device *dev, + const char *name, + struct clk_hw *parent_hw, + struct regmap *regmap, + unsigned long rate, + int enable_bit) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct clk_fixed_gate *gate_clk; + struct clk_init_data init =3D {}; + int ret; + + gate_clk =3D devm_kzalloc(dev, sizeof(*gate_clk), GFP_KERNEL); + if (!gate_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_fixed_gate_ops; + /* + * These gated clocks may be relied on by external hardware or + * bootloader-enabled paths without an in-kernel client driver. + * Add CLK_IGNORE_UNUSED so the clock framework does not disable + * them when no consumer has claimed them. + */ + init.flags =3D CLK_IGNORE_UNUSED; + + gate_clk->hw.init =3D &init; + gate_clk->regmap =3D regmap; + gate_clk->rate =3D rate; + gate_clk->enable_bit =3D enable_bit; + + ret =3D devm_clk_hw_register(dev, &gate_clk->hw); + if (ret) + return ERR_PTR(ret); + + return &gate_clk->hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -762,6 +885,14 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) hw =3D ERR_PTR(-EINVAL); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8517d26726bsm405934b3a.54.2026.08.14.05.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 05:48:27 -0700 (PDT) From: Luo Jie Date: Fri, 14 Aug 2026 05:48:20 -0700 Subject: [PATCH v3 10/12] clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260814-qcom_ipq5210_cmnpll-v3-10-21c3db378611@oss.qualcomm.com> References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> In-Reply-To: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786711693; l=3700; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=xb7jRYlB1XJZ2ikl81tfQItsu2u2gXXfn0VCM3meJ4Q=; b=n0DlPjFFGX3HvHXRcMoCS+2Ph0MK5Fa+6Fwd5GLyd5rFVCT+RxYwKoztPSpkg08XTSRs7N7WY 6qHGzerujBuAAr9SenhtIhWnYXILJ5IzLAKMy0OuZDb0nLHUmG0Vf8Z X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfX8YqiGeunqVnR UwZjtQ2kCTyuH2u3v/xdp0BE6zt3UQvODmaCTHzM3pIqshswb+Lj+A5kAaHxR91ZduFKlHEAZM9 qrAhmBtxy+j+VUAGfd/W0OlxdKW220uvMwW5Imv5/dLuI+96Lj2/4THhFFwO7oSMoy8YqS2tIko JippEFvB9zI3jqjC/NTo8HFe0XBYYZ+rW5I9NrhKmlITAfz/AwRzJQGbBNvn+HSJ1DLIf2Ce4cT KVSvZ+iJvLSBhtWOKewkU0L6BdoBpPXcLxqiMIAOg2tQuYBvO7Kcqbd0CVbmw1oRLaJGi+nfTQp 0ExaNiJzOSXLape0X+qIYhSfNFDKW0htbnyH5QNiUzS5pGo/cKA4yd+ezC7HfKGIqfPZ+WpbX7p hK7hkpIemAsL2OmT1DC4g+VJVdbudzvt5rH9eXGXxOg7L/XW6n5JJ53E3SfMn+5bdT3ZLq0vPfG MNBt+t/JA7Iu/1CA2sQ== X-Authority-Analysis: v=2.4 cv=DdMnbPtW c=1 sm=1 tr=0 ts=6a7f0e9d cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=P04cmAjberRrbCkX5BgA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfXwsn9D2furvRN jnqJnitNT91T8OkhSDSeEZt3rlRUXvLjYBDiHqTta8s/t7Mftu/cZ/XBwAKWxD/CLJ248WycBmZ JC4ClKcfY93wvUUIhuZKS0itknO8qM4= X-Proofpoint-GUID: 9qWgNRR_HUysesxQ5s-Cq_Ep3ZrsEAn5 X-Proofpoint-ORIG-GUID: 9qWgNRR_HUysesxQ5s-Cq_Ep3ZrsEAn5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-14_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 phishscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608140097 Add the IPQ5210 output clock array and the device match table entry, wiring together all the infrastructure added in the previous patches. The IPQ5210 CMN PLL supplies 12 output clocks: Fixed-rate: XO 24 MHz, sleep 32 kHz Gated fixed-rate: PCS 31.25 MHz, ETH0/1/2 50 MHz, EPHY 50 MHz, ETH 25 MHz Configurable divider: NSS, PPE PON reference: PON (enable/disable + 8-bit divider) EPHY-RAW: 125/312.5 MHz select Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index d5eddedd01ed..6234e7cf3f01 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -55,6 +55,7 @@ =20 #include #include +#include #include #include #include @@ -189,6 +190,18 @@ struct clk_fixed_gate { #define CLK_PLL_GATE(_id, _name, _rate, _bit) \ CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_GATE, _rate, _bit) =20 +#define CLK_PLL_NSS(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_NSS, 0, -1) + +#define CLK_PLL_PPE(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_PPE, 0, -1) + +#define CLK_PLL_PON(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_PON, 0, -1) + +#define CLK_PLL_EPHY_RAW(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_EPHY_RAW, 0, -1) + #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) =20 #define to_clk_fixed_gate(_hw) container_of(_hw, struct clk_fixed_gate, hw) @@ -207,6 +220,22 @@ static const struct cmn_pll_fixed_output_clk ipq5018_o= utput_clks[] =3D { { /* Sentinel */ } }; =20 +static const struct cmn_pll_fixed_output_clk ipq5210_output_clks[] =3D { + CLK_PLL_OUTPUT(IPQ5210_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(IPQ5210_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_GATE(IPQ5210_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL, CLK31P= 25M_EN_BIT), + CLK_PLL_GATE(IPQ5210_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL, CLK50M_EN_= BIT), + CLK_PLL_GATE(IPQ5210_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL, CLK50M_EN_= BIT2_BIT), + CLK_PLL_GATE(IPQ5210_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL, CLK50M_EN_= BIT3_BIT), + CLK_PLL_GATE(IPQ5210_EPHY_50MHZ_CLK, "ephy-50mhz", 50000000UL, CLK250M_EN= _BIT), + CLK_PLL_GATE(IPQ5210_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL, CLK25M_EN_BI= T), + CLK_PLL_NSS(IPQ5210_NSS_CLK, "nss"), + CLK_PLL_PPE(IPQ5210_PPE_CLK, "ppe"), + CLK_PLL_PON(IPQ5210_PON_CLK, "pon"), + CLK_PLL_EPHY_RAW(IPQ5210_EPHY_RAW_CLK, "ephy-raw"), + { /* Sentinel */ } +}; + static const struct cmn_pll_fixed_output_clk ipq6018_output_clks[] =3D { CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL), CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 4165= 00000UL), @@ -995,6 +1024,7 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops =3D { =20 static const struct of_device_id ipq_cmn_pll_clk_ids[] =3D { { .compatible =3D "qcom,ipq5018-cmn-pll", .data =3D &ipq5018_output_clks = }, + { .compatible =3D "qcom,ipq5210-cmn-pll", .data =3D &ipq5210_output_clks = }, { .compatible =3D "qcom,ipq5332-cmn-pll", .data =3D &ipq5332_output_clks = }, { .compatible =3D "qcom,ipq5424-cmn-pll", .data =3D &ipq5424_output_clks = }, { .compatible =3D "qcom,ipq6018-cmn-pll", .data =3D &ipq6018_output_clks = }, --=20 2.43.0 From nobody Fri Aug 14 15:51:39 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8E57470107 for ; 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The reference clock of CMN PLL is routed from XO to the CMN PLL through the WiFi block. XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 15 +++++++++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 26 +++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 941f866ecfe9..7410d092814e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -74,6 +74,21 @@ &uart1 { status =3D "okay"; }; =20 +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically + * enables the right dividers, to ensure the reference clock output + * from WiFi to the CMN PLL is 48 MHZ. + */ +&ref_48mhz_clk { + clock-div =3D <1>; + clock-mult =3D <1>; +}; + &xo_board { clock-frequency =3D <24000000>; }; + +&xo_clk { + clock-frequency =3D <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 2cdc10529c48..52d851a0dc2b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -3,8 +3,9 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 -#include +#include #include +#include #include =20 / { @@ -13,6 +14,12 @@ / { interrupt-parent =3D <&intc>; =20 clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -22,6 +29,11 @@ xo_board: xo-board-clk { compatible =3D "fixed-clock"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8517d26726bsm405934b3a.54.2026.08.14.05.48.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 05:48:30 -0700 (PDT) From: Luo Jie Date: Fri, 14 Aug 2026 05:48:22 -0700 Subject: [PATCH v3 12/12] arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260814-qcom_ipq5210_cmnpll-v3-12-21c3db378611@oss.qualcomm.com> References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> In-Reply-To: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786711693; l=1388; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=U6Opb8TcQbuMMqUTCWCIlKozzx86+MbPY3j42JH8zpo=; b=GoHKPlU3bC0W9TMzVKcDfRktV9jgV4Cilkf9AMRArxgujJcqHehLBQHiUjtBmT+6x0WWUK3+X /f+799d2sS7BjMswFR47ZyxQuzjkRukDxml+yp5khWw9wsZUJoCYv// X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Info: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfX8XnfCEvqM+Hr x8zstRdQ/+DeFhf1mnnP54ING/tFGuGp1L4CZh7KBWA7uW6ilqMet6lV3Kzz1acOR/XEXRR1WfP 1RqYPXsEjYHyfs/9jPIWNeHSnrOjMEI= X-Authority-Analysis: v=2.4 cv=eqzvCIpX c=1 sm=1 tr=0 ts=6a7f0ea0 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=CPdYy-Otk887xBsD2wUA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-GUID: FRVmX-y1oKm3gxligjLQcXMYX1klTBf0 X-Proofpoint-ORIG-GUID: FRVmX-y1oKm3gxligjLQcXMYX1klTBf0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE0MDA5NyBTYWx0ZWRfX71HMYMW4uudB ofN7IJJqBP5VOSr9OXjTcx7CgK908bjrbQmwybF//Zg+dBpK5WlXGZCoL/oPGQC5/FwdJLhyj6M 3cIQwcUyL7B0/YwTr0jTiWnTxbc21LEgdihSG1fxPrPTDjm1W/N0TT0qBCS7K9hd8YD+Rzr+AAE a58mcX5g4QZdgJY337SM63S2rnTMaXevr7DTKlAzZYTKYREKAK+8y9TsgwQV/7LDlCZWQmgK9PK vAO3Ls4s/sVs/7RGNvZ8eiuPAyfv66yGjgNk3VEkmLS7H5a0aeVEltowhvR9H54jI1TeSEJPIZx k4oFqZzqVCuteZqKGcU+IrFNnPf+9KLZeglf2YifR9m8OD8lZ2VxXd85g9RnYpNt7YprfSleJd/ /hzsm0CqaL3qGUv4gvzmZ/+B7KMSWWUK+mH76ryToL/dHNVfp9aojynShCvEgy/icXmy1sQET8s RnU3XtVSPFA42gajzdQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-14_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608140097 xo_board is fixed to 24 MHZ, which is routed from WiFi output clock 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 7 ++++++- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 7410d092814e..fa537633d5f5 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -85,8 +85,13 @@ &ref_48mhz_clk { clock-mult =3D <1>; }; =20 +/* + * The frequency of xo_board is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board { - clock-frequency =3D <24000000>; + clock-div =3D <2>; + clock-mult =3D <1>; }; =20 &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 52d851a0dc2b..0c1ede0f73b2 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -26,7 +26,8 @@ sleep_clk: sleep-clk { }; =20 xo_board: xo-board-clk { - compatible =3D "fixed-clock"; + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; #clock-cells =3D <0>; }; =20 --=20 2.43.0