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charset="utf-8" From: Saurav Sachidanand The L1D prefetcher metrics (l1d_cache_rw_miss_ratio, l1d_demand_accesses, etc.) were incorrectly assigned to MetricGroup "L1I_Prefetcher_Effectivenes= s" and vice versa. This causes 'perf stat --metric-group L1D_Prefetcher_Effect= iveness' to display L1I metrics, which is misleading. Swap the MetricGroup assignments so L1D metrics are in the L1D group and L1I metrics are in the L1I group. Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU ev= ents") Signed-off-by: Saurav Sachidanand Reviewed-by: Besar Wicaksono Reviewed-by: Ian Rogers --- .../arch/arm64/nvidia/t410/metrics.json | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json b/to= ols/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json index b825ede03f54..59474ccb7417 100644 --- a/tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json @@ -346,42 +346,42 @@ "MetricExpr": "l1d_demand_misses / l1d_demand_accesses", "BriefDescription": "This metric measures the ratio of L1 D-cache = Read accesses missed to the total number of L1 D-cache accesses. This gives= an indication of the effectiveness of the L1 D-cache for demand Load or St= ore traffic.", "ScaleUnit": "1per cache access", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_demand_accesses", "MetricExpr": "L1D_CACHE_RW", "BriefDescription": "This metric measures the count of L1 D-cache = accesses incurred on Load or Store by the instruction stream of the program= .", "ScaleUnit": "1count", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_demand_misses", "MetricExpr": "L1D_CACHE_REFILL_RW", "BriefDescription": "This metric measures the count of L1 D-cache = misses incurred on a Load or Store by the instruction stream of the program= .", "ScaleUnit": "1count", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_prf_accuracy", "MetricExpr": "100 * (l1d_useful_prf / l1d_refilled_prf)", "BriefDescription": "This metric measures the fraction of prefetch= ed memory addresses that are used by the instruction stream.", "ScaleUnit": "1percent of prefetch", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_prf_coverage", "MetricExpr": "100 * (l1d_useful_prf / (l1d_demand_misses + l1d_re= filled_prf))", "BriefDescription": "This metric measures the baseline demand cach= e misses which the prefetcher brings into the cache.", "ScaleUnit": "1percent of cache access", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_refilled_prf", "MetricExpr": "L1D_CACHE_REFILL_HWPRF + L1D_CACHE_REFILL_PRFM + L1= D_LFB_HIT_RW_FHWPRF + L1D_LFB_HIT_RW_FPRFM", "BriefDescription": "This metric measures the count of cache lines= refilled by L1 data prefetcher (hardware prefetches or software preload) i= nto L1 D-cache.", "ScaleUnit": "1count", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_tlb_miss_ratio", @@ -402,7 +402,7 @@ "MetricExpr": "L1D_CACHE_HIT_RW_FPRF + L1D_LFB_HIT_RW_FHWPRF + L1D= _LFB_HIT_RW_FPRFM", "BriefDescription": "This metric measures the count of cache lines= refilled by L1 data prefetcher (hardware prefetches or software preload) i= nto L1 D-cache which are further used by Load or Store from the instruction= stream of the program.", "ScaleUnit": "1count", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1i_cache_miss_ratio", @@ -423,42 +423,42 @@ "MetricExpr": "l1i_demand_misses / l1i_demand_accesses", "BriefDescription": "This metric measures the ratio of L1 I-cache = Read accesses missed to the total number of L1 I-cache accesses. This gives= an indication of the effectiveness of the L1 I-cache for demand instructio= n fetch traffic. Note that cache accesses in this cache are demand instruct= ion fetch.", "ScaleUnit": "1per cache access", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_demand_accesses", "MetricExpr": "L1I_CACHE_RD", "BriefDescription": "This metric measures the count of L1 I-cache = accesses caused by an instruction fetch by the instruction stream of the pr= ogram.", "ScaleUnit": "1count", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_demand_misses", "MetricExpr": "L1I_CACHE_REFILL_RD", "BriefDescription": "This metric measures the count of L1 I-cache = misses caused by an instruction fetch by the instruction stream of the prog= ram.", "ScaleUnit": "1count", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_prf_accuracy", "MetricExpr": "100 * (l1i_useful_prf / l1i_refilled_prf)", "BriefDescription": "This metric measures the fraction of prefetch= ed memory addresses that are used by the instruction stream.", "ScaleUnit": "1percent of prefetch", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_prf_coverage", "MetricExpr": "100 * (l1i_useful_prf / (l1i_demand_misses + l1i_re= filled_prf))", "BriefDescription": "This metric measures the baseline demand cach= e misses which the prefetcher brings into the cache.", "ScaleUnit": "1percent of cache access", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_refilled_prf", "MetricExpr": "L1I_CACHE_REFILL_HWPRF + L1I_CACHE_REFILL_PRFM", "BriefDescription": "This metric measures the count of cache lines= refilled by L1 instruction prefetcher (hardware prefetches or software pre= load) into L1 I-cache.", "ScaleUnit": "1count", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_tlb_miss_ratio", @@ -479,7 +479,7 @@ "MetricExpr": "L1I_CACHE_HIT_RD_FPRF", "BriefDescription": "This metric measures the count of cache lines= refilled by L1 instruction prefetcher (hardware prefetches or software pre= load) into L1 I-cache which are further used by instruction stream of the p= rogram.", "ScaleUnit": "1count", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l2_cache_miss_ratio", --=20 2.43.0 From nobody Tue Sep 29 02:02:39 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013058.outbound.protection.outlook.com [40.107.201.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EB2938F255; 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charset="utf-8" The name and description for NVIDIA Tegra410 Olympus implementation-defined event 0x0197 incorrectly indicate a TXREQ limit between one quarter and one half. Correct them to describe a TXREQ limit below one half. Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU ev= ents") Signed-off-by: Besar Wicaksono Reviewed-by: Ian Rogers --- tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json b/tools= /perf/pmu-events/arch/arm64/nvidia/t410/misc.json index 8ff87d844e52..e1b45cc33b18 100644 --- a/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json @@ -316,8 +316,8 @@ }, { "EventCode": "0x0197", - "EventName": "TXREQ_LIMIT_1QUARTER_CYCLES", - "PublicDescription": "Number of cycles in which the dynamic TXREQ = limit is between 1/4 of the L2_TQ_SIZE and 1/2 of the L2_TQ_SIZE." + "EventName": "TXREQ_LIMIT_BELOW_HALF_CYCLES", + "PublicDescription": "Number of cycles in which the dynamic TXREQ = limit is between 0 and 1/2 of the L2_TQ_SIZE." }, { "EventCode": "0x019d", @@ -517,7 +517,7 @@ { "EventCode": "0x01cc", "EventName": "TXREQ_LIMIT_COUNT_CYCLES", - "PublicDescription": "This event increments by the dynamic TXREQ v= alue, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, = TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_1QUAR= TER_CYCLES." + "PublicDescription": "This event increments by the dynamic TXREQ v= alue, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, = TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_BELOW= _HALF_CYCLES." }, { "EventCode": "0x01ce", --=20 2.43.0