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charset="utf-8" Cosmin's Analog Devices address is no longer valid, leaving the ADXL367 binding without a reachable maintainer. Take over maintainership of the binding and add myself to the MAINTAINERS entry alongside Marcelo. Signed-off-by: Antoniu Miclaus Reviewed-by: Nuno S=C3=A1 --- Changes in v2: - New patch. Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml | 2 +- MAINTAINERS | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml b= /Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml index f10d98d34cb8..29689bc38b90 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADXL367 3-Axis Digital Accelerometer =20 maintainers: - - Cosmin Tanislav + - Antoniu Miclaus =20 description: | The ADXL367 is an ultralow power, 3-axis MEMS accelerometer. diff --git a/MAINTAINERS b/MAINTAINERS index 7077ed7c9efe..69e41b262a6d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -641,6 +641,7 @@ F: drivers/iio/accel/adxl355_spi.c =20 ADXL367 THREE-AXIS DIGITAL ACCELEROMETER DRIVER M: Marcelo Schmitt +M: Antoniu Miclaus L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers --=20 2.43.0 From nobody Tue Sep 29 02:34:31 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F7DF442B3E; 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charset="utf-8" The ADXL367 has two independent interrupt output pins, INT1 and INT2, either of which may be wired to the host. Allow the interrupt line that is connected to be described by adding an optional interrupt-names property accepting "INT1" and/or "INT2", and permit a second interrupt entry. interrupt-names is kept optional so existing device trees that only specify a bare interrupts property remain valid. Signed-off-by: Antoniu Miclaus Reviewed-by: Rob Herring (Arm) --- Changes in v2: - No changes. .../devicetree/bindings/iio/accel/adi,adxl367.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml b= /Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml index 29689bc38b90..115170eac058 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml @@ -33,7 +33,14 @@ properties: maxItems: 1 =20 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - enum: [INT1, INT2] + - const: INT2 =20 vdd-supply: true vddio-supply: true @@ -61,6 +68,7 @@ examples: reg =3D <0x53>; interrupt-parent =3D <&gpio>; interrupts =3D <25 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "INT1"; }; }; - | @@ -76,5 +84,6 @@ examples: spi-max-frequency =3D <1000000>; interrupt-parent =3D <&gpio>; interrupts =3D <25 IRQ_TYPE_EDGE_RISING>; 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Thu, 13 Aug 2026 04:15:20 -0400 From: Antoniu Miclaus To: Marcelo Schmitt , Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Subject: [PATCH v2 3/3] iio: accel: adxl367: add support for INT2 interrupt pin Date: Thu, 13 Aug 2026 11:14:52 +0300 Message-ID: <20260813081452.4289-4-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260813081452.4289-1-antoniu.miclaus@analog.com> References: <20260813081452.4289-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: Sg9uVsrfP77LzvXuy-JPoj4lrsIv8DS8 X-Proofpoint-GUID: Sg9uVsrfP77LzvXuy-JPoj4lrsIv8DS8 X-Authority-Analysis: v=2.4 cv=QbJWeMbv c=1 sm=1 tr=0 ts=6a7d7d20 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=Z0pTeXoby7EwIRygza74:22 a=gAnH3GRIAAAA:8 a=HxlKZNGDwPukNFmCmIsA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA1NiBTYWx0ZWRfXzNi+V3uiqA/X aa0guLTMWa9DZgHWOjiNUytHshC72TM5iHTYV6sncywFSYQuEcA3nLSk+cIsmBPKSi9X/ivGtW1 9jNKhej4VsjpMgccP+Nk8nV3VcgY83KZwWaeS9fnmBP5F4VYHWV2dXrhaBW7lcg2JTT3GCh9DIk fz323pCQOJFlBANxV60Q82zZ02gyRg1byKH0b7HFb2AtfGU57wffGBKnT/rMXnJZ+zA60RrauEd 95mNWdtIgMBay/236i5IJoga+Qjb6aKxwQ1s0mAxGLCs3PEtRwO7UbyRbeohzOaLIKfixajW/9E VGbcsMx5nqZWScmXp6WRO0NKwW9qWoVkK9UkcUdNj9KtbeGCjtL1KuJ4BjIR9q2Z5WNK8YOsDpu vOjMfQLBQLK5pzN2gstSIMQfTRKyWXdhRQjjL/2DlQkXjzN6sGKFDbE6ER1lDJuiDqsqfbwg6WG akUlAMevEnTn9YGGXfg== X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA1NiBTYWx0ZWRfX+zVjfCeQfDIK qqLOYP5pk73alqPWo1FPgyKwiIvgFtQQG8ORFQ6QmVI+YJIHnxiHIeTuJb2Hwc7DDH/mafpw5CS MiJlpqDIImGryRFHQJwExXzZTVveuDRaVH+RqDTUbhbBDVW2MywZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_02,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130056 Content-Type: text/plain; charset="utf-8" The ADXL367 provides two independent interrupt output pins, INT1 and INT2, each with its own event mapping register (INTMAP1_LOWER at 0x2A and INTMAP2_LOWER at 0x2B) sharing an identical bit layout. Until now the driver hardcoded INT1 for all interrupt mappings, so a board that routes only INT2 to the host could never receive activity, inactivity or FIFO watermark interrupts. Determine the connected pin from the interrupt-names device tree property using fwnode_irq_get_byname(), and route the interrupt mappings to the matching register. When no interrupt-names are present, default to INT1 to preserve the existing behaviour. Signed-off-by: Antoniu Miclaus --- Changes in v2: - Propagate -EPROBE_DEFER from fwnode_irq_get_byname(). - Drop the redundant irq return; the helper now only selects the INT map register. drivers/iio/accel/adxl367.c | 39 ++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c index 8c3de11a10a3..df385740b17b 100644 --- a/drivers/iio/accel/adxl367.c +++ b/drivers/iio/accel/adxl367.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -81,6 +82,7 @@ #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0) =20 #define ADXL367_REG_INT1_MAP 0x2A +#define ADXL367_REG_INT2_MAP 0x2B #define ADXL367_INT_INACT_MASK BIT(5) #define ADXL367_INT_ACT_MASK BIT(4) #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2) @@ -168,6 +170,8 @@ struct adxl367_state { enum adxl367_odr odr; enum adxl367_range range; =20 + u8 int_map_reg; + unsigned int act_threshold; unsigned int act_time_ms; unsigned int inact_threshold; @@ -366,7 +370,7 @@ static int adxl367_set_act_interrupt_en(struct adxl367_= state *st, { unsigned int mask =3D adxl367_act_int_mask_tbl[act]; =20 - return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, + return regmap_update_bits(st->regmap, st->int_map_reg, mask, en ? mask : 0); } =20 @@ -378,7 +382,7 @@ static int adxl367_get_act_interrupt_en(struct adxl367_= state *st, unsigned int val; int ret; =20 - ret =3D regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val); + ret =3D regmap_read(st->regmap, st->int_map_reg, &val); if (ret) return ret; =20 @@ -401,7 +405,7 @@ static int adxl367_set_act_en(struct adxl367_state *st, static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *s= t, bool en) { - return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, + return regmap_update_bits(st->regmap, st->int_map_reg, ADXL367_INT_FIFO_WATERMARK_MASK, en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0); } @@ -1426,6 +1430,31 @@ static int adxl367_setup(struct adxl367_state *st) return adxl367_set_measure_en(st, true); } =20 +static int adxl367_set_int_map_reg(struct adxl367_state *st) +{ + int irq; + + irq =3D fwnode_irq_get_byname(dev_fwnode(st->dev), "INT1"); + if (irq =3D=3D -EPROBE_DEFER) + return irq; + if (irq > 0) { + st->int_map_reg =3D ADXL367_REG_INT1_MAP; + return 0; + } + + irq =3D fwnode_irq_get_byname(dev_fwnode(st->dev), "INT2"); + if (irq =3D=3D -EPROBE_DEFER) + return irq; + if (irq > 0) { + st->int_map_reg =3D ADXL367_REG_INT2_MAP; + return 0; + } + + /* No interrupt-names: default to INT1 for backwards compatibility. */ + st->int_map_reg =3D ADXL367_REG_INT1_MAP; + return 0; +} + int adxl367_probe(struct device *dev, const struct adxl367_ops *ops, void *context, struct regmap *regmap, int irq) { @@ -1482,6 +1511,10 @@ int adxl367_probe(struct device *dev, const struct a= dxl367_ops *ops, if (ret) return ret; =20 + ret =3D adxl367_set_int_map_reg(st); + if (ret) + return dev_err_probe(st->dev, ret, "Failed to get interrupt\n"); + ret =3D devm_request_threaded_irq(st->dev, irq, NULL, adxl367_irq_handler, IRQF_ONESHOT, indio_dev->name, indio_dev); --=20 2.43.0