From nobody Tue Sep 29 02:35:27 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA105257435; Thu, 13 Aug 2026 03:49:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786592955; cv=none; b=QkWJDQYf2i4NHVT1n+M4YWELDmbLrVL52K8BtvU0eKlrbsT5nvHuvBgSik1gpQHOZDgB3m+KNB+lj+g3JTCwK2o/pNTZwCMGF+DV9TXk7QSz6+Dw4Vqn4OUaYxdUnmwuXKRLEiTb9+zjv0yQqUUhM14jd3Y3wd6tKGiISq6MUBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786592955; c=relaxed/simple; bh=sCT0HGL48C2Dhj6VPptfAkCs427iW18q14blynatI2Y=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=oYiZHVqySdMPBUzNGXNhtxSdrqYEiU79+KsH5CTtbWS6Z4smVCfJYA9BxavxWbx2Nc1doshgkIB80gaiRAf9DyN4QQUhlpBAn5Osla/rmt5Ntf2C2YUu/S2OBlZTcCH/RWIsJJTuObCTOMsJPa7HD0Z94AdqbpVeId6rX1olGnU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=poqtE2kf; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="poqtE2kf" X-UUID: ed3af3e096c911f18dc8c9802ae25ab1-20260813 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=WjW1iFwVtZMI3E3j7mXThCsTi9G0FgFnbg0XkTKJR00=; b=poqtE2kfeYJ/SqCrORfHf54Zrg8U3xp2maMJm5kQIGYN1UF88Sna016SPvC0SfLb3z/MCL43ocSRfNRKXOsMigF7V5N89Fk6DJfmhJU9MTUaNMDM2z59ovCRdaD3e835SKNe/olavSNFFQnXdjWAOXr86Hb6GGqpaCA2HbkpfTY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.19,REQID:f5ea13d7-92e0-4dea-8ea8-3ca671be6dc7,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:7db8b62,CLOUDID:6d77bd36-0807-4c08-acbf-7f2dbfd5bbbf,B ulkID:nil,BulkQuantity:0,SF:102|836|865|888|898,TC:-5,Content:0|15|50|99,E DM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: ed3af3e096c911f18dc8c9802ae25ab1-20260813 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1932425085; Thu, 13 Aug 2026 11:49:03 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 13 Aug 2026 11:49:02 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Thu, 13 Aug 2026 11:49:01 +0800 From: Zexin Wang To: Wim Van Sebroeck , Guenter Roeck , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , Zexin Wang , , , , Subject: [PATCH v2] watchdog: sbsa_gwdt: add early_enable module parameter Date: Thu, 13 Aug 2026 11:48:56 +0800 Message-ID: <20260813034900.20235-1-ot_zexin.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On SBSA platforms using standard UEFI firmware (such as EDK II), the watchdog timer is often enabled during early boot stages but explicitly disabled by the firmware before handing over control to the OS (e.g., during ExitBootServices). This is done to prevent unintended resets while the OS is loading, assuming the OS watchdog driver will take over. However, this leaves a protection gap. If the system hangs between the firmware handover and the userspace watchdog daemon startup, the hardware watchdog will not fire to recover the system. For safety-critical systems that require continuous hardware watchdog protection from the earliest possible moment, this gap is problematic. Add an 'early_enable' module parameter to allow the kernel driver to re-enable the watchdog immediately during probe if it was left disabled by the firmware. By setting the WDOG_HW_RUNNING status bit, the watchdog core is instructed that the hardware is active. As a result, the core's pre-userspace handler (controlled by 'handle_boot_enabled') will automatically issue periodic keepalives until userspace opens the device. This bridges the protection gap seamlessly without requiring firmware modifications and without risking unintended resets during kernel boot. The parameter defaults to false to preserve the traditional behavior. Signed-off-by: Zexin Wang --- .../watchdog/watchdog-parameters.rst | 2 ++ drivers/watchdog/sbsa_gwdt.c | 23 +++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/watchdog/watchdog-parameters.rst b/Documentation= /watchdog/watchdog-parameters.rst index 502cb6adbeda..47867a621ada 100644 --- a/Documentation/watchdog/watchdog-parameters.rst +++ b/Documentation/watchdog/watchdog-parameters.rst @@ -515,6 +515,8 @@ sbsa_gwdt: nowayout: Watchdog cannot be stopped once started (default=3Dkernel config parameter) + early_enable: + Watchdog is started on module insertion (default=3D0) =20 ------------------------------------------------- =20 diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index e04d42cc7774..ed913be3d1cb 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -122,6 +122,11 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=3D" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); =20 +static bool early_enable; +module_param(early_enable, bool, 0); +MODULE_PARM_DESC(early_enable, + "Watchdog is started on module insertion (default=3D0)"); + /* * Arm Base System Architecture 1.0 introduces watchdog v1 which * increases the length watchdog offset register to 48 bits. @@ -296,6 +301,7 @@ static int sbsa_gwdt_probe(struct platform_device *pdev) struct sbsa_gwdt *gwdt; int ret, irq; u32 status; + bool early_action; =20 gwdt =3D devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL); if (!gwdt) @@ -386,14 +392,27 @@ static int sbsa_gwdt_probe(struct platform_device *pd= ev) */ sbsa_gwdt_set_timeout(wdd, wdd->timeout); =20 + early_action =3D early_enable && !(status & SBSA_GWDT_WCS_EN); + if (early_action) { + sbsa_gwdt_start(wdd); + set_bit(WDOG_HW_RUNNING, &wdd->status); + dev_info(dev, "Watchdog early enabled.\n"); + } + watchdog_stop_on_reboot(wdd); ret =3D devm_watchdog_register_device(dev, wdd); - if (ret) + if (ret) { + dev_err(dev, "Failed to register watchdog: %d\n", ret); + if (early_action) { + clear_bit(WDOG_HW_RUNNING, &wdd->status); + sbsa_gwdt_stop(wdd); + } return ret; + } =20 dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=3D%d.%s\n", wdd->timeout, gwdt->clk, action, - status & SBSA_GWDT_WCS_EN ? " [enabled]" : ""); + watchdog_hw_running(wdd) ? " [enabled]" : ""); =20 return 0; } --=20 2.45.2