From nobody Tue Sep 29 02:02:24 2026 Received: from mail-43170.protonmail.ch (mail-43170.protonmail.ch [185.70.43.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 811C240DB3E for ; Thu, 13 Aug 2026 10:44:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786617880; cv=none; b=PibEQJ6urX8S9801BCCFK+Lr2kpGtyd+wxoulL6DhrlKWL6VU5Ce+JHzLIKRM6hja+qKQxV9svW0uXhjCRUdfhoItG2beYRNDsSxvGnZ6dHOLd46n1usxAKizd/zOR1Xsjrg2NLlRpPnDnBHqxb48iTPdLQRS/ajxekGm73aMpc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786617880; c=relaxed/simple; bh=f620hvyXPCGL/uxNApOHGdvi/wX5f7xc6L68aofgPLc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g1cGCYdC2maJW5vWu6zWiIxHthZiEFG7Uyw8KMeqsUyZQ6nLbGs0cLwyntJFcrgpFItpfn0eKcXJSeYpTCzwAghvFMHMK5i9gD4sq0hSw8ts4zaDQ4DfO/GRIpn2rDBAp/jG5tH7c2jcVO1Db+ddHhNYRaeNfhOKO9TqkzAOggg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=onurozkan.dev; spf=pass smtp.mailfrom=onurozkan.dev; dkim=pass (2048-bit key) header.d=onurozkan.dev header.i=@onurozkan.dev header.b=IgxHuxCM; arc=none smtp.client-ip=185.70.43.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=onurozkan.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=onurozkan.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=onurozkan.dev header.i=@onurozkan.dev header.b="IgxHuxCM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=onurozkan.dev; s=protonmail; t=1786617874; x=1786877074; bh=+v9o+NRXK5CCGWPth43KlQ7r3Y+hk4xRaz/0tYZOqNo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=IgxHuxCMmWAV7xoey9bZVA8vnSwSYcqFn4Im6nheM0os2z9QY6FfTrK1p/0lXDNHX mv/OAuQDyRI6AfrTxVCCRj2FWQd/8s4vwmb3i9ubZIEp5VMXqv3+Dl0UdvUC+yz7pU YRJcbiVhCssN30Fe1DASLZHWIP1dpKm7NNo9ivLlZsONpCtB2lP/qbEYD2S5V2kzo6 OfEQzsopgOKvCUQBxc4Rm7Ee4WCP1EQ4/1Q414nyE4+rtowwVeTXodd4B+OfVNgwwm /aGZoLGga4IIkl2tPR/BfNZmL7cIld+550Cuj+W16AHfRYHpkMemzCuCb+u0eTRBsZ HAGEJtHkr+isQ== X-Pm-Submission-Id: 4hLMRz6VQcz2SchM From: =?UTF-8?q?Onur=20=C3=96zkan?= To: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: dakr@kernel.org, aliceryhl@google.com, daniel.almeida@collabora.com, airlied@gmail.com, simona@ffwll.ch, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu, =?UTF-8?q?Onur=20=C3=96zkan?= Subject: [PATCH v4 1/3] rust: workqueue: impl Send and Sync for OwnedQueue Date: Thu, 13 Aug 2026 13:42:04 +0300 Message-ID: <20260813-tyr-reset-impl-v4-1-b36fcd0805b2@onurozkan.dev> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20260813-tyr-reset-impl-v4-0-b36fcd0805b2@onurozkan.dev> References: <20260813-tyr-reset-impl-v4-0-b36fcd0805b2@onurozkan.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Allows OwnedQueue to be used across thread boundaries which is needed from the tyr reset implementation. Reviewed-by: Daniel Almeida Signed-off-by: Onur =C3=96zkan --- rust/kernel/workqueue/mod.rs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/rust/kernel/workqueue/mod.rs b/rust/kernel/workqueue/mod.rs index 933032fc4a85..d766cd9b9175 100644 --- a/rust/kernel/workqueue/mod.rs +++ b/rust/kernel/workqueue/mod.rs @@ -383,6 +383,14 @@ pub struct OwnedQueue { queue: NonNull, } =20 +// SAFETY: `OwnedQueue` has exclusive ownership of the workqueue and acces= ses to workqueues +// are thread safe as documented by the `Send` implementation for `Queue`. +unsafe impl Send for OwnedQueue {} + +// SAFETY: Shared access to an `OwnedQueue` only provides shared access to= its `Queue` which +// is thread safe as documented by the `Sync` implementation for `Queue`. +unsafe impl Sync for OwnedQueue {} + impl Deref for OwnedQueue { type Target =3D Queue; fn deref(&self) -> &Queue { --=20 2.51.2 From nobody Tue Sep 29 02:02:24 2026 Received: from mail-43172.protonmail.ch (mail-43172.protonmail.ch [185.70.43.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5508221883E for ; Thu, 13 Aug 2026 10:44:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786617882; cv=none; b=gnCWKZRXFBO1Hsb1UwBghDYqptzNQGcz3NZErWieitykCIfW5StbXWwY8Sax/w5qk1JwaLmKekVKFitVeiGnu0wEL4D/LsaGmqe8u8yWQGSUQA5e+bSEkp8tGIqh6w+NPdbG0XygXa1Svt1iKB52TbwfbQRFm8kwTiXFvEU58UA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786617882; c=relaxed/simple; bh=KLMHjdeOZqPVCAsOuVuCXyRkdDrSv8YL7ZS+nZzLkOQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=B04eS/KJjWqLTh+SsJBW7jJJXfAo47C6sq/OQ7F2s4vuZmNaNVQ5vRNjM21MO9+GvcA9dK5yZgkgnYeFhiE2nS6truihtpD9FLxsHyYIf6l+bverrsX0z51RjNcqn9nUA+yzBv6chGgTD0WzLooawup7yAxkR4u5wVuMY1B4jsk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=onurozkan.dev; spf=pass smtp.mailfrom=onurozkan.dev; dkim=pass (2048-bit key) header.d=onurozkan.dev header.i=@onurozkan.dev header.b=CGV1BLjF; arc=none smtp.client-ip=185.70.43.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=onurozkan.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=onurozkan.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=onurozkan.dev header.i=@onurozkan.dev header.b="CGV1BLjF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=onurozkan.dev; s=protonmail; t=1786617876; x=1786877076; bh=hMJu3QgsZs8TCdcBeB9Zz/yumkYg03H4j+Dga41n/50=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=CGV1BLjFZx7Pss46APNH6NKOscnSD6hQlMjrybKVruBgnaIhLYXwA9bSNp2JyOZJP /RPVfSJIb/eP73JNeaHFOq6lANg7gVtW/c3AAynbvBuXh4Ci9CgcZdZ2CHfM2NFu/T x3nGtiAhFBx3wOxl9O4vQVtwssC9MuWxTcjZJoiBJraTT8ux1HXnE+B8cmDwRRtjCr Vk0JM+7dJYqMAJW4jhDLTVaOy3pFWG8W1Wb9BF/s8CcsEs0JHsQDD7LGB1lOtP4/rm txxMp+dDWatwhMg2TwGrRHAntytjVofUlrCP6OkuawgnYsdKuVEGKwin0huq3eb0en kmdtaZFlt0RWg== X-Pm-Submission-Id: 4hLMS21hdRz2SchP From: =?UTF-8?q?Onur=20=C3=96zkan?= To: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: dakr@kernel.org, aliceryhl@google.com, daniel.almeida@collabora.com, airlied@gmail.com, simona@ffwll.ch, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu, =?UTF-8?q?Onur=20=C3=96zkan?= , Boris Brezillon Subject: [PATCH v4 2/3] drm/tyr: clear stale IRQ state before soft reset Date: Thu, 13 Aug 2026 13:42:05 +0300 Message-ID: <20260813-tyr-reset-impl-v4-2-b36fcd0805b2@onurozkan.dev> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20260813-tyr-reset-impl-v4-0-b36fcd0805b2@onurozkan.dev> References: <20260813-tyr-reset-impl-v4-0-b36fcd0805b2@onurozkan.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Previous reset may leave the reset completed IRQ set which can make the poll return too early. Clear the IRQ first so the driver waits for the current reset to complete. Reviewed-by: Daniel Almeida Reviewed-by: Boris Brezillon Signed-off-by: Onur =C3=96zkan --- drivers/gpu/drm/tyr/driver.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs index c5063b2be94d..90d6cd988cd2 100644 --- a/drivers/gpu/drm/tyr/driver.rs +++ b/drivers/gpu/drm/tyr/driver.rs @@ -86,6 +86,9 @@ pub(crate) struct TyrDrmRegistrationData<'bound> { } =20 fn issue_soft_reset(dev: &Device, iomem: &IoMem<'_>) -> Result { + // Clear any stale reset IRQ state before issuing a new soft reset. + iomem.write_reg(GPU_IRQ_CLEAR::zeroed().with_reset_completed(true)); + iomem.write_reg(GPU_COMMAND::reset(ResetMode::SoftReset)); =20 poll::read_poll_timeout( --=20 2.51.2 From nobody Tue Sep 29 02:02:24 2026 Received: from mail-106113.protonmail.ch (mail-106113.protonmail.ch [79.135.106.113]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA326416855 for ; Thu, 13 Aug 2026 10:44:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.113 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786617887; cv=none; b=SGDOJc6xkJHubqOoZKeefVmoehr+hn6AD6xO7VRmNH5eiuV86GaWQ/Fa3DdgwFTDI3cuqtENkvLMj4/iQDvktNH6VjX0ax12yo55Dd7Cny04togl/atga64bOzkiO//iOnQUAP1YyxqCHdSyttUpLzg6Pv/u7gWtwPgUUFhmLa8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786617887; c=relaxed/simple; bh=DdFRpmm2EHUoBWsZBt48dJ62Di3pK+rgSzeyTUebLkk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=T+YQtcWKds3zWVKahCjBUmSM/OoBjQAz0mLRZqt/KUUQqahey51NoeQbkHqvdHyunKCIhYEsWPACE6Ffp7Thh0CKkztrwwCsrenDd0JJsAcv0zvqBqUiMsLgf4vpBDvDrgH7QVZvv6bO2qWQ+JWlkE18NtulC9OeZOtP/5AOzs8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=onurozkan.dev; spf=pass smtp.mailfrom=onurozkan.dev; dkim=pass (2048-bit key) header.d=onurozkan.dev header.i=@onurozkan.dev header.b=XZ0fhZC+; arc=none smtp.client-ip=79.135.106.113 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=onurozkan.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=onurozkan.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=onurozkan.dev header.i=@onurozkan.dev header.b="XZ0fhZC+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=onurozkan.dev; s=protonmail; t=1786617880; x=1786877080; bh=PJ+l8TpRd6K7/NQ/LW7YjhLSSgkEciReaAMWfcJj+mc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=XZ0fhZC+D3TVuXPdfEr4YfXdgEdtU41xC18+ecLPg60LAzZj0tCUveDEiihMULZcU KO2uDScXYzmjLD1OXLJIj022ssAT2ifT762LW9CAH1X+dLkWHZRWTfVblBnu4/QW3I C146bCdW/raEA9LFSJW5pgJKlmxbCl5tOpGueoL52kOCvswVk35/KOb/WU6oX/lZ5T wNzhOo8BwEacl8WngLv7QSCn85t/0fJFEyVipDwL7F1zJNbQ+dAwKD/Lr3x4YhGgvY mhcXYJWXISAwOnqirYnkTDQANvLvEMRXCent8Lzng0k/zGYeiPsMBDqKjaSy+mN/Vr jAU7EF0mH+7cQ== X-Pm-Submission-Id: 4hLMS4471bz2SchF From: =?UTF-8?q?Onur=20=C3=96zkan?= To: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: dakr@kernel.org, aliceryhl@google.com, daniel.almeida@collabora.com, airlied@gmail.com, simona@ffwll.ch, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu, =?UTF-8?q?Onur=20=C3=96zkan?= Subject: [PATCH v4 3/3] drm/tyr: add GPU reset infrastructure Date: Thu, 13 Aug 2026 13:42:06 +0300 Message-ID: <20260813-tyr-reset-impl-v4-3-b36fcd0805b2@onurozkan.dev> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20260813-tyr-reset-impl-v4-0-b36fcd0805b2@onurozkan.dev> References: <20260813-tyr-reset-impl-v4-0-b36fcd0805b2@onurozkan.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for scheduling GPU resets on a dedicated workqueue. Track the reset state to avoid queueing another reset while one is already pending or in progress. Use an SRCU based gate with mutex-protected reader admission to block hardware accesses while reset work runs and wait for current users before resetting. Stop new reset requests during teardown and drain any queued or running reset work before releasing the device resources. This is the initial reset infrastructure only. It is not wired to a reset source yet as those will follow in separate work. Link: https://gitlab.freedesktop.org/panfrost/linux/-/work_items/28 Signed-off-by: Onur =C3=96zkan --- drivers/gpu/drm/tyr/driver.rs | 42 ++---- drivers/gpu/drm/tyr/reset.rs | 260 +++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/tyr/reset/hw_gate.rs | 79 +++++++++++ drivers/gpu/drm/tyr/tyr.rs | 1 + 4 files changed, 354 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs index 90d6cd988cd2..bd613ab7e05c 100644 --- a/drivers/gpu/drm/tyr/driver.rs +++ b/drivers/gpu/drm/tyr/driver.rs @@ -8,7 +8,6 @@ device::{ Bound, Core, - Device, DeviceContext, // }, dma::{ @@ -17,13 +16,9 @@ }, drm, drm::ioctl, - io::{ - poll, - Io, // - }, new_mutex, of, - platform, + platform, // prelude::*, regulator, regulator::Regulator, @@ -33,7 +28,6 @@ Arc, Mutex, // }, - time, types::ForLt, // }; =20 @@ -41,10 +35,10 @@ file::TyrDrmFileData, fw::Firmware, gem::BoData, - gpu, gpu::GpuInfo, mmu::Mmu, - regs::gpu_control::*, // + regs::gpu_control::*, + reset, // }; =20 pub(crate) type IoMem<'a> =3D kernel::io::mem::IoMem<'a, SZ_2M>; @@ -67,6 +61,11 @@ pub(crate) struct TyrDrmRegistrationData<'bound> { /// Parent platform device. pub(crate) pdev: &'bound platform::Device, =20 + // `ResetHandle::drop()` drains queued/running works and this must hap= pen + // before clocks/regulators are dropped. So keep this field before the= m to + // ensure the correct drop order. + pub(crate) reset: reset::ResetHandle<'bound>, + /// Firmware sections. pub(crate) fw: Arc>, =20 @@ -85,23 +84,6 @@ pub(crate) struct TyrDrmRegistrationData<'bound> { pub(crate) gpu_info: GpuInfo, } =20 -fn issue_soft_reset(dev: &Device, iomem: &IoMem<'_>) -> Result { - // Clear any stale reset IRQ state before issuing a new soft reset. - iomem.write_reg(GPU_IRQ_CLEAR::zeroed().with_reset_completed(true)); - - iomem.write_reg(GPU_COMMAND::reset(ResetMode::SoftReset)); - - poll::read_poll_timeout( - || Ok(iomem.read(GPU_IRQ_RAWSTAT)), - |status| status.reset_completed(), - time::Delta::from_millis(1), - time::Delta::from_millis(100), - ) - .inspect_err(|_| dev_err!(dev, "GPU reset failed."))?; - - Ok(()) -} - kernel::of_device_table!( OF_TABLE, MODULE_OF_TABLE, @@ -136,8 +118,7 @@ fn probe<'bound>( =20 let iomem =3D Arc::new(request.iomap_sized::()?, GFP_KERNEL= )?; =20 - issue_soft_reset(pdev.as_ref(), &iomem)?; - gpu::l2_power_on(pdev.as_ref(), &iomem)?; + reset::run_reset(pdev.as_ref(), &iomem)?; =20 let gpu_info =3D GpuInfo::new(&iomem); gpu_info.log(pdev.as_ref()); @@ -152,6 +133,10 @@ fn probe<'bound>( =20 let unreg_dev =3D drm::UnregisteredDevice::::new(pde= v, Ok(()))?; =20 + // SAFETY: `ResetHandle` is stored in registration data created wi= th `new_with_lt` + // and is dropped before the borrowed device and MMIO references e= xpire. + let reset =3D unsafe { reset::ResetHandle::new(pdev, iomem.as_arc_= borrow())? }; + let mmu =3D Mmu::new(iomem.as_arc_borrow(), &gpu_info)?; =20 let firmware =3D Firmware::new( @@ -167,6 +152,7 @@ fn probe<'bound>( =20 let reg_data =3D try_pin_init!(TyrDrmRegistrationData { pdev, + reset, fw: firmware, clks <- new_mutex!(Clocks { core: core_clk, diff --git a/drivers/gpu/drm/tyr/reset.rs b/drivers/gpu/drm/tyr/reset.rs new file mode 100644 index 000000000000..a0eabf8ac6d0 --- /dev/null +++ b/drivers/gpu/drm/tyr/reset.rs @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT + +//! Provides asynchronous reset handling for the Tyr DRM driver via [`Rese= tHandle`]. +//! +//! [`ResetHandle::schedule`] runs reset work on a dedicated ordered +//! [`ScopedQueue`] and avoids duplicate pending reset requests. +//! +//! # High-level Execution Flow +//! +//! ```text +//! +------+ schedule() +---------+ reset_work() +------------+ +//! | Idle |------------->| Pending |--------------->| InProgress | +//! +------+ +---------+ +------------+ +//! ^ | +//! | work complete | +//! +---------------------------------------------+ +//! +//! Teardown transitions any state to ShuttingDown, then drains pending and +//! running work. +//! ``` + +mod hw_gate; + +use hw_gate::HwGate; + +use kernel::{ + device::{ + Bound, + Device, // + }, + io::{ + poll, + Io, // + }, + platform, + prelude::*, + sync::{ + atomic::{ + Atomic, + AtomicType, + Full, + Release, // + }, + Arc, + ArcBorrow, // + }, + time, + workqueue::{ + self, + ScopedQueue, + Work, // + }, +}; + +use crate::{ + driver::IoMem, + gpu, + regs::gpu_control::*, // +}; + +/// Lifecycle state of the reset worker. +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(i32)] +enum ResetState { + /// Hardware is available and no reset request exists. + Idle =3D 0, + /// Reset work item is queued and waiting to be claimed by the worker. + Pending =3D 1, + /// Worker has claimed the request and is resetting hardware. + InProgress =3D 2, + /// Teardown has started and no new reset request may start. + ShuttingDown =3D 3, +} + +// SAFETY: `ResetState` and `i32` have the same size and alignment, and are +// round-trip transmutable. +unsafe impl AtomicType for ResetState { + type Repr =3D i32; +} + +/// Internal reset orchestrator that owns the state, [`HwGate`], and work = item. +#[pin_data] +struct Controller<'bound> { + /// Parent platform device. + pdev: &'bound platform::Device, + /// Mapped register space needed for reset operations. + iomem: Arc>, + /// State shared by reset schedulers and the worker. + state: Atomic, + /// Drains reset-sensitive hardware accesses before a reset. + #[pin] + hw: HwGate, + /// Work item backing async reset processing. + #[pin] + work: Work>, +} + +kernel::impl_has_work! { + impl{'bound} HasWork> for Controller<'bound> { self= .work } +} + +impl<'bound> workqueue::WorkItem for Controller<'bound> { + type Pointer =3D Arc; + + fn run(this: Arc) { + this.reset_work(); + } +} + +impl<'bound> Controller<'bound> { + /// Creates an [`Arc`] ready for use. + fn new( + pdev: &'bound platform::Device, + iomem: ArcBorrow<'_, IoMem<'bound>>, + ) -> Result> { + Arc::pin_init( + try_pin_init!(Self { + pdev, + iomem: iomem.into(), + state: Atomic::new(ResetState::Idle), + hw <- HwGate::new(), + work <- kernel::new_work!("tyr::reset"), + }), + GFP_KERNEL, + ) + } + + /// Attempts to transition the reset state from `from` to `to`. + #[inline] + fn try_transition(&self, from: ResetState, to: ResetState) -> bool { + self.state.cmpxchg(from, to, Full).is_ok() + } + + /// Processes one scheduled reset request. + /// + /// If the pending reset cannot be claimed, the worker returns immedia= tely. + /// + /// It first claims [`ResetState::Pending`], then waits for earlier ha= rdware + /// accesses to complete before issuing the reset and returning the wo= rker + /// state to [`ResetState::Idle`]. + /// + /// Panthor reference: + /// - drivers/gpu/drm/panthor/panthor_device.c::panthor_device_reset_w= ork() + fn reset_work(self: &Arc) { + if !self.try_transition(ResetState::Pending, ResetState::InProgres= s) { + return; + } + + dev_info!(self.pdev, "Starting GPU reset.\n"); + + // Wait for current hardware accesses to finish before resetting. + let reset_guard =3D self.hw.close(); + let reset_result =3D run_reset(self.pdev.as_ref(), &self.iomem); + drop(reset_guard); + + if let Err(e) =3D reset_result { + dev_err!(self.pdev, "GPU reset failed: {:?}\n", e); + + // TODO: Unplug the GPU. + // There is no API for unplugging the GPU and this is unreacha= ble + // for now since there are no hardware users for reset API. + } else { + dev_info!(self.pdev, "GPU reset completed.\n"); + } + + let _ =3D self.try_transition(ResetState::InProgress, ResetState::= Idle); + } +} + +/// User-facing handle for scheduling resets. +/// +/// Dropping the handle drains any queued or in-flight reset work before t= he +/// [`ScopedQueue`] and the clock and regulator resources are released. +pub(crate) struct ResetHandle<'bound> { + controller: Arc>, + wq: ScopedQueue<'bound>, +} + +impl<'bound> ResetHandle<'bound> { + /// Creates [`ResetHandle`]. + /// + /// # Safety + /// + /// The returned handle must not be leaked or otherwise prevented from + /// running [`Drop`], since it owns work that may borrow from `'bound`. + pub(crate) unsafe fn new( + pdev: &'bound platform::Device, + iomem: ArcBorrow<'_, IoMem<'bound>>, + ) -> Result { + Ok(Self { + controller: Controller::new(pdev, iomem)?, + // SAFETY: The caller guarantees the handle is dropped. + wq: unsafe { ScopedQueue::new(c"tyr-reset-wq")? }, + }) + } + + /// Schedules a GPU reset on the dedicated workqueue. + /// + /// If a reset is already pending or in progress the call is a no-op. + #[expect(dead_code)] + pub(crate) fn schedule(&self) { + // TODO: Similar to `panthor_device_schedule_reset()` in Panthor, = add a + // power management check once Tyr supports it. + + if self + .controller + .try_transition(ResetState::Idle, ResetState::Pending) + { + let _ =3D self.wq.enqueue(self.controller.clone()); + } + } +} + +impl<'bound> Drop for ResetHandle<'bound> { + fn drop(&mut self) { + // Stop new reset requests before draining queued/running work. + self.controller + .state + .store(ResetState::ShuttingDown, Release); + + // Not required for safety because `wq` will drain on drop, but ke= ep + // cancellation of `controller.work` explicit before fields are dr= opped. + let _ =3D self.controller.work.cancel_sync(); + } +} + +/// Issues a soft reset command and waits for reset-complete IRQ status. +fn issue_soft_reset<'bound>(dev: &'bound Device, io: &IoMem<'bound>= ) -> Result { + // Clear any stale reset-complete IRQ state before issuing a new soft = reset. + io.write_reg(GPU_IRQ_CLEAR::zeroed().with_reset_completed(true)); + + io.write_reg(GPU_COMMAND::reset(ResetMode::SoftReset)); + + poll::read_poll_timeout( + || Ok(io.read(GPU_IRQ_RAWSTAT)), + |status| status.reset_completed(), + time::Delta::from_millis(1), + time::Delta::from_millis(100), + ) + .inspect_err(|_| dev_err!(dev, "GPU reset timed out."))?; + + Ok(()) +} + +/// Runs one synchronous GPU reset pass. +/// +/// Its visibility is `pub(super)` only so the probe path can run an +/// initial reset; it is not part of this module's public API. +/// +/// On success, the GPU is left in a state suitable for reinitialization. +/// +/// The sequence is as follows: +/// - Trigger a GPU soft reset. +/// - Wait for the reset-complete IRQ status. +/// - Power L2 back on. +pub(super) fn run_reset<'bound>(dev: &'bound Device, iomem: &IoMem<= 'bound>) -> Result { + issue_soft_reset(dev, iomem)?; + gpu::l2_power_on(dev, iomem)?; + Ok(()) +} diff --git a/drivers/gpu/drm/tyr/reset/hw_gate.rs b/drivers/gpu/drm/tyr/res= et/hw_gate.rs new file mode 100644 index 000000000000..9c5708fb911d --- /dev/null +++ b/drivers/gpu/drm/tyr/reset/hw_gate.rs @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT + +//! Hardware-access gate for the GPU reset cycle. +//! +//! [`HwGate`] uses a mutex and [`Srcu`] to coordinate reset-sensitive har= dware +//! access with reset. Readers hold the mutex while entering SRCU, then re= lease +//! it before accessing hardware. The reset worker holds the mutex while w= aiting +//! for admitted readers and resetting hardware. + +use kernel::{ + prelude::*, + sync::{ + new_mutex, + srcu, + Mutex, + MutexGuard, + Srcu, // + }, +}; + +/// A gate that coordinates hardware access with the reset worker. +#[pin_data] +pub(super) struct HwGate { + /// Admits readers and is held exclusively while the reset worker owns= the + /// hardware. + #[pin] + gate_lock: Mutex<()>, + /// Drains readers that entered before the reset worker acquired `gate= _lock`. + #[pin] + srcu: Srcu, +} + +impl HwGate { + /// Creates an open hardware-access gate. + pub(super) fn new() -> impl PinInit { + try_pin_init!(Self { + gate_lock <- new_mutex!(()), + srcu <- kernel::new_srcu!(), + }) + } + + /// Enters a reset-sensitive hardware-access section. + #[expect(dead_code)] + fn read(&self) -> HwReadGuard<'_> { + let gate_lock =3D self.gate_lock.lock(); + let srcu =3D self.srcu.read_lock(); + drop(gate_lock); + + HwReadGuard { _srcu: srcu } + } + + /// Stops new readers and drains admitted readers for the reset worker. + /// + /// Callers must serialize write-side access. The reset controller's s= tate + /// machine provides that serialization. + pub(super) fn close(&self) -> HwWriteGuard<'_> { + let gate_lock =3D self.gate_lock.lock(); + + // Holding `gate_lock` prevents new readers from entering SRCU. Re= aders + // admitted before us are enrolled, so wait for their read-side wo= rk. + self.srcu.synchronize(); + + HwWriteGuard { + _gate_lock: gate_lock, + } + } +} + +/// Read section that keeps the reset worker off the hardware while held. +#[must_use =3D "the gate is released when the guard is dropped"] +struct HwReadGuard<'a> { + _srcu: srcu::Guard<'a>, +} + +/// Closed [`HwGate`] held by the reset worker. Reopens on drop. +#[must_use =3D "the gate stays closed until the guard is dropped"] +pub(super) struct HwWriteGuard<'a> { + _gate_lock: MutexGuard<'a, ()>, +} diff --git a/drivers/gpu/drm/tyr/tyr.rs b/drivers/gpu/drm/tyr/tyr.rs index 3f6fe5fbeb0f..63873628c843 100644 --- a/drivers/gpu/drm/tyr/tyr.rs +++ b/drivers/gpu/drm/tyr/tyr.rs @@ -14,6 +14,7 @@ mod gpu; mod mmu; mod regs; +mod reset; mod slot; mod vm; mod wait; --=20 2.51.2