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[86.96.6.50]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49981b62894sm41936365e9.13.2026.08.13.00.49.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2026 00:50:00 -0700 (PDT) From: Abid Ali Date: Thu, 13 Aug 2026 07:49:27 +0000 Subject: [PATCH v3 1/3] net: stmmac: enable MAC rx/tx after DMA start Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-stmmac-rx-fifo-block-v3-1-738acbee55d9@gmail.com> References: <20260813-stmmac-rx-fifo-block-v3-0-738acbee55d9@gmail.com> In-Reply-To: <20260813-stmmac-rx-fifo-block-v3-0-738acbee55d9@gmail.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Russell King , Qingfang Deng Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Abid Ali X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786607395; l=2198; i=dev.taqnialabs@gmail.com; s=20260425; h=from:subject:message-id; bh=oLJsS8Rav70RicuKxT5K0qmNv7lDA+PehXT5PqdKKNQ=; b=hJo3R0HUUrrbix8X3VwmEqUsVK8fR1LNfIWebwZ0c3IPfe14IWCevuyQu7bdSHoIuNgdeoAdz /kxuNoZ6eCFCtBKcosxxy1Ff0Od+wPN6JCggYGfYdAnse5WAN1dZBUD X-Developer-Key: i=dev.taqnialabs@gmail.com; a=ed25519; pk=4Syx51HH/MOySSUpi79M2ToLOdwt1yiNb338eKZBJNk= When the MAC receiver is enabled before the DMA channels are started, incoming frames fill the MTL FIFO with no DMA engine to drain it. If the PHY/Switch is already up at this point, and there is inflow of packets towards EMAC, the per-queue FIFO overflows within this window. Once the FIFO is full, the MTL read controller goes idle and never retries delivery even if the DMA comes alive later on. This behaviour happens due to enabling the MAC RX path before the DMA setup is ready, and any delay between these events increases the chances of blocking the rx path permanently. The EMAC should only accept packets after the DMAs are enabled. Signed-off-by: Abid Ali --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index 3591755ea..1213cb216 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3692,9 +3692,6 @@ static int stmmac_hw_setup(struct net_device *dev) priv->hw->rx_csum =3D 0; } =20 - /* Enable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, true); - /* Set the HW DMA mode and the COE */ stmmac_dma_operation_mode(priv); =20 @@ -3750,6 +3747,9 @@ static int stmmac_hw_setup(struct net_device *dev) /* Start the ball rolling... */ stmmac_start_all_dma(priv); =20 + /* Enable the MAC Rx/Tx */ + stmmac_mac_set(priv, priv->ioaddr, true); + phylink_rx_clk_stop_block(priv->phylink); stmmac_set_hw_vlan_mode(priv, priv->hw); phylink_rx_clk_stop_unblock(priv->phylink); @@ -7189,12 +7189,12 @@ int stmmac_xdp_open(struct net_device *dev) hrtimer_setup(&tx_q->txtimer, stmmac_tx_timer, CLOCK_MONOTONIC, HRTIMER_= MODE_REL); } =20 - /* Enable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, true); - /* Start Rx & Tx DMA Channels */ stmmac_start_all_dma(priv); =20 + /* Enable the MAC Rx/Tx */ + stmmac_mac_set(priv, priv->ioaddr, true); + ret =3D stmmac_request_irq(dev); if (ret) goto irq_error; --=20 2.43.0 From nobody Tue Sep 29 02:33:47 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4A43413D62 for ; Thu, 13 Aug 2026 07:50:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786607411; cv=none; b=XqOOoKTjPaTf9y4RwkI+9AzcWo4d44OTydJ/XhNXLjDkqfcNWBkO5gPKWpcU68Wvhg+Hp+0nYtVngBaqjcEyBbnMuLKBwc8AYOzyoR2ZCFE+O/w/CKTIlAWbT3eMHYfcr18C9vTa4AIY4hHgkR3qGMKr2ZA9i0oGneaKupaI3AI= ARC-Message-Signature: i=1; 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[86.96.6.50]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49981b62894sm41936365e9.13.2026.08.13.00.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2026 00:50:03 -0700 (PDT) From: Abid Ali Date: Thu, 13 Aug 2026 07:49:28 +0000 Subject: [PATCH v3 2/3] net: stmmac: xgmac: tear the datapath down in the documented order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-stmmac-rx-fifo-block-v3-2-738acbee55d9@gmail.com> References: <20260813-stmmac-rx-fifo-block-v3-0-738acbee55d9@gmail.com> In-Reply-To: <20260813-stmmac-rx-fifo-block-v3-0-738acbee55d9@gmail.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Russell King , Qingfang Deng Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Abid Ali X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786607395; l=12201; i=dev.taqnialabs@gmail.com; s=20260425; h=from:subject:message-id; bh=ESYZxOpjwQJFQGrvK/0fmHBJZ2ApGs1FgMq+WLSbmd0=; b=tYbzLeG7G/0yhXYb4VLzTrgDosPst99sgrGbG0SCj1jk3diHOZTIEGg+1zaCREpzhritq7zyu KjdcUq0eTq6AtNre+gBqvZoBZZAn3/TSI4upF6Nc4yHhHozyitZmNoc X-Developer-Key: i=dev.taqnialabs@gmail.com; a=ed25519; pk=4Syx51HH/MOySSUpi79M2ToLOdwt1yiNb338eKZBJNk= The driver stops all DMA channels at once and only some paths disable the MAC afterwards. The databook requires the reverse order with a wait at each stage, otherwise a frame can be left stranded in the MTL FIFOs and reappear as corruption on the next bring-up. Add four optional DMA callbacks and drive them from a new stmmac_datapath_teardown(): 1) stop the Tx DMA channels, wait for stopped 2) wait for the MTL Tx queues to drain into the MAC 3) disable the MAC Tx and Rx 4) wait for the MTL Rx queues to drain into the Rx DMA 5) stop the Rx DMA channels, wait for stopped These are implemented for the XGMAC variant. TPS and RPS are latched, so clear them in the matching start op. __stmmac_release() calls phylink_stop() after the teardown rather than before it, as mac_link_down() clears TE and RE and stages 2 and 4 cannot progress once the MAC is disabled. The Wake-on-LAN path in stmmac_suspend() keeps the old sequence, as it has to leave the receiver enabled. Signed-off-by: Abid Ali --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 8 +++ drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 82 ++++++++++++++++++= ++++ drivers/net/ethernet/stmicro/stmmac/hwif.h | 17 +++++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 73 ++++++++++++++----- 4 files changed, 164 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index 51943705a..2e3f26000 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -291,6 +291,10 @@ #define XGMAC_TTC GENMASK(6, 4) #define XGMAC_TXQEN GENMASK(3, 2) #define XGMAC_TSF BIT(1) +#define XGMAC_MTL_TXQ_DEBUG(x) (0x00001108 + (0x80 * (x))) +#define XGMAC_TXQSTS BIT(4) +#define XGMAC_TRCSTS GENMASK(2, 1) +#define XGMAC_TRCSTS_READ 0x1 #define XGMAC_MTL_TCx_ETS_CONTROL(x) (0x00001110 + (0x80 * (x))) #define XGMAC_MTL_TCx_QUANTUM_WEIGHT(x) (0x00001118 + (0x80 * (x))) #define XGMAC_MTL_TCx_SENDSLOPE(x) (0x0000111c + (0x80 * (x))) @@ -306,6 +310,9 @@ #define XGMAC_EHFC BIT(7) #define XGMAC_RSF BIT(5) #define XGMAC_RTC GENMASK(1, 0) +#define XGMAC_MTL_RXQ_DEBUG(x) (0x00001148 + (0x80 * (x))) +#define XGMAC_PRXQ GENMASK(29, 16) +#define XGMAC_RXQSTS GENMASK(5, 4) #define XGMAC_MTL_RXQ_FLOW_CONTROL(x) (0x00001150 + (0x80 * (x))) #define XGMAC_RFD GENMASK(31, 17) #define XGMAC_RFA GENMASK(15, 1) @@ -389,6 +396,7 @@ #define XGMAC_NIS BIT(15) #define XGMAC_AIS BIT(14) #define XGMAC_FBE BIT(12) +#define XGMAC_RPS BIT(8) #define XGMAC_RBU BIT(7) #define XGMAC_RI BIT(6) #define XGMAC_TBU BIT(2) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 03437f1cf..df3700a0d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -4,6 +4,7 @@ * stmmac XGMAC support. */ =20 +#include #include #include "stmmac.h" #include "dwxgmac2.h" @@ -251,6 +252,9 @@ static void dwxgmac2_dma_start_tx(struct stmmac_priv *p= riv, { u32 value; =20 + /* TPS is latched once set, so clear it on every Tx DMA start. */ + writel(XGMAC_TPS, ioaddr + XGMAC_DMA_CH_STATUS(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); value |=3D XGMAC_TXST; writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); @@ -279,6 +283,9 @@ static void dwxgmac2_dma_start_rx(struct stmmac_priv *p= riv, { u32 value; =20 + /* RPS is latched once set, so clear it on every Rx DMA start. */ + writel(XGMAC_RPS, ioaddr + XGMAC_DMA_CH_STATUS(chan)); + value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); value |=3D XGMAC_RXST; writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); @@ -582,6 +589,77 @@ static int dwxgmac2_enable_tbs(struct stmmac_priv *pri= v, void __iomem *ioaddr, return 0; } =20 +static int dwxgmac2_tx_dma_stopped(struct stmmac_priv *priv, + void __iomem *ioaddr, u32 chan) +{ + u32 value; + int ret; + + ret =3D readl_poll_timeout(ioaddr + XGMAC_DMA_CH_STATUS(chan), value, + value & XGMAC_TPS, 100, 10000); + if (ret) + netdev_warn(priv->dev, "Tx DMA channel %u stop timeout\n", + chan); + + return ret; +} + +static int dwxgmac2_tx_mtl_drain(struct stmmac_priv *priv, + void __iomem *ioaddr, u32 queue) +{ + u32 value; + int ret; + + /* Wait until the queue is empty and its read controller is no longer + * pulling a frame out towards the MAC. + */ + ret =3D readl_poll_timeout(ioaddr + XGMAC_MTL_TXQ_DEBUG(queue), value, + !(value & XGMAC_TXQSTS) && + FIELD_GET(XGMAC_TRCSTS, value) !=3D + XGMAC_TRCSTS_READ, + 100, 10000); + if (ret) + netdev_warn(priv->dev, "MTL Tx queue %u drain timeout\n", + queue); + + return ret; +} + +static int dwxgmac2_rx_mtl_drain(struct stmmac_priv *priv, + void __iomem *ioaddr, u32 queue) +{ + u32 value; + int ret; + + /* Wait until no packet is left in the queue and the queue reports + * itself empty. + */ + ret =3D readl_poll_timeout(ioaddr + XGMAC_MTL_RXQ_DEBUG(queue), value, + !FIELD_GET(XGMAC_PRXQ, value) && + !FIELD_GET(XGMAC_RXQSTS, value), + 100, 10000); + if (ret) + netdev_warn(priv->dev, "MTL Rx queue %u drain timeout\n", + queue); + + return ret; +} + +static int dwxgmac2_rx_dma_stopped(struct stmmac_priv *priv, + void __iomem *ioaddr, u32 chan) +{ + u32 value; + int ret; + + ret =3D readl_poll_timeout(ioaddr + XGMAC_DMA_CH_STATUS(chan), value, + value & XGMAC_RPS, 100, 10000); + if (ret) + netdev_warn(priv->dev, "Rx DMA channel %u stop timeout\n", + chan); + + return ret; +} + const struct stmmac_dma_ops dwxgmac210_dma_ops =3D { .reset =3D dwxgmac2_dma_reset, .init =3D dwxgmac2_dma_init, @@ -610,4 +688,8 @@ const struct stmmac_dma_ops dwxgmac210_dma_ops =3D { .set_bfsize =3D dwxgmac2_set_bfsize, .enable_sph =3D dwxgmac2_enable_sph, .enable_tbs =3D dwxgmac2_enable_tbs, + .tx_dma_stopped =3D dwxgmac2_tx_dma_stopped, + .tx_mtl_drain =3D dwxgmac2_tx_mtl_drain, + .rx_mtl_drain =3D dwxgmac2_rx_mtl_drain, + .rx_dma_stopped =3D dwxgmac2_rx_dma_stopped, }; diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ether= net/stmicro/stmmac/hwif.h index e6317b94f..23a6915ac 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h @@ -229,6 +229,15 @@ struct stmmac_dma_ops { bool en, u32 chan); int (*enable_tbs)(struct stmmac_priv *priv, void __iomem *ioaddr, bool en, u32 chan); + /* Ordered datapath teardown */ + int (*tx_dma_stopped)(struct stmmac_priv *priv, void __iomem *ioaddr, + u32 chan); + int (*tx_mtl_drain)(struct stmmac_priv *priv, void __iomem *ioaddr, + u32 queue); + int (*rx_mtl_drain)(struct stmmac_priv *priv, void __iomem *ioaddr, + u32 queue); + int (*rx_dma_stopped)(struct stmmac_priv *priv, void __iomem *ioaddr, + u32 chan); }; =20 #define stmmac_dma_init(__priv, __args...) \ @@ -289,6 +298,14 @@ struct stmmac_dma_ops { stmmac_do_void_callback(__priv, dma, enable_sph, __priv, __args) #define stmmac_enable_tbs(__priv, __args...) \ stmmac_do_callback(__priv, dma, enable_tbs, __priv, __args) +#define stmmac_tx_dma_stopped(__priv, __args...) \ + stmmac_do_callback(__priv, dma, tx_dma_stopped, __priv, __args) +#define stmmac_tx_mtl_drain(__priv, __args...) \ + stmmac_do_callback(__priv, dma, tx_mtl_drain, __priv, __args) +#define stmmac_rx_mtl_drain(__priv, __args...) \ + stmmac_do_callback(__priv, dma, rx_mtl_drain, __priv, __args) +#define stmmac_rx_dma_stopped(__priv, __args...) \ + stmmac_do_callback(__priv, dma, rx_dma_stopped, __priv, __args) =20 struct mac_device_info; struct net_device; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index 1213cb216..cc3a0ae0c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2569,6 +2569,52 @@ static void stmmac_stop_all_dma(struct stmmac_priv *= priv) stmmac_stop_tx_dma(priv, chan); } =20 +/** + * stmmac_datapath_teardown - ordered datapath teardown as per IP specific= ation + * @priv: driver private structure + * Description: + * When teardown ops are available, follow the databook ordered teardown + * sequence. + * Follows the legacy stop + MAC disable for variants without the feature. + */ +static void stmmac_datapath_teardown(struct stmmac_priv *priv) +{ + u32 rx_channels_count =3D priv->plat->rx_queues_to_use; + u32 tx_channels_count =3D priv->plat->tx_queues_to_use; + u32 chan; + + /* Stop all TX DMA channels */ + for (chan =3D 0; chan < tx_channels_count; chan++) + stmmac_stop_tx_dma(priv, chan); + + /* Wait for every TX DMA channel to report itself stopped */ + if (priv->hw->dma->tx_dma_stopped) + for (chan =3D 0; chan < tx_channels_count; chan++) + stmmac_tx_dma_stopped(priv, priv->ioaddr, chan); + + /* Wait for the MTL TX queues to finish pushing into the MAC */ + if (priv->hw->dma->tx_mtl_drain) + for (chan =3D 0; chan < tx_channels_count; chan++) + stmmac_tx_mtl_drain(priv, priv->ioaddr, chan); + + /* Disable the MAC TX and RX */ + stmmac_mac_set(priv, priv->ioaddr, false); + + /* Wait for the MTL RX queues to drain into the RX DMA */ + if (priv->hw->dma->rx_mtl_drain) + for (chan =3D 0; chan < rx_channels_count; chan++) + stmmac_rx_mtl_drain(priv, priv->ioaddr, chan); + + /* Stop all RX DMA channels */ + for (chan =3D 0; chan < rx_channels_count; chan++) + stmmac_stop_rx_dma(priv, chan); + + /* Wait for every RX DMA channel to report itself stopped */ + if (priv->hw->dma->rx_dma_stopped) + for (chan =3D 0; chan < rx_channels_count; chan++) + stmmac_rx_dma_stopped(priv, priv->ioaddr, chan); +} + /** * stmmac_dma_operation_mode - HW DMA operation mode * @priv: driver private structure @@ -4238,9 +4284,6 @@ static void __stmmac_release(struct net_device *dev) struct stmmac_priv *priv =3D netdev_priv(dev); u8 chan; =20 - /* Stop and disconnect the PHY */ - phylink_stop(priv->phylink); - stmmac_disable_all_queues(priv); =20 for (chan =3D 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -4251,8 +4294,11 @@ static void __stmmac_release(struct net_device *dev) /* Free the IRQ lines */ stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); =20 - /* Stop TX/RX DMA and clear the descriptors */ - stmmac_stop_all_dma(priv); + /* Has to run before mac_link_down() disables the MAC. */ + stmmac_datapath_teardown(priv); + + /* Stop and disconnect the PHY */ + phylink_stop(priv->phylink); =20 /* Release and free the Rx/Tx resources */ free_dma_desc_resources(priv, &priv->dma_conf); @@ -7109,15 +7155,12 @@ void stmmac_xdp_release(struct net_device *dev) /* Free the IRQ lines */ stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 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[86.96.6.50]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49981b62894sm41936365e9.13.2026.08.13.00.50.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2026 00:50:06 -0700 (PDT) From: Abid Ali Date: Thu, 13 Aug 2026 07:49:29 +0000 Subject: [PATCH v3 3/3] net: stmmac: xgmac: decouple the MAC Rx/Tx enables from the DMA ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-stmmac-rx-fifo-block-v3-3-738acbee55d9@gmail.com> References: <20260813-stmmac-rx-fifo-block-v3-0-738acbee55d9@gmail.com> In-Reply-To: <20260813-stmmac-rx-fifo-block-v3-0-738acbee55d9@gmail.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Russell King , Qingfang Deng Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Abid Ali X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786607395; l=2080; i=dev.taqnialabs@gmail.com; s=20260425; h=from:subject:message-id; bh=qmoEogHzK1kCxSGOvURN6pvKNeVEIJOqlmVkcFUU4k0=; b=rzTcfJD/m9BixYhCaji13vn4qbBwNoxVD/oaLnmlUzxXCfmODBqWnrSf5nTQM5ppGCPRJBZDt IApnsUdlaZ4Ai1SmPMzKD0imBYft7f/SrzI32pt1QtDnleeekqzlx/F X-Developer-Key: i=dev.taqnialabs@gmail.com; a=ed25519; pk=4Syx51HH/MOySSUpi79M2ToLOdwt1yiNb338eKZBJNk= The XGMAC per-channel DMA start and stop ops also raise and lower MAC_Tx_Configuration.TE and MAC_Rx_Configuration.RE. Those bits are global, not per channel, so an op meant to touch one channel reconfigures the whole MAC. stmmac_tx_err() restarting a single Tx channel clears TE and stops transmit on every other channel too. Signed-off-by: Abid Ali --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index df3700a0d..8e27bc58c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -258,10 +258,6 @@ static void dwxgmac2_dma_start_tx(struct stmmac_priv *= priv, value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); value |=3D XGMAC_TXST; writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); - - value =3D readl(ioaddr + XGMAC_TX_CONFIG); - value |=3D XGMAC_CONFIG_TE; - writel(value, ioaddr + XGMAC_TX_CONFIG); } =20 static void dwxgmac2_dma_stop_tx(struct stmmac_priv *priv, void __iomem *i= oaddr, @@ -272,10 +268,6 @@ static void dwxgmac2_dma_stop_tx(struct stmmac_priv *p= riv, void __iomem *ioaddr, value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); value &=3D ~XGMAC_TXST; writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); - - value =3D readl(ioaddr + XGMAC_TX_CONFIG); - value &=3D ~XGMAC_CONFIG_TE; - writel(value, ioaddr + XGMAC_TX_CONFIG); } =20 static void dwxgmac2_dma_start_rx(struct stmmac_priv *priv, @@ -289,10 +281,6 @@ static void dwxgmac2_dma_start_rx(struct stmmac_priv *= priv, value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); value |=3D XGMAC_RXST; writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); - - value =3D readl(ioaddr + XGMAC_RX_CONFIG); - value |=3D XGMAC_CONFIG_RE; - writel(value, ioaddr + XGMAC_RX_CONFIG); } =20 static void dwxgmac2_dma_stop_rx(struct stmmac_priv *priv, void __iomem *i= oaddr, --=20 2.43.0