From nobody Tue Sep 29 02:35:29 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0742943B4B5; Thu, 13 Aug 2026 08:00:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608050; cv=none; b=flLTFjvZ1FCEl5ijZ5ZCh9mWT11ZMGR7NlEmzFxKnXcPuxx+aEQ02JgVJPZYcoKl5xKDcyrdtYarOHOtsAiMPiD8UY9BVS8TWEUAdHYSVrzQ0YuIosJ3/Uw5gJkGGJs2Ln4PO/gKCmp8w0E1vYWd8rFfCOGbwvI0A0qTS/tmPH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608050; c=relaxed/simple; bh=yHdmiAPQ/DLjafhN20LGUa1e7GGdEALSGNUKB9tN76Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UGY8Wz6q9kGlw4NNyhBgqfWfgox2W4qFFKKnL777c001a+J5jDky8PsioRyid1UiUcSD6/+xqCvKuZONVCz+/O0MlWWU9Ma9pnqxRa0+lswmlU1N7mHvyxTggmS8vifbUxpoZlKuQKqYb7FORCSlE2UQd77yORb2S/8hVpEFDIc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Bb1b5FEI; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Bb1b5FEI" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id E407E4E411E3; Thu, 13 Aug 2026 08:00:40 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B08EA602B8; Thu, 13 Aug 2026 08:00:40 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5993711C4DA89; Thu, 13 Aug 2026 10:00:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1786608036; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Mj1W4Xh6Pt/T1x73ejVnasGPl6YiZcBTAo3uVZZ4NOU=; b=Bb1b5FEIZYGBz0uAdmssUhx5XFWabH/TcHg7k5nqBIOsBpbBvirf22v69K97X7FgdzXckZ flVYaixqOcd9U/A7oMi3o6gCvy1tTIg/d7araEKDUgVSYtUM1p8Upfe5j2saWulaJtfMPP 08ZWLAXw9Xa2GyB5JeBddmOJ/PwYXTSqqoNlxEXeWblu4HltHCt2TF8h5hKxj2zx8kWCC5 6ibH3Yti1balIiHyYxai+ClTjjR6mSObVqro60SRz109Ild5duXolQhFOoP7Aor/hibQ2V 0fqErLPm1hLZ/Kf/u/K5X8hjN3CwFZFRKwCKs7SyhpHGp0WuVcPwSzY85PWkHA== From: Miquel Raynal Date: Thu, 13 Aug 2026 10:00:21 +0200 Subject: [PATCH 1/5] spi: ma35d1-qspi: Remove redundant reset operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-perso-ma35d1-upstream-qspi-v1-1-b217b9870eb1@bootlin.com> References: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> In-Reply-To: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Mark Brown Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The bus width is always set before every operation, no need to reset it manually at the end of each transfer. Signed-off-by: Miquel Raynal --- drivers/spi/spi-ma35d1-qspi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/spi/spi-ma35d1-qspi.c b/drivers/spi/spi-ma35d1-qspi.c index 541d5d72484c..929546dbe38f 100644 --- a/drivers/spi/spi-ma35d1-qspi.c +++ b/drivers/spi/spi-ma35d1-qspi.c @@ -502,7 +502,6 @@ static int nuvoton_qspi_mem_exec_op(struct spi_mem *mem, } =20 out_deassert_cs: - nuvoton_qspi_set_bus_width(qspi, 1, SPI_MEM_DATA_IN); nuvoton_qspi_mem_set_cs(spi, false); =20 return ret; @@ -556,7 +555,6 @@ static int nuvoton_qspi_transfer_one(struct spi_control= ler *ctlr, nuvoton_qspi_set_bus_width(qspi, buswidth, dir); ret =3D nuvoton_qspi_txrx(qspi, xfer->tx_buf, xfer->rx_buf, xfer->len); - nuvoton_qspi_set_bus_width(qspi, 1, SPI_MEM_DATA_IN); =20 return ret; } --=20 2.54.0 From nobody Tue Sep 29 02:35:29 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6355C43B6E2; Thu, 13 Aug 2026 08:00:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608054; cv=none; b=fWz9fKEcGt+nlgSOjitVXdOpZuqt0YEvs+5DBoWbDgFQ4hB868P4vupUgcb5iXc8VJFW7k2wvf1WW3iA5zlHvVYLMWDrqm5qwoj41TApBJjHXdyd5hczjnLBH3bdnqUP58aOWbXLXOjT2cIshUC736kZb01kqZkn0vQ+7V8/asg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608054; c=relaxed/simple; bh=5r10Z5YAkTY7zx2eXhOuwocd6nGgofKPRvCnBmKlQ0M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=t06M84AzKynQSXXF1q0+eUalYF6HRx4n8hPDokxRUr+9EXv+9vz2XQ8Xe0TELCM795utmXIjKKAcIB6yA6bovrXXUNBljGBhkILPI4yZ7dFi8Kgq8/394wmZYEhtjaHIdQjgQKv0R6kFK8qWIbUtcHOVn/BGOAzKElaw3RGYDUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ib4VW7KY; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ib4VW7KY" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 41D611A15EF; Thu, 13 Aug 2026 08:00:46 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 157C1602B8; Thu, 13 Aug 2026 08:00:46 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 883CC11C4DA87; Thu, 13 Aug 2026 10:00:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1786608041; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=N6G3NRNZL8dSdQJqaXUc7ZO7iQogO5DBd4K7lMUQSdA=; b=ib4VW7KYU46KzTXHYDafEspQZM4S0cqhD1JqOA6kHiAMR1t96rkndmvEXnUyFyWu62pRvw lqseLjWi8grmQtjTm/FNTVZUj3sehmAkn1UxOUrSTFRtUtSg82UETwqqmLLt7lFmMUzzeT nVeHPxkpNTBgJo69u9jNbGNpCqnGUrFNfNEWqJlPySsfcixqd7ezWFjkI6HeA85W3WtkFU OwLkhSfrxUpptGVFGBuf0v7Z5QcsoVbVe5mqBZXHKTWxqmjTekIp5gsEG1KDdrpS6qrH/x 4N2lq6qx6jdcW9mgusEZpG3pwMjuIqYZhQM3F7gbxyy1u0p+v8JQ39er7cy1Qg== From: Miquel Raynal Date: Thu, 13 Aug 2026 10:00:22 +0200 Subject: [PATCH 2/5] spi: ma35d1-qspi: Move speed setting to bus configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-perso-ma35d1-upstream-qspi-v1-2-b217b9870eb1@bootlin.com> References: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> In-Reply-To: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Mark Brown Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The speed setting is wrongly placed inside the "setup transfer" helper, since the bus configuration may require the speed to be correct. Indeed, DTR mode (not yet available) divides by 2 the bus clock when enabled. As a result, to remain at a constant clock speed (and improve the data rate), we must double the bus clock when enabling DTR. In order to prepare for this change, move all the bus configuration required for each step of the operation inside a unique helper called nuvoton_qspi_configure_bus(). Signed-off-by: Miquel Raynal --- drivers/spi/spi-ma35d1-qspi.c | 69 +++++++++++++++++++++++++++------------= ---- 1 file changed, 44 insertions(+), 25 deletions(-) diff --git a/drivers/spi/spi-ma35d1-qspi.c b/drivers/spi/spi-ma35d1-qspi.c index 929546dbe38f..b4fd0ab4bd31 100644 --- a/drivers/spi/spi-ma35d1-qspi.c +++ b/drivers/spi/spi-ma35d1-qspi.c @@ -131,11 +131,15 @@ static int nuvoton_qspi_reset_fifo(struct nuvoton_qsp= i *qspi) 1, NUVOTON_QSPI_TIMEOUT_US); } =20 -static int nuvoton_qspi_set_speed(struct nuvoton_qspi *qspi, u32 speed_hz) +static int nuvoton_qspi_set_speed(struct spi_device *spi, u32 speed_hz) { + struct nuvoton_qspi *qspi =3D spi_controller_get_devdata(spi->controller); unsigned long clk_rate; u32 div; =20 + if (!speed_hz) + speed_hz =3D spi->max_speed_hz; + if (!speed_hz) return -EINVAL; =20 @@ -174,24 +178,16 @@ static int nuvoton_qspi_set_bits_per_word(struct nuvo= ton_qspi *qspi, u8 bpw) return 0; } =20 -static int nuvoton_qspi_setup_transfer(struct spi_device *spi, - u32 speed_hz, u8 bpw) +static int nuvoton_qspi_setup_transfer(struct spi_device *spi, u8 bpw) { struct nuvoton_qspi *qspi =3D spi_controller_get_devdata(spi->controller); u32 mode =3D spi->mode & SPI_MODE_X_MASK; u32 ctl =3D 0; int ret; =20 - if (!speed_hz) - speed_hz =3D spi->max_speed_hz; - if (!bpw) bpw =3D NUVOTON_QSPI_DEFAULT_BPW; =20 - ret =3D nuvoton_qspi_set_speed(qspi, speed_hz); - if (ret) - return ret; - ret =3D nuvoton_qspi_set_bits_per_word(qspi, bpw); if (ret) return ret; @@ -216,11 +212,18 @@ static int nuvoton_qspi_setup_transfer(struct spi_dev= ice *spi, return 0; } =20 -static void nuvoton_qspi_set_bus_width(struct nuvoton_qspi *qspi, - unsigned int buswidth, - enum spi_mem_data_dir dir) +static int nuvoton_qspi_configure_bus(struct spi_device *spi, + unsigned int buswidth, + enum spi_mem_data_dir dir, + u32 speed_hz) { + struct nuvoton_qspi *qspi =3D spi_controller_get_devdata(spi->controller); u32 ctl =3D 0; + int ret; + + ret =3D nuvoton_qspi_set_speed(spi, speed_hz); + if (ret) + return ret; =20 if (buswidth =3D=3D 4) ctl |=3D NUVOTON_QSPI_CTL_QUADIOEN_MASK; @@ -234,6 +237,8 @@ static void nuvoton_qspi_set_bus_width(struct nuvoton_q= spi *qspi, NUVOTON_QSPI_CTL_QUADIOEN_MASK | NUVOTON_QSPI_CTL_DUALIOEN_MASK | NUVOTON_QSPI_CTL_DATDIR_MASK, ctl); + + return 0; } =20 static u32 nuvoton_qspi_tx_byte(const void *txbuf, unsigned int idx) @@ -459,14 +464,17 @@ static int nuvoton_qspi_mem_exec_op(struct spi_mem *m= em, int ret; int i; =20 - ret =3D nuvoton_qspi_setup_transfer(spi, op->max_freq, - NUVOTON_QSPI_DEFAULT_BPW); + ret =3D nuvoton_qspi_setup_transfer(spi, NUVOTON_QSPI_DEFAULT_BPW); if (ret) return ret; =20 nuvoton_qspi_mem_set_cs(spi, true); =20 - nuvoton_qspi_set_bus_width(qspi, op->cmd.buswidth, SPI_MEM_DATA_OUT); + ret =3D nuvoton_qspi_configure_bus(spi, op->cmd.buswidth, SPI_MEM_DATA_OU= T, + op->max_freq); + if (ret) + goto out_deassert_cs; + ret =3D nuvoton_qspi_txrx(qspi, &opcode, NULL, 1); if (ret) goto out_deassert_cs; @@ -475,24 +483,33 @@ static int nuvoton_qspi_mem_exec_op(struct spi_mem *m= em, for (i =3D 0; i < op->addr.nbytes; i++) addr[i] =3D op->addr.val >> (8 * (op->addr.nbytes - i - 1)); =20 - nuvoton_qspi_set_bus_width(qspi, op->addr.buswidth, - SPI_MEM_DATA_OUT); + ret =3D nuvoton_qspi_configure_bus(spi, op->addr.buswidth, SPI_MEM_DATA_= OUT, + op->max_freq); + if (ret) + goto out_deassert_cs; + ret =3D nuvoton_qspi_txrx(qspi, addr, NULL, op->addr.nbytes); if (ret) goto out_deassert_cs; } =20 if (op->dummy.nbytes) { - nuvoton_qspi_set_bus_width(qspi, op->dummy.buswidth, - SPI_MEM_DATA_OUT); + ret =3D nuvoton_qspi_configure_bus(spi, op->dummy.buswidth, SPI_MEM_DATA= _OUT, + op->max_freq); + if (ret) + goto out_deassert_cs; + ret =3D nuvoton_qspi_txrx(qspi, NULL, NULL, op->dummy.nbytes); if (ret) goto out_deassert_cs; } =20 if (op->data.nbytes) { - nuvoton_qspi_set_bus_width(qspi, op->data.buswidth, - op->data.dir); + ret =3D nuvoton_qspi_configure_bus(spi, op->data.buswidth, op->data.dir, + op->max_freq); + if (ret) + goto out_deassert_cs; + ret =3D nuvoton_qspi_txrx(qspi, op->data.dir =3D=3D SPI_MEM_DATA_OUT ? op->data.buf.out : NULL, @@ -528,8 +545,7 @@ static int nuvoton_qspi_transfer_one(struct spi_control= ler *ctlr, unsigned int buswidth =3D 1; int ret; =20 - ret =3D nuvoton_qspi_setup_transfer(spi, xfer->speed_hz, - xfer->bits_per_word); + ret =3D nuvoton_qspi_setup_transfer(spi, xfer->bits_per_word); if (ret) return ret; =20 @@ -552,7 +568,10 @@ static int nuvoton_qspi_transfer_one(struct spi_contro= ller *ctlr, buswidth =3D 2; } =20 - nuvoton_qspi_set_bus_width(qspi, buswidth, dir); + ret =3D nuvoton_qspi_configure_bus(spi, buswidth, dir, xfer->speed_hz); + if (ret) + return ret; + ret =3D nuvoton_qspi_txrx(qspi, xfer->tx_buf, xfer->rx_buf, xfer->len); =20 --=20 2.54.0 From nobody Tue Sep 29 02:35:29 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6662643BDB5; Thu, 13 Aug 2026 08:00:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608058; cv=none; b=N1qOU3xaYovd7CwuJ6PDaCMvAVCouCTwVm6cle3EF4hZmTo0vQmjtI7giHQaBpL5cZWrrw7S8G3nqNefdchvJXt+9CCqFiqQbwgO7cVw1eDinUjTefvl9PKOCaT4PyH3DsZb0eOSf7f8aaBHc5FNNJTfSRSElNt0xLb8lSDZ2bo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608058; c=relaxed/simple; bh=Y6GyRy+pYwVlujyYu458ZLcw0pidccVC75fZb2hUsC8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kre9aOjHAeRgqK3cb/H7oLHuKvmYCKOi/eWixy3YIU6X2hG+5rdA8yfSXPcdgdawNS2H3wjP50kOfzUpzQzuYbgahTCin1yGwQCnAzuIRxlf9iunuYQ9yaMlYOIHbjuPtk4O1nSVQ7AioYQ4kAZUppPWlhc/IDycFwxrUOzRv8M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=beVUD+L0; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="beVUD+L0" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 896DC1A15F0; Thu, 13 Aug 2026 08:00:51 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5E70B602B8; Thu, 13 Aug 2026 08:00:51 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EAB3011C4DA82; Thu, 13 Aug 2026 10:00:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1786608046; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=V50cHfNVXO7uf9mb9fH4B1oU3NTB/2Ru1jMT/LE3OM0=; b=beVUD+L0htQxAeOyD+aibag5BufjMqNXsaV6iGVbTrUpPVr6IVnDzn+UYLD7F8JtfghM1g 2WtZo5RGM6ypbRBvAbFdgMHU7mcSDUFT2/koNehb3kRcmD+MIC0/9xJqA4H6Y3ZGKM8aio AmtdZ7rSAUjPy2GfF83Y+1/UC1oY4eeKHV1EiVPeGSBoBsrfLh/ob7KtbqP9fsjki5tRLe kkKLRcNAslbvtio0MDy7ZBw16Q4U+hbanuOxtJDfYnVMYIoEUYknDCP5BXzcYy3yC3izzN HpF7ya91N02K9H2yIlxkrbfWYkcUzLpRGRzGBINuv3mPXerdEcoQPcnN/aPK9Q== From: Miquel Raynal Date: Thu, 13 Aug 2026 10:00:23 +0200 Subject: [PATCH 3/5] spi: ma35d1-qspi: Allow several command bytes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-perso-ma35d1-upstream-qspi-v1-3-b217b9870eb1@bootlin.com> References: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> In-Reply-To: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Mark Brown Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The controller is capable of sending several bytes for the command, it does not even know this is a command. Just mimic the address steps here to allow double byte commands, which may be needed for DTR support. Signed-off-by: Miquel Raynal --- drivers/spi/spi-ma35d1-qspi.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-ma35d1-qspi.c b/drivers/spi/spi-ma35d1-qspi.c index b4fd0ab4bd31..027a9433f2b1 100644 --- a/drivers/spi/spi-ma35d1-qspi.c +++ b/drivers/spi/spi-ma35d1-qspi.c @@ -395,9 +395,6 @@ static bool nuvoton_qspi_mem_supports_op(struct spi_mem= *mem, op->dummy.buswidth > 4 || op->data.buswidth > 4) return false; =20 - if (op->cmd.nbytes !=3D 1) - return false; - if (op->addr.nbytes > 4) return false; =20 @@ -459,8 +456,7 @@ static int nuvoton_qspi_mem_exec_op(struct spi_mem *mem, { struct spi_device *spi =3D mem->spi; struct nuvoton_qspi *qspi =3D spi_controller_get_devdata(spi->controller); - u8 opcode =3D op->cmd.opcode; - u8 addr[4]; + u8 cmd[2], addr[4]; int ret; int i; =20 @@ -470,12 +466,15 @@ static int nuvoton_qspi_mem_exec_op(struct spi_mem *m= em, =20 nuvoton_qspi_mem_set_cs(spi, true); =20 + for (i =3D 0; i < op->cmd.nbytes; i++) + cmd[i] =3D op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1)); + ret =3D nuvoton_qspi_configure_bus(spi, op->cmd.buswidth, SPI_MEM_DATA_OU= T, op->max_freq); if (ret) goto out_deassert_cs; =20 - ret =3D nuvoton_qspi_txrx(qspi, &opcode, NULL, 1); + ret =3D nuvoton_qspi_txrx(qspi, cmd, NULL, op->cmd.nbytes); if (ret) goto out_deassert_cs; =20 --=20 2.54.0 From nobody Tue Sep 29 02:35:29 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73D1F43B49F for ; Thu, 13 Aug 2026 08:01:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608064; cv=none; b=jJZZFm6jRURhftfp6AZl3V/bKXY23ZAbvdIW3JxZMBpT5lEfewy+1QtV5qDQgxavUEUs/hUbdRhjMabZCeS3vGu9oIsjshL7Ost7JjF/fVSwilffWxZpqN1ZWFDx1HXu2Q9FE+vj3Wb1SUka78Hvb0NeMmymkIrXS6zSinzVYPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608064; c=relaxed/simple; bh=mnQ46co/9iuYUM/Yd5Z6+Uo7JC6kFiKYVYth8cN9zPw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MyDcRVDdPY7m5653IO1UUV/+5/iWc+ADBWulbOianaz3p7k87ny1S7nEQDecJj48BlUBY4IrBbiuX13HJ5ixvGfJeoLqUe+kZe8FKIe7AxY3CkyULElor+iMoVtj2tQm+VgxjUcwjsN4/AE8rkKI/ZJwIiSeUnRbyPxLkFlvjXs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=bwAboqmH; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="bwAboqmH" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 0682E4E411E0; Thu, 13 Aug 2026 08:00:57 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CF57F602B8; Thu, 13 Aug 2026 08:00:56 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3CFA211C4DA93; Thu, 13 Aug 2026 10:00:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1786608052; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=xx36mDPNFgstttg20qSUlurhDbVJ78nN9n4MYm6WP0k=; b=bwAboqmHaigF17vxw6fNyWDm2Xf5/hEIncR+VdBQqhYrOUVg+J3C8/87O81nBcLVwLjxGr sFJYDpBjyD2Qmk/IUgj9YZvs7NeCTzIHxZ/7zNgbiqNOvDkGaeQh83OvwL+RmKUbvWcKjv zUEL+XQt72bPRJ0SalMB9LGv3N+blRnHwv7rz+tDZ+985cySpRdhmXpimW89ce25FPjA2Q pblHlQr3yl4yA4Bu5FFKjw+lQTypgxHAuSQCoUSQDdsuNGehu8KwX76CGAYgyIsqwnTVR6 rFlEWgmy/ZJ0aR2pvPHHYGGygLf7BnXYqoNCxyIkeVU00KV5FHqWq4zAWcxwZQ== From: Miquel Raynal Date: Thu, 13 Aug 2026 10:00:24 +0200 Subject: [PATCH 4/5] spi: ma35d1-qspi: Add DTR support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-perso-ma35d1-upstream-qspi-v1-4-b217b9870eb1@bootlin.com> References: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> In-Reply-To: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Mark Brown Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The controller has DTR support, a bit must be set for it. The behaviour is interesting though, as the speed won't improve when enabled. This is because there seems to be an internal divisor (/2) which keeps the rate equal when DTR is enabled. As a result, this commit also doubles the target bus speed, which in practice does not happen. This way, there is a real gain: Before: $ flash_speed /dev/mtd0 -dc10 eraseblock write speed is 1000 KiB/s [...] eraseblock read speed is 1199 KiB/s [...] After: $ flash_speed /dev/mtd0 -dc10 eraseblock write speed is 985 KiB/s [...] eraseblock read speed is 1540 KiB/s [...] Signed-off-by: Miquel Raynal --- drivers/spi/spi-ma35d1-qspi.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-ma35d1-qspi.c b/drivers/spi/spi-ma35d1-qspi.c index 027a9433f2b1..9965a11573d8 100644 --- a/drivers/spi/spi-ma35d1-qspi.c +++ b/drivers/spi/spi-ma35d1-qspi.c @@ -31,6 +31,7 @@ #define NUVOTON_QSPI_RX_OFFSET 0x30 /* Data Receive Register, RO */ =20 /* QSPI Control Register bit masks */ +#define NUVOTON_QSPI_CTL_DTREN_MASK BIT(23) /* DTR I/O Mode Enable */ #define NUVOTON_QSPI_CTL_QUADIOEN_MASK BIT(22) /* Quad I/O Mode Enable */ #define NUVOTON_QSPI_CTL_DUALIOEN_MASK BIT(21) /* Dual I/O Mode Enable */ #define NUVOTON_QSPI_CTL_DATDIR_MASK BIT(20) /* Data Port Direction Contro= l */ @@ -131,7 +132,7 @@ static int nuvoton_qspi_reset_fifo(struct nuvoton_qspi = *qspi) 1, NUVOTON_QSPI_TIMEOUT_US); } =20 -static int nuvoton_qspi_set_speed(struct spi_device *spi, u32 speed_hz) +static int nuvoton_qspi_set_speed(struct spi_device *spi, u32 speed_hz, bo= ol dtr) { struct nuvoton_qspi *qspi =3D spi_controller_get_devdata(spi->controller); unsigned long clk_rate; @@ -143,6 +144,10 @@ static int nuvoton_qspi_set_speed(struct spi_device *s= pi, u32 speed_hz) if (!speed_hz) return -EINVAL; =20 + /* Experimentally, when enabling DTR the frequency is cut in half */ + if (dtr) + speed_hz *=3D 2; + if (qspi->speed_hz =3D=3D speed_hz) return 0; =20 @@ -215,16 +220,19 @@ static int nuvoton_qspi_setup_transfer(struct spi_dev= ice *spi, u8 bpw) static int nuvoton_qspi_configure_bus(struct spi_device *spi, unsigned int buswidth, enum spi_mem_data_dir dir, - u32 speed_hz) + u32 speed_hz, bool dtr) { struct nuvoton_qspi *qspi =3D spi_controller_get_devdata(spi->controller); u32 ctl =3D 0; int ret; =20 - ret =3D nuvoton_qspi_set_speed(spi, speed_hz); + ret =3D nuvoton_qspi_set_speed(spi, speed_hz, dtr); if (ret) return ret; =20 + if (dtr) + ctl |=3D NUVOTON_QSPI_CTL_DTREN_MASK; + if (buswidth =3D=3D 4) ctl |=3D NUVOTON_QSPI_CTL_QUADIOEN_MASK; else if (buswidth =3D=3D 2) @@ -234,6 +242,7 @@ static int nuvoton_qspi_configure_bus(struct spi_device= *spi, ctl |=3D NUVOTON_QSPI_CTL_DATDIR_MASK; =20 nuvoton_qspi_update_bits(qspi, NUVOTON_QSPI_CTL_OFFSET, + NUVOTON_QSPI_CTL_DTREN_MASK | NUVOTON_QSPI_CTL_QUADIOEN_MASK | NUVOTON_QSPI_CTL_DUALIOEN_MASK | NUVOTON_QSPI_CTL_DATDIR_MASK, ctl); @@ -470,7 +479,7 @@ static int nuvoton_qspi_mem_exec_op(struct spi_mem *mem, cmd[i] =3D op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1)); =20 ret =3D nuvoton_qspi_configure_bus(spi, op->cmd.buswidth, SPI_MEM_DATA_OU= T, - op->max_freq); + op->max_freq, op->cmd.dtr); if (ret) goto out_deassert_cs; =20 @@ -483,7 +492,7 @@ static int nuvoton_qspi_mem_exec_op(struct spi_mem *mem, addr[i] =3D op->addr.val >> (8 * (op->addr.nbytes - i - 1)); =20 ret =3D nuvoton_qspi_configure_bus(spi, op->addr.buswidth, SPI_MEM_DATA_= OUT, - op->max_freq); + op->max_freq, op->addr.dtr); if (ret) goto out_deassert_cs; =20 @@ -494,7 +503,7 @@ static int nuvoton_qspi_mem_exec_op(struct spi_mem *mem, =20 if (op->dummy.nbytes) { ret =3D nuvoton_qspi_configure_bus(spi, op->dummy.buswidth, SPI_MEM_DATA= _OUT, - op->max_freq); + op->max_freq, op->dummy.dtr); if (ret) goto out_deassert_cs; =20 @@ -505,7 +514,7 @@ static int nuvoton_qspi_mem_exec_op(struct spi_mem *mem, =20 if (op->data.nbytes) { ret =3D nuvoton_qspi_configure_bus(spi, op->data.buswidth, op->data.dir, - op->max_freq); + op->max_freq, op->data.dtr); if (ret) goto out_deassert_cs; =20 @@ -531,6 +540,7 @@ static const struct spi_controller_mem_ops nuvoton_qspi= _mem_ops =3D { =20 static const struct spi_controller_mem_caps nuvoton_qspi_mem_caps =3D { .per_op_freq =3D true, + .dtr =3D true, }; =20 static int nuvoton_qspi_transfer_one(struct spi_controller *ctlr, @@ -567,7 +577,8 @@ static int nuvoton_qspi_transfer_one(struct spi_control= ler *ctlr, buswidth =3D 2; } =20 - ret =3D nuvoton_qspi_configure_bus(spi, buswidth, dir, xfer->speed_hz); + ret =3D nuvoton_qspi_configure_bus(spi, buswidth, dir, xfer->speed_hz, + xfer->dtr_mode); if (ret) return ret; =20 --=20 2.54.0 From nobody Tue Sep 29 02:35:29 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48A8F43CE71 for ; Thu, 13 Aug 2026 08:01:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608069; cv=none; b=Yb5xos9xAMRgEgC/UmrBgFclzd6Lrf5pHkYo89T6wl0Nkkwi//hBRj9MbEwqyK0iil1jM73zbwsNp6oHuf42iEf0hwO899TB0PPRf6jQ7XK5sQ679q26Hv2JIIeP+0AZx4WVNLR/lq5S+/DOZP6u/sFs/y/SGqlEdRm3KimSkO4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786608069; c=relaxed/simple; bh=nK/NHuU1xXkaVbgaeuL+VrC9Bacw7Wnb6/yhTL5rXvc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U8Uo+EnjBDoB2VhW4AdOOUfh4OlljyNgtbEjXFC7l+x8OT+B+RXVHXUSnf+3onbKjJc/YR+oF/koVV+arXNWuaSypqGzqz4zrXmK/tFaDMf+6X22JIy6skHPE53Q9HQnpGJVtHddlPrRujbAwOVrjobzGRVL6wOXN1/C/uc0hRc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=1dB4TCyi; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="1dB4TCyi" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 74CAC1A15F0; Thu, 13 Aug 2026 08:01:03 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 49918602B8; Thu, 13 Aug 2026 08:01:03 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 81A9511C4DA8E; Thu, 13 Aug 2026 10:00:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1786608058; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=zj84OFZz5gnRYignK4t6ga1YzryGPYdWrXYJ76F0Jgc=; b=1dB4TCyirgki1jlciw49iYZSNvLXgM7koNktnDBZ611HsvioCX0gRZAiKyKx9a40KIbJC/ JHoUGwNV77a/Vw4/88K5I9nyU3kzvgsfoaS1T/ffkUBxx7FBsnUqSIquXB8VoJs5mQZSSC dEoBEQXLKsZ60ZbvnkGixXC6XTgWl8jepBtTD8WaCxi6M97cmLaCQqSo/K9pQhKxuRrrho 4MlCbI1EMeH/Bg7VnRS8D5+BqfWOQesZ92bar/EEMS9eJ29+AFcZZzoTmHrs4oUlmQo8WX p+7WJGxXy5fBaSATaYUFno78WuIdzSmPXx4eQPfMbac+8F8LrjETyusVy2zmDg== From: Miquel Raynal Date: Thu, 13 Aug 2026 10:00:25 +0200 Subject: [PATCH 5/5] spi: ma35d1-qspi: Use the existing update helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-perso-ma35d1-upstream-qspi-v1-5-b217b9870eb1@bootlin.com> References: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> In-Reply-To: <20260813-perso-ma35d1-upstream-qspi-v1-0-b217b9870eb1@bootlin.com> To: Jacky Huang , Shan-Chun Hung , Mark Brown Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Read modify writes are already covered by a local helper, so use it. No functional change. Signed-off-by: Miquel Raynal --- drivers/spi/spi-ma35d1-qspi.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-ma35d1-qspi.c b/drivers/spi/spi-ma35d1-qspi.c index 9965a11573d8..7f938d0c6f1f 100644 --- a/drivers/spi/spi-ma35d1-qspi.c +++ b/drivers/spi/spi-ma35d1-qspi.c @@ -115,10 +115,11 @@ static int nuvoton_qspi_reset_fifo(struct nuvoton_qsp= i *qspi) { u32 val; =20 - val =3D nuvoton_qspi_read(qspi, NUVOTON_QSPI_FIFOCTL_OFFSET); - val |=3D NUVOTON_QSPI_FIFOCTL_TXRST_MASK | - NUVOTON_QSPI_FIFOCTL_RXRST_MASK; - nuvoton_qspi_write(qspi, val, NUVOTON_QSPI_FIFOCTL_OFFSET); + nuvoton_qspi_update_bits(qspi, NUVOTON_QSPI_FIFOCTL_OFFSET, + NUVOTON_QSPI_FIFOCTL_TXRST_MASK | + NUVOTON_QSPI_FIFOCTL_RXRST_MASK, + NUVOTON_QSPI_FIFOCTL_TXRST_MASK | + NUVOTON_QSPI_FIFOCTL_RXRST_MASK); =20 /* * Give the controller a short time to latch the FIFO reset request @@ -356,9 +357,9 @@ static int nuvoton_qspi_hw_init(struct nuvoton_qspi *qs= pi) NUVOTON_QSPI_CTL_LSB_MASK, NUVOTON_QSPI_CTL_TXNEG_MASK); =20 - val =3D nuvoton_qspi_read(qspi, NUVOTON_QSPI_CTL_OFFSET); - nuvoton_qspi_write(qspi, val | NUVOTON_QSPI_CTL_SPIEN_MASK, - NUVOTON_QSPI_CTL_OFFSET); + nuvoton_qspi_update_bits(qspi, NUVOTON_QSPI_CTL_OFFSET, + NUVOTON_QSPI_CTL_SPIEN_MASK, + NUVOTON_QSPI_CTL_SPIEN_MASK); =20 ret =3D readl_poll_timeout(qspi->regs + NUVOTON_QSPI_STATUS_OFFSET, val, (val & NUVOTON_QSPI_STATUS_SPIENSTS_MASK), --=20 2.54.0