From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 455443B42DD; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; cv=none; b=lfTvLScHUH/ACowhU4041JzqQCCypo4VGow6BHfqdsJgco7tXQNKaIiWylme4W98arssZCKtVonpH00a2kN64rkFPxjXxXAG0JpN586OmexYHl8klt16CiVAxrlUEqzAJxN8r4F8GUx02x0jVtAnNOVOyEm9F1koOIL/NTph7sI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; c=relaxed/simple; bh=Vj1DHrmGR0tyVO+ZlDxsQgZLtvtVuNtuX+cbxrGaewI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MEQaKtMuQMSOuJdbBLEjoSGMfxsWmK3KRam4Or0Avr+xh9EeD83IFKsecSbKKNHkxarMxMFbMXili5xBkzebLz+f8qhg1w3VwgNxAR+T4s8TQKo5j+UThN5gNxAPIY08M8KL5iyJ64JRc7nmPs4fYPr7WkhrbjfvE3ct6BQatgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UwLk7aUX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UwLk7aUX" Received: by smtp.kernel.org (Postfix) with ESMTPS id AEFCDC2BCC7; Thu, 13 Aug 2026 11:59:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786622399; bh=Vj1DHrmGR0tyVO+ZlDxsQgZLtvtVuNtuX+cbxrGaewI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UwLk7aUX6eblDL5+ILVIy7EMM+xYUVYYERWPlhowguzjo3XQYAkSihclHOJ0jBZE8 kX/niZlh3Hpj8iVdIQRUfMS1FMjjrNKJ0gPAuqwJfvd7ENbvUdUvd6WvrNoE2jcXWl Nvu9dSI9sHLK457S3hKaK/skYCaUO9yZRMZyWF2LNStIyVNmS3CtWnT2K9lTMv30LK TGKtmkPHakzRIs/vsbKrU1cBFs8fC6IhqLryj5iqVsx07Uoe3PS8PIV8IFtHy9boso S0ny6pXHhpAOIXAKz9DHbb3n0w77C/G//FiWqpZb1+Hx8bL3+F3q0UEMAnJW6bxAsb 4JFpZP0t8yr6g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EAF9C5B572; Thu, 13 Aug 2026 11:59:59 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:31 +0800 Subject: [PATCH v5 01/15] dt-bindings: arm: aspeed: Add Anacapa EVT1 EVT2 DVT board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-1-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Conor Dooley X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=985; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=Sw+OWK3YcWaJDMswc4oOvzoue3GKb6ZepbG6V99kpbc=; b=Um55I6CVH1x3FcJbngRYHo3gZ8DbRaJiyMXDx6AbqYHQ6ZCPaaBQ44jhg4oELVPsZ3bXgqO79 b+i5I3R1XGmDvK44ZrYD92TWtlq0ieC2qjMGWtxiIdrbdXSZPpBZ8Pm X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Document Anacapa BMC EVT1, EVT2, and DVT compatibles. Signed-off-by: Colin Huang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index dd7996960de3..1c1570143bd9 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -84,6 +84,9 @@ properties: - asus,ast2600-kommando-ipmi-card - asus,x4tf-bmc - facebook,anacapa-bmc + - facebook,anacapa-bmc-dvt + - facebook,anacapa-bmc-evt1 + - facebook,anacapa-bmc-evt2 - facebook,bletchley-bmc - facebook,catalina-bmc - facebook,clemente-bmc --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 494E4416852; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; cv=none; b=dCrRNy0iC85ihItRUg54LtfTPGH/FSJ0TDMwKfIukYH9uzdvOLWidMXUt2dvX4gy//shEtV8GH8rMyht06aLDyepauEGudBqUYdbWg4x/ipnC7uSKjz4Dy39mX35IdsmPaF8K55edLSlXN4CQzc9tS4mc5rt5cQi8pt4JzHRpg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; c=relaxed/simple; bh=wTcuzLI2ct+fGUPlDKB1c2kxlyfr3lfvfGuWXF6KK2M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aX0imOciVZNlr6RiKmNDTsxHAkrWUvMF688dsXq361NoE1cW3tWPFaGOIV/0WOdo58aoTWbcgfD3BoQQsdtcmFBek3E566B8W1gdak/jpmf/mlVShX/rxSrXyFJI0WAA5tEtFp8t6qz5SYI7UrTXviXeZJNOou6LltyyTV/QRNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VLlYtMdL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VLlYtMdL" Received: by smtp.kernel.org (Postfix) with ESMTPS id D8D4BC2BCF5; Thu, 13 Aug 2026 11:59:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786622399; bh=wTcuzLI2ct+fGUPlDKB1c2kxlyfr3lfvfGuWXF6KK2M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VLlYtMdLGUoSzhn7I2tuQ7m8cnm6L5nFDmuVg09OxNIiUF4A+eCD40nITHzDeOkxS sK7Ef0evuH8umML16fVdAcNDYHb0Q+MZt3jm6E7Tu+gPtMzzY6KDnWaHCshAM/bFs5 exYTXyJsyH5SZF7Gqs4eqZPvy0Vygaaw2ckzlxJJcOJLdFLHe5lMc2o9I+im0E96NW QyMyGDAusLPYKlFAGysOq+9P7RtLwqi6+Z5NC+DLqcTfALjNohgSOtsoNoBTfvnXWr 7oNF7e6PexzFr9NRDqsJ8ormBkutVStTLtHs5zoB+P0MblZhzYcaGIKFvInlc17AAM pb3j6NkaYFzqA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC7D6C5DF66; Thu, 13 Aug 2026 11:59:59 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:32 +0800 Subject: [PATCH v5 02/15] ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-2-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=47120; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=b/0WBLSG/a1bCS1KHVOFus0mkvN/u7D8sEkXmyaubX4=; b=W0AiLaii3qk7zI05P9K+KRsy2TcwBUxS+INc58pGOh8JVsz22K0tWKxEJ45/6NtAeK34WX4JM /vOauRuRsULDDUADz+V3K1J/RYE4wTYkRCKKQ/9oR3qbL6cU9kGHFNH X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang This commit introduces an EVT1 development-phase devicetree for the Facebook Anacapa BMC. It updates the top-level wrapper DTS to include the EVT1 hardware revision file. A dedicated EVT1 DTS is added as the base revision for subsequent board variants. The top-level aspeed-bmc-facebook-anacapa.dts now includes the EVT1 devicetree, allowing EVT2 and DVT revisions to inherit from a common baseline while preserving a single build target for Anacapa. Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1079 ++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1077 +---------------= --- 2 files changed, 1080 insertions(+), 1076 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts new file mode 100644 index 000000000000..a095be48a3fe --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts @@ -0,0 +1,1079 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model =3D "Facebook Anacapa BMC"; + compatible =3D "facebook,anacapa-bmc-evt1", "aspeed,ast2600"; + + aliases { + serial0 =3D &uart1; + serial1 =3D &uart2; + serial2 =3D &uart3; + serial3 =3D &uart4; + serial4 =3D &uart5; + i2c16 =3D &i2c0mux0ch0; + i2c17 =3D &i2c0mux0ch1; + i2c18 =3D &i2c0mux0ch2; + i2c19 =3D &i2c0mux0ch3; + i2c20 =3D &i2c1mux0ch0; + i2c21 =3D &i2c1mux0ch1; + i2c22 =3D &i2c1mux0ch2; + i2c23 =3D &i2c1mux0ch3; + i2c24 =3D &i2c4mux0ch0; + i2c25 =3D &i2c4mux0ch1; + i2c26 =3D &i2c4mux0ch2; + i2c27 =3D &i2c4mux0ch3; + i2c28 =3D &i2c4mux0ch4; + i2c29 =3D &i2c4mux0ch5; + i2c30 =3D &i2c4mux0ch6; + i2c31 =3D &i2c4mux0ch7; + i2c32 =3D &i2c8mux0ch0; + i2c33 =3D &i2c8mux0ch1; + i2c34 =3D &i2c8mux0ch2; + i2c35 =3D &i2c8mux0ch3; + i2c36 =3D &i2c10mux0ch0; + i2c37 =3D &i2c10mux0ch1; + i2c38 =3D &i2c10mux0ch2; + i2c39 =3D &i2c10mux0ch3; + i2c40 =3D &i2c10mux0ch4; + i2c41 =3D &i2c10mux0ch5; + i2c42 =3D &i2c10mux0ch6; + i2c43 =3D &i2c10mux0ch7; + i2c44 =3D &i2c11mux0ch0; + i2c45 =3D &i2c11mux0ch1; + i2c46 =3D &i2c11mux0ch2; + i2c47 =3D &i2c11mux0ch3; + i2c48 =3D &i2c11mux0ch4; + i2c49 =3D &i2c11mux0ch5; + i2c50 =3D &i2c11mux0ch6; + i2c51 =3D &i2c11mux0ch7; + i2c52 =3D &i2c13mux0ch0; + i2c53 =3D &i2c13mux0ch1; + i2c54 =3D &i2c13mux0ch2; + i2c55 =3D &i2c13mux0ch3; + i2c56 =3D &i2c13mux0ch4; + i2c57 =3D &i2c13mux0ch5; + i2c58 =3D &i2c13mux0ch6; + i2c59 =3D &i2c13mux0ch7; + }; + + chosen { + stdout-path =3D "serial4:57600n8"; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + label =3D "bmc_heartbeat_amber"; + gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + + led-1 { + label =3D "fp_id_amber"; + default-state =3D "off"; + gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + video_engine_memory: video { + size =3D <0x02c00000>; + alignment =3D <0x00100000>; + compatible =3D "shared-dma-pool"; + reusable; + }; + + gfx_memory: framebuffer { + size =3D <0x01000000>; + alignment =3D <0x01000000>; + compatible =3D "shared-dma-pool"; + reusable; + }; + }; + + p3v3_bmc_aux: regulator-p3v3-bmc-aux { + compatible =3D "regulator-fixed"; + regulator-name =3D "p3v3_bmc_aux"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + spi_gpio: spi { + compatible =3D "spi-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects =3D <1>; + status =3D "okay"; + + tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency =3D <33000000>; + reg =3D <0>; + }; + }; +}; + +&adc0 { + aspeed,int-vref-microvolt =3D <2500000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + status =3D "okay"; +}; + +&adc1 { + aspeed,int-vref-microvolt =3D <2500000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc10_default>; + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&fmc { + status =3D "okay"; + + flash@0 { + status =3D "okay"; + m25p,fast-read; + label =3D "bmc"; + spi-max-frequency =3D <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status =3D "okay"; + m25p,fast-read; + label =3D "alt-bmc"; + spi-max-frequency =3D <50000000>; + }; +}; + +&gfx { + status =3D "okay"; + memory-region =3D <&gfx_memory>; +}; + +&gpio0 { + gpio-line-names =3D + + /*A0-A7*/ + "","","","","","","","", + + /*B0-B7*/ + "BATTERY_DETECT", "", "", "BMC_READY", + "", "FM_ID_LED", "", "", + + /*C0-C7*/ + "","","","","","","","", + + /*D0-D7*/ + "","","","","","","","", + + /*E0-E7*/ + "","","","","","","","", + + /*F0-F7*/ + "","","","","","","","", + + /*G0-G7*/ + "FM_MUX1_SEL", "", "", "", + "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", + + /*H0-H7*/ + "","","","","","","","", + + /*I0-I7*/ + "", "", "", "", + "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", + + /*J0-J7*/ + "","","","","","","","", + + /*K0-K7*/ + "","","","","","","","", + + /*L0-L7*/ + "","","","","","","","", + + /*M0-M7*/ + "", "BMC_FRU_WP", "", "", + "", "", "", "", + + /*N0-N7*/ + "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", + "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", + + /*O0-O7*/ + "","","","","","","","", + + /*P0-P7*/ + "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", + "PWR_LED", "", "", "BMC_HEARTBEAT_N", + + /*Q0-Q7*/ + "","","","","","","","", + + /*R0-R7*/ + "","","","","","","","", + + /*S0-S7*/ + "", "", "SYS_BMC_PWRBTN_N", "", + "", "", "", "RUN_POWER_FAULT", + + /*T0-T7*/ + "","","","","","","","", + + /*U0-U7*/ + "","","","","","","","", + + /*V0-V7*/ + "","","","","","","","", + + /*W0-W7*/ + "","","","","","","","", + + /*X0-X7*/ + "","","","","","","","", + + /*Y0-Y7*/ + "","","","","","","","", + + /*Z0-Z7*/ + "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", + "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; +}; + +&gpio1 { + gpio-line-names =3D + /*18A0-18A7*/ + "","","","","","","","", + + /*18B0-18B7*/ + "","","","", + "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2", "", + + /*18C0-18C7*/ + "","","","","","","","", + + /*18D0-18D7*/ + "","","","","","","","", + + /*18E0-18E3*/ + "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; +}; + +// L Bridge Board +&i2c0 { + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c2048"; + reg =3D <0x50>; + pagesize =3D <128>; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c0mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c0mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c0mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// R Bridge Board +&i2c1 { + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c2048"; + reg =3D <0x50>; + pagesize =3D <128>; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c1mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c1mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c1mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c1mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// MB - E1.S +&i2c4 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c4mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// AMC +&i2c5 { + status =3D "okay"; +}; + +// MB +&i2c6 { + status =3D "okay"; + + // HPM FRU + eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; +}; + +// SCM +&i2c7 { + status =3D "okay"; + + +}; + +// MB - PDB +&i2c8 { + status =3D "okay"; + + i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c8mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1f { + compatible =3D "ti,adc128d818"; + reg =3D <0x1f>; + ti,mode =3D /bits/ 8 <1>; + }; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "", + "", "", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", + "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", + "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", + "", "RPDB_FAN1_PRSNT_N_R", + "", "RPDB_FAN2_PRSNT_N_R", + "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", + "", ""; + }; + + // R-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + i2c8mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N","", + "","", + "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R",""; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", + "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", + "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", + "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", + "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", + "","", + "","", + "",""; + }; + + // L-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + i2c8mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c8mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// SCM +&i2c9 { + status =3D "okay"; + + // SCM FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + + // BSM FRU + eeprom@56 { + compatible =3D "atmel,24c64"; + reg =3D <0x56>; + }; +}; + +// R Bridge Board +&i2c10 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c10mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "","", + "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", + "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", + "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", + "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", + "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", + "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", + "",""; + }; + + // R Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + i2c10mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// L Bridge Board +&i2c11 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "","", + "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", + "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", + "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", + "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", + "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", + "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", + "",""; + }; + + // L Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + i2c11mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// Debug Card +&i2c12 { + status =3D "okay"; +}; + +// MB +&i2c13 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c13mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1f { + compatible =3D "ti,adc128d818"; + reg =3D <0x1f>; + ti,mode =3D /bits/ 8 <1>; + }; + }; + i2c13mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + // HPM BRD ID FRU + eeprom@51 { + compatible =3D "atmel,24c256"; + reg =3D <0x51>; + }; + }; + i2c13mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nfc@28 { + compatible =3D "nxp,nxp-nci-i2c"; + reg =3D <0x28>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; + +// SCM +&i2c14 { + status =3D "okay"; +}; + +&i2c15 { + status =3D "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg =3D <0xca8>; + status =3D "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg =3D <0xca2>; + status =3D "okay"; +}; + +&lpc_ctrl { + status =3D "okay"; +}; + +&mac2 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ncsi3_default>; + use-ncsi; +}; + +&sgpiom0 { + ngpios =3D <128>; + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out - in - out */ + /* A0-A7 line 0-15 */ + "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", + "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", + "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", + "", "", "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "", + "Channel5_leakage_EAM1", "", + "Channel6_leakage_CPU_DIMM", "", + "Channel7_leakage_EAM2", "", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "", "", "", + "", "", "", "", + "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", + "", "", "", "", + + /* D0-D7 line 48-63 */ + "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", + "AMC_BRD_PRSNT_CPLD_L", "", "", "", + "", "", "", "", + + /* E0-E7 line 64-79 */ + "AMC_PDB_EAMHSC0_CPLD_EN_R", "", + "AMC_PDB_EAMHSC1_CPLD_EN_R", "", + "AMC_PDB_EAMHSC2_CPLD_EN_R", "", + "AMC_PDB_EAMHSC3_CPLD_EN_R", "", + "", "", "", "", + "", "", "", "", + + /* F0-F7 line 80-95 */ + "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", + "PWRGD_PVDDCR_CPU0_P0", "", + "", "", "", "", + "", "", "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "PWRGD_CHEH_CPU0_FPGA", "", + "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", + "", "", + + /* H0-H7 line 112-127 */ + "PWRGD_P3V3", "", + "P12V_DDR_IP_PWRGD_R", "", + "P12V_DDR_AH_PWRGD_R", "", + "PWRGD_P12V_VRM1_CPLD_PG_R", "", + "PWRGD_P12V_VRM0_CPLD_PG_R", "", + "PWRGD_PDB_HSC4_CPLD_PG_R", "", + "PWRGD_PVDD18_S5_P0_PG", "", + "PWRGD_PVDD33_S5_P0_PG", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "EAM0_CPU_MOD_PWR_GD_R", "", + "EAM1_CPU_MOD_PWR_GD_R", "", + "PRSNT_EDSFF_BOOT_N", "", + "EAM3_CPU_MOD_PWR_GD_R", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BIRDGE_R", "", + "PRSNT_R_BIRDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "", "", "", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", + "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", + "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "", "", "", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "", + "FM_PWRGD_CPU0_PWROK", "", + "wS5_PWR_Ready", "", + "wS0_ON_N", "PWRGD_P1V0_AUX"; + status =3D "okay"; +}; + +// BIOS Flash +&spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi2_default>; + status =3D "okay"; + reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + label =3D "pnor"; + spi-max-frequency =3D <12000000>; + spi-tx-bus-width =3D <2>; + spi-rx-bus-width =3D <2>; + status =3D "okay"; + }; +}; + +// HOST BIOS Debug +&uart1 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +// BMC Debug Console +&uart5 { + status =3D "okay"; +}; + +&uart_routing { + status =3D "okay"; +}; + +&uhci { + status =3D "okay"; +}; + +&vhub { + status =3D "okay"; + pinctrl-names =3D "default"; +}; + +&video { + status =3D "okay"; + memory-region =3D <&video_engine_memory>; +}; + +&wdt1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdtrst1_default>; + aspeed,reset-type =3D "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration =3D <256>; + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 1fddf3a5d138..209eef65cedb 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,1079 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 -/dts-v1/; -#include "aspeed-g6.dtsi" -#include -#include +#include "aspeed-bmc-facebook-anacapa-evt1.dts" =20 -/ { - model =3D "Facebook Anacapa BMC"; - compatible =3D "facebook,anacapa-bmc", "aspeed,ast2600"; - - aliases { - serial0 =3D &uart1; - serial1 =3D &uart2; - serial2 =3D &uart3; - serial3 =3D &uart4; - serial4 =3D &uart5; - i2c16 =3D &i2c0mux0ch0; - i2c17 =3D &i2c0mux0ch1; - i2c18 =3D &i2c0mux0ch2; - i2c19 =3D &i2c0mux0ch3; - i2c20 =3D &i2c1mux0ch0; - i2c21 =3D &i2c1mux0ch1; - i2c22 =3D &i2c1mux0ch2; - i2c23 =3D &i2c1mux0ch3; - i2c24 =3D &i2c4mux0ch0; - i2c25 =3D &i2c4mux0ch1; - i2c26 =3D &i2c4mux0ch2; - i2c27 =3D &i2c4mux0ch3; - i2c28 =3D &i2c4mux0ch4; - i2c29 =3D &i2c4mux0ch5; - i2c30 =3D &i2c4mux0ch6; - i2c31 =3D &i2c4mux0ch7; - i2c32 =3D &i2c8mux0ch0; - i2c33 =3D &i2c8mux0ch1; - i2c34 =3D &i2c8mux0ch2; - i2c35 =3D &i2c8mux0ch3; - i2c36 =3D &i2c10mux0ch0; - i2c37 =3D &i2c10mux0ch1; - i2c38 =3D &i2c10mux0ch2; - i2c39 =3D &i2c10mux0ch3; - i2c40 =3D &i2c10mux0ch4; - i2c41 =3D &i2c10mux0ch5; - i2c42 =3D &i2c10mux0ch6; - i2c43 =3D &i2c10mux0ch7; - i2c44 =3D &i2c11mux0ch0; - i2c45 =3D &i2c11mux0ch1; - i2c46 =3D &i2c11mux0ch2; - i2c47 =3D &i2c11mux0ch3; - i2c48 =3D &i2c11mux0ch4; - i2c49 =3D &i2c11mux0ch5; - i2c50 =3D &i2c11mux0ch6; - i2c51 =3D &i2c11mux0ch7; - i2c52 =3D &i2c13mux0ch0; - i2c53 =3D &i2c13mux0ch1; - i2c54 =3D &i2c13mux0ch2; - i2c55 =3D &i2c13mux0ch3; - i2c56 =3D &i2c13mux0ch4; - i2c57 =3D &i2c13mux0ch5; - i2c58 =3D &i2c13mux0ch6; - i2c59 =3D &i2c13mux0ch7; - }; - - chosen { - stdout-path =3D "serial4:57600n8"; - }; - - iio-hwmon { - compatible =3D "iio-hwmon"; - io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 2>; - }; - - leds { - compatible =3D "gpio-leds"; - - led-0 { - label =3D "bmc_heartbeat_amber"; - gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - linux,default-trigger =3D "heartbeat"; - }; - - led-1 { - label =3D "fp_id_amber"; - default-state =3D "off"; - gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type =3D "memory"; - reg =3D <0x80000000 0x80000000>; - }; - - reserved-memory { - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - video_engine_memory: video { - size =3D <0x02c00000>; - alignment =3D <0x00100000>; - compatible =3D "shared-dma-pool"; - reusable; - }; - - gfx_memory: framebuffer { - size =3D <0x01000000>; - alignment =3D <0x01000000>; - compatible =3D "shared-dma-pool"; - reusable; - }; - }; - - p3v3_bmc_aux: regulator-p3v3-bmc-aux { - compatible =3D "regulator-fixed"; - regulator-name =3D "p3v3_bmc_aux"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - }; - - spi_gpio: spi { - compatible =3D "spi-gpio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; - cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - num-chipselects =3D <1>; - status =3D "okay"; - - tpm@0 { - compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; - spi-max-frequency =3D <33000000>; - reg =3D <0>; - }; - }; -}; - -&adc0 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; - status =3D "okay"; -}; - -&adc1 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_adc10_default>; - status =3D "okay"; -}; - -&ehci1 { - status =3D "okay"; -}; - -&fmc { - status =3D "okay"; - - flash@0 { - status =3D "okay"; - m25p,fast-read; - label =3D "bmc"; - spi-max-frequency =3D <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; - - flash@1 { - status =3D "okay"; - m25p,fast-read; - label =3D "alt-bmc"; - spi-max-frequency =3D <50000000>; - }; -}; - -&gfx { - status =3D "okay"; - memory-region =3D <&gfx_memory>; -}; - -&gpio0 { - gpio-line-names =3D - - /*A0-A7*/ - "","","","","","","","", - - /*B0-B7*/ - "BATTERY_DETECT", "", "", "BMC_READY", - "", "FM_ID_LED", "", "", - - /*C0-C7*/ - "","","","","","","","", - - /*D0-D7*/ - "","","","","","","","", - - /*E0-E7*/ - "","","","","","","","", - - /*F0-F7*/ - "","","","","","","","", - - /*G0-G7*/ - "FM_MUX1_SEL", "", "", "", - "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", - - /*H0-H7*/ - "","","","","","","","", - - /*I0-I7*/ - "", "", "", "", - "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", - - /*J0-J7*/ - "","","","","","","","", - - /*K0-K7*/ - "","","","","","","","", - - /*L0-L7*/ - "","","","","","","","", - - /*M0-M7*/ - "", "BMC_FRU_WP", "", "", - "", "", "", "", - - /*N0-N7*/ - "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", - "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", - - /*O0-O7*/ - "","","","","","","","", - - /*P0-P7*/ - "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", - "PWR_LED", "", "", "BMC_HEARTBEAT_N", - - /*Q0-Q7*/ - "","","","","","","","", - - /*R0-R7*/ - "","","","","","","","", - - /*S0-S7*/ - "", "", "SYS_BMC_PWRBTN_N", "", - "", "", "", "RUN_POWER_FAULT", - - /*T0-T7*/ - "","","","","","","","", - - /*U0-U7*/ - "","","","","","","","", - - /*V0-V7*/ - "","","","","","","","", - - /*W0-W7*/ - "","","","","","","","", - - /*X0-X7*/ - "","","","","","","","", - - /*Y0-Y7*/ - "","","","","","","","", - - /*Z0-Z7*/ - "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", - "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; -}; - -&gpio1 { - gpio-line-names =3D - /*18A0-18A7*/ - "","","","","","","","", - - /*18B0-18B7*/ - "","","","", - "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", - "FM_BOARD_BMC_REV_ID2", "", - - /*18C0-18C7*/ - "","","","","","","","", - - /*18D0-18D7*/ - "","","","","","","","", - - /*18E0-18E3*/ - "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; -}; - -// L Bridge Board -&i2c0 { - status =3D "okay"; - - eeprom@50 { - compatible =3D "atmel,24c2048"; - reg =3D <0x50>; - pagesize =3D <128>; - }; - - i2c-mux@70 { - compatible =3D "nxp,pca9546"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c0mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// R Bridge Board -&i2c1 { - status =3D "okay"; - - eeprom@50 { - compatible =3D "atmel,24c2048"; - reg =3D <0x50>; - pagesize =3D <128>; - }; - - i2c-mux@70 { - compatible =3D "nxp,pca9546"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c1mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// MB - E1.S -&i2c4 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c4mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// AMC -&i2c5 { - status =3D "okay"; -}; - -// MB -&i2c6 { - status =3D "okay"; - - // HPM FRU - eeprom@50 { - compatible =3D "atmel,24c256"; - reg =3D <0x50>; - }; -}; - -// SCM -&i2c7 { - status =3D "okay"; - - -}; - -// MB - PDB -&i2c8 { - status =3D "okay"; - - i2c-mux@72 { - compatible =3D "nxp,pca9546"; - reg =3D <0x72>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c8mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - adc@1f { - compatible =3D "ti,adc128d818"; - reg =3D <0x1f>; - ti,mode =3D /bits/ 8 <1>; - }; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", - "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", - "RPDB_FAN_CT_FAN_FAIL_R_N", "", - "", "", - "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", - "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", - "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", - "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", - "RPDB_PGD_P3V3_STBY_PWRGD_R", - "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; - }; - - gpio@24 { - compatible =3D "nxp,pca9555"; - reg =3D <0x24>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", - "RPDB_PWRGD_P50V_HSC4_SYS_R", - "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", - "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", - "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", - "", "RPDB_FAN1_PRSNT_N_R", - "", "RPDB_FAN2_PRSNT_N_R", - "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", - "", ""; - }; - - // R-PDB FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - }; - i2c8mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", - "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", - "LPDB_FAN_CT_FAN_FAIL_R_N","", - "","", - "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", - "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", - "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", - "LPDB_PWRGD_P50V_HSC5_SYS_R",""; - }; - - gpio@24 { - compatible =3D "nxp,pca9555"; - reg =3D <0x24>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", - "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", - "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", - "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", - "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", - "","", - "","", - "",""; - }; - - // L-PDB FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - }; - i2c8mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c8mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// SCM -&i2c9 { - status =3D "okay"; - - // SCM FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - - // BSM FRU - eeprom@56 { - compatible =3D "atmel,24c64"; - reg =3D <0x56>; - }; -}; - -// R Bridge Board -&i2c10 { - status =3D "okay"; - - i2c-mux@71 { - compatible =3D "nxp,pca9548"; - reg =3D <0x71>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c10mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - gpio-line-names =3D - "","", - "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", - "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", - "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", - "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", - "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", - "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", - "",""; - }; - - // R Bridge Board FRU - eeprom@52 { - compatible =3D "atmel,24c256"; - reg =3D <0x52>; - }; - }; - i2c10mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// L Bridge Board -&i2c11 { - status =3D "okay"; - - i2c-mux@71 { - compatible =3D "nxp,pca9548"; - reg =3D <0x71>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c11mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - gpio-line-names =3D - "","", - "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", - "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", - "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", - "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", - "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", - "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", - "",""; - }; - - // L Bridge Board FRU - eeprom@52 { - compatible =3D "atmel,24c256"; - reg =3D <0x52>; - }; - }; - i2c11mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// Debug Card -&i2c12 { - status =3D "okay"; -}; - -// MB -&i2c13 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c13mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - adc@1f { - compatible =3D "ti,adc128d818"; - reg =3D <0x1f>; - ti,mode =3D /bits/ 8 <1>; - }; - }; - i2c13mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - // HPM BRD ID FRU - eeprom@51 { - compatible =3D "atmel,24c256"; - reg =3D <0x51>; - }; - }; - i2c13mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - nfc@28 { - compatible =3D "nxp,nxp-nci-i2c"; - reg =3D <0x28>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -// SCM -&i2c14 { - status =3D "okay"; -}; - -&i2c15 { - status =3D "okay"; -}; - -&kcs2 { - aspeed,lpc-io-reg =3D <0xca8>; - status =3D "okay"; -}; - -&kcs3 { - aspeed,lpc-io-reg =3D <0xca2>; - status =3D "okay"; -}; - -&lpc_ctrl { - status =3D "okay"; -}; - -&mac2 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_ncsi3_default>; - use-ncsi; -}; - -&sgpiom0 { - ngpios =3D <128>; - bus-frequency =3D <2000000>; - gpio-line-names =3D - /*in - out - in - out */ - /* A0-A7 line 0-15 */ - "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", - "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", - "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", - "", "", "", "", - - /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "", - "Channel5_leakage_EAM1", "", - "Channel6_leakage_CPU_DIMM", "", - "Channel7_leakage_EAM2", "", - - /* C0-C7 line 32-47 */ - "RSVD_RMC_GPIO3", "", "", "", - "", "", "", "", - "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", - "", "", "", "", - - /* D0-D7 line 48-63 */ - "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", - "AMC_BRD_PRSNT_CPLD_L", "", "", "", - "", "", "", "", - - /* E0-E7 line 64-79 */ - "AMC_PDB_EAMHSC0_CPLD_EN_R", "", - "AMC_PDB_EAMHSC1_CPLD_EN_R", "", - "AMC_PDB_EAMHSC2_CPLD_EN_R", "", - "AMC_PDB_EAMHSC3_CPLD_EN_R", "", - "", "", "", "", - "", "", "", "", - - /* F0-F7 line 80-95 */ - "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", - "PWRGD_PVDDCR_CPU0_P0", "", - "", "", "", "", - "", "", "", "", - - /* G0-G7 line 96-111 */ - "L_PRSNT_EDSFF0_N", "", - "L_PRSNT_EDSFF1_N", "", - "R_PRSNT_EDSFF2_N", "", - "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", - "PWRGD_CHEH_CPU0_FPGA", "", - "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", - "", "", - - /* H0-H7 line 112-127 */ - "PWRGD_P3V3", "", - "P12V_DDR_IP_PWRGD_R", "", - "P12V_DDR_AH_PWRGD_R", "", - "PWRGD_P12V_VRM1_CPLD_PG_R", "", - "PWRGD_P12V_VRM0_CPLD_PG_R", "", - "PWRGD_PDB_HSC4_CPLD_PG_R", "", - "PWRGD_PVDD18_S5_P0_PG", "", - "PWRGD_PVDD33_S5_P0_PG", "", - - /* I0-I7 line 128-143 */ - "EAM0_BRD_PRSNT_R_L", "", - "EAM1_BRD_PRSNT_R_L", "", - "EAM2_BRD_PRSNT_R_L", "", - "EAM3_BRD_PRSNT_R_L", "", - "EAM0_CPU_MOD_PWR_GD_R", "", - "EAM1_CPU_MOD_PWR_GD_R", "", - "PRSNT_EDSFF_BOOT_N", "", - "EAM3_CPU_MOD_PWR_GD_R", "", - - /* J0-J7 line 144-159 */ - "PRSNT_L_BIRDGE_R", "", - "PRSNT_R_BIRDGE_R", "", - "BRIDGE_L_MAIN_PG_R", "", - "BRIDGE_R_MAIN_PG_R", "", - "BRIDGE_L_STBY_PG_R", "", - "BRIDGE_R_STBY_PG_R", "", - "", "", "", "", - - /* K0-K7 line 160-175 */ - "ADC_I2C_ALERT_N", "", - "TEMP_I2C_ALERT_R_L", "", - "CPU0_VR_SMB_ALERT_CPLD_N", "", - "COVER_INTRUDER_R_N", "", - "HANDLE_INTRUDER_CPLD_N", "", - "IRQ_MCIO_CPLD_WAKE_R_N", "", - "APML_CPU0_ALERT_R_N", "", - "PDB_ALERT_R_N", "", - - /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", - "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", - "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", - - /* M0-M7 line 192-207 */ - "EAM0_SMERR_CPLD_R_L", "", - "EAM1_SMERR_CPLD_R_L", "", - "EAM2_SMERR_CPLD_R_L", "", - "EAM3_SMERR_CPLD_R_L", "", - "CPU0_SMERR_N_R", "", - "CPU0_NV_SAVE_N_R", "", - "PDB_PWR_LOSS_CPLD_N", "", - "IRQ_BMC_SMI_ACTIVE_R_N", "", - - /* N0-N7 line 208-223 */ - "AMCROT_BMC_S5_RDY_R", "", - "AMC_RDY_R", "", - "AMC_STBY_PGOOD_R", "", - "CPU_AMC_SLP_S5_R_L", "", - "AMC_CPU_EAMPG_R", "", - "", "", "", "", - - /* O0-O7 line 224-239 */ - "HPM_PWR_FAIL", "Port80_b0", - "FM_DIMM_IP_FAIL", "Port80_b1", - "FM_DIMM_AH_FAIL", "Port80_b2", - "AMC_THERMTRIP_ASSERT", "Port80_b3", - "CPU_THERMTRIP_ASSERT", "Port80_b4", - "PVDDCR_SOC_P0_OCP_L", "Port80_b5", - "CPLD_SGPIO_RDY", "Port80_b6", - "", "Port80_b7", - - /* P0-P7 line 240-255 */ - "CPU0_SLP_S5_N_R", "NFC_VEN", - "CPU0_SLP_S3_N_R", "", - "FM_CPU0_PWRGD", "", - "PWRGD_RMC", "", - "FM_RST_CPU0_RESET_N", "", - "FM_PWRGD_CPU0_PWROK", "", - "wS5_PWR_Ready", "", - "wS0_ON_N", "PWRGD_P1V0_AUX"; - status =3D "okay"; -}; - -// BIOS Flash -&spi2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_spi2_default>; - status =3D "okay"; - reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; - - flash@0 { - compatible =3D "jedec,spi-nor"; - label =3D "pnor"; - spi-max-frequency =3D <12000000>; - spi-tx-bus-width =3D <2>; - spi-rx-bus-width =3D <2>; - status =3D "okay"; - }; -}; - -// HOST BIOS Debug -&uart1 { - status =3D "okay"; -}; - -&uart3 { - status =3D "okay"; -}; - -&uart4 { - status =3D "okay"; -}; - -// BMC Debug Console -&uart5 { - status =3D "okay"; -}; - -&uart_routing { - status =3D "okay"; -}; - -&uhci { - status =3D "okay"; -}; - -&vhub { - status =3D "okay"; - pinctrl-names =3D "default"; -}; - -&video { - status =3D "okay"; - memory-region =3D <&video_engine_memory>; -}; - -&wdt1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_wdtrst1_default>; - aspeed,reset-type =3D "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - aspeed,ext-pulse-duration =3D <256>; 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Thu, 13 Aug 2026 11:59:59 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:33 +0800 Subject: [PATCH v5 03/15] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-3-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=5864; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=uFd3k24VxEypaHLespXpLRjwFFWss5Y43arELHuz9Hk=; b=TBYlPuvOsM9bDcK0FYWJE2UD2QbC/w1OSMvXwTtlAiQWusFTznZ+jXCZ8UimnevIIFI7o6qBv nps64VLkgymDOnqklpS6+XiU74CVTB+1QXtjOHjUC5D1gP0L0UBPLE/ X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Add a development-phase devicetree for the Facebook Anacapa BMC EVT2 hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 178 +++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 179 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts new file mode 100644 index 000000000000..4a6ae7c6cbf8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-bmc-facebook-anacapa-evt1.dts" + +/ { + model =3D "Facebook Anacapa BMC"; + compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; +}; + +&sgpiom0 { + ngpios =3D <128>; + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "", "JTAG_CPLD_TRST_R_N", + "", "", + "", "", + "", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "", "", + "", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; + + status =3D "okay"; +}; + diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 209eef65cedb..1848ca347621 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 -#include "aspeed-bmc-facebook-anacapa-evt1.dts" +#include "aspeed-bmc-facebook-anacapa-evt2.dts" =20 --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D30D74734FF; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Thu, 13 Aug 2026 11:59:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786622400; bh=llREHz/Ut+hQdQkpSFZF+fPnWztP0SkUaAfxensGHXU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=f33DiTKlZNiEQQT3L8a8hwvRlEjB4eKFSJGjKx0jnc5o6Tn3LhFm8YfRhWGcGgoW8 jIXqOVmOR64D6FQ6ClkxPO2LmJa3sp0GdrGROjRjcl6PmAoAwYkpjOe3P+UGRyNjNX VE3kT71FWuE3+Ale3z+cB/JSCgZpuni9TKJSIkLk7aPVVEPnb7DFSuTwxmTNCvvISZ CRQliA+o5TqKkSb+krhIUKJjOAqHjpjEBJ8OKj03kPazdBagq45AnoFrlXz21QdhMR 0aaPsn3FF2QWtBIr8ynA3VpRwz5PEvZhJBIBOinHgjtFQ7+ec4Z9jJ2w2gxCtrR6L0 PoL0Etw3hOPnQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D805AC5DF67; Thu, 13 Aug 2026 11:59:59 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:34 +0800 Subject: [PATCH v5 04/15] ARM: dts: aspeed: anacapa: Add DVT devicetree inheriting EVT2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-4-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=6004; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=4qBFnetVkREYSIu12suaMhNwE7VlH8Jb8tWdL8ayTVM=; b=h+XFuin/EwVaKR8Pu/zT40CqOnPn11XsIfz39WpeSxBYHn4cIqgIOzfeRqU+iI4Jz/86ojQro VFD7MX6r3i3A55KF+L+DOR+tVoI8b+TBIxOCMIerHTyEmPqi3HL1x4o X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Add a development-phase devicetree for the Facebook Anacapa BMC DVT hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 178 +++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 179 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts new file mode 100644 index 000000000000..0eb547ad0ec1 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-bmc-facebook-anacapa-evt2.dts" + +/ { + model =3D "Facebook Anacapa BMC"; + compatible =3D "facebook,anacapa-bmc-dvt", "aspeed,ast2600"; +}; + +&sgpiom0 { + ngpios =3D <128>; + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", + "R_EAM1_NIC_CBL_PRSNT_L", "", + "L_EAM0_NIC_CBL_PRSNT_L", "", + "L_EAM1_NIC_CBL_PRSNT_L", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "P12V_PWR_CABLE_PRSNT_L_R", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "RBB_Cable_Present", "", + "LBB_Cable_Present", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; + + status =3D "okay"; +}; + diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 1848ca347621..c74b211c42e6 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 -#include "aspeed-bmc-facebook-anacapa-evt2.dts" +#include "aspeed-bmc-facebook-anacapa-dvt.dts" =20 --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44B3047427D; Thu, 13 Aug 2026 12:00:01 +0000 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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PHD4+8iY" Received: by smtp.kernel.org (Postfix) with ESMTPS id 14EAAC4AF0B; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786622401; bh=LdloDJM8DI8AB4ZLQsP/+vZzjiWKgFCiLWLBMA7iRMU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PHD4+8iY4g64WfA6GeqgD2dm0vqsQA/8sYXhk/vVU82SO1QyronzXhDyAVV6Ky2eX 7RtPGAyT6dTkiarhtwQABKOQ0jt/GJmUcd3irB8VNtsom8tHpt8meyHe/vt+36EbL6 QI14lFHb9qk4i+XjtYuR2z6r8d7JPyI86PszjaesIaK2hwGTnBAeMd7xkvX74Cj+ry SCqmD5ynZRDwH0KiBooGtlSsFAa/umAl0K0D5BKs/gG13DkogXDHkGoIJRfB0n6rYD 4QmiZQkD3YsEvNkWgfqXZn6YGPM51HPff8atlxqnBeHr5La3aOIx8wJtAwUwIVWNqr 4MIjavFY3mxZA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E50A5C5B572; Thu, 13 Aug 2026 11:59:59 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:35 +0800 Subject: [PATCH v5 05/15] ARM: dts: aspeed: anacapa: Add additional EEPROM node for SCM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-5-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=1250; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=NAF+xcmhfBdWvCk+Ea9KmPCdarcFxDgMq2cQBYIvfaY=; b=GHwHvs4ys0MLQH953QcqjpV0BvokVUy7o0nAOQbdm3qoZx99LemxUR3/Xq4QtB8pqC9EY7EDN /RpFy7xbMRECJ40iZUiEavkTN83q8+x9aduHyCXZl7TNP1u1n0hKvEO X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang The SCM FRU EEPROM I2C address differs between SCM revisions: - Rev B uses address 0x50 - Rev C/D/E/F and later use address 0x51 Add an additional AT24C128 EEPROM node at 0x51 on i2c9 so the same device tree can support multiple SCM revisions. Signed-off-by: Colin Huang --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 4a6ae7c6cbf8..1901a325c72c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -8,6 +8,20 @@ / { compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; }; =20 +// SCM +&i2c9 { + + // SCM FRU + // | DC-SCM Rev | Slave address of eeprom | + // |-------------------|--------------------------| + // | Rev B | 0x50 | + // | Rev C/D/E/F/above | 0x51 | + eeprom@51 { + compatible =3D "atmel,24c128"; + reg =3D <0x51>; + }; +}; + &sgpiom0 { ngpios =3D <128>; bus-frequency =3D <2000000>; --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEE8E472F83; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; cv=none; b=fhtYmrnk3JLDhvX21pIq6mwo5fMgBCXhuFI9AfptGY5cvdmHcpBfs2AzUxKi8/VKthWme17KT5470cl0qSWXm0LHKx+REntEge6A3tcjYPMUkcGKGtPynm9ubLEwRECyjRny6l8/UX6a9gCouCBXob3j3MhhoSM3Z/KvH2HCABY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; c=relaxed/simple; bh=FoLZfGD6uyaU5BQXg5Am0hO9ZEAWctWsieG0YVFNjNM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eEZ+d1KS+87hfnZz8Ywomv5WjnEwUGKj/IPBHqiLFSXrkNg2mnjsjV2KmHSCTLjqLUtU6WSigftvr0G9ELDnjHaYL2417AsLouzFeI3yVbpAYyBFw5c0GOYTMB1A/8ox9orR5E2En3R+eNh6Hx5BJ1ZLwYF/JmjdEjZ7Hwiaie4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PefcQlh6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PefcQlh6" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1CC72C2BD00; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786622400; bh=FoLZfGD6uyaU5BQXg5Am0hO9ZEAWctWsieG0YVFNjNM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PefcQlh6zJF3yqBV7Pro1oH+U96FS4z8irsFo7cGWB0KYbEJW9XnQq0Iy2Y0p4vER 23VgKDqIzIx/sGicoE7ArYXblLXemamjRiziUV2W2F9cIR8RvAEm8TgvWfNOrnHB0+ CdET7ijOCyrLxxw9vMME67nhYjx4H8uGAMSQeRe0f7k6WLstVKeszeNldKxM6+0vRY oa1JX6zbbNXFefM1xwcOQwvYOH1ZqTi0tOeHKQrQds+H1aE033GOnJreXE9fSDznva 7q9NL952mfbKwHuz/2zmuUtaf9I4PCfkUwowPwIBJ4krlauxoN8naK2sIAT28e8wpJ SXycH123+c+aQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F052BC5DF69; Thu, 13 Aug 2026 11:59:59 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:36 +0800 Subject: [PATCH v5 06/15] ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-6-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Carl Lee X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=854; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=ogPWoxlP9zHHWVbVILynjOOXZGqV6RgIxVGA6kDFSUc=; b=Xzj5DalG+aiFRpcfA+06+fcwnTU8Td1CoS3EF2nJ5pr8VMxHJSPZM4kgMCqrGfQel1OgpTWXY m6bbLJwFz0HB/09rm20/yqzgZ50lBUxpVgIiwp7Djc447ulFCRvaS15 X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Carl Lee Add eeprom device node for NFC adaptor board FRU. Signed-off-by: Carl Lee --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 13 +++++++++= ++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 1901a325c72c..c7bffa7c6557 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -22,6 +22,19 @@ eeprom@51 { }; }; =20 +// MB +&i2c13 { + i2c-mux@70 { + i2c13mux0ch7: i2c@7 { + // NFC adaptor board FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + }; +}; + &sgpiom0 { ngpios =3D <128>; bus-frequency =3D <2000000>; --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEF41472F8A; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; cv=none; b=A77oK8PZ4pfxOMY+EsB5Wyo30MSC2xiBml/ol7lJeTYFXJnFJT69TUqrGkuU8xXOh0pM8O6jzgMDVaGHWE0cPTF/3wB4G50e7w3oJtLNJxn0ERAg9I1iNuCY8gjEGduC9Pb7xC0Ly4MTSRD0WEp+GlGdKtpczI/SuQJWN7ZWnK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; c=relaxed/simple; bh=k65C478t9LS6ybUmJ6TjN8D7vgzFZCksmeumxEQZ8Wo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KuMlxiWjLkqbaSVJ2hNm3WvspUv19VN58gygA1wetWFfwb/ZiQeFzZ9sAu7NXEAlYQZfF7ojGiLFX8qjmNJWMjqLxFr1NlN6oinRvgh0f29NWlgJTtx8dHBeQ2rbQn7TDQ2iLHSZ+6DXaEmZiSOfm5MvqW08TwHlF/0b1RfL7rA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lvkB3xA7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lvkB3xA7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 25CC0C32781; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786622400; bh=k65C478t9LS6ybUmJ6TjN8D7vgzFZCksmeumxEQZ8Wo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lvkB3xA7ZUggxd62T2EQdw29xvWCTWX6bJJz+bv5e3lV5Z5jjg4PIz44Z8PaKqAqe URTHnHOZc4VJYwisaeW4yRbtSRot98AoINoaiUHClmGXbo1aZHTAD541JBgcqpC3IV JLX2droK/jfcTpvsYfL3olU73L3YrAaQah23BFUlSdhP/APMRU/Jbc9o5RH1wQuG25 PWuA9UseUiPj8e3ZvrlvLXK++5hk1bjtJGO2qr5CZk0+Fhq9zlLuXAlRvJmAjT+3P0 GEGPeU8XxXdn2UyK/OjokxrglaGBOUoDXIdeuaEZLbDW5O5x4Dv87otw6K+WyOVVVX Ky4+5mwTGH13Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B8A0C5CFDB; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:37 +0800 Subject: [PATCH v5 07/15] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-7-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=1875; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=3/IZc5ckSnwOY8uhbyA0jZSDZ3Dvh/PJORxqtTJG7yA=; b=Gi8/BUaK6w/lKB1qUOTSspYGZjOdu9INBp5iNvnYDcG7DCdDLt20S4ocFvStYtDvtxWDm9KIa 26YnUygqETECBixfRo80FOtfZv9WwQ0KpDk9+SXwm+/70w3t5dDt6+y X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Update the LPDB and RPDB fan GPIO line names to align with the platform fan numbering scheme. The LPDB fan GPIOs are named FAN0 through FAN4, while the RPDB fan GPIOs are named FAN5 through FAN8. This keeps the GPIO line names consistent with the fan inventory and platform-level fan numbering. Signed-off-by: Rex Fu Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 33 ++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index c7bffa7c6557..ff393ad7cdb7 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -8,6 +8,39 @@ / { compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; }; =20 +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c8mux0ch0: i2c@0 { + gpio@24 { + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + }; + i2c8mux0ch1: i2c@1 { + gpio@24 { + gpio-line-names =3D + "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG","LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG","LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R","LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R","LPDB_FAN4_PRSNT_N_R", + "","", + "","", + "",""; + }; + }; + }; +}; + // SCM &i2c9 { =20 --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2D2F473C9C; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622401; cv=none; b=G/9tugy+2Yg0CbqkH1bRQI2vtkDhIdH9j8ZlbsAAMJa5ZGVCLd3wKE+WV25FXNGUBcflGMmTI9P5vi9miDm47bQnKf6LqS/2awlir8mGAPH1+jphgnhAR8J46U2txjz1ZmcyplMnJywuSJ76IBf+MpIs+u2lskwLftxGFemCwiU= ARC-Message-Signature: i=1; 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a=ed25519-sha256; t=1786622378; l=3214; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=BGZCKTF8QAag1qskLE0ofPzySUEOSMb3NZgJbIMmwIo=; b=tRnCdt4HSTs3hCltmEhSl2IJBUqZkdHlCNGz1d1Sabm22vJGqKb75T93B8qcX0xc4HkM3vwlY ISTLQn7AdYgCzKvzR3UwUsQynWFKP2PSEpnvc/tFoR7VwEn963jPVMO X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Andy Chung Add the mctp-controller property to enable frontend NIC management via PLDM over MCTP. Also add EEPROM device for NIC FRU and reorder the I2C virtual bus index accroding to the system silkscreen index. Signed-off-by: Andy Chung --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 119 +++++++++++++++++= ++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index ff393ad7cdb7..703284721224 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -8,6 +8,25 @@ / { compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; }; =20 +&{/aliases} { + i2c36 =3D &i2c11mux0ch5; + i2c37 =3D &i2c11mux0ch6; + i2c38 =3D &i2c11mux0ch7; + i2c39 =3D &i2c11mux0ch0; + i2c40 =3D &i2c11mux0ch1; + i2c41 =3D &i2c11mux0ch2; + i2c42 =3D &i2c11mux0ch3; + i2c43 =3D &i2c11mux0ch4; + i2c44 =3D &i2c10mux0ch1; + i2c45 =3D &i2c10mux0ch2; + i2c46 =3D &i2c10mux0ch3; + i2c47 =3D &i2c10mux0ch4; + i2c48 =3D &i2c10mux0ch5; + i2c49 =3D &i2c10mux0ch6; + i2c50 =3D &i2c10mux0ch7; + i2c51 =3D &i2c10mux0ch0; +}; + // MB - PDB &i2c8 { i2c-mux@72 { @@ -55,6 +74,106 @@ eeprom@51 { }; }; =20 +// R Bridge Board +&i2c10 { + multi-master; + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c10mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c10mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c10mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c10mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + }; +}; + +// L Bridge Board +&i2c11 { + multi-master; + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-9-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Peter Shen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=2147; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=WNTfq2afBfA8+J3QozrER71+gm8MPJIV48F5xeH186s=; b=523oHOdDWNNkRW7XTPHdzWMnEQ5tIse+VNgOaa8eWqFLogKrRThVuWdrld7oCDY3L8NeG0j/J 3HRRLnhQlH8AQcnA3yfPRny/BtFO39kPcKvvyRdhbeRq0QuOKvauhYy X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Add shunt resistor configuration for LTC4287 hot-swap controllers on Anacapa EVT2 platform. The resistor values are required for accurate current and power measurement by the driver. These settings reflect the actual BOM used on EVT2, where different sense resistor values (150 uOhm and 250 uOhm) are populated across rails. Without this configuration, the reported readings would be incorrect. Signed-off-by: Peter Shen --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 35 ++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 703284721224..f913fa3f622d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -31,6 +31,26 @@ / { &i2c8 { i2c-mux@72 { i2c8mux0ch0: i2c@0 { + power-monitor@42 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x42>; + shunt-resistor-micro-ohms =3D <150>; + }; + power-monitor@43 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x43>; + shunt-resistor-micro-ohms =3D <150>; + }; + power-monitor@44 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x44>; + shunt-resistor-micro-ohms =3D <250>; + }; + power-monitor@45 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x45>; + shunt-resistor-micro-ohms =3D <250>; + }; gpio@24 { gpio-line-names =3D "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", @@ -45,6 +65,21 @@ gpio@24 { }; }; i2c8mux0ch1: i2c@1 { + power-monitor@40 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x40>; + shunt-resistor-micro-ohms =3D <150>; + }; + power-monitor@41 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x41>; + shunt-resistor-micro-ohms =3D <150>; + }; + power-monitor@45 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x45>; + shunt-resistor-micro-ohms =3D <250>; + }; gpio@24 { gpio-line-names =3D "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2469473C8C; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622401; cv=none; b=JbX4KU7OIEEwTjVdWEh+6WoG8SPc254fink9vdxVjCiZXYGLaKBj1WHUWlWZQE3qlmF16EBvTR/mAUWIqajDadFPOhcc7U/DGwzUYxmTG/1r4oojYyA+maJ54/2+5YcqWQKi8S3eBmKFcZyftDFCdOZ1K8sC7D0TA//uL6ZqaN8= ARC-Message-Signature: i=1; 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b=CDTLL/gr1So9I4/cCdLXlp0oyJFuhpj/N2CtoHB+1bhvJzPDp4pG7APAwNH1GNtDn xtT6/ZjSPxwxTErTCYw1F2rC2k/etY89VpS0JrFosxzd3IlXfNjuVpjN8d8MBm9ACL uDR8sveCpp7tAARnfmpSj1vxBH49BwliEnNPyo6oh+yYfc+MM4oze0WJx58kx6TY9s T3lJa+MzxL4yBgzjl63EpB2Uxqpr2LeM293+UcGzEth1GabD5KsZ3LiQuZ8w/gWy22 rkhnba1Mu3qx2vy+PSlcpI3PYK2Ug3wj/pxYJDv9ZLb7Z4WV0h8d/Rqi9pluvEXRVb T32IgLMo6bbpw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33935C5CFEB; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:40 +0800 Subject: [PATCH v5 10/15] ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-10-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=3733; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=iRt5dSDALZ6dumrYugDV1SM8iNqVZO1lxfanv1TXY2Q=; b=Rcpi1/hWJBtFFO983ci0PvRhB4Kf7s3+Vwvvx17PoSzpamxGe+SeVUlZawFIYbGG1p7o1uFHX qzZgAW53nUGAedIhMAIWmmhjlTOsXNJhbyYzEZjWYBakVTSYzCWfX/M X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Add PCA9554 GPIO expanders for PDB fuse monitor signals on the Anacapa DVT board. The patch adds GPIO expander definitions for both the left and right PDBs under the i2c8 multiplexer and updates the associated gpio-line-names to reflect the final signal assignments. Signed-off-by: Rex Fu --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 87 ++++++++++++++++++= ++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts index 0eb547ad0ec1..f09dd1abe77d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -8,6 +8,93 @@ / { compatible =3D "facebook,anacapa-bmc-dvt", "aspeed,ast2600"; }; =20 +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c8mux0ch0: i2c@0 { + gpio@22 { + gpio-line-names =3D + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TMP432_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "RPDB_VERID_A0", + "RPDB_VERID_A1", "RPDB_VERID_A2", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_P12V_MB_VRM_ALERT_R_N", + "RPDB_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + gpio@24 { + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "RPDB_SKU_ID0", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + gpio@38 { + compatible =3D "nxp,pca9554"; + reg =3D <0x38>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "RPDB_P50V_FUSE2_TVS1", "RPDB_P50V_FUSE2_TVS2", + "RPDB_P50V_FUSE3_TVS1", "RPDB_P50V_FUSE3_TVS2", + "RPDB_P50V_FUSE4_TVS1", "", + "", ""; + }; + }; + i2c8mux0ch1: i2c@1 { + gpio@22 { + gpio-line-names =3D + "LPDB_FAN_FULL_SPEED_R_N", "LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N", "LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N", "LPDB_VERID_A0", + "LPDB_VERID_A1", "LPDB_VERID_A2", + "LPDB_ALERT_P50V_HSC0_R_N", "LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N", "LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R", "LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R", "BARKLIP_PRSNT_N_R3"; + }; + gpio@24 { + gpio-line-names =3D + "LPDB_P50V_FAN0_R2_PG", "LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG", "LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG", "LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R", "LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R", "LPDB_FAN4_PRSNT_N_R", + "LPDB_SKU_ID0", "", + "", "", + "", "LPDB_PG_P3V3_R"; + }; + gpio@38 { + compatible =3D "nxp,pca9554"; + reg =3D <0x38>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "LPDB_P50V_FUSE0_TVS1", "LPDB_P50V_FUSE0_TVS2", + "LPDB_P50V_FUSE1_TVS1", "LPDB_P50V_FUSE1_TVS2", + "LPDB_P50V_FUSE5_TVS1", "", + "", ""; + }; + }; + }; +}; + &sgpiom0 { ngpios =3D <128>; bus-frequency =3D <2000000>; --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F063474261; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-11-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=2439; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=vmghXUBmwzP2rgOwg7WGwWzuzw+iRgP5cEGqkIrQPXw=; b=pEFjHbiPWEuuAx+9aKAgOXonLGB9aaADwUMzcXOZvctDmNGlfeDK6UPme8VQqK7e1ouGlwKsb soUm2NLhSotCEnIOPDuSe0xobuTniSUSZ/Uqyk8hbrtbeoc2Y1Saz7W X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Remove the board location suffixes from the leakage present GPIO line names. The channel number is enough to identify each leakage present signal. Signed-off-by: Rex Fu --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 28 +++++++++++-------= ---- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts index f09dd1abe77d..f710046f79bc 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -111,32 +111,32 @@ &sgpiom0 { "", "", =20 /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", - "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", - "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", - "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + "Channel0_leakage", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage", "CPLD_BUF_R_AGPIO331", =20 /* C0-C7 line 32-47 */ "RSVD_RMC_GPIO3", "RTM_MUX_L", "LEAK_DETECT_RMC_N", "RTM_MUX_R", "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", - "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "Channel6_leakage_present", "whdt_sel", "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", "R_EAM1_NIC_CBL_PRSNT_L", "", "L_EAM0_NIC_CBL_PRSNT_L", "", "L_EAM1_NIC_CBL_PRSNT_L", "", =20 /* D0-D7 line 48-63 */ - "Channel0_leakage_present_EAM3", "", - "Channel1_leakage_present_EAM0", "", - "Channel2_leakage_present_Manifold1", "", - "Channel4_leakage_present_Manifold2", "", + "Channel0_leakage_present", "", + "Channel1_leakage_present", "", + "Channel2_leakage_present", "", + "Channel4_leakage_present", "", "AMC_BRD_PRSNT_CPLD_L", "", - "Channel7_leakage_present_EAM2", "", + "Channel7_leakage_present", "", "", "", "", "", =20 --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44C5F47427F; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-12-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=941; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=f6LU0FAv4z223NfwbW5+xtWf2s69Q4QEuw+6jPL4YpI=; b=hxmqSUUNDPFUSi5olnMyqpzfvJ1Z1bOj6dU+/km8oNPb+g1XvRmOkm/uKa1kUDaYRoIa0YqE9 2aaFkPODsyODkknuDeC+bw75S52+eNE2N5JNs+wP2WhQZQqClhSoVSv X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Specify the 3.3 V auxiliary rail as the SPI flash VCC supply to avoid using the dummy regulator during device initialization. Signed-off-by: Rex Fu --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index f913fa3f622d..cb4b815f1803 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -27,6 +27,22 @@ / { i2c51 =3D &i2c10mux0ch0; }; =20 +&fmc { + flash@0 { + vcc-supply =3D <&p3v3_bmc_aux>; + }; + flash@1 { + vcc-supply =3D <&p3v3_bmc_aux>; + }; +}; + +// BIOS Flash +&spi2 { + flash@0 { + vcc-supply =3D <&p3v3_bmc_aux>; + }; +}; + // MB - PDB &i2c8 { i2c-mux@72 { --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44A2447427A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-13-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=27217; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=9caKRgfNZf0Q4hB3JVLKUxfesytPJFOG/3lCSi3lw6E=; b=jURynCfVVIrHtCYGVcEvex+UT4750m5a3pSQXZu5oXxq+yPoBghHXqg6aDDHDW/O1Pn7dREOa RC5B7uKBOB5A+nWKW1SAUaBfM2ekxjDgU9udglCO+U6khL2doxEImnF X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Run scripts/dtc/dt-check-style --mode strict against the Facebook Anacapa board device trees and fix the reported violations: - aspeed-bmc-facebook-anacapa.dts: drop a duplicate trailing blank line at end of file. - aspeed-bmc-facebook-anacapa-dvt.dts, aspeed-bmc-facebook-anacapa-evt2.dts, aspeed-bmc-facebook-anacapa-evt1.dts: - reorder compatible/model so compatible comes first - add required blank lines before child nodes and before the status property - sort properties into the tool's canonical bucket order (e.g. bus-frequency before gpio-line-names before ngpios before status in the &sgpiom0 override, m25p,fast-read/label ordering in flash@0, #gpio-cells/gpio-controller/gpio-line-names ordering in gpio@24 and gpio@38) - align multi-line property continuations (io-channels, pinctrl-0) under the opening '<' column - fix child-name-order and child-address-order violations (framebuffer before video in reserved-memory, gpio@24 before power-monitor@N, regulator-p3v3-bmc-aux before reserved-memory) - remove redundant node labels that were never &-referenced anywhere in the tree (i2c8mux0ch0, i2c8mux0ch1, i2c13mux0ch7, spi_gpio); these labels only existed for node-merge overrides via #include and are not needed since nodes merge by name and unit address One unused-labels warning remains in evt1.dts for the p3v3_bmc_aux label: it is genuinely referenced via "&p3v3_bmc_aux" in aspeed-bmc-facebook-anacapa-evt2.dts, which #include's evt1.dts. dt-check-style only tracks same-file references for non-.dtsi files, so this is a known false positive of the per-file checker given this board family's #include-based override architecture, and is not fixed here to avoid breaking the regulator reference. All four files pass "dt-check-style --mode strict" except for that documented false positive. Signed-off-by: Colin Huang --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 31 +-- .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 222 +++++++++++++----= ---- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 83 +++++--- .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1 - 4 files changed, 210 insertions(+), 127 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts index f710046f79bc..ce5aecc984c8 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -4,14 +4,14 @@ #include "aspeed-bmc-facebook-anacapa-evt2.dts" =20 / { - model =3D "Facebook Anacapa BMC"; compatible =3D "facebook,anacapa-bmc-dvt", "aspeed,ast2600"; + model =3D "Facebook Anacapa BMC"; }; =20 // MB - PDB &i2c8 { i2c-mux@72 { - i2c8mux0ch0: i2c@0 { + i2c@0 { gpio@22 { gpio-line-names =3D "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TMP432_U8_ALERT_R_N", @@ -25,6 +25,7 @@ gpio@22 { "RPDB_PGD_P3V3_STBY_PWRGD_R", "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; }; + gpio@24 { gpio-line-names =3D "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", @@ -37,23 +38,25 @@ gpio@24 { "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", "", ""; }; + gpio@38 { compatible =3D "nxp,pca9554"; reg =3D <0x38>; - gpio-controller; #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; =20 gpio-line-names =3D "RPDB_P50V_FUSE2_TVS1", "RPDB_P50V_FUSE2_TVS2", "RPDB_P50V_FUSE3_TVS1", "RPDB_P50V_FUSE3_TVS2", "RPDB_P50V_FUSE4_TVS1", "", "", ""; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; }; }; - i2c8mux0ch1: i2c@1 { + + i2c@1 { gpio@22 { gpio-line-names =3D "LPDB_FAN_FULL_SPEED_R_N", "LPDB_I2C_TEMP75_U8_ALERT_R_N", @@ -65,6 +68,7 @@ gpio@22 { "LPDB_EAM0_PRSNT_MOS_N_R", "LPDB_EAM1_PRSNT_MOS_N_R", "LPDB_PWRGD_P50V_HSC5_SYS_R", "BARKLIP_PRSNT_N_R3"; }; + gpio@24 { gpio-line-names =3D "LPDB_P50V_FAN0_R2_PG", "LPDB_P50V_FAN1_R2_PG", @@ -76,27 +80,27 @@ gpio@24 { "", "", "", "LPDB_PG_P3V3_R"; }; + gpio@38 { compatible =3D "nxp,pca9554"; reg =3D <0x38>; - gpio-controller; #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; =20 gpio-line-names =3D "LPDB_P50V_FUSE0_TVS1", "LPDB_P50V_FUSE0_TVS2", "LPDB_P50V_FUSE1_TVS1", "LPDB_P50V_FUSE1_TVS2", "LPDB_P50V_FUSE5_TVS1", "", "", ""; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; }; }; }; }; =20 &sgpiom0 { - ngpios =3D <128>; bus-frequency =3D <2000000>; gpio-line-names =3D /*in - out */ @@ -260,6 +264,7 @@ &sgpiom0 { "AMC_FAIL", "HPM_CPLD_RISCV_RST", "S0_ON", ""; =20 + ngpios =3D <128>; + status =3D "okay"; }; - diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts index a095be48a3fe..f27ec52f9d56 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts @@ -6,15 +6,10 @@ #include =20 / { - model =3D "Facebook Anacapa BMC"; compatible =3D "facebook,anacapa-bmc-evt1", "aspeed,ast2600"; + model =3D "Facebook Anacapa BMC"; =20 aliases { - serial0 =3D &uart1; - serial1 =3D &uart2; - serial2 =3D &uart3; - serial3 =3D &uart4; - serial4 =3D &uart5; i2c16 =3D &i2c0mux0ch0; i2c17 =3D &i2c0mux0ch1; i2c18 =3D &i2c0mux0ch2; @@ -59,6 +54,11 @@ aliases { i2c57 =3D &i2c13mux0ch5; i2c58 =3D &i2c13mux0ch6; i2c59 =3D &i2c13mux0ch7; + serial0 =3D &uart1; + serial1 =3D &uart2; + serial2 =3D &uart3; + serial3 =3D &uart4; + serial4 =3D &uart5; }; =20 chosen { @@ -68,93 +68,96 @@ chosen { iio-hwmon { compatible =3D "iio-hwmon"; io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 2>; + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; }; =20 leds { compatible =3D "gpio-leds"; =20 led-0 { - label =3D "bmc_heartbeat_amber"; gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + label =3D "bmc_heartbeat_amber"; linux,default-trigger =3D "heartbeat"; }; =20 led-1 { - label =3D "fp_id_amber"; default-state =3D "off"; gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + label =3D "fp_id_amber"; }; }; =20 memory@80000000 { - device_type =3D "memory"; reg =3D <0x80000000 0x80000000>; + device_type =3D "memory"; + }; + + p3v3_bmc_aux: regulator-p3v3-bmc-aux { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "p3v3_bmc_aux"; }; =20 reserved-memory { + ranges; #address-cells =3D <1>; #size-cells =3D <1>; - ranges; =20 - video_engine_memory: video { - size =3D <0x02c00000>; - alignment =3D <0x00100000>; + gfx_memory: framebuffer { compatible =3D "shared-dma-pool"; + alignment =3D <0x01000000>; reusable; + size =3D <0x01000000>; }; =20 - gfx_memory: framebuffer { - size =3D <0x01000000>; - alignment =3D <0x01000000>; + video_engine_memory: video { compatible =3D "shared-dma-pool"; + alignment =3D <0x00100000>; reusable; + size =3D <0x02c00000>; }; }; =20 - p3v3_bmc_aux: regulator-p3v3-bmc-aux { - compatible =3D "regulator-fixed"; - regulator-name =3D "p3v3_bmc_aux"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - }; - - spi_gpio: spi { + spi { compatible =3D "spi-gpio"; #address-cells =3D <1>; - #size-cells =3D <0>; + cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; =20 - sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; - cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; num-chipselects =3D <1>; + sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + #size-cells =3D <0>; + status =3D "okay"; =20 tpm@0 { compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; - spi-max-frequency =3D <33000000>; reg =3D <0>; + spi-max-frequency =3D <33000000>; }; }; }; =20 &adc0 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + pinctrl-names =3D "default"; + aspeed,int-vref-microvolt =3D <2500000>; + status =3D "okay"; }; =20 &adc1 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_adc10_default>; + pinctrl-names =3D "default"; + aspeed,int-vref-microvolt =3D <2500000>; + status =3D "okay"; }; =20 @@ -166,24 +169,27 @@ &fmc { status =3D "okay"; =20 flash@0 { - status =3D "okay"; - m25p,fast-read; label =3D "bmc"; spi-max-frequency =3D <50000000>; + m25p,fast-read; + + status =3D "okay"; #include "openbmc-flash-layout-128.dtsi" }; =20 flash@1 { - status =3D "okay"; - m25p,fast-read; label =3D "alt-bmc"; spi-max-frequency =3D <50000000>; + m25p,fast-read; + + status =3D "okay"; }; }; =20 &gfx { - status =3D "okay"; memory-region =3D <&gfx_memory>; + + status =3D "okay"; }; =20 &gpio0 { @@ -310,24 +316,27 @@ i2c-mux@70 { compatible =3D "nxp,pca9546"; reg =3D <0x70>; #address-cells =3D <1>; - #size-cells =3D <0>; i2c-mux-idle-disconnect; + #size-cells =3D <0>; =20 i2c0mux0ch0: i2c@0 { reg =3D <0>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c0mux0ch1: i2c@1 { reg =3D <1>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c0mux0ch2: i2c@2 { reg =3D <2>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c0mux0ch3: i2c@3 { reg =3D <3>; #address-cells =3D <1>; @@ -350,24 +359,27 @@ i2c-mux@70 { compatible =3D "nxp,pca9546"; reg =3D <0x70>; #address-cells =3D <1>; - #size-cells =3D <0>; i2c-mux-idle-disconnect; + #size-cells =3D <0>; =20 i2c1mux0ch0: i2c@0 { reg =3D <0>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c1mux0ch1: i2c@1 { reg =3D <1>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c1mux0ch2: i2c@2 { reg =3D <2>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c1mux0ch3: i2c@3 { reg =3D <3>; #address-cells =3D <1>; @@ -384,44 +396,51 @@ i2c-mux@70 { compatible =3D "nxp,pca9548"; reg =3D <0x70>; #address-cells =3D <1>; - #size-cells =3D <0>; i2c-mux-idle-disconnect; + #size-cells =3D <0>; =20 i2c4mux0ch0: i2c@0 { reg =3D <0>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c4mux0ch1: i2c@1 { reg =3D <1>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c4mux0ch2: i2c@2 { reg =3D <2>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c4mux0ch3: i2c@3 { reg =3D <3>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c4mux0ch4: i2c@4 { reg =3D <4>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c4mux0ch5: i2c@5 { reg =3D <5>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c4mux0ch6: i2c@6 { reg =3D <6>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c4mux0ch7: i2c@7 { reg =3D <7>; #address-cells =3D <1>; @@ -449,8 +468,6 @@ eeprom@50 { // SCM &i2c7 { status =3D "okay"; - - }; =20 // MB - PDB @@ -461,8 +478,8 @@ i2c-mux@72 { compatible =3D "nxp,pca9546"; reg =3D <0x72>; #address-cells =3D <1>; - #size-cells =3D <0>; i2c-mux-idle-disconnect; + #size-cells =3D <0>; =20 i2c8mux0ch0: i2c@0 { reg =3D <0>; @@ -478,11 +495,8 @@ adc@1f { gpio@22 { compatible =3D "nxp,pca9555"; reg =3D <0x22>; - gpio-controller; #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; =20 gpio-line-names =3D "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", @@ -495,16 +509,16 @@ gpio@22 { "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", "RPDB_PGD_P3V3_STBY_PWRGD_R", "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; }; =20 gpio@24 { compatible =3D "nxp,pca9555"; reg =3D <0x24>; - gpio-controller; #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; =20 gpio-line-names =3D "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", @@ -516,6 +530,9 @@ gpio@24 { "", "RPDB_FAN2_PRSNT_N_R", "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", "", ""; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; }; =20 // R-PDB FRU @@ -524,6 +541,7 @@ eeprom@50 { reg =3D <0x50>; }; }; + i2c8mux0ch1: i2c@1 { reg =3D <1>; #address-cells =3D <1>; @@ -532,11 +550,8 @@ i2c8mux0ch1: i2c@1 { gpio@22 { compatible =3D "nxp,pca9555"; reg =3D <0x22>; - gpio-controller; #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; =20 gpio-line-names =3D "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", @@ -547,16 +562,16 @@ gpio@22 { "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", "LPDB_PWRGD_P50V_HSC5_SYS_R",""; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; }; =20 gpio@24 { compatible =3D "nxp,pca9555"; reg =3D <0x24>; - gpio-controller; #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; =20 gpio-line-names =3D "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", @@ -567,6 +582,9 @@ gpio@24 { "","", "","", "",""; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; }; =20 // L-PDB FRU @@ -575,11 +593,13 @@ eeprom@50 { reg =3D <0x50>; }; }; + i2c8mux0ch2: i2c@2 { reg =3D <2>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c8mux0ch3: i2c@3 { reg =3D <3>; #address-cells =3D <1>; @@ -613,34 +633,39 @@ i2c-mux@71 { compatible =3D "nxp,pca9548"; reg =3D <0x71>; #address-cells =3D <1>; - #size-cells =3D <0>; i2c-mux-idle-disconnect; + #size-cells =3D <0>; =20 i2c10mux0ch0: i2c@0 { reg =3D <0>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c10mux0ch1: i2c@1 { reg =3D <1>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c10mux0ch2: i2c@2 { reg =3D <2>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c10mux0ch3: i2c@3 { reg =3D <3>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c10mux0ch4: i2c@4 { reg =3D <4>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c10mux0ch5: i2c@5 { reg =3D <5>; #address-cells =3D <1>; @@ -649,8 +674,8 @@ i2c10mux0ch5: i2c@5 { gpio@22 { compatible =3D "nxp,pca9555"; reg =3D <0x22>; - gpio-controller; #gpio-cells =3D <2>; + gpio-controller; =20 gpio-line-names =3D "","", @@ -669,11 +694,13 @@ eeprom@52 { reg =3D <0x52>; }; }; + i2c10mux0ch6: i2c@6 { reg =3D <6>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c10mux0ch7: i2c@7 { reg =3D <7>; #address-cells =3D <1>; @@ -690,34 +717,39 @@ i2c-mux@71 { compatible =3D "nxp,pca9548"; reg =3D <0x71>; #address-cells =3D <1>; - #size-cells =3D <0>; i2c-mux-idle-disconnect; + #size-cells =3D <0>; =20 i2c11mux0ch0: i2c@0 { reg =3D <0>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c11mux0ch1: i2c@1 { reg =3D <1>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c11mux0ch2: i2c@2 { reg =3D <2>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c11mux0ch3: i2c@3 { reg =3D <3>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c11mux0ch4: i2c@4 { reg =3D <4>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c11mux0ch5: i2c@5 { reg =3D <5>; #address-cells =3D <1>; @@ -726,8 +758,8 @@ i2c11mux0ch5: i2c@5 { gpio@22 { compatible =3D "nxp,pca9555"; reg =3D <0x22>; - gpio-controller; #gpio-cells =3D <2>; + gpio-controller; =20 gpio-line-names =3D "","", @@ -746,11 +778,13 @@ eeprom@52 { reg =3D <0x52>; }; }; + i2c11mux0ch6: i2c@6 { reg =3D <6>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c11mux0ch7: i2c@7 { reg =3D <7>; #address-cells =3D <1>; @@ -772,24 +806,27 @@ i2c-mux@70 { compatible =3D "nxp,pca9548"; reg =3D <0x70>; #address-cells =3D <1>; - #size-cells =3D <0>; i2c-mux-idle-disconnect; + #size-cells =3D <0>; =20 i2c13mux0ch0: i2c@0 { reg =3D <0>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c13mux0ch1: i2c@1 { reg =3D <1>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c13mux0ch2: i2c@2 { reg =3D <2>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c13mux0ch3: i2c@3 { reg =3D <3>; #address-cells =3D <1>; @@ -801,6 +838,7 @@ adc@1f { ti,mode =3D /bits/ 8 <1>; }; }; + i2c13mux0ch4: i2c@4 { reg =3D <4>; #address-cells =3D <1>; @@ -812,16 +850,19 @@ eeprom@51 { reg =3D <0x51>; }; }; + i2c13mux0ch5: i2c@5 { reg =3D <5>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c13mux0ch6: i2c@6 { reg =3D <6>; #address-cells =3D <1>; #size-cells =3D <0>; }; + i2c13mux0ch7: i2c@7 { reg =3D <7>; #address-cells =3D <1>; @@ -831,10 +872,10 @@ nfc@28 { compatible =3D "nxp,nxp-nci-i2c"; reg =3D <0x28>; =20 + enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; interrupt-parent =3D <&sgpiom0>; - interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; =20 - enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; + interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; }; }; }; @@ -851,11 +892,13 @@ &i2c15 { =20 &kcs2 { aspeed,lpc-io-reg =3D <0xca8>; + status =3D "okay"; }; =20 &kcs3 { aspeed,lpc-io-reg =3D <0xca2>; + status =3D "okay"; }; =20 @@ -864,14 +907,14 @@ &lpc_ctrl { }; =20 &mac2 { - status =3D "okay"; - pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_ncsi3_default>; + pinctrl-names =3D "default"; use-ncsi; + + status =3D "okay"; }; =20 &sgpiom0 { - ngpios =3D <128>; bus-frequency =3D <2000000>; gpio-line-names =3D /*in - out - in - out */ @@ -1011,22 +1054,28 @@ &sgpiom0 { "FM_PWRGD_CPU0_PWROK", "", "wS5_PWR_Ready", "", "wS0_ON_N", "PWRGD_P1V0_AUX"; + + ngpios =3D <128>; + status =3D "okay"; }; =20 // BIOS Flash &spi2 { - pinctrl-names =3D "default"; + reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; pinctrl-0 =3D <&pinctrl_spi2_default>; + + pinctrl-names =3D "default"; + status =3D "okay"; - reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; =20 flash@0 { compatible =3D "jedec,spi-nor"; label =3D "pnor"; spi-max-frequency =3D <12000000>; - spi-tx-bus-width =3D <2>; spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + status =3D "okay"; }; }; @@ -1058,22 +1107,25 @@ &uhci { }; =20 &vhub { - status =3D "okay"; pinctrl-names =3D "default"; + + status =3D "okay"; }; =20 &video { - status =3D "okay"; memory-region =3D <&video_engine_memory>; + + status =3D "okay"; }; =20 &wdt1 { - pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_wdtrst1_default>; - aspeed,reset-type =3D "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; + pinctrl-names =3D "default"; aspeed,ext-active-high; aspeed,ext-pulse-duration =3D <256>; + aspeed,ext-push-pull; + aspeed,external-signal; + aspeed,reset-type =3D "soc"; + status =3D "okay"; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index cb4b815f1803..482ba3f161ed 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -4,8 +4,8 @@ #include "aspeed-bmc-facebook-anacapa-evt1.dts" =20 / { - model =3D "Facebook Anacapa BMC"; compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; + model =3D "Facebook Anacapa BMC"; }; =20 &{/aliases} { @@ -31,6 +31,7 @@ &fmc { flash@0 { vcc-supply =3D <&p3v3_bmc_aux>; }; + flash@1 { vcc-supply =3D <&p3v3_bmc_aux>; }; @@ -46,79 +47,87 @@ flash@0 { // MB - PDB &i2c8 { i2c-mux@72 { - i2c8mux0ch0: i2c@0 { + i2c@0 { + gpio@24 { + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + power-monitor@42 { compatible =3D "lltc,ltc4287"; reg =3D <0x42>; shunt-resistor-micro-ohms =3D <150>; }; + power-monitor@43 { compatible =3D "lltc,ltc4287"; reg =3D <0x43>; shunt-resistor-micro-ohms =3D <150>; }; + power-monitor@44 { compatible =3D "lltc,ltc4287"; reg =3D <0x44>; shunt-resistor-micro-ohms =3D <250>; }; + power-monitor@45 { compatible =3D "lltc,ltc4287"; reg =3D <0x45>; shunt-resistor-micro-ohms =3D <250>; }; + }; + + i2c@1 { gpio@24 { gpio-line-names =3D - "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", - "RPDB_PWRGD_P50V_HSC4_SYS_R", - "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", - "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", - "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", - "", "RPDB_FAN5_PRSNT_N_R", - "", "RPDB_FAN6_PRSNT_N_R", - "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", - "", ""; + "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG","LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG","LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R","LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R","LPDB_FAN4_PRSNT_N_R", + "","", + "","", + "",""; }; - }; - i2c8mux0ch1: i2c@1 { + power-monitor@40 { compatible =3D "lltc,ltc4287"; reg =3D <0x40>; shunt-resistor-micro-ohms =3D <150>; }; + power-monitor@41 { compatible =3D "lltc,ltc4287"; reg =3D <0x41>; shunt-resistor-micro-ohms =3D <150>; }; + power-monitor@45 { compatible =3D "lltc,ltc4287"; reg =3D <0x45>; shunt-resistor-micro-ohms =3D <250>; }; - gpio@24 { - gpio-line-names =3D - "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", - "LPDB_P50V_FAN2_R2_PG","LPDB_P50V_FAN3_R2_PG", - "LPDB_P50V_FAN4_R2_PG","LPDB_FAN0_PRSNT_N_R", - "LPDB_FAN1_PRSNT_N_R","LPDB_FAN2_PRSNT_N_R", - "LPDB_FAN3_PRSNT_N_R","LPDB_FAN4_PRSNT_N_R", - "","", - "","", - "",""; - }; }; }; }; =20 // SCM &i2c9 { - // SCM FRU // | DC-SCM Rev | Slave address of eeprom | // |-------------------|--------------------------| // | Rev B | 0x50 | // | Rev C/D/E/F/above | 0x51 | + eeprom@51 { compatible =3D "atmel,24c128"; reg =3D <0x51>; @@ -128,6 +137,7 @@ eeprom@51 { // R Bridge Board &i2c10 { multi-master; + mctp@10 { compatible =3D "mctp-i2c-controller"; reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; @@ -139,30 +149,37 @@ i2c-mux@71 { i2c10mux0ch1: i2c@1 { mctp-controller; // BE NIC FRU + eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; }; }; + i2c10mux0ch2: i2c@2 { mctp-controller; // BE NIC FRU + eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; }; }; + i2c10mux0ch3: i2c@3 { mctp-controller; // BE NIC FRU + eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; }; }; + i2c10mux0ch4: i2c@4 { mctp-controller; // BE NIC FRU + eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; @@ -174,6 +191,7 @@ eeprom@50 { // L Bridge Board &i2c11 { multi-master; + mctp@10 { compatible =3D "mctp-i2c-controller"; reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; @@ -185,38 +203,47 @@ i2c-mux@71 { i2c11mux0ch0: i2c@0 { mctp-controller; // FE NIC FRU + eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; }; }; + i2c11mux0ch1: i2c@1 { mctp-controller; // BE NIC FRU + eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; }; }; + i2c11mux0ch2: i2c@2 { mctp-controller; // BE NIC FRU + eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; }; }; + i2c11mux0ch3: i2c@3 { mctp-controller; // BE NIC FRU + eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; }; }; + i2c11mux0ch4: i2c@4 { mctp-controller; // BE NIC FRU + eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; @@ -228,7 +255,7 @@ eeprom@50 { // MB &i2c13 { i2c-mux@70 { - i2c13mux0ch7: i2c@7 { + i2c@7 { // NFC adaptor board FRU eeprom@50 { compatible =3D "atmel,24c128"; @@ -239,7 +266,6 @@ eeprom@50 { }; =20 &sgpiom0 { - ngpios =3D <128>; bus-frequency =3D <2000000>; gpio-line-names =3D /*in - out */ @@ -403,6 +429,7 @@ &sgpiom0 { "AMC_FAIL", "HPM_CPLD_RISCV_RST", "S0_ON", ""; =20 + ngpios =3D <128>; + status =3D "okay"; }; - diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index c74b211c42e6..a9512ea771e3 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,3 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 #include "aspeed-bmc-facebook-anacapa-dvt.dts" - --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3771E474272; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-14-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=819; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=oxTF20CYiA7RH6T7z/fDB4EwQ1KdT7fYEEX/g/uzaW4=; b=yqV5uqb6ufRzAE5RQBXJYWysUIhzgVy0VSJP+HK2eco3jzvaBlc5EzKqNhmEsySCR4W0wyfZJ +muB2m33F5VC6z+kLptDpOQkx5MBIr9Br537nLY+hjPowEzW6s4nKP+ X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Remove the board-specific SPI2 reg property override and rely on the default SPI2 memory window definition provided by aspeed-g6.dtsi. Signed-off-by: Colin Huang --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts index f27ec52f9d56..d613b5b9d6b0 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts @@ -1062,7 +1062,6 @@ &sgpiom0 { =20 // BIOS Flash &spi2 { - reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; pinctrl-0 =3D <&pinctrl_spi2_default>; =20 pinctrl-names =3D "default"; --=20 2.34.1 From nobody Tue Sep 29 02:02:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69D9E4746C2; Thu, 13 Aug 2026 12:00:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622401; cv=none; b=m0U7fRBYqVn9zGUXlzeqe5z3VkStzJPVYeaFfHw7nXkLAa/DGyvC9iN8IEc/DKjmNpd2cPu/w0dWkXgL2iphmnPfK/Bsp6ZsOGwxEnVjWS6Ho1YIFPIChsXRo1LzCzpnGvwNhOglP3gj3hMSxMPr8Troumo74y4H+1oDHJ2mft8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622401; c=relaxed/simple; bh=uLvqSnLxFTr/El1MUjQjU5tqTpJ5ohRAn7CKilpJxCg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AZ4RRqd5TZ/ed1FXkYcnpNnmrbPh+YY0Gzv3/59lbvW17p8KYMtQ8VSdH8td1o8K4Y8Gjo+3QNAsLjusU10R2vJhIzv0z6Tt3o2f5pLEesT1jRnMJHnRXMfto7kr2p4gHLKh8EskleToES/ykdrcihyBqe/SnbQSdJFLMQCoDXs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jIuftnYb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jIuftnYb" Received: by smtp.kernel.org (Postfix) with ESMTPS id BE39CC2BCC7; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786622401; bh=uLvqSnLxFTr/El1MUjQjU5tqTpJ5ohRAn7CKilpJxCg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=jIuftnYb97EcU4lSittDbG2omUlz++SJbnX7RSS4N+MRpMbe9WvyOFi3HLds+nZq/ zLUH2p4CUOa7XGD5806qyBP69SgNdc4WHL9XFkRkKBZUGn6vDq2umTvYB+xo1CHGPF 2CI0C2UZtDHRob/r/JwJr2KsQDBi/muBDDNcGqurEEsxq9NjjS6vkizIJZO3Dgm5fJ bVPTpB6fNie/e0GqiyPwlPbH8plita48zovkKzKd6sApGjPvXeF/AADvV2yo5mqvNA gpm3NtSTgLx5JLphAnAMoxBdcNwRmI5z7pXLevWVsjUG/IKXUeTLfw0RuGKvihBJVL AfW1gACuqQPag== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7631DC5DF74; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:45 +0800 Subject: [PATCH v5 15/15] ARM: dts: aspeed: anacapa: Remove redundant vhub pinctrl-names Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-15-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=708; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=wZdptsf5KZoTZdsrUVb6bffHaz43HHnvSy2YjypcUzQ=; b=MNt1Xza2YC6AF1CLGYg5+fmVk3XcUzlYvu95056SM6MqhkXzcaRkrr1IQA22bjZap3PORfade w/MHSUsshQbCLMjz2y0SW7ThkUYvZHr+3ilQAmi6wMoioflnFU1XQyj X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Remove the pinctrl-names property from the vhub node since it is already defined in aspeed-g6.dtsi. Signed-off-by: Colin Huang --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts index d613b5b9d6b0..039b016ae06c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts @@ -1106,8 +1106,6 @@ &uhci { }; =20 &vhub { - pinctrl-names =3D "default"; - status =3D "okay"; }; =20 --=20 2.34.1