From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4BB4474267; Thu, 13 Aug 2026 13:57:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629479; cv=none; b=aEltXK7td74adRP4wQ7T2z66BO0VXw0N1uxG5UKUgw4BAlXuT66R0KWFieaNxjcuMfz7TbIfNrdDwv+wa0lTkXreE/GzD7UMR7rlT/SPk4NDesmfN1DPqsPloGKhDeVw0mdhxbrez73oq/sXLWnv4wpgkvUnOZULppiFt4kwMzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629479; c=relaxed/simple; bh=9dLWNekOW7HQhEmclDiDF6QjCSUcsR4qui0ysyPSuiw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=DA341yvSAAx5BkNxvVBvq4Wzh/+xWSuqDht0l9j93DYmxhRQcNx9ZgP/LAmArVcTSJztRWjJ1xPpaKK/c6bDZyJyhcL0M+t18Uq3TSJ79x+V87DpvYayCDiOlccM9JRwFCC99fgMyj1w5/PgGiRqywnWvEE0JAe1TrU+sKar0rM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=Bs2monDH; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="Bs2monDH" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCdCPo1876657; Thu, 13 Aug 2026 09:57:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=TB9tO /z5NV0BOnA9GWvBJSKU6yk3k3e4I+lhO8xRQM0=; b=Bs2monDHA8lgmTUPN0f9o JqpcrNQNrAXT8DI4Iujf7Cz8mj13OFH7lgbz4GHakr6reXPdKuVKtm/uwjziuNK6 DYHLEQr3wEWiuF7P6nHjFGRiWOgfWb4sFPIARLnYWS0GIC5wE+eSZ6o9rrUC4wJt d77RnFfDNX8qruJ4TJp7NazcANVIE+zwGGaI2wR0ODmhTKHaUBTi257mzywMIhp0 E3/h6CC0wYRFvjmOPWtyALIZvgWkMFCB3c6PMO+G4f1wVmseb0JZGevgf/+eXR1G bc1XkCfuXlmFHelna7oQWuHc29lzG37KsT+L0iU3a3+yA2sbXjXfZ9b8bTMb1pN8 A== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e4b0daj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:57:46 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDvjen024606 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:57:45 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:57:45 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:57:45 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwT006802; Thu, 13 Aug 2026 09:57:38 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:56:54 +0200 Subject: [PATCH v3 01/14] dt-bindings: iio: adc: Add AD7768 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-1-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=12321; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=9dLWNekOW7HQhEmclDiDF6QjCSUcsR4qui0ysyPSuiw=; b=aDrTF1+d4sZStr2H77v3kWRmvIDapkjOZ5FRz50jsC0V2M3VKe/PGGz8qC19iehXP+rpE6wlE RQh/PvkiZ6RBIdb+f1ypRRt8pQLzTiLBTdj/xmYpasqZ/CiRLe/Qong X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: G7vZWczCsQNL5Yu7sn_dz0lXysjgzPAD X-Proofpoint-ORIG-GUID: G7vZWczCsQNL5Yu7sn_dz0lXysjgzPAD X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX4QdsAgLbvDvf LmNWb81Y+GeREZaZy5F1V583G+w2vQdXafwSsZzmHSe2s/aV91JpdGOJMImSoENl5cld/SznX7j ytEm1IO3ij718FvBXVPc2wbLpVXsfSpXeTvAzvlHAJijjCAiOYNt X-Authority-Analysis: v=2.4 cv=ZZYt8MVA c=1 sm=1 tr=0 ts=6a7dcd5a cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=Z0pTeXoby7EwIRygza74:22 a=gEfo2CItAAAA:8 a=gAnH3GRIAAAA:8 a=NEAV23lmAAAA:8 a=VwQbUJbxAAAA:8 a=pGLkceISAAAA:8 a=9KVYkBU6uCY3fGsyMq0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX3nZRhvDZDa7+ sE/a3BLIVgBU7eXiHEMrPtFqeipfRhHIvak5tkLjUtVSU+1FcjpVR8qNHmGw8z8uy/jm28/cnr4 xUyX2bSza03nQa7Rzo4Ye5umrLcxcMDnVtS/sWt0Yd7teecUfuX8e6ygrWbHMHhbU5oAzOYq0k1 BKGkVqCnI8SA/i0c+QHovWL5kUMsU7IVeVGjtw8SabUi7sfn5Fz4FZFJNoc6hZ3qO+aj3WW19wG Iiqs5oP22uWvcRZ68hnRD0uR6ic8T0I6Nw8gGD1/S/Dbqf8YPMk4D9VAxYCuYlF2avzm95DkpBR 9xoOFbgwtV0NM0qg/Nwez2m446a+Qwa/8DDEg/RJ9k1qa+0HkN2H2Q+9A3DQBVBp36uyen4AF9X bP/3i3peUjzRxg5zdmAkXpECRLZgJesGzf3ajuAcCwkTy3LSTaVD4J3xbJVMXu9pVehnmSbr7kp ctOkeXAxf47F9ohKK7w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Devicetree Bindings for AD7768-4 (4 channel) and AD7768 (8 channel) simultaneous sampling ADCs. Signed-off-by: Janani Sunil --- .../devicetree/bindings/iio/adc/adi,ad7768.yaml | 338 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 345 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7768.yaml new file mode 100644 index 000000000000..54241436f47f --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml @@ -0,0 +1,338 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7768.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD7768 and AD7768-4 ADC + +maintainers: + - Janani Sunil + +description: | + The AD7768 is an 8-channel, 24-bit simultaneous sampling ADC with config= urable + power and performance modes. The AD7768-4 is a 4-channel version. + + This binding covers SPI mode only (register access via SPI). Pin control= mode, + where configuration is set via hardware pins rather than SPI registers, = is not + supported. + + The io-backend represents the high-speed data output interface, consumin= g the + DOUTx data lines, DCLK (data clock), and DRDY (data ready) signals. + + Datasheet at: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7768.pdf + + HDL reference design: + https://github.com/analogdevicesinc/hdl/tree/main/projects/ad7768evb + +properties: + compatible: + enum: + - adi,ad7768 + - adi,ad7768-4 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + Master clock (MCLK). Can be supplied as a CMOS clock on the XTAL2/MC= LK + pin, a crystal oscillator connected between the XTAL1 and XTAL2 pins= , or + an LVDS differential clock on the XTAL1/XTAL2 pin pair. The clock so= urce + is selected by the CLK_SEL hardware pin. + + avdd1-supply: + description: + Analog supply voltage for the AVDD1A and AVDD1B pins (5V =C2=B1 10% = with + respect to AVSS). Powers the analog front end, reference input, and + common-mode output circuitry. Both pins must be tied to the same + potential. + + avss-supply: + description: + Negative analog supply rail for the AVSS1A, AVSS1B, AVSS2A, AVSS2B, + and AVSS pins. This rail is referenced to DGND and all AVSS pins must + be tied to the same potential. In single-supply operation AVSS is + nominally 0V; in split-supply operation it can range from 0V to + -2.75V with respect to DGND. + + avdd2-supply: + description: + Analog supply voltage for the AVDD2A and AVDD2B pins (2V to 5.5V with + respect to AVSS). Connects to internal 1.8V analog LDO regulators th= at + power the ADC core. Both pins must be tied to the same potential. + + iovdd-supply: + description: + Digital supply voltage IOVDD (2.25V to 3.6V with respect to DGND). + Sets the logic levels for all interface pins and powers the digital + processing core via an internal LDO. For 1.8V operation (1.72V to + 1.88V), IOVDD must be tied to the DREGCAP pin. + + ref1-supply: + description: + Differential reference voltage supply for the REF1+/REF1- input pair. + REF1+ voltage range is from (AVSS + 1V) to AVDD1; REF1- voltage range + is from AVSS to (AVDD1 - 1V). The differential reference voltage ran= ge + is 1V to |AVDD1 - AVSS|. On the AD7768 this reference is used for + channels 0 to 3; on the AD7768-4 for channels 0 and 1. + + ref2-supply: + description: + Differential reference voltage supply for the REF2+/REF2- input pair. + REF2+ voltage range is from (AVSS + 1V) to AVDD1; REF2- voltage range + is from AVSS to (AVDD1 - 1V). The differential reference voltage ran= ge + is 1V to |AVDD1 - AVSS|. On the AD7768 this reference is used for + channels 4 to 7; on the AD7768-4 for channels 2 and 3. + + reset-gpios: + maxItems: 1 + description: GPIO connected to the active-low RESET pin + + start-gpios: + maxItems: 1 + description: + GPIO connected to the START pin. An active-low pulse on this pin + synchronizes the device to other AD7768 devices. When not used, this + pin must be tied to a logic high level through a pull-up resistor. + When used, SYNC_OUT must be wired back to SYNC_IN on all devices in + the synchronization chain. + + sync-in-gpios: + maxItems: 1 + description: + GPIO connected to the SYNC_IN pin. Receives the synchronization pulse + generated on SYNC_OUT in response to a START pulse. Must be synchron= ous + to the MCLK clock domain. In multi-device or daisy-chained systems, + two successive synchronization pulses must be applied to guarantee a= ll + ADCs are synchronized. + + sync-out-gpios: + maxItems: 1 + description: + GPIO connected to the SYNC_OUT pin. Outputs a synchronization pulse + synchronous to MCLK in response to a START pulse or SPI_SYNC command. + In single-device configurations this pin must be wired back to SYNC_= IN. + In multi-device configurations it can be routed to the SYNC_IN pins = of + all devices in the chain. + + gpio-controller: true + + '#gpio-cells': + const: 2 + + adi,data-lines-number: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + description: + Number of DOUTx lines used for the high-speed data output interface + (distinct from the SPI control interface). AD7768 supports 1, 2, or 8 + lines; AD7768-4 supports 1 or 4 lines. Defaults to the maximum number + of lines for the selected variant if omitted. + + regulators: + type: object + description: Container for the on-chip VCM regulator. + additionalProperties: false + + properties: + vcm-output: + type: object + description: + The VCM pin provides a buffered common-mode voltage output used = to + bias the analog inputs. It supports three fixed output levels of + 1650000 uV, 2500000 uV, and 2140000 uV, as well as a + supply-dependent (AVDD1 - AVSS) / 2 output derived from + avdd1-supply. Select the voltage by setting regulator-min-microv= olt + and regulator-max-microvolt to the same value. Use + regulator-always-on when no DT consumer node references the VCM + output. The VCM circuitry is associated with channel 0. When VCM= is + used externally, channel@0 must be present and kept enabled beca= use + placing channel 0 in standby disables the VCM output. + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + io-backends: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^channel@[0-7]$": + type: object + description: | + Represents the external channels which are connected to the device. + AD7768 supports channels 0-7, AD7768-4 supports channels 0-3. + + properties: + reg: + minimum: 0 + maximum: 7 + description: The channel number + + adi,prechargebuf-pos-enable: + type: boolean + description: Enable positive input precharge buffer + + adi,prechargebuf-neg-enable: + type: boolean + description: Enable negative input precharge buffer + + adi,refbuf-pos-enable: + type: boolean + description: Enable positive reference buffer + + adi,refbuf-neg-enable: + type: boolean + description: Enable negative reference buffer + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - avdd1-supply + - avss-supply + - avdd2-supply + - iovdd-supply + - ref1-supply + - ref2-supply + - io-backends + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + const: adi,ad7768-4 + then: + properties: + adi,data-lines-number: + enum: [1, 4] + patternProperties: + "^channel@[0-3]$": + properties: + reg: + maximum: 3 + "^channel@[4-7]$": false + else: + properties: + adi,data-lines-number: + enum: [1, 2, 8] + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad7768"; + reg =3D <0>; + spi-max-frequency =3D <1000000>; + + avdd1-supply =3D <&avdd1_regulator>; + avss-supply =3D <&avss_regulator>; + avdd2-supply =3D <&avdd2_regulator>; + iovdd-supply =3D <&iovdd_regulator>; + ref1-supply =3D <&ref1_regulator>; + ref2-supply =3D <&ref2_regulator>; + reset-gpios =3D <&gpio0 86 GPIO_ACTIVE_LOW>; + + clocks =3D <&ad7768_mclk>; + + adi,data-lines-number =3D <8>; + gpio-controller; + #gpio-cells =3D <2>; + + io-backends =3D <&iio_backend>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + + channel@1 { + reg =3D <1>; + adi,prechargebuf-pos-enable; + adi,prechargebuf-neg-enable; + adi,refbuf-pos-enable; + adi,refbuf-neg-enable; + }; + + channel@7 { + reg =3D <7>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + }; + }; + + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1 { + compatible =3D "adi,ad7768-4"; + reg =3D <1>; + spi-max-frequency =3D <1000000>; + + avdd1-supply =3D <&avdd1_regulator>; + avss-supply =3D <&avss_regulator>; + avdd2-supply =3D <&avdd2_regulator>; + iovdd-supply =3D <&iovdd_regulator>; + ref1-supply =3D <&ref1_regulator>; + ref2-supply =3D <&ref2_regulator>; + + clocks =3D <&ad7768_mclk>; + + adi,data-lines-number =3D <4>; + + io-backends =3D <&iio_backend>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + regulators { + vcm-output { + regulator-name =3D "vcm-output"; + regulator-min-microvolt =3D <2140000>; + regulator-max-microvolt =3D <2140000>; + regulator-always-on; + }; + }; + + channel@0 { + reg =3D <0>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + + channel@3 { + reg =3D <3>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 2b1ec46c5919..d667a0411f28 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1633,6 +1633,13 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad7= 768-1.yaml F: drivers/iio/adc/ad7768-1.c F: include/dt-bindings/iio/adc/adi,ad7768-1.h =20 +ANALOG DEVICES INC AD7768 DRIVER +M: Janani Sunil +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml + ANALOG DEVICES INC AD7780 DRIVER M: Michael Hennerich M: Renato Lui Geh --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC8A34772A9; Thu, 13 Aug 2026 13:57:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629480; cv=none; b=TV53MjGeXBXoHtODgnjethdSSuVQQvFC3ct92rUS9DG4FwZIZBCjFHP9cz2UlGutmlk/ew7wnLtIU6iKjRsgLcuSkcSmsgJ6fNf0Cp1meMslA9RnI4JeSzZaeJoFR/hGAL4DL/LcqIT0CBqNv5Nv8QNKFaxGNCl79Fc3rRh+TkU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629480; c=relaxed/simple; bh=Ppp+RGxCEecjTpxXjCNm4l8VHRbYg8JEe6sv0mNQS5I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=A2Fg98rC09a6XZUPt4m4vcqy8dmICed1XC976Fpkii0vm1mLSe9XkHnfwNaRKlNzcg8GMGgQB8ibo8zkv1aeEOljoLaBYw0k7vB34k4YGPaa0T0o1XY58/1ot1vU8CS3vh1ht5T4uCgxdv+igtvzl4300G/P+93v3q4SnOVQmPY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=gdt7vSqV; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="gdt7vSqV" Received: from pps.filterd (m0516787.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCaDbP2129164; Thu, 13 Aug 2026 09:57:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=7KDq9 azkBxHmggf+i7QO8gZmXPtaA+gV7wWItUf68f0=; b=gdt7vSqVL8JCy0Fv5V2+o KiWs2iyaKhfhYuQe/d7b6U/SAtT5p58pE78AKpyM8IOEy0/VBOL6UKBw14yUQKmt Z2n94na3XQmX1w7OIPLBaDdx78kLLLHA2Vfg3hldG4aTJ//YbkbZP8QGG8lgmhqJ YKRQaA+BJBFvmyHq0GOv88KaKrFRwO08Qj3UaVgOp4K/4fX60C3Q2t6sC6cbVFqX XmZGUn9iAtljGM6RnZZopxYtQ38A7PBYT+slKYLTrBlUth4hDTwVnksnwDDhBm55 0pMtdyQavnJHjFKvmD2N8YYvno+QXLvglYsCvWJO8hnpLkWKvNA4NKb54yshurcs w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e2wgcca-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:57:49 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDvmkP024621 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:57:48 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:57:48 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:57:48 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwU006802; Thu, 13 Aug 2026 09:57:41 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:56:55 +0200 Subject: [PATCH v3 02/14] iio: backend: Add support for CRC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-2-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=3865; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=Ppp+RGxCEecjTpxXjCNm4l8VHRbYg8JEe6sv0mNQS5I=; b=3XK0tW+Pt3hZJNBmkdj8L844OUZ7VhdzRgW4NrmLqBoIpqXVpOGliGQdQsU+U1rch4Igok6Q8 w4hNG7N7z5RDyGLiNVYtnPyeToIGIRvfMzVcaVuRMvnuIXGykkrVLBB X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX0baWQPRQhA/I CJHoKPtbF/zErDaaIxZGtgFHUZmJhAbue+CTvdpPHKwV6cWw59aWxqTV9K5r/AUnWFIY/9jBQCI 4cgDHAs1XgtFlXZdU1U/ap/jwzStYejkUls5b6WG6Fdeyj2iQQgD X-Proofpoint-GUID: 4zU9zMSLxFzLeqpUQ7K1fyM10TVn51n3 X-Authority-Analysis: v=2.4 cv=UJzt2ify c=1 sm=1 tr=0 ts=6a7dcd5d cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=gAnH3GRIAAAA:8 a=KKt7U01DjHU_5c1eSo8A:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX4VuKgn5ERgPH nak9DDokM9t1/pSKEnVoqc5f6pepm3SXJeoDK5+Sczlq0W2RbLM9ZeeGTpWqeu61mb7HZ2o9zvh dSM87aA1IWM03z9+fbx4IJMyExpYNqZ3l7X+fDEFj8vdDgmhPxEI5e0oNioAsh1wro37xoj5Vzm 5sKV+JWwtUwZEEBJ3sSgYPlCtaBn2GWPR45bm88JpknzZrJ235AninJ2yau/5cDApzdCPRZK9b4 7RZczLZEbon9vh0zxi1b+L2hzuh5195C9szPt3YN6mzNFnchSUU71HHLR+s6nF9Wt4UWFlu9Ada wxfIEdxnikD0v3L+kz6k32zuPjCF9HERWZxxGMcCX6U22pg6CkAF0KNoRbcejNpWDH0bZoKk8NO CjFu92FfH9E9ELIY3t7qudakpdsDPjmzgSHZh6K0dZHM23Oy5CR9zWz9YlFjl98o4g5xUoUc3Qf zl4d1uEFp1gdA2+JyQQ== X-Proofpoint-ORIG-GUID: 4zU9zMSLxFzLeqpUQ7K1fyM10TVn51n3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Add a backend operation to enable or disable Cyclic Redundancy Check processing for data integrity verification. When enabled, the backend will generate, verify, or process CRC information for data samples transmitted over the interface, allowing the host to detect corrupted samples. Signed-off-by: Janani Sunil --- drivers/iio/industrialio-backend.c | 33 +++++++++++++++++++++++++++++++++ include/linux/iio/backend.h | 6 ++++++ 2 files changed, 39 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index f7a4be8ec320..792c2333b057 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -886,6 +886,39 @@ int iio_backend_num_lanes_set(struct iio_backend *back= , unsigned int num_lanes) } EXPORT_SYMBOL_NS_GPL(iio_backend_num_lanes_set, "IIO_BACKEND"); =20 +/** + * iio_backend_crc_enable - Enable the CRC generation. + * @back: Backend device + * + * Enable Cyclic Redundancy Check processing for data integrity verificati= on. + * When enabled, the backend will generate, verify, or process CRC informa= tion + * for data samples transmitted over the interface. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_crc_enable(struct iio_backend *back) +{ + return iio_backend_op_call(back, crc_enable); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_crc_enable, "IIO_BACKEND"); + +/** + * iio_backend_crc_disable - Disable the CRC generation. + * @back: Backend device + * + * Disable Cyclic Redundancy Check processing. When disabled, the backend = will + * stop generating, verifying, or processing CRC information for data samp= les. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_crc_disable(struct iio_backend *back) +{ + return iio_backend_op_call(back, crc_disable); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_crc_disable, "IIO_BACKEND"); + /** * iio_backend_ddr_enable - Enable interface DDR (Double Data Rate) mode * @back: Backend device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 3f95ed1fdf9e..eddaddb47bea 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -133,6 +133,8 @@ enum iio_backend_capabilities { * @filter_type_set: Set filter type. * @interface_data_align: Perform the data alignment process. * @num_lanes_set: Set the number of lanes enabled. + * @crc_enable: Enable CRC generation and verification. + * @crc_disable: Disable CRC generation and verification. * @ddr_enable: Enable interface DDR (Double Data Rate) mode. * @ddr_disable: Disable interface DDR (Double Data Rate) mode. * @data_stream_enable: Enable data stream. @@ -189,6 +191,8 @@ struct iio_backend_ops { enum iio_backend_filter_type type); int (*interface_data_align)(struct iio_backend *back, u32 timeout_us); int (*num_lanes_set)(struct iio_backend *back, unsigned int num_lanes); + int (*crc_enable)(struct iio_backend *back); + int (*crc_disable)(struct iio_backend *back); int (*ddr_enable)(struct iio_backend *back); int (*ddr_disable)(struct iio_backend *back); int (*data_stream_enable)(struct iio_backend *back); @@ -237,6 +241,8 @@ int iio_backend_filter_type_set(struct iio_backend *bac= k, enum iio_backend_filter_type type); int iio_backend_interface_data_align(struct iio_backend *back, u32 timeout= _us); int iio_backend_num_lanes_set(struct iio_backend *back, unsigned int num_l= anes); +int iio_backend_crc_enable(struct iio_backend *back); +int iio_backend_crc_disable(struct iio_backend *back); int iio_backend_ddr_enable(struct iio_backend *back); int iio_backend_ddr_disable(struct iio_backend *back); int iio_backend_data_stream_enable(struct iio_backend *back); --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C9FE481AA9; Thu, 13 Aug 2026 13:58:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629484; cv=none; b=XaLIqvtEsHIMQiVc+uGeoSCr2PlOSxeqO94pwGlDVuan1FmEZdBADbBGqCEegYanzAlUQfGH/lAfq+0nEcJewTH44te6slU+OgGqUrwTNy6j6/b6R/6hOO5Vuc7aYAazz6zm4k+CkWWgQb+V3r8AQCdGlnVMk29ka4APKzFygWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629484; c=relaxed/simple; bh=Ia5cdUwhQp5bspVUqQ3iF/ZRqYMDFIcD31k3fE8TCuc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ryALwYoe8Ac3QRbjAsbsbKX8UxSwLoiEtzWCTHzx8RMzKoPGCYANH+nTXayDMBP6ZfV+sQENEIlBj7njGGj4QqbEnEC8GI3/SsIzp1xxMwekfoMFUBQAYS4ZRexd1tt6J7Y6z2xOahldHksy+juNtvRKM7L410ks8n831/OXaqw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=Jp2qA4oz; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="Jp2qA4oz" Received: from pps.filterd (m0516787.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCa9Gs2129073; Thu, 13 Aug 2026 09:57:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=isQfr O1kOgift38KlUFUSiekVqhdQPQpvCxC62CsfNk=; b=Jp2qA4ozg2FT0P35xFplQ LnyoOsVGx+TDIGHKnUtg9TvZhlSew8u+P3oIBKS1Avos/a1nB0JGtfg6tDnTt43v VzuPbbcQLM5d9W+Dzsel7zI9yqAKBgoIZjfCOYXde717Og+1MXI4qV+aIfypqaVT 0GZx8CX1lvSRK06gowsTHjz8wcOVCg4U/Ezak3MOmQHGxTxe20fjqPZ6Zx6//Dp6 CCWTdp0CKPryp0Sd9KiBj88Rlc6rI+0KcOzt1ZD6liFqcWZeUpkfl/n9wdeUCN86 rHJLWLomgYmsU7eQJ7yuRqWbGKEG5rX0fl2Xrs1yZSTQ0py6Wd79QLi83wW9BNxJ A== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e2wgccd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:57:52 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDvpwH024627 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:57:51 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:57:51 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:57:51 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwV006802; Thu, 13 Aug 2026 09:57:43 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:56:56 +0200 Subject: [PATCH v3 03/14] iio: adc: adi-axi-adc: Initialize state mutex Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-3-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=880; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=Ia5cdUwhQp5bspVUqQ3iF/ZRqYMDFIcD31k3fE8TCuc=; b=oQfK7VzcS3kp6oQYyevlMmhFpg9D/2WaT/V2fzCyghFgvUgzem4uY7gUrUrjLAkPSt152NsVV 9g7frGVSZ0XC7aXiFS/0kMSwx3x7c2rzQo/xhiLyLAaxU/BPpEIIFHR X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfXy+p3SRv2nYh1 T0VWlYXdZC/9d98P5zDQeBSsorMzSrLGeMO/T/RoHv8xRDooob/pDX5EF9QYi+vHqyA6uSsgD4d a7AwyFi3k0//TLQ/197Mfpt/XLV2MhLe01NDyCS+909GWdhQHD8X X-Proofpoint-GUID: rOKYSVvznp6u39O8MfQo8CWUhGxkzZcN X-Authority-Analysis: v=2.4 cv=UJzt2ify c=1 sm=1 tr=0 ts=6a7dcd60 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=gAnH3GRIAAAA:8 a=_ljTvifiVFBlT2kRk7cA:9 a=QEXdDO2ut3YA:10 a=zZCYzV9kfG8A:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfXyLTU2CKwC1n9 jLZW5NWgvawqXjkHo4hjQ967CS32it49node5i2GXfW+vODCHBrUgB03TMj0XAz8XFtj7Ld/oA4 DaQ+LSHMYh1DpOaOWTqKWsJ62mEGkltNPlvErtZu+FHzIwSOwl5Cw5rv5Emyc/sqcYDDSsyABdY hppXhwSrrfs8moM7HY63f0rg9JXqQp0Bz/z/jLm7+5VHpKp2kbZ/heUS5L0PfZOJY4O+MRroCda 3RS9sOUMPNM+83A1H2V2WLq7x7U2wXQXM+iVUVlzz1/wBYEEn80W8yYxRYllmJRcscxtOSI5xwP N+knlZ7J1cudv+rLnaySE08dMGyopIPozVIq9m8OtuiGE2Md75P2QgODHFExZq0TZPbaolRMrKG rtq+9UjbEAonXgt4yj3JBsLcRPR4Ri7QG+EwQXpr0BcaAkenxE9vFNbovmo2vUkw4BNTDyZCilq AVm3NXNMi5hMgG3B5cg== X-Proofpoint-ORIG-GUID: rOKYSVvznp6u39O8MfQo8CWUhGxkzZcN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 The AXI ADC register access paths serialize transactions with st->lock, but probe does not initialize it. Initialize the mutex before registering the backend. Fixes: 7ecb8ee5c93b ("iio: adc: adi-axi-adc: support digital interface cali= bration") Signed-off-by: Janani Sunil --- drivers/iio/adc/adi-axi-adc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 26b9c75bd4d8..b5e59b1871b6 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -684,6 +684,10 @@ static int adi_axi_adc_probe(struct platform_device *p= dev) if (!st) return -ENOMEM; =20 + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBE40481FCA; Thu, 13 Aug 2026 13:58:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629486; cv=none; b=hlQs0pN+08pHJeDuX1lslpybgWaJdPi6xOLGbsE9I+OU1G0l2OH85eSYSkzLDeL36QtImrZhBk18/KJeKJt6QSohw7aymEk4l+7V/l8SibXzwD75i7VRwscx7XHdWWTIyEVOFXkdGZeu9oSUeryQ87CL0NBYXncp3ESelaqJ2po= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629486; c=relaxed/simple; bh=BC3GY2a0PfAaf1anUYAI3VBIwF6NWvD9eEF7jo39oM4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=tt8GVSLzNHyRxk/0CYsPnaVeK4U+Ypjk1xJUvGsIrUHSkREsW1/Gx1fKFPLbZaYwwz/vGC+MIfJLmpiIWkLsGMeKrthCuXeDfUXl4AgTae/w66tNgQRuv/xu9goxpp+P/TExFztfN7bRaIE3GajxTFQjo3VasADUMQ3esI9ai8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=cbjzSc8d; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="cbjzSc8d" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCdD631876680; Thu, 13 Aug 2026 09:57:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=meDou IdYda+dFUbpyjE577+DP2BMvJelM4xTd/l8MgY=; b=cbjzSc8dmyq0kD84QoJSD 72vFMDyGAZjAy8Us7e3ZwPnnc9X+7fI93mw7OkS5b0deiLtmpAjVUGXWcSd/7Hmm BRuWwhm71SvplMS8/kK4JF6LGR4SaVUrbzf+z5reTs/gnCKySJjzAuxp7RV4rI3N 7YwdMLVpNcoYfVn1inTzray4i7LLqam0DMVD5OjjzdPpx9wkZtK+g/UHZZvF01n4 MIEJTpoQOaApncBHg6N6DDlLu+2fvdAObEfwAt2Gjt347mbosk1+9pzdmPlgvy66 OFtVOpopkPCNQcq8sIw7ZWKXtRw2r7oKZ22Huc8Ag1ExHMAskXaijw/q07HrC44O g== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e4b0dax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:57:55 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDvsdM024631 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:57:54 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:57:54 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:57:53 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:57:53 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwW006802; Thu, 13 Aug 2026 09:57:46 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:56:57 +0200 Subject: [PATCH v3 04/14] iio: adc: adi-axi-adc: Add support for CRC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-4-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=2211; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=BC3GY2a0PfAaf1anUYAI3VBIwF6NWvD9eEF7jo39oM4=; b=AVi+Nh2JQ4ixXN+MnBZEc5QeXGJI0S3MmbOLsiCNK39sdRqdRTixpl5YV+46U3Gw9O4jSF4jL Sfz3ginynpvB53T8TvnV3fTpDo9ZbWXu2Y6+F44xxuBukPNjkeTirAw X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: fsUhZO1XOSu0qGaLjQ977imB8ynPzayr X-Proofpoint-ORIG-GUID: fsUhZO1XOSu0qGaLjQ977imB8ynPzayr X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX6ViOH4KUmnL1 UA9vNLKcgxPhuUqPyOQjcaICriqRWeRY+Rl8VlXYtOxJAvmrh0GuGYljy/CHSeGwMYzds5olwE7 yrhWQf5HetHaGCSLUaz3UErw0IM4rlxh1wicHDiihi26Ryi/zuwq X-Authority-Analysis: v=2.4 cv=ZZYt8MVA c=1 sm=1 tr=0 ts=6a7dcd63 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=Z0pTeXoby7EwIRygza74:22 a=gAnH3GRIAAAA:8 a=xcMXqGzQfnDy9uQaBxsA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX56CXMqmJJGIU 3WeV6+etHKX7boorpQurbyaUOhRi6tBbWbKlsuRor7RL/N358E0tGFkbCp9UZYxMwp3q5Q2HSaj Y6yP9Ml60yOPM8ttm3s0op/+KqhGPyhLH+RDIkpBGCWwjN+teA0rTOoXkrfetCjU5NohwgeGSeO qmXecUiImT3hGM8/DzUAnESEodd8A9M4DHwu4sg9sDQnd8pPTGXUI+jMS82XXbGsfFBrxSHr9Rs fW+2Z39FhPNMZA8zOzdbbXlfWsL73cHXzrit9HIRrcEIaFC4kAzl4pjtRbhL19L+X9WoPtyLBcM L5W9qN//ryhF2lS4AKXmM2rHkxlpxBCZt4/ap3eERDY+dAkVQXJwbaihBp8JuV5GKNV/xb2IFG+ 4sBWt0AmZqSajO5Ycce9KumVfFMUQoYiGFojKEC9YkIkuUy9DaN+KeksrJ8FXh/WxbhJ4kL1lSX zGXuLh646mkoyziNNsQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Add support for enabling and disabling Cyclic Redundancy Check (CRC) processing in the AXI ADC backend. CRC provides data integrity verification for high-speed ADC data streams, ensuring reliable data transfer between the ADC frontend and backend processing systems. Signed-off-by: Janani Sunil --- drivers/iio/adc/adi-axi-adc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index b5e59b1871b6..e8f149e230e7 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -47,6 +47,9 @@ #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) =20 #define ADI_AXI_ADC_REG_CNTRL_3 0x004c +/* Bit 8 is common to all AXI ADC cores; bits 7-0 are per-HDL-project. */ +#define ADI_AXI_ADC_CNTRL_3_CRC_EN_MASK BIT(8) + #define AXI_AD485X_CNTRL_3_OS_EN_MSK BIT(2) #define AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(1, 0) #define AXI_AD485X_PACKET_FORMAT_20BIT 0x0 @@ -567,6 +570,22 @@ static int axi_adc_reg_access(struct iio_backend *back= , unsigned int reg, return regmap_write(st->regmap, reg, writeval); } =20 +static int axi_adc_crc_enable(struct iio_backend *back) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + + return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, + ADI_AXI_ADC_CNTRL_3_CRC_EN_MASK); +} + +static int axi_adc_crc_disable(struct iio_backend *back) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + + return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, + ADI_AXI_ADC_CNTRL_3_CRC_EN_MASK); +} + static const struct regmap_config axi_adc_regmap_config =3D { .val_bits =3D 32, .reg_bits =3D 32, @@ -615,6 +634,8 @@ static const struct iio_backend_ops adi_axi_adc_ops =3D= { .num_lanes_set =3D axi_adc_num_lanes_set, .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access), .debugfs_print_chan_status =3D iio_backend_debugfs_ptr(axi_adc_debugfs_pr= int_chan_status), + .crc_enable =3D axi_adc_crc_enable, + .crc_disable =3D axi_adc_crc_disable, }; =20 static const struct iio_backend_info adi_axi_adc_generic =3D { --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F06F047DFB0; Thu, 13 Aug 2026 13:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629496; cv=none; b=O/CGa9+426KMhdMGDJiPAcEIqgE7oCpJsiPqyAvVuyIcVvJdisIwc6AaANe0fed5db8MHAXp1WeNHifrVsXdPppoD68j7W55oOfqwWhZ3xDiH9pXJqnO7uPI4p9p4XkxBY4Ez8AW0zpeSuLCZEpEFsMjmaEWsOIz25VGF++HKRE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629496; c=relaxed/simple; bh=E5B2OaIBLDeI1RSWlHUeJNyFB/GOxWKzHckv5Bvjuhk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=mQxFdMAQMrKMMjejIrhwC7S7OE34baXsu5KBxldHCUwelQ6Gpn8YGs3HGp1zjgfL+BbUEECqVS/BkVIO/srO48J4PCO8hvsY+pixdWMtuoVwuxFPzlKRjh5tZJMzzuegQVse8EZgS70Nw8p0oJWODdobqx/Fs2n0BNlokUoGqhs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=uhxZFIGK; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="uhxZFIGK" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCXQvQ1492149; Thu, 13 Aug 2026 09:57:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=AaD+Q +vrXQYUOva/L3ikcAB4dSA8mP5I/NLMB+yZKQk=; b=uhxZFIGKQ6ochYJzINBbS fvVnMIs+HszTTTYsLh3Wpq93QeQri4vump35/r99B0a6anPle49rr/qzB+xyyxqh COeTw8dUP37iN8A1L9bi+Qkc3qLEV22dqBgslF7lsd6yUYmfSoXPbE+ydebpefLb +gzzghlfQqvHFy2kwUman3R17pZ6wRioh5yqZEtgEni+N/ENImeFOENgUGYrfBYd FP5E4oP9sR2g2HLklE5M4YGeRe6LJbs8bp6rim7Z8QOGE3XjcGGHdcFh0a7khyKN /GaP50GdKxYTPFq3ghuJIhGOTnsMQs0vTsvRr/3Gw7Hz3NuQR1CiczzzwcL5y/U+ g== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e1n8dv4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:57:57 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDvuYZ024636 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:57:56 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:57:56 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:57:56 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwX006802; Thu, 13 Aug 2026 09:57:49 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:56:58 +0200 Subject: [PATCH v3 05/14] iio: adc: Add AD7768 and AD7768-4 core support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-5-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=25915; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=E5B2OaIBLDeI1RSWlHUeJNyFB/GOxWKzHckv5Bvjuhk=; b=7GQPJcwD5+2wpqoix53iTmg55WIavuAytCvOkD3sXWeRomSQqwTVspENnWu5pPG1MDQDVL8rS pmJOb6r3hM3ARE+8loaIXkjThvrdAsxPxV6gxLV1lsrUXmtFhpH/p66 X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX2p6okhKA46av sBgXRQevIAHdogUWg0PO2RyehCdQUknooMUkUPR1jMu5yYxclTXghrSe3hEKaf+wzcKgmljv7a6 65BEK3qW5AJeVbk6LNueyNr29lbNELcxn5mftfYi6r3PRMijhcxOmJSqKluL1KP3B6ZSrhfABSL 6MWv9JqIn1D4+3gcEhLPywYHLUN6y+Bi74918covbx6GWCWvVjOVyun/yR3Txl0qdKHGOVzJW25 8Jdpr85BI470K+WcFgCaU/f692j9rbgtckokEYhPDzemlZnG784B0rpEgy75LyAveN+QOLlZQyX i6K6gwI3zjkRimjmgWek7WeLB3DQax1zi8CX8pzp2p0eFd12vSRtoKTUMiljopWOFzZynpwuM1i HV3KO4LEduLLivmYu5ugV0Q5yKjta6wEDC0Fua4stsIXGFVZWFqI/YUZGac65sOWf7BeRxpu/Ze YSQKP35vU6XCwEQclxw== X-Proofpoint-ORIG-GUID: 9cWfEvRK8LmA9ZjZ6AeM03dLqIw9q7dj X-Proofpoint-GUID: 9cWfEvRK8LmA9ZjZ6AeM03dLqIw9q7dj X-Authority-Analysis: v=2.4 cv=fLoJG5ae c=1 sm=1 tr=0 ts=6a7dcd65 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=gAnH3GRIAAAA:8 a=VwQbUJbxAAAA:8 a=pSgA_9LbZru-KsQaZlcA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX+pXbJqlYguQF UleJ+DmSJGK0OGkZIXK761WBOnAXhdfWWtljUwPgxU0SHv5pmfXcrRZ114mpab45rGIh8buLWG/ m5ikBP0vVa8XfPHXUiEVyjCOKDc/Z6VqiQXuwjbCKZ2EevKfPcXg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 suspectscore=0 spamscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Add core support for the AD7768 and AD7768-4 simultaneous sampling ADCs. Configure supplies, clock and reset, use a custom regmap bus for the SPI protocol, and parse the enabled channels and input buffer settings from devicetree. Connect the converter to an IIO backend for buffered capture with CRC, provide a fixed safe wideband sampling configuration and add runtime power management. Signed-off-by: Janani Sunil --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 15 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad7768.c | 813 +++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 830 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d667a0411f28..dc94e7803a7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1639,6 +1639,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml +F: drivers/iio/adc/ad7768.c =20 ANALOG DEVICES INC AD7780 DRIVER M: Michael Hennerich diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index d1b198cb8a80..d621d859e1d6 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -429,6 +429,21 @@ config AD7766 To compile this driver as a module, choose M here: the module will be called ad7766. =20 +config AD7768 + tristate "Analog Devices AD7768/AD7768-4 ADC driver" + depends on SPI + depends on REGULATOR || COMPILE_TEST + select AUXILIARY_BUS + select IIO_BUFFER + select IIO_BACKEND + select REGMAP + help + Say yes here to build support for Analog Devices AD7768 and AD7768-4 + SPI analog to digital converters. + + To compile this driver as a module, choose M here: the module will be + called ad7768. + config AD7768_1 tristate "Analog Devices AD7768-1 ADC driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 0f90b75577ff..3e896c8aa7c3 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_AD7606_IFACE_SPI) +=3D ad7606_spi.o obj-$(CONFIG_AD7606) +=3D ad7606.o obj-$(CONFIG_AD7625) +=3D ad7625.o obj-$(CONFIG_AD7766) +=3D ad7766.o +obj-$(CONFIG_AD7768) +=3D ad7768.o obj-$(CONFIG_AD7768_1) +=3D ad7768-1.o obj-$(CONFIG_AD7779) +=3D ad7779.o obj-$(CONFIG_AD7780) +=3D ad7780.o diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c new file mode 100644 index 000000000000..9b908ce0a1c3 --- /dev/null +++ b/drivers/iio/adc/ad7768.c @@ -0,0 +1,813 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD7768 ADC driver + * + * Copyright 2018-2026 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define AD7768_REG_GPIO_CONTROL 0x0E + +/* AD7768 registers definition */ +#define AD7768_REG_CH_STANDBY 0x00 +#define AD7768_REG_CH_MODE(x) (0x01 + (x)) +#define AD7768_REG_CH_MODE_SEL 0x03 +#define AD7768_REG_POWER_MODE 0x04 +#define AD7768_REG_GENERAL_CONFIG 0x05 +#define AD7768_REG_DATA_CONTROL 0x06 +#define AD7768_REG_INTERFACE_CFG 0x07 +#define AD7768_REG_REV_ID 0x0A +#define AD7768_REG_PRECHARGE_BUF1 0x11 +#define AD7768_REG_PRECHARGE_BUF2 0x12 +#define AD7768_REG_REFP_BUF 0x13 +#define AD7768_REG_REFN_BUF 0x14 +#define AD7768_REG_OFFSET_BASE 0x1E +#define AD7768_REG_GAIN_BASE 0x36 +#define AD7768_REG_PHASE_BASE 0x4E +#define AD7768_REG_OFFSET(ch) ((AD7768_REG_OFFSET_BASE + (3 * (ch)))) +#define AD7768_REG_GAIN(ch) ((AD7768_REG_GAIN_BASE + (3 * (ch)))) +#define AD7768_REG_PHASE(ch) ((AD7768_REG_PHASE_BASE + (ch))) +#define __AD7768_4_REG_MAP(ch) ((ch) < 2 ? (ch) : ((ch) + 2)) +#define AD7768_4_REG_OFFSET(ch) \ + (AD7768_REG_OFFSET_BASE + (3 * __AD7768_4_REG_MAP(ch))) +#define AD7768_4_REG_GAIN(ch) \ + (AD7768_REG_GAIN_BASE + (3 * __AD7768_4_REG_MAP(ch))) +#define AD7768_4_REG_PHASE(ch) (AD7768_REG_PHASE_BASE + __AD7768_4_REG_MA= P(ch)) +#define AD7768_REG_DIAGNOSTIC_RX 0x56 +#define AD7768_REG_CHOP_CTRL 0x59 + +/* AD7768_REG_CH_MODE */ +#define AD7768_CH_MODE_FILTER_TYPE_MSK BIT(3) +#define AD7768_CH_MODE_FILTER_TYPE_MODE(x) (((x) & 0x1) << 3) +#define AD7768_CH_MODE_DEC_RATE_MSK GENMASK(2, 0) +#define AD7768_CH_MODE_DEC_RATE_MODE(x) (((x) & 0x7) << 0) + +/* AD7768_REG_POWER_MODE */ +#define AD7768_SLEEP_MODE_MSK BIT(7) +#define AD7768_POWER_MODE_POWER_MODE_MSK GENMASK(5, 4) +#define AD7768_POWER_MODE_POWER_MODE(x) (((x) & 0x3) << 4) +#define AD7768_POWER_MODE_MCLK_DIV_MSK GENMASK(1, 0) + +/* AD7768_REG_DATA_CONTROL */ +#define AD7768_DATA_CONTROL_SPI_RESET_1 0x03 +#define AD7768_DATA_CONTROL_SPI_RESET_2 0x02 +#define AD7768_DATA_CONTROL_SPI_SYNC_MSK BIT(7) + +/* AD7768_REG_INTERFACE_CFG */ +#define AD7768_INTERFACE_CFG_DCLK_DIV_MSK GENMASK(1, 0) +#define AD7768_INTERFACE_CFG_DCLK_DIV_MODE(x) (4 - ffs(x)) +#define AD7768_MAX_DCLK_DIV 8 + +#define AD7768_INTERFACE_CFG_CRC_SELECT_MSK GENMASK(3, 2) +/* Hardware supports CRC every 4 or 16 samples; backend supports 4-sample = only */ +#define AD7768_INTERFACE_CFG_CRC_SELECT FIELD_PREP(GENMASK(3, 2), 0x01) + +/* AD7768_REG_GENERAL_CONFIG */ +/* AD7768_REG_PRECHARGE_BUF1 and 2*/ +#define AD7768_PREBUF_POS_EN(ch) BIT((ch) * 2) +#define AD7768_PREBUF_NEG_EN(ch) BIT(((ch) * 2) + 1) + +#define AD7768_SPI_READ_CMD BIT(15) +#define AD7768_SPI_REG_MASK GENMASK(14, 8) +#define AD7768_SPI_DATA_MASK GENMASK(7, 0) +#define AD7768_SAMPLE_SIZE 32 +#define AD7768_MAX_CHANNEL 8 +#define AD7768_REV_ID_VAL 0x06 + +enum ad7768_power_modes { + AD7768_LOW_POWER_MODE, + AD7768_MEDIAN_MODE, + AD7768_FAST_MODE, + AD7768_NUM_POWER_MODES +}; + +struct ad7768_precharge_config { + bool prebufp_en; + bool prebufn_en; + bool refbufp; + bool refbufn; +}; + +struct ad7768_chip_info { + const char *name; + unsigned int num_channels; + const struct regmap_config *regmap_config; + const unsigned int *available_datalines; + unsigned int num_datalines; + const u8 *chan_map; + u8 prebuf_split; +}; + +struct ad7768_state { + struct regmap *regmap; + struct mutex lock; /* Protects device register access and configuration */ + struct clk *mclk; + unsigned int datalines; + const struct ad7768_chip_info *chip_info; + struct iio_backend *back; + + __be16 d16 __aligned(IIO_DMA_MINALIGN); +}; + +static const unsigned int ad7768_available_datalines[] =3D { + 1, 2, 8, +}; + +static const unsigned int ad7768_4_available_datalines[] =3D { + 1, 4, +}; + +static const u8 ad7768_chan_map[] =3D { + 0, 1, 2, 3, 4, 5, 6, 7, +}; + +static const u8 ad7768_4_chan_map[] =3D { + 0, 1, 4, 5, +}; + +static const char * const ad7768_supply_names[] =3D { + "avss", "avdd2", "iovdd", "ref1", "ref2", +}; + +static u8 ad7768_map_power_mode_to_regval(u8 x) +{ + return x ? (x + 1) : 0; +} + +static u8 ad7768_channel_mask(const struct ad7768_state *st, u8 ch) +{ + return BIT(st->chip_info->chan_map[ch]); +} + +static u8 ad7768_all_channels_mask(const struct ad7768_state *st) +{ + u8 mask =3D 0; + + for (unsigned int ch =3D 0; ch < st->chip_info->num_channels; ch++) + mask |=3D ad7768_channel_mask(st, ch); + + return mask; +} + +static u8 ad7768_precharge_buf1_mask(const struct ad7768_state *st, u16 va= l) +{ + return val & GENMASK(st->chip_info->prebuf_split - 1, 0); +} + +static u8 ad7768_precharge_buf2_mask(const struct ad7768_state *st, u16 va= l) +{ + return (val >> st->chip_info->prebuf_split) & + GENMASK(st->chip_info->prebuf_split - 1, 0); +} + +static int ad7768_regmap_read(void *context, const void *reg_buf, + size_t reg_size, void *val_buf, size_t val_size) +{ + struct spi_device *spi =3D context; + struct ad7768_state *st =3D spi_get_drvdata(spi); + u8 *data_val =3D val_buf; + unsigned int reg; + int ret; + struct spi_transfer t[] =3D { + { + .tx_buf =3D &st->d16, + .len =3D 2, + .cs_change =3D 1, + }, { + /* + * The second transfer clocks out the readback data, so + * we must provide dummy TX bytes while receiving the + * response. The device ignores MOSI in this phase, so + * reuse st->d16 for both TX and RX. + */ + .tx_buf =3D &st->d16, + .rx_buf =3D &st->d16, + .len =3D 2, + }, + }; + + reg =3D *(const u8 *)reg_buf; + + st->d16 =3D be16_replace_bits(cpu_to_be16(AD7768_SPI_READ_CMD), reg, + AD7768_SPI_REG_MASK); + + ret =3D spi_sync_transfer(spi, t, ARRAY_SIZE(t)); + if (ret) + return ret; + + *data_val =3D be16_get_bits(st->d16, AD7768_SPI_DATA_MASK); + + return 0; +} + +static int ad7768_regmap_write(void *context, const void *data, size_t cou= nt) +{ + struct spi_device *spi =3D context; + + return spi_write(spi, data, count); +} + +static const struct regmap_bus ad7768_regmap_bus =3D { + .read =3D ad7768_regmap_read, + .write =3D ad7768_regmap_write, + .reg_format_endian_default =3D REGMAP_ENDIAN_BIG, + .val_format_endian_default =3D REGMAP_ENDIAN_BIG, +}; + +static bool ad7768_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AD7768_REG_CH_STANDBY ... AD7768_REG_REV_ID: + case AD7768_REG_GPIO_CONTROL ... AD7768_REG_REFN_BUF: + return true; + case AD7768_REG_OFFSET(0) ... AD7768_REG_OFFSET(7) + 2: + case AD7768_REG_GAIN(0) ... AD7768_REG_GAIN(7) + 2: + case AD7768_REG_PHASE(0) ... AD7768_REG_PHASE(7): + case AD7768_REG_DIAGNOSTIC_RX ... AD7768_REG_CHOP_CTRL: + return true; + default: + return false; + } +} + +static bool ad7768_4_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AD7768_REG_CH_STANDBY ... AD7768_REG_REV_ID: + case AD7768_REG_GPIO_CONTROL ... AD7768_REG_REFN_BUF: + return true; + case AD7768_4_REG_OFFSET(0) ... AD7768_4_REG_OFFSET(1) + 2: + case AD7768_4_REG_OFFSET(2) ... AD7768_4_REG_OFFSET(3) + 2: + case AD7768_4_REG_GAIN(0) ... AD7768_4_REG_GAIN(1) + 2: + case AD7768_4_REG_GAIN(2) ... AD7768_4_REG_GAIN(3) + 2: + case AD7768_4_REG_PHASE(0) ... AD7768_4_REG_PHASE(1): + case AD7768_4_REG_PHASE(2) ... AD7768_4_REG_PHASE(3): + case AD7768_REG_DIAGNOSTIC_RX ... AD7768_REG_CHOP_CTRL: + return true; + default: + return false; + } +} + +static const struct regmap_config ad7768_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D AD7768_REG_CHOP_CTRL, + .use_single_read =3D true, + .use_single_write =3D true, + .readable_reg =3D ad7768_readable_reg, +}; + +static const struct regmap_config ad7768_4_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D AD7768_REG_CHOP_CTRL, + .use_single_read =3D true, + .use_single_write =3D true, + .readable_reg =3D ad7768_4_readable_reg, +}; + +static int ad7768_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(regmap_get_device(st->regmap), = pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static int ad7768_sync(struct ad7768_state *st) +{ + int ret; + + ret =3D regmap_update_bits(st->regmap, AD7768_REG_DATA_CONTROL, + AD7768_DATA_CONTROL_SPI_SYNC_MSK, 0); + if (ret) + return ret; + + return regmap_update_bits(st->regmap, AD7768_REG_DATA_CONTROL, + AD7768_DATA_CONTROL_SPI_SYNC_MSK, + FIELD_PREP(AD7768_DATA_CONTROL_SPI_SYNC_MSK, 1)); +} + +static int ad7768_configure_capture(struct ad7768_state *st) +{ + unsigned int dclk_div; + unsigned int regval; + int ret; + + regval =3D ad7768_map_power_mode_to_regval(AD7768_FAST_MODE); + ret =3D regmap_update_bits(st->regmap, AD7768_REG_POWER_MODE, + AD7768_POWER_MODE_POWER_MODE_MSK | + AD7768_POWER_MODE_MCLK_DIV_MSK, + AD7768_POWER_MODE_POWER_MODE(regval) | + FIELD_PREP(AD7768_POWER_MODE_MCLK_DIV_MSK, regval)); + if (ret) + return ret; + + /* + * Start with the wideband filter and a decimation rate of 64. This + * supports every valid data-line configuration at the maximum MCLK. + */ + ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(0), + AD7768_CH_MODE_FILTER_TYPE_MSK | + AD7768_CH_MODE_DEC_RATE_MSK, + AD7768_CH_MODE_FILTER_TYPE_MODE(0) | + AD7768_CH_MODE_DEC_RATE_MODE(1)); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD7768_REG_CH_MODE_SEL, 0); + if (ret) + return ret; + + dclk_div =3D 8 * st->datalines / st->chip_info->num_channels; + ret =3D regmap_update_bits(st->regmap, AD7768_REG_INTERFACE_CFG, + AD7768_INTERFACE_CFG_DCLK_DIV_MSK, + AD7768_INTERFACE_CFG_DCLK_DIV_MODE(dclk_div)); + if (ret) + return ret; + + return ad7768_sync(st); +} + +static int ad7768_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + unsigned int channel_mask; + unsigned int standby_mask; + unsigned int c; + int ret; + + channel_mask =3D ad7768_all_channels_mask(st); + standby_mask =3D channel_mask; + for (c =3D 0; c < st->chip_info->num_channels; c++) { + if (test_bit(c, scan_mask)) + standby_mask &=3D ~ad7768_channel_mask(st, c); + } + + ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_STANDBY, + channel_mask, standby_mask); + if (ret) + return ret; + + for (c =3D 0; c < st->chip_info->num_channels; c++) { + if (test_bit(c, scan_mask)) + ret =3D iio_backend_chan_enable(st->back, c); + else + ret =3D iio_backend_chan_disable(st->back, c); + if (ret) + return ret; + } + + return 0; +} + +static const struct ad7768_chip_info ad7768_chip_info =3D { + .name =3D "ad7768", + .num_channels =3D 8, + .regmap_config =3D &ad7768_regmap_config, + .available_datalines =3D ad7768_available_datalines, + .num_datalines =3D ARRAY_SIZE(ad7768_available_datalines), + .chan_map =3D ad7768_chan_map, + .prebuf_split =3D 8, +}; + +static const struct ad7768_chip_info ad7768_4_chip_info =3D { + .name =3D "ad7768-4", + .num_channels =3D 4, + .regmap_config =3D &ad7768_4_regmap_config, + .available_datalines =3D ad7768_4_available_datalines, + .num_datalines =3D ARRAY_SIZE(ad7768_4_available_datalines), + .chan_map =3D ad7768_4_chan_map, + .prebuf_split =3D 4, +}; + +static int ad7768_buffer_preenable(struct iio_dev *indio_dev) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + return pm_runtime_resume_and_get(regmap_get_device(st->regmap)); +} + +static int ad7768_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + pm_runtime_put_autosuspend(regmap_get_device(st->regmap)); + return 0; +} + +static const struct iio_buffer_setup_ops ad7768_buffer_ops =3D { + .preenable =3D ad7768_buffer_preenable, + .postdisable =3D ad7768_buffer_postdisable, +}; + +static const struct iio_info ad7768_info =3D { + .debugfs_reg_access =3D ad7768_reg_access, + .update_scan_mode =3D ad7768_update_scan_mode, +}; + +static int ad7768_configure_precharge_buffers(struct iio_dev *indio_dev, + struct ad7768_precharge_config *precharge_cfg) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + u8 prebuf1_val, prebuf2_val; + u16 prebuf_mask =3D 0; + u8 refbufp_val =3D 0; + u8 refbufn_val =3D 0; + int ret; + u8 ch; + + for (ch =3D 0; ch < indio_dev->num_channels; ch++) { + u8 channel =3D indio_dev->channels[ch].channel; + + if (precharge_cfg[channel].prebufp_en) + prebuf_mask |=3D AD7768_PREBUF_POS_EN(channel); + + if (precharge_cfg[channel].prebufn_en) + prebuf_mask |=3D AD7768_PREBUF_NEG_EN(channel); + + if (precharge_cfg[channel].refbufp) + refbufp_val |=3D ad7768_channel_mask(st, channel); + + if (precharge_cfg[channel].refbufn) + refbufn_val |=3D ad7768_channel_mask(st, channel); + } + + prebuf1_val =3D ad7768_precharge_buf1_mask(st, ~prebuf_mask); + prebuf2_val =3D ad7768_precharge_buf2_mask(st, ~prebuf_mask); + + ret =3D regmap_write(st->regmap, AD7768_REG_PRECHARGE_BUF1, prebuf1_val); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD7768_REG_PRECHARGE_BUF2, prebuf2_val); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD7768_REG_REFP_BUF, refbufp_val); + if (ret) + return ret; + + return regmap_write(st->regmap, AD7768_REG_REFN_BUF, refbufn_val); +} + +static int ad7768_parse_config(struct iio_dev *indio_dev, + struct device *dev) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + const unsigned int *available_datalines; + struct ad7768_precharge_config precharge_cfg[AD7768_MAX_CHANNEL] =3D { }; + struct iio_chan_spec *chan; + unsigned int num_channels; + unsigned int channel; + unsigned int i, len; + int chan_idx =3D 0; + int ret; + + num_channels =3D 0; + device_for_each_child_node_scoped(dev, child) { + if (!fwnode_property_present(child, "reg")) + continue; + + num_channels++; + } + + if (!num_channels || num_channels > st->chip_info->num_channels) + return dev_err_probe(dev, -EINVAL, "Invalid number of channels\n"); + + chan =3D devm_kcalloc(indio_dev->dev.parent, num_channels, + sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + indio_dev->channels =3D chan; + indio_dev->num_channels =3D num_channels; + + ret =3D regmap_write(st->regmap, AD7768_REG_CH_STANDBY, + ad7768_all_channels_mask(st)); + if (ret) + return ret; + + device_for_each_child_node_scoped(dev, child) { + if (!fwnode_property_present(child, "reg")) + continue; + + ret =3D fwnode_property_read_u32(child, "reg", &channel); + if (ret) + return dev_err_probe(dev, ret, + "Failed to parse reg property of %pfwP\n", + child); + + if (channel >=3D st->chip_info->num_channels) + return dev_err_probe(dev, -EINVAL, + "Invalid channel number %d from firmware\n", + channel); + + ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_STANDBY, + ad7768_channel_mask(st, channel), 0); + if (ret) + return ret; + + if (fwnode_property_read_bool(child, "adi,prechargebuf-pos-enable")) + precharge_cfg[channel].prebufp_en =3D true; + + if (fwnode_property_read_bool(child, "adi,prechargebuf-neg-enable")) + precharge_cfg[channel].prebufn_en =3D true; + + if (fwnode_property_read_bool(child, "adi,refbuf-pos-enable")) + precharge_cfg[channel].refbufp =3D true; + + if (fwnode_property_read_bool(child, "adi,refbuf-neg-enable")) + precharge_cfg[channel].refbufn =3D true; + + chan[chan_idx] =3D (struct iio_chan_spec) { + .type =3D IIO_VOLTAGE, + .indexed =3D 1, + .address =3D channel, + .channel =3D channel, + .scan_index =3D channel, + .scan_type =3D { + .sign =3D 's', + .realbits =3D 24, + .storagebits =3D 32, + }, + }; + chan_idx++; + } + + ret =3D ad7768_configure_precharge_buffers(indio_dev, precharge_cfg); + if (ret) + return ret; + + st->datalines =3D st->chip_info->available_datalines[st->chip_info->num_d= atalines - 1]; + ret =3D device_property_read_u32(dev, "adi,data-lines-number", + &st->datalines); + if (ret && ret !=3D -EINVAL) + return dev_err_probe(dev, ret, + "Invalid \"adi,data-lines-number\" property\n"); + + available_datalines =3D st->chip_info->available_datalines; + len =3D st->chip_info->num_datalines; + + for (i =3D 0; i < len; i++) { + if (available_datalines[i] =3D=3D st->datalines) + break; + } + + if (i =3D=3D len) + return dev_err_probe(dev, -EINVAL, + "Invalid data-lines-number %d for %s\n", + st->datalines, st->chip_info->name); + + return ad7768_configure_capture(st); +} + +static int ad7768_reset(struct ad7768_state *st) +{ + struct reset_control *reset_ctrl; + unsigned long reset_low_us; + unsigned long mclk; + int ret; + + reset_ctrl =3D devm_reset_control_get_optional_exclusive(regmap_get_devic= e(st->regmap), + NULL); + if (IS_ERR(reset_ctrl)) + return PTR_ERR(reset_ctrl); + + if (reset_ctrl) { + mclk =3D clk_get_rate(st->mclk); + if (!mclk) + return -EINVAL; + + /* Minimum RESET low pulse width: 2 x tMCLK (datasheet Table 1). */ + reset_low_us =3D DIV_ROUND_UP_ULL(2ULL * USEC_PER_SEC, mclk); + + ret =3D reset_control_assert(reset_ctrl); + if (ret) + return ret; + + fsleep(max_t(unsigned long, 1, reset_low_us)); + + ret =3D reset_control_deassert(reset_ctrl); + if (ret) + return ret; + } else { + ret =3D regmap_write(st->regmap, AD7768_REG_DATA_CONTROL, + AD7768_DATA_CONTROL_SPI_RESET_1); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD7768_REG_DATA_CONTROL, + AD7768_DATA_CONTROL_SPI_RESET_2); + if (ret) + return ret; + } + + /* ADC start-up time after reset: 1.66 ms max (datasheet Table 1) */ + fsleep(2000); + + return 0; +} + +static int ad7768_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + unsigned int spi_readback, rev_id; + struct iio_dev *indio_dev; + struct ad7768_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + spi_set_drvdata(spi, st); + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + st->chip_info =3D spi_get_device_match_data(spi); + + ret =3D devm_regulator_get_enable(dev, "avdd1"); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable AVDD1 supply\n"); + + ret =3D devm_regulator_bulk_get_enable(dev, + ARRAY_SIZE(ad7768_supply_names), + ad7768_supply_names); + if (ret) + return ret; + + st->mclk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(st->mclk)) + return PTR_ERR(st->mclk); + + st->regmap =3D devm_regmap_init(dev, &ad7768_regmap_bus, spi, + st->chip_info->regmap_config); + if (IS_ERR(st->regmap)) + return PTR_ERR(st->regmap); + + ret =3D ad7768_reset(st); + if (ret) + return ret; + + /* Dummy SPI register read to discard the Reset response from the chip */ + ret =3D regmap_read(st->regmap, AD7768_REG_REV_ID, &spi_readback); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD7768_REG_REV_ID, &rev_id); + if (ret) + return ret; + + if (rev_id !=3D AD7768_REV_ID_VAL) + dev_warn(dev, "Unexpected revision ID 0x%02x\n", rev_id); + + ret =3D ad7768_parse_config(indio_dev, dev); + if (ret) + return ret; + + ret =3D regmap_update_bits(st->regmap, AD7768_REG_INTERFACE_CFG, + AD7768_INTERFACE_CFG_CRC_SELECT_MSK, + AD7768_INTERFACE_CFG_CRC_SELECT); + if (ret) + return ret; + + indio_dev->name =3D st->chip_info->name; + indio_dev->info =3D &ad7768_info; + + st->back =3D devm_iio_backend_get(dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + ret =3D devm_iio_backend_request_buffer(dev, st->back, indio_dev); + if (ret) + return ret; + + ret =3D iio_backend_num_lanes_set(st->back, st->datalines); + if (ret) + return ret; + + ret =3D iio_backend_crc_enable(st->back); + if (ret) + return ret; + + ret =3D devm_iio_backend_enable(dev, st->back); + if (ret) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 2000); + pm_runtime_use_autosuspend(dev); + ret =3D devm_pm_runtime_set_active_enabled(dev); + if (ret) + return ret; + + indio_dev->setup_ops =3D &ad7768_buffer_ops; + + ret =3D devm_iio_device_register(dev, indio_dev); + if (ret) + return ret; + + ret =3D pm_request_autosuspend(dev); + if (ret < 0 && ret !=3D -EAGAIN) + return dev_err_probe(dev, ret, + "Failed to request initial autosuspend\n"); + + return 0; +} + +static int ad7768_runtime_suspend(struct device *dev) +{ + struct ad7768_state *st =3D dev_get_drvdata(dev); + + return regmap_set_bits(st->regmap, AD7768_REG_POWER_MODE, + AD7768_SLEEP_MODE_MSK); +} + +static int ad7768_runtime_resume(struct device *dev) +{ + struct ad7768_state *st =3D dev_get_drvdata(dev); + int ret; + + ret =3D regmap_clear_bits(st->regmap, AD7768_REG_POWER_MODE, + AD7768_SLEEP_MODE_MSK); + if (ret) + return ret; + + /* Empirically determined delay to re-enable ADC and digital clocks.*/ + fsleep(20000); + + return 0; +} + +static DEFINE_RUNTIME_DEV_PM_OPS(ad7768_pm_ops, ad7768_runtime_suspend, + ad7768_runtime_resume, NULL); + +static const struct of_device_id ad7768_of_match[] =3D { + { .compatible =3D "adi,ad7768", .data =3D &ad7768_chip_info }, + { .compatible =3D "adi,ad7768-4", .data =3D &ad7768_4_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, ad7768_of_match); + +static const struct spi_device_id ad7768_spi_id[] =3D { + {"ad7768", (kernel_ulong_t)&ad7768_chip_info}, + {"ad7768-4", (kernel_ulong_t)&ad7768_4_chip_info}, + { } +}; +MODULE_DEVICE_TABLE(spi, ad7768_spi_id); + +static struct spi_driver ad7768_driver =3D { + .probe =3D ad7768_probe, + .driver =3D { + .name =3D "ad7768", + .of_match_table =3D ad7768_of_match, + .pm =3D pm_ptr(&ad7768_pm_ops), + }, + .id_table =3D ad7768_spi_id, +}; +module_spi_driver(ad7768_driver); + +MODULE_AUTHOR("Stefan Popa "); +MODULE_AUTHOR("Janani Sunil "); +MODULE_DESCRIPTION("Analog Devices AD7768 ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_BACKEND"); --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4875A48165B; Thu, 13 Aug 2026 13:58:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629495; cv=none; b=E+aiTKgWmFaKizXouKy8qhoY+EfZAlSF2UezWpDS0k9yE/dcZhQH6NE2nmGELxTfl011WClXo6lAWpZ/qIM4Lr8T+bT1Id5w26EIjI0SxLgrdtIX/oOZVZbp45rVLHBsH7Hig0b/r2N+WXaGzUT36mRjInmubzOgWp9QnM2Nku8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629495; c=relaxed/simple; bh=MRlxmvZgUYvkNw2WavYW1bUulKMKjOx0Bzp3UgavGss=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=c2WhXttL2nQEsxMt/cC4pMLIY7bMHbGPSbcArZOa8fSX5yWZAncPnIdBNm47p2bUHVXk/H6+XFFz0M/ziXm8bQx0cL8VEbnGMMenaHesUhnEsb0bV5okcHjxBuIQ7iCGAtvdOhNGSMoTFgf8m0ELZ1YPdQMteQv2Kz+jhY+nOjE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=BYpKWnK6; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="BYpKWnK6" Received: from pps.filterd (m0516787.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCa9WQ2129076; Thu, 13 Aug 2026 09:58:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=OF2Mz 7c+7fxGrlrx3o7QaxleGrvmmjB4c+JnSruOJZQ=; b=BYpKWnK6DFBl+IAIbix8K IesLXaCGsMTAwqoHzyDMiGFssOm4Lw1B4sjKqFR77JnosmCkXKnleyeKV5GQPsYM ux1V2sXi4zPovx/Uv0NeTMOMrm9S8MPXncJOMANFUAMWrTStuYVireTpmaX7IFVj LxsLtlBqcPzZVZxjgFLB3CCrvUkYy7VqTRBjUTPt45O9pv3EaYNCOFD1NkS/nWl7 C+vhtoQgdZ4SQfFqzBr0G6rnNCXekiXf4eLW1Kkss9Ia0ehFHILeZlwXuKe14AIF 00ozinSHX2eVxAbCguLtfMuGLl/FX32mEXWINpkEwiRLzzUcJ1N9FsP+bzztfIGG g== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e2wgccm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:58:00 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDvx5T024639 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:57:59 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:57:59 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:57:59 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwY006802; Thu, 13 Aug 2026 09:57:51 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:56:59 +0200 Subject: [PATCH v3 06/14] iio: adc: ad7768: Add configurable sampling modes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-6-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=20056; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=MRlxmvZgUYvkNw2WavYW1bUulKMKjOx0Bzp3UgavGss=; b=PFsKzy01Rfc5j+toAiZddIUJTJ8X0kfwbr4NnW89SvJNsQlkzzT0hNBWx79k7EqHj1E4JwL/e GZD5t0Lg3HaApA3efJAZbrY1ursfpdMuIjvgWiNqcWsaT8XmRDLj3VK X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfXyNd4vnjYYekK Zz6NVuER8szyyjcJZXVGbc4udeVJmYrjWqfxjFxYCarRLR9rxrbPrQxGeO9deycF/v75kK2V0qb sAvaHzhTNaX+lyqcuR1XtvzB1tj2VRR6U/Xz3xnlNzjtWHMhVXML X-Proofpoint-GUID: B0XFVwvkd7d-UbMIQ0Jxh5zvaGY2xbj8 X-Authority-Analysis: v=2.4 cv=UJzt2ify c=1 sm=1 tr=0 ts=6a7dcd68 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=gAnH3GRIAAAA:8 a=1WhRpiEg_uwopUd1aA8A:9 a=QEXdDO2ut3YA:10 a=br55WurUj89AL1qEz8Q6:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX2UaDWbTdwuG3 P4Xwu2H3+OvlzKCW5Nxswe+XCrN3TVTmI4d1OBKskckHqZ04f1nl6KbWW9vxz8BRhfFGawuyyVr 3TlfqTUAX2u76gxrUxq3+24i33lY2FBKpM20VVX/prBCrblNGBaj7Ic8RzxfMAWRcEO7BurJEXX tWbyiAm/hfkCnmpdAl4KQ7UPs5b7A+S+lJBzPDtviBOP7u1wSEb/yuekt0JgkwWDOuQyU9RFQS5 q5SfTOQBm0PUS/lEDaCIjVXTxHz9PY2SEq7pkDGwcmieJYR4B/8Gh4KW/v27gaaIISrvvEheowf W5iIokhNB9ZBMR5u+bzSyXHQ0qtZgxmapNyrEr9V//pzV5hCA0Ea6JHbcC8qf/5JfXutAsFzFD+ Lnyg7WNODi2RYU9+4tntk1JDy4Plzd74jsz94D/aC78zOmCn0I2mQGF+IBv6t9VoBe/lqW2mh+r FQ4366BKm6A/qiy9Zzw== X-Proofpoint-ORIG-GUID: B0XFVwvkd7d-UbMIQ0Jxh5zvaGY2xbj8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Derive the available output data rates from MCLK and expose per-channel sampling frequency and filter controls. Select the fastest compatible power mode for the enabled channels and map matching sampling frequency and filter combinations onto the two hardware channel profiles. Configure the data clock divider and wait for the selected filters to settle before capture. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 507 +++++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 477 insertions(+), 30 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 9b908ce0a1c3..3849f544a1e5 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -94,8 +95,17 @@ #define AD7768_SPI_REG_MASK GENMASK(14, 8) #define AD7768_SPI_DATA_MASK GENMASK(7, 0) #define AD7768_SAMPLE_SIZE 32 +#define MAX_FREQ_PER_MODE 6 #define AD7768_MAX_CHANNEL 8 +#define AD7768_NUM_CHANNEL_MODES 2 #define AD7768_REV_ID_VAL 0x06 +#define AD7768_WIDEBAND_SETTLING_SAMPLES 68 +#define AD7768_SINC5_SETTLING_SAMPLES 7 + +enum ad7768_filter_type { + AD7768_FILTER_TYPE_WIDEBAND, + AD7768_FILTER_TYPE_SINC5, +}; =20 enum ad7768_power_modes { AD7768_LOW_POWER_MODE, @@ -104,6 +114,8 @@ enum ad7768_power_modes { AD7768_NUM_POWER_MODES }; =20 +#define AD7768_MAX_FREQS (MAX_FREQ_PER_MODE + AD7768_NUM_POWER_MODES) + struct ad7768_precharge_config { bool prebufp_en; bool prebufn_en; @@ -111,6 +123,17 @@ struct ad7768_precharge_config { bool refbufn; }; =20 +struct ad7768_freq_config { + unsigned int freq_hz; + unsigned int dec_rate; +}; + +struct ad7768_avail_freq { + unsigned int n_freqs; + unsigned int freqs[MAX_FREQ_PER_MODE]; + struct ad7768_freq_config freq_cfg[MAX_FREQ_PER_MODE]; +}; + struct ad7768_chip_info { const char *name; unsigned int num_channels; @@ -126,12 +149,26 @@ struct ad7768_state { struct mutex lock; /* Protects device register access and configuration */ struct clk *mclk; unsigned int datalines; + enum ad7768_power_modes power_mode; const struct ad7768_chip_info *chip_info; + struct ad7768_avail_freq avail_freq[AD7768_NUM_POWER_MODES]; + unsigned int n_freqs; + int freqs[AD7768_MAX_FREQS]; + unsigned int ch_freq[AD7768_MAX_CHANNEL]; + enum ad7768_filter_type ch_filter[AD7768_MAX_CHANNEL]; struct iio_backend *back; =20 __be16 d16 __aligned(IIO_DMA_MINALIGN); }; =20 +static const int ad7768_dec_rate[MAX_FREQ_PER_MODE] =3D { + 32, 64, 128, 256, 512, 1024, +}; + +static const int ad7768_mclk_div[3] =3D { + 32, 8, 4, +}; + static const unsigned int ad7768_available_datalines[] =3D { 1, 2, 8, }; @@ -323,61 +360,253 @@ static int ad7768_sync(struct ad7768_state *st) FIELD_PREP(AD7768_DATA_CONTROL_SPI_SYNC_MSK, 1)); } =20 -static int ad7768_configure_capture(struct ad7768_state *st) +static int ad7768_set_power_mode(struct ad7768_state *st, unsigned int mod= e) { - unsigned int dclk_div; unsigned int regval; int ret; =20 - regval =3D ad7768_map_power_mode_to_regval(AD7768_FAST_MODE); + if (mode >=3D AD7768_NUM_POWER_MODES) + return -EINVAL; + + regval =3D ad7768_map_power_mode_to_regval(mode); ret =3D regmap_update_bits(st->regmap, AD7768_REG_POWER_MODE, - AD7768_POWER_MODE_POWER_MODE_MSK | - AD7768_POWER_MODE_MCLK_DIV_MSK, - AD7768_POWER_MODE_POWER_MODE(regval) | - FIELD_PREP(AD7768_POWER_MODE_MCLK_DIV_MSK, regval)); + AD7768_POWER_MODE_POWER_MODE_MSK, + AD7768_POWER_MODE_POWER_MODE(regval)); if (ret) return ret; =20 - /* - * Start with the wideband filter and a decimation rate of 64. This - * supports every valid data-line configuration at the maximum MCLK. - */ - ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(0), - AD7768_CH_MODE_FILTER_TYPE_MSK | - AD7768_CH_MODE_DEC_RATE_MSK, - AD7768_CH_MODE_FILTER_TYPE_MODE(0) | - AD7768_CH_MODE_DEC_RATE_MODE(1)); + ret =3D regmap_update_bits(st->regmap, AD7768_REG_POWER_MODE, + AD7768_POWER_MODE_MCLK_DIV_MSK, + FIELD_PREP(AD7768_POWER_MODE_MCLK_DIV_MSK, regval)); if (ret) return ret; =20 - ret =3D regmap_write(st->regmap, AD7768_REG_CH_MODE_SEL, 0); + ret =3D ad7768_sync(st); if (ret) return ret; =20 - dclk_div =3D 8 * st->datalines / st->chip_info->num_channels; - ret =3D regmap_update_bits(st->regmap, AD7768_REG_INTERFACE_CFG, - AD7768_INTERFACE_CFG_DCLK_DIV_MSK, - AD7768_INTERFACE_CFG_DCLK_DIV_MODE(dclk_div)); - if (ret) - return ret; + st->power_mode =3D mode; =20 - return ad7768_sync(st); + return 0; } =20 -static int ad7768_update_scan_mode(struct iio_dev *indio_dev, - const unsigned long *scan_mask) +static int ad7768_set_clk_divs(struct ad7768_state *st, + unsigned int freq) +{ + unsigned int mclk, dclk, dclk_div, i; + struct ad7768_freq_config f_cfg =3D {}; + unsigned int chan_per_doutx; + + mclk =3D clk_get_rate(st->mclk); + + chan_per_doutx =3D st->chip_info->num_channels / st->datalines; + if (!chan_per_doutx) + return -EINVAL; + + for (i =3D 0; i < st->avail_freq[st->power_mode].n_freqs; i++) { + f_cfg =3D st->avail_freq[st->power_mode].freq_cfg[i]; + if (freq =3D=3D f_cfg.freq_hz) + break; + } + + if (i =3D=3D st->avail_freq[st->power_mode].n_freqs) + return -EINVAL; + + dclk =3D f_cfg.freq_hz * AD7768_SAMPLE_SIZE * chan_per_doutx; + if (!dclk || dclk > mclk) + return -EINVAL; + + /* Set dclk_div to the nearest power of 2 less than the original value */ + dclk_div =3D DIV_ROUND_CLOSEST(mclk, dclk); + if (dclk_div > AD7768_MAX_DCLK_DIV) + dclk_div =3D AD7768_MAX_DCLK_DIV; + else + dclk_div =3D rounddown_pow_of_two(dclk_div); + + return regmap_update_bits(st->regmap, AD7768_REG_INTERFACE_CFG, + AD7768_INTERFACE_CFG_DCLK_DIV_MSK, + AD7768_INTERFACE_CFG_DCLK_DIV_MODE(dclk_div)); +} + +static bool ad7768_freq_supported(const struct ad7768_state *st, + unsigned int mode, unsigned int freq) +{ + for (unsigned int i =3D 0; i < st->avail_freq[mode].n_freqs; i++) { + if (freq =3D=3D st->avail_freq[mode].freq_cfg[i].freq_hz) + return true; + } + + return false; +} + +static bool ad7768_freq_supported_in_any_mode(const struct ad7768_state *s= t, + unsigned int freq) +{ + for (unsigned int mode =3D 0; mode < AD7768_NUM_POWER_MODES; mode++) { + if (ad7768_freq_supported(st, mode, freq)) + return true; + } + + return false; +} + +static int ad7768_set_lowest_noise_mode(struct ad7768_state *st, + const unsigned long *scan_mask) +{ + unsigned int channel; + unsigned int mode =3D AD7768_NUM_POWER_MODES; + + /* + * The output data rate ranges overlap between the power modes. At a + * common ODR, the faster mode has lower noise, so prefer the fastest + * mode that supports every enabled channel. + */ + while (mode--) { + for (channel =3D 0; channel < st->chip_info->num_channels; channel++) { + if (test_bit(channel, scan_mask) && + !ad7768_freq_supported(st, mode, st->ch_freq[channel])) + break; + } + + if (channel =3D=3D st->chip_info->num_channels) + return ad7768_set_power_mode(st, mode); + } + + return -EINVAL; +} + +static int ad7768_set_mode_decimation(struct ad7768_state *st, + unsigned int freq, unsigned int mode) +{ + struct ad7768_freq_config f_cfg =3D {}; + unsigned int i; + + for (i =3D 0; i < st->avail_freq[st->power_mode].n_freqs; i++) { + f_cfg =3D st->avail_freq[st->power_mode].freq_cfg[i]; + if (freq =3D=3D f_cfg.freq_hz) + break; + } + + if (i =3D=3D st->avail_freq[st->power_mode].n_freqs) + return -EINVAL; + + return regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(mode), + AD7768_CH_MODE_DEC_RATE_MSK, + AD7768_CH_MODE_DEC_RATE_MODE(f_cfg.dec_rate)); +} + +static int ad7768_set_sampling_freq(struct iio_dev *indio_dev, + unsigned int freq, unsigned int ch) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + if (!freq) + return -EINVAL; + + if (!ad7768_freq_supported_in_any_mode(st, freq)) + return -EINVAL; + + guard(mutex)(&st->lock); + + st->ch_freq[ch] =3D freq; + + return 0; +} + +static void ad7768_filter_wait(const unsigned int *mode_freq, + const enum ad7768_filter_type *mode_filter, + const bool *mode_used) +{ + unsigned int t_settle_us =3D 0; + + for (unsigned int mode =3D 0; mode < AD7768_NUM_CHANNEL_MODES; mode++) { + unsigned int t_mode_us; + unsigned int settling_samples; + + if (!mode_used[mode] || !mode_freq[mode]) + continue; + + if (mode_filter[mode] =3D=3D AD7768_FILTER_TYPE_SINC5) + settling_samples =3D AD7768_SINC5_SETTLING_SAMPLES; + else + settling_samples =3D AD7768_WIDEBAND_SETTLING_SAMPLES; + + t_mode_us =3D DIV_ROUND_UP(settling_samples * USEC_PER_SEC, + mode_freq[mode]); + t_settle_us =3D max(t_settle_us, t_mode_us); + } + + if (t_settle_us) + fsleep(t_settle_us); +} + +static int ad7768_find_matching_mode(const bool *mode_used, + const unsigned int *mode_freq, + const enum ad7768_filter_type *mode_filter, + unsigned int freq, + enum ad7768_filter_type filter) +{ + unsigned int mode; + + for (mode =3D 0; mode < AD7768_NUM_CHANNEL_MODES; mode++) { + if (!mode_used[mode] || + (mode_freq[mode] =3D=3D freq && mode_filter[mode] =3D=3D filter)) + return mode; + } + + return -EINVAL; +} + +static int ad7768_apply_channel_modes(struct iio_dev *indio_dev, + const unsigned long *scan_mask) { struct ad7768_state *st =3D iio_priv(indio_dev); + unsigned int mode_freq[AD7768_NUM_CHANNEL_MODES]; + enum ad7768_filter_type mode_filter[AD7768_NUM_CHANNEL_MODES]; + bool mode_used[AD7768_NUM_CHANNEL_MODES] =3D { }; unsigned int channel_mask; unsigned int standby_mask; + unsigned int max_freq =3D 0; unsigned int c; - int ret; + int mode, ret; + + guard(mutex)(&st->lock); + + ret =3D ad7768_set_lowest_noise_mode(st, scan_mask); + if (ret =3D=3D -EINVAL) + return dev_err_probe(regmap_get_device(st->regmap), ret, + "No power mode supports all enabled channel frequencies\n"); + if (ret) + return ret; =20 channel_mask =3D ad7768_all_channels_mask(st); standby_mask =3D channel_mask; + for (c =3D 0; c < st->chip_info->num_channels; c++) { - if (test_bit(c, scan_mask)) - standby_mask &=3D ~ad7768_channel_mask(st, c); + unsigned int mask; + + if (!test_bit(c, scan_mask)) + continue; + + standby_mask &=3D ~ad7768_channel_mask(st, c); + + mode =3D ad7768_find_matching_mode(mode_used, mode_freq, + mode_filter, st->ch_freq[c], + st->ch_filter[c]); + if (mode < 0) + return dev_err_probe(regmap_get_device(st->regmap), -EINVAL, + "Enabled channels require more than %d mode profiles\n", + AD7768_NUM_CHANNEL_MODES); + + mode_freq[mode] =3D st->ch_freq[c]; + mode_filter[mode] =3D st->ch_filter[c]; + mode_used[mode] =3D true; + + mask =3D ad7768_channel_mask(st, c); + ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_MODE_SEL, + mask, mode ? mask : 0); + if (ret) + return ret; } =20 ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_STANDBY, @@ -385,6 +614,117 @@ static int ad7768_update_scan_mode(struct iio_dev *in= dio_dev, if (ret) return ret; =20 + for (mode =3D 0; mode < AD7768_NUM_CHANNEL_MODES; mode++) { + if (!mode_used[mode]) + continue; + + ret =3D ad7768_set_mode_decimation(st, mode_freq[mode], mode); + if (ret) + return ret; + + ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(mode), + AD7768_CH_MODE_FILTER_TYPE_MSK, + AD7768_CH_MODE_FILTER_TYPE_MODE(mode_filter[mode])); + if (ret) + return ret; + + max_freq =3D max(max_freq, mode_freq[mode]); + } + + ret =3D ad7768_set_clk_divs(st, max_freq); + if (ret) + return ret; + + ret =3D ad7768_sync(st); + if (ret) + return ret; + + /* Apply a filter settling time (Datasheet table 35 and 36) */ + ad7768_filter_wait(mode_freq, mode_filter, mode_used); + + return 0; +} + +static int ad7768_read_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + int *val, int *val2, long info) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(regmap_get_device(st->regmap), = pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + if (info !=3D IIO_CHAN_INFO_SAMP_FREQ) + return -EINVAL; + + guard(mutex)(&st->lock); + *val =3D st->ch_freq[chan->channel]; + + return IIO_VAL_INT; +} + +static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long info) +{ + if (info =3D=3D IIO_CHAN_INFO_SAMP_FREQ) + return IIO_VAL_INT; + + return -EINVAL; +} + +static int ad7768_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(regmap_get_device(st->regmap), = pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + if (info =3D=3D IIO_CHAN_INFO_SAMP_FREQ) + return ad7768_set_sampling_freq(indio_dev, val, chan->channel); + + return -EINVAL; +} + +static int ad7768_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + if (info !=3D IIO_CHAN_INFO_SAMP_FREQ) + return -EINVAL; + + *vals =3D st->freqs; + *type =3D IIO_VAL_INT; + *length =3D st->n_freqs; + + return IIO_AVAIL_LIST; +} + +static int ad7768_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + unsigned int c; + int ret; + + ret =3D ad7768_apply_channel_modes(indio_dev, scan_mask); + if (ret) + return ret; + for (c =3D 0; c < st->chip_info->num_channels; c++) { if (test_bit(c, scan_mask)) ret =3D iio_backend_chan_enable(st->back, c); @@ -439,9 +779,73 @@ static const struct iio_buffer_setup_ops ad7768_buffer= _ops =3D { =20 static const struct iio_info ad7768_info =3D { .debugfs_reg_access =3D ad7768_reg_access, + .read_raw =3D ad7768_read_raw, + .write_raw_get_fmt =3D ad7768_write_raw_get_fmt, + .write_raw =3D ad7768_write_raw, + .read_avail =3D ad7768_read_avail, .update_scan_mode =3D ad7768_update_scan_mode, }; =20 +static void ad7768_set_available_sampl_freq(struct ad7768_state *st) +{ + struct ad7768_avail_freq *avail_freq; + unsigned int mclk =3D clk_get_rate(st->mclk); + unsigned int mode; + + for (mode =3D 0; mode < AD7768_NUM_POWER_MODES; mode++) { + avail_freq =3D &st->avail_freq[mode]; + for (unsigned int dec =3D ARRAY_SIZE(ad7768_dec_rate); dec > 0; dec--) { + struct ad7768_freq_config freq_cfg; + + freq_cfg.dec_rate =3D dec - 1; + freq_cfg.freq_hz =3D mclk / (ad7768_dec_rate[dec - 1] * + ad7768_mclk_div[mode]); + avail_freq->freqs[avail_freq->n_freqs] =3D freq_cfg.freq_hz; + avail_freq->freq_cfg[avail_freq->n_freqs++] =3D freq_cfg; + } + } + + if (st->datalines =3D=3D 1 && + st->chip_info->num_channels =3D=3D AD7768_MAX_CHANNEL) + st->avail_freq[AD7768_FAST_MODE].n_freqs--; + + for (mode =3D 0; mode < AD7768_NUM_POWER_MODES; mode++) { + avail_freq =3D &st->avail_freq[mode]; + for (unsigned int i =3D 0; i < avail_freq->n_freqs; i++) { + unsigned int freq =3D avail_freq->freqs[i]; + + if (st->n_freqs && st->freqs[st->n_freqs - 1] >=3D freq) + continue; + + st->freqs[st->n_freqs++] =3D freq; + } + } +} + +static int ad7768_set_filter_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + guard(mutex)(&st->lock); + st->ch_filter[chan->channel] =3D mode; + return 0; +} + +static int ad7768_get_filter_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + return st->ch_filter[chan->channel]; +} + static int ad7768_configure_precharge_buffers(struct iio_dev *indio_dev, struct ad7768_precharge_config *precharge_cfg) { @@ -487,16 +891,37 @@ static int ad7768_configure_precharge_buffers(struct = iio_dev *indio_dev, return regmap_write(st->regmap, AD7768_REG_REFN_BUF, refbufn_val); } =20 +static const char *const ad7768_filter_types[] =3D { + [AD7768_FILTER_TYPE_WIDEBAND] =3D "wideband", + [AD7768_FILTER_TYPE_SINC5] =3D "sinc5", +}; + +static const struct iio_enum ad7768_filter_types_enum =3D { + .items =3D ad7768_filter_types, + .num_items =3D ARRAY_SIZE(ad7768_filter_types), + .set =3D ad7768_set_filter_mode, + .get =3D ad7768_get_filter_mode, +}; + +static struct iio_chan_spec_ext_info ad7768_ext_info[] =3D { + IIO_ENUM("filter_type", IIO_SEPARATE, + &ad7768_filter_types_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, &ad7768_filter_types_enum= ), + {} +}; + static int ad7768_parse_config(struct iio_dev *indio_dev, struct device *dev) { struct ad7768_state *st =3D iio_priv(indio_dev); + const struct ad7768_avail_freq *avail_freq; const unsigned int *available_datalines; struct ad7768_precharge_config precharge_cfg[AD7768_MAX_CHANNEL] =3D { }; struct iio_chan_spec *chan; unsigned int num_channels; unsigned int channel; unsigned int i, len; + unsigned int default_freq; int chan_idx =3D 0; int ret; =20 @@ -558,6 +983,9 @@ static int ad7768_parse_config(struct iio_dev *indio_de= v, =20 chan[chan_idx] =3D (struct iio_chan_spec) { .type =3D IIO_VOLTAGE, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_separate_available =3D + BIT(IIO_CHAN_INFO_SAMP_FREQ), .indexed =3D 1, .address =3D channel, .channel =3D channel, @@ -567,6 +995,7 @@ static int ad7768_parse_config(struct iio_dev *indio_de= v, .realbits =3D 24, .storagebits =3D 32, }, + .ext_info =3D ad7768_ext_info, }; chan_idx++; } @@ -582,6 +1011,22 @@ static int ad7768_parse_config(struct iio_dev *indio_= dev, return dev_err_probe(dev, ret, "Invalid \"adi,data-lines-number\" property\n"); =20 + ad7768_set_available_sampl_freq(st); + + /* Start in fast mode; capture setup may select another compatible mode. = */ + scoped_guard(mutex, &st->lock) { + ret =3D ad7768_set_power_mode(st, AD7768_FAST_MODE); + } + if (ret) + return dev_err_probe(dev, ret, "Failed to set power mode\n"); + + avail_freq =3D &st->avail_freq[AD7768_FAST_MODE]; + default_freq =3D avail_freq->freq_cfg[avail_freq->n_freqs - 1].freq_hz; + for (i =3D 0; i < st->chip_info->num_channels; i++) { + st->ch_freq[i] =3D default_freq; + st->ch_filter[i] =3D AD7768_FILTER_TYPE_WIDEBAND; + } + available_datalines =3D st->chip_info->available_datalines; len =3D st->chip_info->num_datalines; =20 @@ -595,7 +1040,7 @@ static int ad7768_parse_config(struct iio_dev *indio_d= ev, "Invalid data-lines-number %d for %s\n", st->datalines, st->chip_info->name); =20 - return ad7768_configure_capture(st); + return 0; } =20 static int ad7768_reset(struct ad7768_state *st) @@ -679,6 +1124,8 @@ static int ad7768_probe(struct spi_device *spi) st->mclk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(st->mclk)) return PTR_ERR(st->mclk); + if (!clk_get_rate(st->mclk)) + return dev_err_probe(dev, -EINVAL, "MCLK rate must be non-zero\n"); =20 st->regmap =3D devm_regmap_init(dev, &ad7768_regmap_bus, spi, st->chip_info->regmap_config); --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B172D48381C; Thu, 13 Aug 2026 13:58:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629497; cv=none; b=iRi0It748aGyCwj153QGPqA48Vmd2i2BJ2+0743st8bZd5HUug+JEgdFmRrRzavjdgGKTBW9jrZj6dr2UwnR2jHiAYAA/aJTr8Nj9wULJhl6k/xx3IyvuXi42zOMBOIQhVsNyboDsN7OgbPRPm96w1jiuEVb5BVp/Rc1DHjKqrE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629497; c=relaxed/simple; bh=UJWSoyXKe14qXIpvAb3M5QVG4cT+Njcg5l1hFRvSyHY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=daUmmH5qaTNXIenSnFM5d6f8RBg7da5DthLN1reNDY5JEcgB3SkbJ6hqbClJXChIYVw7frGfGRZ9Xdw9y6TFEBW3IFy9/9tbF9HEg4tNV2QAlh2w+zdGPJs0OIOz+PehzZt2aG0W6G5YK6Pk7DnjhFqvqawwD73GkbnFQPX9s7Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=ymh2Catq; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="ymh2Catq" Received: from pps.filterd (m0516787.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCa7xl2129063; Thu, 13 Aug 2026 09:58:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=vERAW jWK/FBbrldkzn0mpkTsowpwRtCAi+3UBq7AKno=; b=ymh2CatqR4F0q5AiuwvRD dMZEmxmevMETuw+8ThO6NsRS2Q0rA8arv5kblMGX5g1R2DrkcIlEMcIEVnpjcxbo eM812CyIVOIX2FctD9aw9FF8jymnYAlw9AmXWA+ZJ666jl0iXkgWETDipJNpwzI0 O92kyxHam756BpM8OqkI1lrfUrS9NVFJEvQaEeCTUbQK95f7s7MBTnGxB1LMB4U7 NMKtbJls5kRIIfBJgtoeaP1RFmfZtSVjVRrnV4+2KQdRs5cBeT034HUqSbYBSWez pUjCWYgmGBGyb/tJ4h7DIOD5Dvam4M9hAtqiFNh628pRTEVRUAIZ4Ct0YsEBZc0g w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e2wgccp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:58:02 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDw1d8024645 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:58:01 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:01 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:58:01 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwZ006802; Thu, 13 Aug 2026 09:57:54 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:57:00 +0200 Subject: [PATCH v3 07/14] iio: adc: ad7768: Add calibration controls Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-7-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=6085; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=UJWSoyXKe14qXIpvAb3M5QVG4cT+Njcg5l1hFRvSyHY=; b=9bkyBcjPZ2yzJ22h1QyxZ1T2T8Qi775ijwyl2B19vahytQIboKiJwph62joJ5SnAgbi3bOQP/ ul+KVIGZLYMDFxyBbBQgj2NiZvqlosyi4Gp4K+Srrla+82UM9zrPk7N X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfXx/Inru+u/Esx 3zdv6kI6W2MX5FhBBJNJkQUm8MIIh8dmO2rMQ2NG87FUvsUd+E9HG5X7Kn7HsZs95t0aR5Aky95 RTlh5et2gruN47p/3EG+S5EdDd6cML5pGVGCLq1TxMFdtIJ+ZTPh X-Proofpoint-GUID: W6y3S3N0m7lIOrhv0MW_X3lyb0Ljd60Z X-Authority-Analysis: v=2.4 cv=UJzt2ify c=1 sm=1 tr=0 ts=6a7dcd6a cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=gAnH3GRIAAAA:8 a=XhVhMDlc3cf8FCRBbCAA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX9XHj2m3R1lvT +kS/w8bd64Nv1qyc3YBIBjlf+k0HXgK/FU+JiWRz1XHQR9G/Cp8F2iFm458WkUQyzgfs7PdUAo8 1whhAWo7fI+O+r9uuvCO4Hp4c+ZeKqq0Ii9/zmT9iiV3jo99EiIfN8LV1vDIOKo4nSegA5acO1M /2ppJ4NgtJJKXYJmEw+awbeer4EG4GVi/xNOs8Vj26H/gFkOzeU9jltIg0+0e99ihCNcStAH59Z 4ofx1crhZkAGO3Y3GNNJCPBJmiZk3wh/MQaanqGNf+hbCCG4Zw2Q7/xzW4qZhLrlG3u6pZpCx8E 4ITNSLj13rXMM4JYkWhqhdI1aVNxraF7X5mqx6lRJ6IW6yJx5WgFp6o+I5VIv22kgNTM+MThN6v psGHAeU6CdbZXBCeuoDV1fJg1q4Bg9ZZqrJOPOUIFEde1+WhsSBWV3axR4t6uBYgHPPp/NuT69z 7zJaooHeGOg0YGvxhPQ== X-Proofpoint-ORIG-GUID: W6y3S3N0m7lIOrhv0MW_X3lyb0Ljd60Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Expose the per-channel offset and gain calibration registers through the IIO calibbias and calibscale attributes. Use bulk regmap operations and unaligned big-endian helpers to transfer the three register bytes. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 119 ++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 108 insertions(+), 11 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 3849f544a1e5..08721079bb37 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -25,6 +25,7 @@ #include #include #include +#include =20 #include #include @@ -98,6 +99,7 @@ #define MAX_FREQ_PER_MODE 6 #define AD7768_MAX_CHANNEL 8 #define AD7768_NUM_CHANNEL_MODES 2 +#define AD7768_CALIB_REG_MSK GENMASK(23, 0) #define AD7768_REV_ID_VAL 0x06 #define AD7768_WIDEBAND_SETTLING_SAMPLES 68 #define AD7768_SINC5_SETTLING_SAMPLES 7 @@ -209,6 +211,18 @@ static u8 ad7768_all_channels_mask(const struct ad7768= _state *st) return mask; } =20 +static unsigned int ad7768_offset_reg(const struct ad7768_state *st, + unsigned int ch) +{ + return AD7768_REG_OFFSET(st->chip_info->chan_map[ch]); +} + +static unsigned int ad7768_gain_reg(const struct ad7768_state *st, + unsigned int ch) +{ + return AD7768_REG_GAIN(st->chip_info->chan_map[ch]); +} + static u8 ad7768_precharge_buf1_mask(const struct ad7768_state *st, u16 va= l) { return val & GENMASK(st->chip_info->prebuf_split - 1, 0); @@ -327,6 +341,48 @@ static const struct regmap_config ad7768_4_regmap_conf= ig =3D { .readable_reg =3D ad7768_4_readable_reg, }; =20 +static unsigned int ad7768_get_calib_reg_base(struct ad7768_state *st, + const struct iio_chan_spec *chan, + bool is_gain) +{ + if (is_gain) + return ad7768_gain_reg(st, chan->address); + + return ad7768_offset_reg(st, chan->address); +} + +static int ad7768_read_calib_value(struct ad7768_state *st, + unsigned int base_reg, unsigned int *val) +{ + u8 data[3]; + int ret; + + guard(mutex)(&st->lock); + + ret =3D regmap_bulk_read(st->regmap, base_reg, data, ARRAY_SIZE(data)); + if (ret) + return ret; + + *val =3D get_unaligned_be24(data); + + return 0; +} + +static int ad7768_write_calib_value(struct ad7768_state *st, + unsigned int base_reg, unsigned int val) +{ + u8 data[3]; + + if (val > AD7768_CALIB_REG_MSK) + return -EINVAL; + + put_unaligned_be24(val, data); + + guard(mutex)(&st->lock); + + return regmap_bulk_write(st->regmap, base_reg, data, ARRAY_SIZE(data)); +} + static int ad7768_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, @@ -650,6 +706,8 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long info) { struct ad7768_state *st =3D iio_priv(indio_dev); + unsigned int base_reg; + unsigned int calib; int ret; =20 PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(regmap_get_device(st->regmap), = pm); @@ -657,22 +715,44 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, if (ret) return ret; =20 - if (info !=3D IIO_CHAN_INFO_SAMP_FREQ) - return -EINVAL; + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: { + guard(mutex)(&st->lock); + *val =3D st->ch_freq[chan->channel]; + return IIO_VAL_INT; + } + case IIO_CHAN_INFO_CALIBBIAS: + base_reg =3D ad7768_get_calib_reg_base(st, chan, false); + ret =3D ad7768_read_calib_value(st, base_reg, &calib); + if (ret) + return ret; =20 - guard(mutex)(&st->lock); - *val =3D st->ch_freq[chan->channel]; + *val =3D calib; + return IIO_VAL_INT; + case IIO_CHAN_INFO_CALIBSCALE: + base_reg =3D ad7768_get_calib_reg_base(st, chan, true); + ret =3D ad7768_read_calib_value(st, base_reg, &calib); + if (ret) + return ret; =20 - return IIO_VAL_INT; + *val =3D calib; + return IIO_VAL_INT; + default: + return -EINVAL; + } } =20 static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, long info) { - if (info =3D=3D IIO_CHAN_INFO_SAMP_FREQ) + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + case IIO_CHAN_INFO_CALIBBIAS: + case IIO_CHAN_INFO_CALIBSCALE: return IIO_VAL_INT; - - return -EINVAL; + default: + return -EINVAL; + } } =20 static int ad7768_write_raw(struct iio_dev *indio_dev, @@ -680,6 +760,7 @@ static int ad7768_write_raw(struct iio_dev *indio_dev, int val, int val2, long info) { struct ad7768_state *st =3D iio_priv(indio_dev); + unsigned int base_reg; int ret; =20 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); @@ -691,10 +772,24 @@ static int ad7768_write_raw(struct iio_dev *indio_dev, if (ret) return ret; =20 - if (info =3D=3D IIO_CHAN_INFO_SAMP_FREQ) + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: return ad7768_set_sampling_freq(indio_dev, val, chan->channel); + case IIO_CHAN_INFO_CALIBBIAS: + if (val < 0 || val > AD7768_CALIB_REG_MSK) + return -EINVAL; =20 - return -EINVAL; + base_reg =3D ad7768_get_calib_reg_base(st, chan, false); + return ad7768_write_calib_value(st, base_reg, val); + case IIO_CHAN_INFO_CALIBSCALE: + if (val < 0 || val > AD7768_CALIB_REG_MSK) + return -EINVAL; + + base_reg =3D ad7768_get_calib_reg_base(st, chan, true); + return ad7768_write_calib_value(st, base_reg, val); + default: + return -EINVAL; + } } =20 static int ad7768_read_avail(struct iio_dev *indio_dev, @@ -983,7 +1078,9 @@ static int ad7768_parse_config(struct iio_dev *indio_d= ev, =20 chan[chan_idx] =3D (struct iio_chan_spec) { .type =3D IIO_VOLTAGE, - .info_mask_separate =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_separate =3D BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CALIBSCALE) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), .indexed =3D 1, --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93882480DE8; Thu, 13 Aug 2026 13:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629498; cv=none; b=YtkD2zZmV6peYAiCXBUbcx6TNJkfLh8qR04/lvhJEP9rxAG+sh5iLOy259nRI0/EnRHYNXfvDrqEsvRRjZbHW9mujjx3HibZUIo9XqLp6DvU4telmM4kV+EtzyLGXHxwg8johEyXWBv2mOx9BPB/vJlQ6+UCgkv7xKXGC6NwkzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629498; c=relaxed/simple; bh=031BCJtxUXX6B1ACSYHhPP3qepuD5qBFVO6CqEsk818=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=eVDJnnBwVhrDUHPH+8815zeqoiNuqC+c7eC3IroZ/j73Rb6k6e5rQSZOA4KLKX88IyMvjwUiAuiGM8OEgTq43baNvab9fQOKUzjfWRl8LUOpSUyxOxWNubmL3ac+mvkqCrsjkQnl0/bS+Y0b14se9+g1k8C/aCVAcM2LagAb0uk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=X35Sljl8; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="X35Sljl8" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCdCeL1876660; Thu, 13 Aug 2026 09:58:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=2doGa yEixqGplIb8Uz/5lY28sycBGbNDX8ArpvHDKBA=; b=X35Sljl8NFGqONduW0A2x pFJsuSDkqLBI97Hmbe++PIN/7WnJQPkU3c8oG7HUKmJQiEH6MMnelXNnApH2nooK ngy4r9xvABVp1GwDE9NVh4w6h46izEuszsMOPN8qigsDPgpK/0m7NJ6j2zTtLBSY 5dnZP4DmXip+o3vVu6pNcmDTztbG7iZNlPIYJikyFJl3fi/79hQu60fdIyYgLcT3 IeqWeQ5oXHQxNRT7TB9etqFm13HFZNEH+s2pbjUPFQortJY8V0cI/2l3MmtiSN2M +MEjyJivdhFZRzDdKld6dFdwa05cfPUE+lCCWszgFI8GG14EQhwFRytQMh9wemeV w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e4b0dbg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:58:05 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDw4b2024657 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:58:04 -0400 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:04 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:04 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:58:04 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwa006802; Thu, 13 Aug 2026 09:57:57 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:57:01 +0200 Subject: [PATCH v3 08/14] iio: adc: ad7768: Add per-channel conversion delay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-8-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=6597; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=031BCJtxUXX6B1ACSYHhPP3qepuD5qBFVO6CqEsk818=; b=VbNLVJoUxz4enrfdt5d0rfzXiurlXAeKtmvrie8zhxzxwCE83jTav5ExZ6twoVmHhVjH1ih9+ pg1+mR+sR5qAkxQATRnXu3dPAm37HNUrOiDkdOXx+6t8jG79hNN4fyz X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: QqrjfuwdIanX5wvb2DZIvfEj53E7jlT5 X-Proofpoint-ORIG-GUID: QqrjfuwdIanX5wvb2DZIvfEj53E7jlT5 X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfXyNHngJbgKKbD cShjb+idVsn5XdhJXCdnPu8iEx3FXSSkcVb49EaVfI0Isl1ltU5PQVSJMIHO8UH97ADwg9afwBn yLegSjW0dFP0AOTZAxo/Fl2u1BY6GNBZR5fo7JLB/tSqUb053uQJ X-Authority-Analysis: v=2.4 cv=ZZYt8MVA c=1 sm=1 tr=0 ts=6a7dcd6d cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=Z0pTeXoby7EwIRygza74:22 a=gAnH3GRIAAAA:8 a=QS77uNcazL5vWiXudcsA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX9HmA9/Ug+oki gSMlw6S3gQGZo/5qT/NJ2vvQ6xITf7xKEulbNZKoNRS6kTZxzdw3qX7eShLwk4XAx464+HuhEB+ 0GdvInUS3LoGWsZ4VchxKA0uUOHdvu4rLfo/Qw7ZHdmjlXMF8OU5GFHfnnmysufytvsGy0JJbxv +chA6NyabSouXAbTjMwVjfMDNVIaqF4Ub8K52Y2f8wgCVN7GhN2EjGxpIOLUDOQE8zb0ZaojivW GHyKDi5IeaQwshCI+NNPc+yiYw0Cl/PtVbPDCduwi6pkrdJqbgw7PIpbZoFON0yCLDoAXk0/g3b VI6VGX0/jqzoezgiB74beYEYmle1yzRAvttN8As4DqXN9CiTO/Rko/O+rTuTDpILwAYa636Z56M eLT4b3jQBcCCXBNhmt4o4qTCuqyizsgFd0s+8TkVtUjnI0xxd6z4mqtR3vqHOCcAasf3i08Q/nS ZbHWsmEDSfv/BleXdhA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Expose the per-channel synchronization phase offset through the IIO conversion-delay attribute. Derive the delay resolution from MCLK, power mode and decimation rate. Validate the requested delay and program the corresponding phase register when applying the active channel configuration. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 146 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 146 insertions(+) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 08721079bb37..d332695cc75d 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include =20 @@ -130,6 +131,12 @@ struct ad7768_freq_config { unsigned int dec_rate; }; =20 +struct ad7768_convdelay_params { + unsigned int shift; + unsigned int max_raw; + u64 step_ps; +}; + struct ad7768_avail_freq { unsigned int n_freqs; unsigned int freqs[MAX_FREQ_PER_MODE]; @@ -157,6 +164,7 @@ struct ad7768_state { unsigned int n_freqs; int freqs[AD7768_MAX_FREQS]; unsigned int ch_freq[AD7768_MAX_CHANNEL]; + u64 ch_convdelay_ps[AD7768_MAX_CHANNEL]; enum ad7768_filter_type ch_filter[AD7768_MAX_CHANNEL]; struct iio_backend *back; =20 @@ -223,6 +231,12 @@ static unsigned int ad7768_gain_reg(const struct ad776= 8_state *st, return AD7768_REG_GAIN(st->chip_info->chan_map[ch]); } =20 +static unsigned int ad7768_phase_reg(const struct ad7768_state *st, + unsigned int ch) +{ + return AD7768_REG_PHASE(st->chip_info->chan_map[ch]); +} + static u8 ad7768_precharge_buf1_mask(const struct ad7768_state *st, u16 va= l) { return val & GENMASK(st->chip_info->prebuf_split - 1, 0); @@ -569,6 +583,105 @@ static int ad7768_set_sampling_freq(struct iio_dev *i= ndio_dev, return 0; } =20 +static int ad7768_get_freq_cfg(struct ad7768_state *st, unsigned int freq, + struct ad7768_freq_config *f_cfg) +{ + for (unsigned int i =3D 0; + i < st->avail_freq[st->power_mode].n_freqs; i++) { + *f_cfg =3D st->avail_freq[st->power_mode].freq_cfg[i]; + if (freq =3D=3D f_cfg->freq_hz) + return 0; + } + + return -EINVAL; +} + +static int ad7768_get_convdelay_params(struct ad7768_state *st, unsigned i= nt ch, + struct ad7768_convdelay_params *params) +{ + struct ad7768_freq_config f_cfg; + unsigned int dec_rate; + unsigned int mult; + u64 mclk; + int ret; + + ret =3D ad7768_get_freq_cfg(st, st->ch_freq[ch], &f_cfg); + if (ret) + return ret; + + dec_rate =3D ad7768_dec_rate[f_cfg.dec_rate]; + switch (dec_rate) { + case 32: + params->shift =3D 3; + params->max_raw =3D 31; + mult =3D 1; + break; + case 64: + params->shift =3D 2; + params->max_raw =3D 63; + mult =3D 1; + break; + case 128: + params->shift =3D 1; + params->max_raw =3D 127; + mult =3D 1; + break; + case 256: + params->shift =3D 0; + params->max_raw =3D 255; + mult =3D 1; + break; + case 512: + params->shift =3D 0; + params->max_raw =3D 255; + mult =3D 2; + break; + case 1024: + params->shift =3D 0; + params->max_raw =3D 255; + mult =3D 4; + break; + default: + return -EINVAL; + } + + mclk =3D clk_get_rate(st->mclk); + if (!mclk) + return -EINVAL; + + params->step_ps =3D DIV_ROUND_CLOSEST_ULL((u64)mult * + PSEC_PER_SEC * + ad7768_mclk_div[st->power_mode], + mclk); + + return 0; +} + +static int ad7768_set_channel_convdelay(struct ad7768_state *st, + unsigned int ch) +{ + struct ad7768_convdelay_params params; + u64 delay_ps =3D st->ch_convdelay_ps[ch]; + u64 max_delay_ps; + u64 raw; + int ret; + + ret =3D ad7768_get_convdelay_params(st, ch, ¶ms); + if (ret) + return ret; + + max_delay_ps =3D (u64)params.max_raw * params.step_ps; + if (delay_ps > max_delay_ps) + return -EINVAL; + + raw =3D DIV_ROUND_CLOSEST_ULL(delay_ps, params.step_ps); + if (raw > params.max_raw) + return -EINVAL; + + return regmap_write(st->regmap, ad7768_phase_reg(st, ch), + raw << params.shift); +} + static void ad7768_filter_wait(const unsigned int *mode_freq, const enum ad7768_filter_type *mode_filter, const bool *mode_used) @@ -687,6 +800,19 @@ static int ad7768_apply_channel_modes(struct iio_dev *= indio_dev, max_freq =3D max(max_freq, mode_freq[mode]); } =20 + for (c =3D 0; c < st->chip_info->num_channels; c++) { + if (!test_bit(c, scan_mask)) + continue; + + ret =3D ad7768_set_channel_convdelay(st, c); + if (ret =3D=3D -EINVAL) + return dev_err_probe(regmap_get_device(st->regmap), ret, + "Invalid conversion delay for channel %u\n", + c); + if (ret) + return ret; + } + ret =3D ad7768_set_clk_divs(st, max_freq); if (ret) return ret; @@ -737,6 +863,13 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, =20 *val =3D calib; return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: { + guard(mutex)(&st->lock); + iio_val_s64_decompose(st->ch_convdelay_ps[chan->channel], + val, val2); + + return IIO_VAL_DECIMAL64_PICO; + } default: return -EINVAL; } @@ -750,6 +883,8 @@ static int ad7768_write_raw_get_fmt(struct iio_dev *ind= io_dev, case IIO_CHAN_INFO_CALIBBIAS: case IIO_CHAN_INFO_CALIBSCALE: return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + return IIO_VAL_DECIMAL64_PICO; default: return -EINVAL; } @@ -760,6 +895,7 @@ static int ad7768_write_raw(struct iio_dev *indio_dev, int val, int val2, long info) { struct ad7768_state *st =3D iio_priv(indio_dev); + s64 delay_ps; unsigned int base_reg; int ret; =20 @@ -787,6 +923,15 @@ static int ad7768_write_raw(struct iio_dev *indio_dev, =20 base_reg =3D ad7768_get_calib_reg_base(st, chan, true); return ad7768_write_calib_value(st, base_reg, val); + case IIO_CHAN_INFO_CONVDELAY: { + delay_ps =3D iio_val_s64_compose(val, val2); + if (delay_ps < 0) + return -EINVAL; + + guard(mutex)(&st->lock); + st->ch_convdelay_ps[chan->channel] =3D delay_ps; + return 0; + } default: return -EINVAL; } @@ -1080,6 +1225,7 @@ static int ad7768_parse_config(struct iio_dev *indio_= dev, .type =3D IIO_VOLTAGE, .info_mask_separate =3D BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_CALIBSCALE) | + BIT(IIO_CHAN_INFO_CONVDELAY) | BIT(IIO_CHAN_INFO_SAMP_FREQ), .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD528481AB0; Thu, 13 Aug 2026 13:58:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629501; cv=none; b=JgxEcZN6Y8vkkvC0obnt6GtyRyyrTkIGBQTl/VrdcczqlTAuRkDalsHMARMWdmh8zRYCJMa0KSw7OTKYAZrEjs3em+/8jukoE2pzpaFZ3sDzJkv1wpOL1F0fygfEFAhPbH+E2XiiBfNy5jQLMbALKwoMJweRWNMTxf7v9unrTog= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629501; c=relaxed/simple; bh=VLK6BSdElRIJyRqz8EE1UHbbon9eqmgepSi5c3GZU+c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=rh2cSh/XOSKlxphgzax+AFiE297Zgllqhglz9AM9eXO/wMjc4hbXmUYW9fmm0V8FnJ9dInIGhYrOlf9+l+2l+DGZeSdthOM1FPCAAivCs6pwKmVl9ikJEE4+W9y1mJKXOwTt3eu1Stjqm5SIhakMN9LNZ2ZYGyTXYKIVoHP0Qb0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=kdnqSes+; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="kdnqSes+" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCL8iJ2350818; Thu, 13 Aug 2026 09:58:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=U1npV qNDBpW4WUXfgmfmjrbD8Kydy5EGCIG2ZWZIFJk=; b=kdnqSes+wHaIiRQBSqBN9 gL250NdXI3E5DR9k37APuvgVSbv98OvN327idWmDzyVdpsUKgUL7g1yqfrhxJcEo b+edKySGEaQzQPbb9Vq3UXnzhYmr9oEFK+RQuySPckf19eszT1XO1KcXPZ0kO168 WPTiTU34DgQwZAIkuFzngD1KzseOPl6mf6y+mSG+ty1vFWKkZQkspSgmIh+H3MCT zIVo/7EKWC8VhKWbu9jAU9FLWPHqiZ1zHyPwTHD7+H/ULSMUyd9TZa29dINSiV0+ bTePWYjzdGdY6NbLfwM501apa8MhEtb4tMdSao+4jqJkVkaEzR9Gdm0sBMf/bLVR g== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g19w9hwct-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:58:08 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDw71q024660 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:58:07 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:07 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:58:07 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwb006802; Thu, 13 Aug 2026 09:57:59 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:57:02 +0200 Subject: [PATCH v3 09/14] iio: adc: ad7768: Add VCM regulator support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-9-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=6327; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=VLK6BSdElRIJyRqz8EE1UHbbon9eqmgepSi5c3GZU+c=; b=PDnlQaeN+yrJYU+YdN74QhfBVwAsaD1LbWBWc3zUkJTcWMzPOPwbo7GaP6cTjAeTVqgu/WmJn dkeFnYS4cBwCqv0KI28fAyZeAGkgtJdmRKBdSlYm+/mxoiPQV3fHbVm X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfXxPN4PWPzBPpd H8945wl9+2zFP8d6AuPvWfNRFIWR9Ahs9q9MinBRLtw0j0D4DufZwu0GUaFcavuyA0Uy9DZlSkZ FHCFG1tUNqIBy9ZqKYapqOs5gjwMCuJzDYUcXkynW/eCKKiOzqeBUYXPqa1AbavH/4XY9U8p/Fq GfWrDyM0aZRsA2FmkBK6SHh2BKMjZH2LrewCtV3XKKDpjgh2IyU/ADqQEfB+3Eo0Hj2Ag/26eUC FlV+xKWxepBFSf9/X6grIZ1BSiJSG2u8hO6ogLBip/UTnqVYNPkcG1XUGzCl95CG3aghaOB/c9G 0N4LZ8SLnkY/J7UTAcC6TIasnU6br38wstZA1Q/VDYEHnMkR837g2cO7GES/CjCc3DIlVWzrG4Y 6iLE1V+LOvaCF834hRSHEvcE+R9Hliw8uic27Nyu6GF8bxxqz48jVZICXg+A51SrboRxbGIT80h 6KltM3yR1IkC+Ekb3dQ== X-Proofpoint-GUID: dqTQAvw0e9JdX5RIKaKPsbPPVP4tR-ik X-Proofpoint-ORIG-GUID: dqTQAvw0e9JdX5RIKaKPsbPPVP4tR-ik X-Authority-Analysis: v=2.4 cv=f/R4wuyM c=1 sm=1 tr=0 ts=6a7dcd70 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=uXIjobp8t2wMuQ0fPvqm:22 a=gAnH3GRIAAAA:8 a=-yOam_tWmGQwaYRI1VcA:9 a=QEXdDO2ut3YA:10 a=br55WurUj89AL1qEz8Q6:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX4lbudSvZ9jaK Hjt56CeYrixBo6xUoV92IjquphkZn9clNGwyD6C6DJK5X4ljuSRLG9uY5Qg5x48cmZ7qX9yBfrr 85DV5lalRUKYDfBWCQWP83lgc86h8/c+EcROvXK7fvGMx+b4Yc6w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Expose the on-chip common mode voltage output through the regulator framework. Support the three fixed output levels and the supply-dependent AVDD1/2 setting. Keep the ADC runtime active while VCM is enabled and release the runtime PM reference when the output is disabled. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 157 +++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 155 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index d332695cc75d..d7151b1fa863 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -89,6 +90,8 @@ #define AD7768_INTERFACE_CFG_CRC_SELECT FIELD_PREP(GENMASK(3, 2), 0x01) =20 /* AD7768_REG_GENERAL_CONFIG */ +#define AD7768_GEN_CONFIG_VCM_SEL_MSK GENMASK(1, 0) +#define AD7768_GEN_CONFIG_VCM_PD BIT(4) /* AD7768_REG_PRECHARGE_BUF1 and 2*/ #define AD7768_PREBUF_POS_EN(ch) BIT((ch) * 2) #define AD7768_PREBUF_NEG_EN(ch) BIT(((ch) * 2) + 1) @@ -167,10 +170,154 @@ struct ad7768_state { u64 ch_convdelay_ps[AD7768_MAX_CHANNEL]; enum ad7768_filter_type ch_filter[AD7768_MAX_CHANNEL]; struct iio_backend *back; + struct regulator_dev *vcm_rdev; + unsigned int avdd1_uV; =20 __be16 d16 __aligned(IIO_DMA_MINALIGN); }; =20 +static const unsigned int ad7768_vcm_voltage_table[] =3D { + 0, 1650000, 2500000, 2140000, +}; + +static int ad7768_vcm_list_voltage(struct regulator_dev *rdev, + unsigned int selector) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + + if (selector >=3D ARRAY_SIZE(ad7768_vcm_voltage_table)) + return -EINVAL; + + if (!selector) + return DIV_ROUND_CLOSEST(st->avdd1_uV, 2); + + return ad7768_vcm_voltage_table[selector]; +} + +static int ad7768_vcm_enable(struct regulator_dev *rdev) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + int ret; + + ret =3D pm_runtime_resume_and_get(regmap_get_device(st->regmap)); + if (ret < 0) + return ret; + + ret =3D regmap_clear_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_PD); + if (ret) + pm_runtime_put_autosuspend(regmap_get_device(st->regmap)); + + return ret; +} + +static int ad7768_vcm_disable(struct regulator_dev *rdev) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + int ret; + + ret =3D regmap_set_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_PD); + if (ret) + return ret; + + pm_runtime_put_autosuspend(regmap_get_device(st->regmap)); + + return 0; +} + +static int ad7768_vcm_is_enabled(struct regulator_dev *rdev) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + int ret; + + PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(regmap_get_device(st->regmap), = pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + ret =3D regmap_test_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_PD); + if (ret < 0) + return ret; + + return !ret; +} + +static int ad7768_vcm_set_voltage_sel(struct regulator_dev *rdev, + unsigned int selector) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + int ret; + + PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(regmap_get_device(st->regmap), = pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + return regmap_update_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_SEL_MSK, selector); +} + +static int ad7768_vcm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + unsigned int val; + int ret; + + PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(regmap_get_device(st->regmap), = pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD7768_REG_GENERAL_CONFIG, &val); + if (ret) + return ret; + + return FIELD_GET(AD7768_GEN_CONFIG_VCM_SEL_MSK, val); +} + +static const struct regulator_ops ad7768_vcm_ops =3D { + .enable =3D ad7768_vcm_enable, + .disable =3D ad7768_vcm_disable, + .is_enabled =3D ad7768_vcm_is_enabled, + .list_voltage =3D ad7768_vcm_list_voltage, + .set_voltage_sel =3D ad7768_vcm_set_voltage_sel, + .get_voltage_sel =3D ad7768_vcm_get_voltage_sel, +}; + +static const struct regulator_desc ad7768_vcm_desc =3D { + .name =3D "vcm", + .of_match =3D of_match_ptr("vcm-output"), + .regulators_node =3D "regulators", + .n_voltages =3D ARRAY_SIZE(ad7768_vcm_voltage_table), + .ops =3D &ad7768_vcm_ops, + .type =3D REGULATOR_VOLTAGE, + .owner =3D THIS_MODULE, +}; + +static int ad7768_register_vcm_regulator(struct device *dev, + struct ad7768_state *st) +{ + struct regulator_config config =3D { + .dev =3D dev, + .driver_data =3D st, + }; + int ret; + + /* + * Start with VCM disabled so each enabled state is paired with the + * runtime PM reference acquired by ad7768_vcm_enable(). + */ + ret =3D regmap_set_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_PD); + if (ret) + return ret; + + st->vcm_rdev =3D devm_regulator_register(dev, &ad7768_vcm_desc, &config); + return PTR_ERR_OR_ZERO(st->vcm_rdev); +} + static const int ad7768_dec_rate[MAX_FREQ_PER_MODE] =3D { 32, 64, 128, 256, 512, 1024, }; @@ -1354,10 +1501,12 @@ static int ad7768_probe(struct spi_device *spi) =20 st->chip_info =3D spi_get_device_match_data(spi); =20 - ret =3D devm_regulator_get_enable(dev, "avdd1"); - if (ret) + ret =3D devm_regulator_get_enable_read_voltage(dev, "avdd1"); + if (ret < 0) return dev_err_probe(dev, ret, "Failed to enable AVDD1 supply\n"); =20 + st->avdd1_uV =3D ret; + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad7768_supply_names), ad7768_supply_names); @@ -1430,6 +1579,10 @@ static int ad7768_probe(struct spi_device *spi) if (ret) return ret; =20 + ret =3D ad7768_register_vcm_regulator(dev, st); + if (ret) + return dev_err_probe(dev, ret, "Failed to register VCM regulator\n"); + indio_dev->setup_ops =3D &ad7768_buffer_ops; =20 ret =3D devm_iio_device_register(dev, indio_dev); --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBB274854EE; Thu, 13 Aug 2026 13:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629502; cv=none; b=D28PrpNFO16cVR3XWIWP4vR/FM3P9XU3UlR2OzoqGcbch1B0ykP5gJUUKd03OGiYx5XTupQy+U6HVK7Q50ziDYH7fh86Ilc83Xc3/N61wj4Zi98wicVfufc0P8DRLLiNPOqXDXtIugAJdnv19BB0u9oD7+EzX69EmwCpLFWTvs0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629502; c=relaxed/simple; bh=HUPRSNGBRBkwytYIMHIZFp5Yf5l+/20hpie4kreZN0Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=PVD9Z6Vklh8IgVmK7fJIqbHKh9/8XymfW4dkaDT309q/09biyEW7Ypy2s/+DPsEKNcKu+aSdOHBBNTTK5KlF3YSM/GhX+UJz3vBMGO+vrNMCwZ0cI3bN3PoiLOc6oyv2yiNjUq+N2jOhN57kDGDJVFVZF1owaxuGae4g+v6aBOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=xGFm/ns3; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="xGFm/ns3" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCdBXH1876654; Thu, 13 Aug 2026 09:58:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=ECltM ExzMgvrvbKms5wAtvDG5I3R3mZp7N+wEcmWj3U=; b=xGFm/ns3zPGqiBOP8B6v+ 3o1PUbJvRdyOCBR+JZOzdwLqw9KMr7h3EXLPJ1xl85t0mGSjNO5fAnRj2u84nAsP 4I+gcQi/ak7pTc4R1WBJIdYlTqxfAwSdWt4l6q94gUlcto0LJkmNRNiopBbP+g5P WstPjLoaqz612Uzqm11QpshK1UqvAar3cAvd0fN3wXNHlnkiv2Mcs+UaZc+KjCUD 0J2ut8BzdPOTw1NqUIBqe7WLwgLcBmPYIlkujs2OZHpPPZtlpm67Ze8YCVNFAFUQ V6TjbE169TAIY8Mt9YzYZzUX54csHxV0wb6lfOpLKj2M4A535Tn3LlpvbzCJtvzX Q== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e4b0dbq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:58:10 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDw9K8024663 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:58:09 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:09 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:09 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:58:09 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwc006802; Thu, 13 Aug 2026 09:58:02 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:57:03 +0200 Subject: [PATCH v3 10/14] iio: adc: ad7768: Register GPIO auxiliary device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-10-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=1874; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=HUPRSNGBRBkwytYIMHIZFp5Yf5l+/20hpie4kreZN0Q=; b=q1xPuDKQ54ZC52JJOPLmXwOP8B3HGJKOm8U09bEV+zmRqPe/sNq2JreqQ3lFKslYalUsfXlwR lyCYagXUD1aCshmsNZO8pZbdUaRh+23mrvOHBST/ES4a/++V/UrbbGA X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: WP-cc7pLAity1t82eGOPPkyQgXcRRUP_ X-Proofpoint-ORIG-GUID: WP-cc7pLAity1t82eGOPPkyQgXcRRUP_ X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX1pp4gFuP8q5D SwuLG1hbMN9qANymAnUC01Ra2dxMlkYXyAGP+TGmjjs4Qc/krsgVtf/jADsx60VE0f7hJujoNOu OpC5Tf1GRfkTr7UHAQy95otmI1cCVTeZ0EqNFlOWAEuCu0jktGuO X-Authority-Analysis: v=2.4 cv=ZZYt8MVA c=1 sm=1 tr=0 ts=6a7dcd72 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=Z0pTeXoby7EwIRygza74:22 a=gAnH3GRIAAAA:8 a=QNlN7d7LqMGTcrNWFyAA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfXzTzyGCMNApiT wkc2x7W48UGPckk2ZdwkvPi74jvYVKHEehtm436OgVRNq+XxJ3vW+Vq+yhcidluyaPXiY5tFdzn pIe41bL5oDnbKzcraEh3KLo9YvJ8Kw0Hb8kwy1fHDfbsSlL9cpz0epcRSdTpsIKfqug7rOX5cPh RwVVYIr6Ho+f/m0Z9tIlXsSRTfZIt4oRxkGYw/QbNYXBRE2l17lCwWyDCcD/eiGnCkHA4rj0mLe ts1/vIUQYvU9MjM3MMj+dvdOyFDex5CvdOjJHQTRzFOSmP3U6jWh4R5f4LZl+/x6Njehs1/u7df x3n8tsGQQEaa9nRft2WfGfvnMwuwy8D4hz+a5/23Sc47UjKNXgGcAEHRZklZgu7Yb49Ey+/DQkr Hg5ZWG4tBAIYN2MPu/G/edNQb3OnoYFagi6/nahm50yL4/AVrt2ZeNMV4QPPN0F9rUj2CXPnxTT FcfLVcATZHrCWu/7HPg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Register an auxiliary device when the AD7768 is described as a GPIO controller. This allows the GPIO driver to share the parent regmap and runtime power-management state. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index d7151b1fa863..6df219610b65 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -1209,6 +1210,27 @@ static void ad7768_set_available_sampl_freq(struct a= d7768_state *st) } } =20 +static int ad7768_gpio_adev_init(struct ad7768_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + struct spi_device *spi =3D to_spi_device(dev); + struct auxiliary_device *adev; + int id; + + if (!device_property_read_bool(dev, "gpio-controller")) + return 0; + + /* Use the SPI bus number and chip select to derive a stable per-device I= D. */ + id =3D (spi->controller->bus_num << 8) | spi_get_chipselect(spi, 0); + adev =3D __devm_auxiliary_device_create(dev, KBUILD_MODNAME, "gpio", + NULL, id); + if (!adev) + return dev_err_probe(dev, -ENODEV, + "Failed to create GPIO auxiliary device\n"); + + return 0; +} + static int ad7768_set_filter_mode(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, unsigned int mode) @@ -1585,6 +1607,10 @@ static int ad7768_probe(struct spi_device *spi) =20 indio_dev->setup_ops =3D &ad7768_buffer_ops; =20 + ret =3D ad7768_gpio_adev_init(st); + if (ret) + return ret; + ret =3D devm_iio_device_register(dev, indio_dev); if (ret) return ret; --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E476348096F; Thu, 13 Aug 2026 13:58:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629504; cv=none; b=FoO+xVmz4nSvDhvL+PFG4KKtXDl6QI4wL5BYebo1Mp+Mhhk0TIwJQ+oLXuY6wwkB93ykn8maTnXIV4HOeDD8+1Ba4v0iyEqE/nMS0aKiFN6PZGL2O01wFKGsXahkhuLCEFERfWVV6f+rhLRncqaOBuO2DaIaeSH06NCT8T/tFS8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629504; c=relaxed/simple; bh=NWYOhHtZJC5C8vlx1JYeY3SjFF04a4RG6WWrunhpQ+o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=aLE7DVLMZYxeD7wUxliZJbRrsmO3sG7q8FvAqlqHC/yzTNNsG5sEuN6Tx1AqTh5uFJFhVWvT/9djEuHOnjhRn8FH/qhhtJRTwk8S4m5BVHLnhrblwJSwSBFthrfz4obApCv28D+VoZq7lNn78yNaqgj7iCfVHUq6gV1r4yOASGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=jLm5oO8/; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="jLm5oO8/" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCLBMH2350839; Thu, 13 Aug 2026 09:58:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=n2tIM QzIRKyXAT8qFCJoy88FHUbrTFIZYmRm8jitVJA=; b=jLm5oO8/SBbfa6pRMd+du mIepoIv/20TnjwSEJ0zHDEZBQadBGKlTvG3G0qEOgqozRJq+1wTQNGGWDgw0Aoz4 GKinIKiJ+yKph6q7rzojUH456jQAxPbeyf7Z/QH48gWq/2GPFcf80RCSA99o1ZfC cD0cmYMOe6O1822fKa20mlaRIzKvxgyooEZ4QU9slkWPp/KbWFEh41SV1ailbAB2 6+cK9gPqxT2dDpsT8kD8Q1odX7vtBE/GYD5aqfZcxMYUoQ4+9c5jJNAfvWEdHtdT LLmRt8QdROlfGMcz1M7McTVRYvbjiqwq3LoNGZyHjI68nQj2z9MuY7laB8Cv/Bgt A== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g19w9hwdc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:58:13 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDwCPQ024669 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:58:12 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:12 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:12 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:58:12 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwd006802; Thu, 13 Aug 2026 09:58:05 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:57:04 +0200 Subject: [PATCH v3 11/14] gpio: regmap: Use regmap_test_bits() for single bit reads Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-11-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=1848; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=NWYOhHtZJC5C8vlx1JYeY3SjFF04a4RG6WWrunhpQ+o=; b=cvYjBjqytBnOluGxhttr1DSChbjBYEaWatECQKi7ZlVukNuydaVsPvyFoPY+isQfCUCfEHcfV DwK055h1K8HAhQkN1Ja7HG0MLc/Wm2NJmecGoTmiqNOcdy8iAuwFOmd X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX1R47NlPbU9bG eVPA5EnvF1zY0NQIWPPAcRXc0kb2Prbnfo0Thrsgn/woRzcLIaII4BSLSgYZ55YL/emdhjLNMfo ZoWwfKLBAlaPgS7d+wgzDcSD4FtruGlrBdn6U1b9U/YfUOmENnJnaAWjREGMn2wDKX8K+iGX51d BjcBa4O3GQhyjsMwWKsCEMtVqjL/Ac7VsIoqEhP90OhWTPkXG1zu97/f0gkyCIDk2egHJxf5eE2 6/sEDpkaMBJ57AcVL9W6ixhe3FBPIUdITN73AcI+9I1+pH1hSaKfRUqFt12bvrVe83H+jGEKvoA 4qZyWqbmUrClYMlqTupaqX57+xzMjfaOwPY4PXgnwNOyLFxSBocayTfe4l1HHI8UjKOIgfeKJst tGx6Ku42WaFuyjDv/e9erw85IwQQdpIHudgUc9nrbgPmG44j8T82R5KfffbZoikb4bK8encEOn7 FqtdXwUYsR+B8UrSp+w== X-Proofpoint-GUID: WUm76sUEueqhyQT1IlajtBLO8l_10oMd X-Proofpoint-ORIG-GUID: WUm76sUEueqhyQT1IlajtBLO8l_10oMd X-Authority-Analysis: v=2.4 cv=f/R4wuyM c=1 sm=1 tr=0 ts=6a7dcd75 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=uXIjobp8t2wMuQ0fPvqm:22 a=gAnH3GRIAAAA:8 a=A82TumGDDQIy_PWe51QA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX9n9qtetLtCdQ DbKpj2EaSl1ZrSEl0L/pBUOIPz8yxPahMAdXJATe4miwnAo+n9ywWZVpBHL2z8XHlCs69BupqrN aX7tMXBdkdx/9XSJ0j50CaeL74VPmGfpU6cpztvzRgZ88cV3Tvx7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Use regmap_test_bits() when reading a single GPIO value from a normal register and when reading the direction bit. Signed-off-by: Janani Sunil Reviewed-by: Linus Walleij Reviewed-by: Michael Walle --- drivers/gpio/gpio-regmap.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index 51b4d69b8740..a5188f8569e3 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -84,14 +84,15 @@ static int gpio_regmap_get(struct gpio_chip *chip, unsi= gned int offset) return ret; =20 /* ensure we don't spoil any register cache with pin input values */ - if (gpio->reg_dat_base =3D=3D gpio->reg_set_base) + if (gpio->reg_dat_base =3D=3D gpio->reg_set_base) { ret =3D regmap_read_bypassed(gpio->regmap, reg, &val); - else - ret =3D regmap_read(gpio->regmap, reg, &val); - if (ret) - return ret; + if (ret) + return ret; =20 - return !!(val & mask); + return !!(val & mask); + } + + return regmap_test_bits(gpio->regmap, reg, mask); } =20 static int gpio_regmap_set(struct gpio_chip *chip, unsigned int offset, @@ -157,7 +158,7 @@ static int gpio_regmap_get_direction(struct gpio_chip *= chip, unsigned int offset) { struct gpio_regmap *gpio =3D gpiochip_get_data(chip); - unsigned int base, val, reg, mask; + unsigned int base, reg, mask; int invert, ret; =20 if (gpio_regmap_fixed_direction(gpio, offset)) { @@ -186,11 +187,11 @@ static int gpio_regmap_get_direction(struct gpio_chip= *chip, if (ret) return ret; =20 - ret =3D regmap_read(gpio->regmap, reg, &val); - if (ret) + ret =3D regmap_test_bits(gpio->regmap, reg, mask); + if (ret < 0) return ret; =20 - if (!!(val & mask) ^ invert) + if (ret ^ invert) return GPIO_LINE_DIRECTION_OUT; else return GPIO_LINE_DIRECTION_IN; --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E462483BC7; Thu, 13 Aug 2026 13:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629508; cv=none; b=PNXdgPQB2P3FnD5Pk6F9E4gsl+WM8Xt7xucYFrgDyzKOL4kxixQUEjJfd6NS3OPz4q3cPD4ZNxr1svJmSE+TY29LpmlQOi146rkItuca6vgPO8N70GnK72oPWerPjy4bGFo6/pVGmfn/l1Gyx/X2NIgYYViz3KIU3c1cf088axs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629508; c=relaxed/simple; bh=BuxT9qg53qzC6Bm2kjwBO93j/6wjnoLQIvbUESOMCuk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=GQxSxipv+/B5HbjBE/XCpjcdD8Ti37xN0T9FcQfTgrWyvgOsXHSojWQlTHnhi0xp1LwLdwvyBHg0bBl4Vy2oQGCKqRD/zLuMTBaiSW5WJht785FLCfnFKWCxwJxW2yGMB3tXHh+X0pT3TLnqsi61axYnUOCDxqbN42h1aJdjyec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=F/EvL5y5; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="F/EvL5y5" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCXRgP1492205; Thu, 13 Aug 2026 09:58:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=HeMrL pY9mbTXa0W++ean40OknpJiJccP1J10S41S9pI=; b=F/EvL5y5gJJXYHUBi+hrV OV9+srRP34lkyDds7CYfeZPqNP1hszfyHb23yJT5ESy1T5+OaH20wSUmGAR+oaki 2MnDi8FsCfUeQKoC1/sYNo8yXJes2UAajE2y2e34EuFIt0E/3WyydFG6OYRLxNJU RGVYdfJELzkP2AzdV0sLnzwJ8jgqCpn12fDx1S3zm12qfjGNa/8mFl/vhoRVbHQZ 8LxRzBO6/eOgZq2kdq0aRjKi5knbkWZ2n1Uy/3TIzPDWrfMCV7rDkmDBorfzCIxR Zinlqs5TUbaa0l/7ETuTz64iEazzp5yMPcRXTXX/CVkKbHpOFEYy7So8Yttb/OHW Q== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e1n8dwc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:58:15 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDwEL2024672 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:58:14 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:14 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:58:14 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwe006802; Thu, 13 Aug 2026 09:58:07 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:57:05 +0200 Subject: [PATCH v3 12/14] gpio: regmap: Add optional runtime PM support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-12-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=8368; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=BuxT9qg53qzC6Bm2kjwBO93j/6wjnoLQIvbUESOMCuk=; b=VOfypmMZviME4WE/ns2ilZBU6CERv1HPdwKvW8FP2/V31hKdORgUlI21J42nvDm7ez8yojIwm JbMCUHqSi8WD2tQAWKrSBtwJAHbkpnMYhUcimoWxpOGJ9ETzT6iVqtn X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX5dxXNbgnt4Xr La89m/E23yoRO8i4/bRf6aXGLCQY+Mk0gQtCirJmB/MDjLtlivW+GAfoKoblIuVCrGbdtgPAgl7 iPbILk2SLoJfwiVog0Jertz7CTDO1uOKI5mFiseBIqPBhf8DjCK/AdDB8v54hHEmBOx8M01crbQ a38Zer1T96zhHUtcNLg+v4KXCl40B/RX9CXq1XIxq3abI2aV0WSLejOGfwdx67u5glS8QZ0KHJt Z+79VkL0QYKnsnSMtrquAg3zg7AEgVsz/14NMTZQDDg7vs6fVBebImoIlpVqtDAMCEzjxp3nbKJ 7cEXw7+ZTg8n46o+z/tbsRpVfpokDSToNudMsTxqZCLiT8PKyVpmr6J4Vqwy9VyYVbg9Oi2f36E iMm7A8UzSyGUzFgSvWpkOwq2ZhkmnqPTx+cUHA4ZHIG0APbawnVuXg3uoGJx4LYhXXg/QJJPIFX G5pGCm4M64HOmg3/EEQ== X-Proofpoint-ORIG-GUID: EgsbFUSQiCm5IXn5CqxULdKQzVaO4538 X-Proofpoint-GUID: EgsbFUSQiCm5IXn5CqxULdKQzVaO4538 X-Authority-Analysis: v=2.4 cv=fLoJG5ae c=1 sm=1 tr=0 ts=6a7dcd78 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=gAnH3GRIAAAA:8 a=lWN7PXLlU04E1KMc-cYA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfXy5HUwXddN3MR l9cZdODc3Q1+/USE/euDvBnOdkyuNGB6wh0Og3Gv+r2UmCI4KZ9lBMe05Trm6H+SCvup0BDGkBa NzuM2ieSnkkIQUQ09osLpQsXsji90yeRwSrKuJGq6PTCm0uO2PX+ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 suspectscore=0 spamscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Some gpio-regmap consumers share their regmap with a parent device that may be runtime suspended. GPIO register accesses must resume that device first. Add an optional pm_dev field and acquire it before register translation or access. Release it using runtime autosuspend after each operation. Keep the device active across the complete direction-output sequence and propagate failure when setting the initial output value. Signed-off-by: Janani Sunil Reviewed-by: Linus Walleij Reviewed-by: Michael Walle --- drivers/gpio/gpio-regmap.c | 102 ++++++++++++++++++++++++++++++++++++----= ---- include/linux/gpio/regmap.h | 2 + 2 files changed, 87 insertions(+), 17 deletions(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index a5188f8569e3..4d5d92c15679 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,7 @@ struct gpio_regmap { unsigned int reg_clr_base; unsigned int reg_dir_in_base; unsigned int reg_dir_out_base; + struct device *pm_dev; unsigned long *fixed_direction_mask; unsigned long *fixed_direction_output; =20 @@ -67,6 +69,22 @@ static int gpio_regmap_simple_xlate(struct gpio_regmap *= gpio, return 0; } =20 +static int gpio_regmap_runtime_get(struct gpio_regmap *gpio) +{ + if (!gpio->pm_dev) + return 0; + + return pm_runtime_resume_and_get(gpio->pm_dev); +} + +static void gpio_regmap_runtime_put(struct gpio_regmap *gpio) +{ + if (!gpio->pm_dev) + return; + + pm_runtime_put_autosuspend(gpio->pm_dev); +} + static int gpio_regmap_get(struct gpio_chip *chip, unsigned int offset) { struct gpio_regmap *gpio =3D gpiochip_get_data(chip); @@ -79,20 +97,28 @@ static int gpio_regmap_get(struct gpio_chip *chip, unsi= gned int offset) else base =3D gpio_regmap_addr(gpio->reg_set_base); =20 - ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + ret =3D gpio_regmap_runtime_get(gpio); if (ret) return ret; =20 + ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + if (ret) + goto out_pm_put; + /* ensure we don't spoil any register cache with pin input values */ if (gpio->reg_dat_base =3D=3D gpio->reg_set_base) { ret =3D regmap_read_bypassed(gpio->regmap, reg, &val); if (ret) - return ret; + goto out_pm_put; =20 - return !!(val & mask); + ret =3D !!(val & mask); + } else { + ret =3D regmap_test_bits(gpio->regmap, reg, mask); } =20 - return regmap_test_bits(gpio->regmap, reg, mask); +out_pm_put: + gpio_regmap_runtime_put(gpio); + return ret; } =20 static int gpio_regmap_set(struct gpio_chip *chip, unsigned int offset, @@ -103,10 +129,14 @@ static int gpio_regmap_set(struct gpio_chip *chip, un= signed int offset, unsigned int reg, mask, mask_val; int ret; =20 - ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + ret =3D gpio_regmap_runtime_get(gpio); if (ret) return ret; =20 + ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + if (ret) + goto out_pm_put; + if (val) mask_val =3D mask; else @@ -118,6 +148,8 @@ static int gpio_regmap_set(struct gpio_chip *chip, unsi= gned int offset, else ret =3D regmap_update_bits(gpio->regmap, reg, mask, mask_val); =20 +out_pm_put: + gpio_regmap_runtime_put(gpio); return ret; } =20 @@ -128,6 +160,10 @@ static int gpio_regmap_set_with_clear(struct gpio_chip= *chip, unsigned int base, reg, mask; int ret; =20 + ret =3D gpio_regmap_runtime_get(gpio); + if (ret) + return ret; + if (val) base =3D gpio_regmap_addr(gpio->reg_set_base); else @@ -135,9 +171,13 @@ static int gpio_regmap_set_with_clear(struct gpio_chip= *chip, =20 ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); if (ret) - return ret; + goto out_pm_put; =20 - return regmap_write(gpio->regmap, reg, mask); + ret =3D regmap_write(gpio->regmap, reg, mask); + +out_pm_put: + gpio_regmap_runtime_put(gpio); + return ret; } =20 static bool gpio_regmap_fixed_direction(struct gpio_regmap *gpio, @@ -183,18 +223,26 @@ static int gpio_regmap_get_direction(struct gpio_chip= *chip, return -ENOTSUPP; } =20 - ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + ret =3D gpio_regmap_runtime_get(gpio); if (ret) return ret; =20 + ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + if (ret) + goto out_pm_put; + ret =3D regmap_test_bits(gpio->regmap, reg, mask); if (ret < 0) - return ret; + goto out_pm_put; =20 if (ret ^ invert) - return GPIO_LINE_DIRECTION_OUT; + ret =3D GPIO_LINE_DIRECTION_OUT; else - return GPIO_LINE_DIRECTION_IN; + ret =3D GPIO_LINE_DIRECTION_IN; + +out_pm_put: + gpio_regmap_runtime_put(gpio); + return ret; } =20 static int gpio_regmap_try_direction_fixed(struct gpio_regmap *gpio, @@ -237,16 +285,24 @@ static int gpio_regmap_set_direction(struct gpio_chip= *chip, return -ENOTSUPP; } =20 - ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + ret =3D gpio_regmap_runtime_get(gpio); if (ret) return ret; =20 + ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + if (ret) + goto out_pm_put; + if (invert) val =3D output ? 0 : mask; else val =3D output ? mask : 0; =20 - return regmap_update_bits(gpio->regmap, reg, mask, val); + ret =3D regmap_update_bits(gpio->regmap, reg, mask, val); + +out_pm_put: + gpio_regmap_runtime_put(gpio); + return ret; } =20 static int gpio_regmap_direction_input(struct gpio_chip *chip, @@ -261,6 +317,10 @@ static int gpio_regmap_direction_output(struct gpio_ch= ip *chip, struct gpio_regmap *gpio =3D gpiochip_get_data(chip); int ret; =20 + ret =3D gpio_regmap_runtime_get(gpio); + if (ret) + return ret; + /* * First check if this is gonna work on a fixed direction line, * if it doesn't (i.e. this is a fixed input line), then do not @@ -269,12 +329,18 @@ static int gpio_regmap_direction_output(struct gpio_c= hip *chip, if (gpio_regmap_fixed_direction(gpio, offset)) { ret =3D gpio_regmap_try_direction_fixed(gpio, offset, true); if (ret) - return ret; + goto out_pm_put; } =20 - gpio_regmap_set(chip, offset, value); + ret =3D gpio_regmap_set(chip, offset, value); + if (ret) + goto out_pm_put; =20 - return gpio_regmap_set_direction(chip, offset, true); + ret =3D gpio_regmap_set_direction(chip, offset, true); + +out_pm_put: + gpio_regmap_runtime_put(gpio); + return ret; } =20 void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio) @@ -324,6 +390,7 @@ struct gpio_regmap *gpio_regmap_register(const struct g= pio_regmap_config *config gpio->reg_clr_base =3D config->reg_clr_base; gpio->reg_dir_in_base =3D config->reg_dir_in_base; gpio->reg_dir_out_base =3D config->reg_dir_out_base; + gpio->pm_dev =3D config->pm_dev; =20 chip =3D &gpio->gpio_chip; chip->parent =3D config->parent; @@ -331,7 +398,8 @@ struct gpio_regmap *gpio_regmap_register(const struct g= pio_regmap_config *config chip->base =3D -1; chip->names =3D config->names; chip->label =3D config->label ?: dev_name(config->parent); - chip->can_sleep =3D regmap_might_sleep(config->regmap); + chip->can_sleep =3D config->pm_dev || + regmap_might_sleep(config->regmap); chip->init_valid_mask =3D config->init_valid_mask; =20 chip->request =3D gpiochip_generic_request; diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index 06255756710d..aae32a569914 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -29,6 +29,7 @@ struct regmap; * @reg_clr_base: (Optional) clear register base address * @reg_dir_in_base: (Optional) in setting register base address * @reg_dir_out_base: (Optional) out setting register base address + * @pm_dev: (Optional) Device to use for runtime power management. * @reg_stride: (Optional) May be set if the registers (of the * same type, dat, set, etc) are not consecutive. * @ngpio_per_reg: (Optional) Number of GPIOs per register @@ -92,6 +93,7 @@ struct gpio_regmap_config { unsigned int reg_clr_base; unsigned int reg_dir_in_base; unsigned int reg_dir_out_base; + struct device *pm_dev; int reg_stride; int ngpio_per_reg; struct irq_domain *irq_domain; --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0FB9489861; Thu, 13 Aug 2026 13:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629510; cv=none; b=pEj+ckH6uY0jcbYUvyip2wzEvRNxSZ17XFNzo4KKWGS4xKVfPBZHY6IXvQJ4YNbJr4Sv1ADtieOHfyOfDlTUgKNgITJhKJ5YV/moFvCOtx6hEX2lQulEPNys3LNiQ+/R0GhNekaQvrUiErFVUtnE+8nC/J14DGubiYe0I4BLbso= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629510; c=relaxed/simple; bh=oEmSGeSrbNCBZZXeCuSPWvIF2sVljJpjdDE7pwsZgWA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=DiQsicGL0f5u1KBFADmVqKwPfWA9jObWqPURtf9xSQ4vXS+YQTC5V+QJUWBVDG1PATeI925G7y/VKyaOHzVr432rK3BLNsgVdNoHvVbg19/4cDFlIaYl4+6uTnmtw73PndGdCL/a9haVybxyFDw54oNzr9Hr8U8/LBXwzRLqbvs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=BpPmYHr3; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="BpPmYHr3" Received: from pps.filterd (m0516787.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCa7xo2129063; Thu, 13 Aug 2026 09:58:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=9+hFX d4DsxheWxMCY2zoI6o7bFqwS7pZ/JW/lwY44uc=; b=BpPmYHr3oAGMYPGpIFpRz 9Ff2psGWBkRRU4zzYeNcKImIIwYnlgCv77IG7EPWm4hExAiUIjmVdbPmRwrorhGq 1fzFnjvruxxDITzlNoqZxkTLaBsd6RMSgYMOTKvxc8CDUBhGR7A9kx382G3piqj0 clGYZ2U5xt4/NZTB9j6L3pEZ1Go1/43X/v4zGxuwdogDCijL1FIagH+1NrOM8Zuv JMoz5JCd3h3y7vEf6Kj+3HZtk3NqbufNo6ugRUvlgnD1vVQimX2kT3guTuDab+Ca uGSGlXYiNp+pJjIxJZxcq3Xs/lHaJvED83AoQ23HnexOqTRdeDaKyt52egPB78r8 w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e2wgcdn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:58:18 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDwHGF024678 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:58:17 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:17 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:17 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:58:17 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwf006802; Thu, 13 Aug 2026 09:58:10 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:57:06 +0200 Subject: [PATCH v3 13/14] gpio: ad7768: Add AD7768 GPIO auxiliary driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-13-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=5503; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=oEmSGeSrbNCBZZXeCuSPWvIF2sVljJpjdDE7pwsZgWA=; b=ylV8XBrf++uv1m9ZbGWRf18zCweJvWZPp+4p4u3t7MKer/A9alO4+4FxjTiu2WZI2drmfhPSO yzKsh15cC4MA2USmN91KB22AYDDqPvgZ4spkQeLl32bmR1IejHF8ddD X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX0XqvLMctxbtz q9I7nkECtYz13hlg3Xaxh8SE7s3tiSaA1JYmQBsLPa7JywC3MuQ7iOD92FgQcB8PrOCUBqkewZt FMZw+q3Lqq2jcT6QEoIXeJLcchS+nHbgeyh0sJhr73MFWaeyTAHU X-Proofpoint-GUID: 5_Jr1i0zX66DcuZ_Jr6fivIPsQV9251H X-Authority-Analysis: v=2.4 cv=UJzt2ify c=1 sm=1 tr=0 ts=6a7dcd7a cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=gAnH3GRIAAAA:8 a=VwQbUJbxAAAA:8 a=DyYY1DdFIiypQHwlAEwA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfXyzbOjOwmoviD fjN3nkvS6w8fvyOOiobkYly8gjti2ymLJOMfvOqx+5GkcQkSLRHqwIX1GRL5a9qHEe4VCEeWRl0 bMFIoFXNUrqAdSzqOSSFzXITRsFAdON0+Ud/CdacbIEylOpz3reK0Hb7T3yLgnda6As68uoQFDT Y32oGhF1VfhxK0E0ZZOUPqsDpGMsMA1fzVGoGrjLNtFNEDh1444APp78yCfsCna1cg9KN6mAY+H MYwi7jpiX1qhYSnRk+59dx6/qeC6Yd7dPkgxcpGGk/wHdC540cNAFN5jY+p20nCRFfAkItY8uXE VBdLEHu5rZz0fBs3RXNMkuMBXH32/1okfmzpzGRBNaORajfuo1EbwaU5uHsF8ya3xG0Fd8wMvmV kkV9vqSQ8Ghd6/PNDls0OMZTBMe/wSclg+N9hc2CDZVCZpHlGmg6zgz3qRj2pEN7hGxgxMjkMuR eRI1CL9T/rd0PABClkg== X-Proofpoint-ORIG-GUID: 5_Jr1i0zX66DcuZ_Jr6fivIPsQV9251H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 The AD7768 provides five GPIOs controlled through registers shared with the parent IIO device. Register an auxiliary gpio-regmap driver and use the parent device for runtime PM. The device has separate input-state and output-latch registers. Add a reg_mask_xlate() callback that checks the line direction and reads the programmed output latch for output lines while retaining input-state reads for input lines. Signed-off-by: Janani Sunil Reviewed-by: Linus Walleij --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 12 +++++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-ad7768.c | 106 +++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 120 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index dc94e7803a7c..3de7ebcc4ee7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1639,6 +1639,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml +F: drivers/gpio/gpio-ad7768.c F: drivers/iio/adc/ad7768.c =20 ANALOG DEVICES INC AD7780 DRIVER diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 28cf6d2e83c2..85cb0c82a823 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1796,6 +1796,18 @@ endmenu menu "Auxiliary Bus GPIO drivers" depends on AUXILIARY_BUS =20 +config GPIO_AD7768 + tristate "Analog Devices AD7768 GPIO support" + depends on AD7768 + depends on GPIOLIB + select GPIO_REGMAP + help + Say yes here to expose the AD7768 utility pins as GPIOs when the + device tree node is marked as a GPIO controller. + + To compile this driver as a module, choose M here: the module will be + called gpio-ad7768. + config GPIO_LTC4283 tristate "Analog Devices LTC4283 GPIO support" depends on SENSORS_LTC4283 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 4d0e900402fc..d2921963efc7 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_GPIO_104_IDI_48) +=3D gpio-104-idi-48.o obj-$(CONFIG_GPIO_104_IDIO_16) +=3D gpio-104-idio-16.o obj-$(CONFIG_GPIO_74X164) +=3D gpio-74x164.o obj-$(CONFIG_GPIO_74XX_MMIO) +=3D gpio-74xx-mmio.o +obj-$(CONFIG_GPIO_AD7768) +=3D gpio-ad7768.o obj-$(CONFIG_GPIO_ADNP) +=3D gpio-adnp.o obj-$(CONFIG_GPIO_ADP5520) +=3D gpio-adp5520.o obj-$(CONFIG_GPIO_ADP5585) +=3D gpio-adp5585.o diff --git a/drivers/gpio/gpio-ad7768.c b/drivers/gpio/gpio-ad7768.c new file mode 100644 index 000000000000..2dad00fac711 --- /dev/null +++ b/drivers/gpio/gpio-ad7768.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD7768 GPIO auxiliary driver + * + * Copyright 2026 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AD7768_REG_GPIO_CONTROL 0x0E +#define AD7768_REG_GPIO_WRITE 0x0F +#define AD7768_REG_GPIO_READ 0x10 + +#define AD7768_GPIO_UGPIO_ENABLE BIT(7) + +#define AD7768_NUM_GPIOS 5 + +static int ad7768_gpio_reg_mask_xlate(struct gpio_regmap *gpio, + unsigned int base, unsigned int offset, + unsigned int *reg, unsigned int *mask) +{ + struct regmap *regmap =3D gpio_regmap_get_drvdata(gpio); + int ret; + + *reg =3D base; + *mask =3D BIT(offset); + + if (base !=3D AD7768_REG_GPIO_READ) + return 0; + + /* + * AD7768 has separate input-state and output-latch registers. For an + * output line, report the programmed value from the output latch; + * input lines continue to use the input-state register. + */ + ret =3D regmap_test_bits(regmap, AD7768_REG_GPIO_CONTROL, *mask); + if (ret < 0) + return ret; + if (ret) + *reg =3D AD7768_REG_GPIO_WRITE; + + return 0; +} + +static int ad7768_gpio_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev =3D &adev->dev; + struct gpio_regmap_config config =3D { + .parent =3D dev, + .label =3D dev_name(dev->parent), + .ngpio =3D AD7768_NUM_GPIOS, + .reg_dat_base =3D AD7768_REG_GPIO_READ, + .reg_set_base =3D AD7768_REG_GPIO_WRITE, + .reg_dir_out_base =3D AD7768_REG_GPIO_CONTROL, + .pm_dev =3D dev->parent, + .reg_mask_xlate =3D ad7768_gpio_reg_mask_xlate, + }; + struct gpio_regmap *gpio; + struct regmap *regmap; + int ret; + + regmap =3D dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + PM_RUNTIME_ACQUIRE_IF_ENABLED_AUTOSUSPEND(dev->parent, pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + ret =3D regmap_set_bits(regmap, AD7768_REG_GPIO_CONTROL, + AD7768_GPIO_UGPIO_ENABLE); + if (ret) + return ret; + + config.regmap =3D regmap; + config.drvdata =3D regmap; + gpio =3D devm_gpio_regmap_register(dev, &config); + + return PTR_ERR_OR_ZERO(gpio); +} + +static const struct auxiliary_device_id ad7768_gpio_ids[] =3D { + { .name =3D "ad7768.gpio" }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, ad7768_gpio_ids); + +static struct auxiliary_driver ad7768_gpio_driver =3D { + .probe =3D ad7768_gpio_probe, + .id_table =3D ad7768_gpio_ids, +}; +module_auxiliary_driver(ad7768_gpio_driver); + +MODULE_AUTHOR("Janani Sunil "); +MODULE_DESCRIPTION("Analog Devices AD7768 GPIO auxiliary driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Tue Sep 29 02:02:43 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80E41481648; Thu, 13 Aug 2026 13:58:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629512; cv=none; b=f14E8sF24SbirSWZuk1/vtEjrjaI4fwQz4+/uOIsB1GrzE7JMT91fCqBmcqeTH8PbUxP+J5CXUI/8xiWg+2VB7Y3GKiNkTOiXxLQ6LFRyCr5Pg3aeWTqK+rbmqPkoP1i8FCs68HZgmtG5P0WYcByTK1K7B67QPMRhsqLqinKeNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786629512; c=relaxed/simple; bh=A/DEAakE0ROEa8wJFK1uJEHCCiy2SFC7S18g1ahfBF4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=E00wDGnmZ7fUZ6En0EyYsWeIVR7JuFwdsPya7S/JASCiHUjVXMLFk2WpncHPs6JfYfBYtRCrBE8bZohE3vWockj8Coz+BezIMv2rFRhe7pcTNkpLhr00RP6Ax9MLZT+vE+abZ2X+q11g8aldJfLQbnyCnifOsC677mfhuMS22nE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=lth2u2+C; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="lth2u2+C" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67DCdBXJ1876654; Thu, 13 Aug 2026 09:58:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=behPR wvmXFt3WByO+1AhdB1TniLCt4aIdt4XTcoJku0=; b=lth2u2+Cyugox1PxOvk4g i1Kxphg4GfkBYoTudRFLkbV5s7avYpZl8dprkRYPsd+xiTix2EFK0xoEAgOkzbMh vds+TXwOkwBbKDxArV9bOGM8gB5r+wRBq7wMgiSp+RSy77qqF1MxUWxw8R2I6JN+ VrFa48qBc9sN78RCu2mFjjXOd5OLVY9cEsvbkgO01qYdr5AY0e35aS+r9bhc5crd /Vl0biEHnpx+0o7+togR4BPpMvKmBDWXygPXgEzUsfunREglEFAhVBvPUKVViu7P aQX77G2o8NNksxsIi95C8NbolFge8mhV+lpm8E4Uo102D6cdPrj+PhpT6ZAGnmSJ Q== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4g1e4b0dca-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Aug 2026 09:58:21 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 67DDwKig024681 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Aug 2026 09:58:20 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Thu, 13 Aug 2026 09:58:20 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Thu, 13 Aug 2026 09:58:20 -0400 Received: from HYB-e1y2fvUQ3cx.ad.analog.com (HYB-e1y2fvUQ3cx.ad.analog.com [10.44.3.60]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 67DDvOwg006802; Thu, 13 Aug 2026 09:58:13 -0400 From: Janani Sunil Date: Thu, 13 Aug 2026 15:57:07 +0200 Subject: [PATCH v3 14/14] Documentation: iio: Add AD7768 Documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260813-ad7768-driver-v3-14-cb554399ad26@analog.com> References: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> In-Reply-To: <20260813-ad7768-driver-v3-0-cb554399ad26@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786629444; l=9510; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=A/DEAakE0ROEa8wJFK1uJEHCCiy2SFC7S18g1ahfBF4=; b=HcjcalddGt4/egM7Q+ecr/y0K/SXyDJ1e81R0mxdFhPZdgXtMdt0sHT9PXFkEGyBUcu9Z3qBL RHNd5H2NcS0DGS9817ey9J4u3ihhosop8ARL3aeOc+50qTWCju0TbAU X-Developer-Key: i=janani.sunil@analog.com; a=ed25519; pk=e25MyjRLPY3RWrYm/LrJ+/+t1MZJUbkgIW5CZg+g+hA= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: GtQElIU_HuAIZZ3sfL0lAPw7UQw5ItW1 X-Proofpoint-ORIG-GUID: GtQElIU_HuAIZZ3sfL0lAPw7UQw5ItW1 X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX2u+RxXsjFuIG V2WkZKwoWGZ0nI2l9iy9SBTYTcR10CQ1OEqUuw63Xn96UQm+f/XeFm5nG8rXAtTISLsClXBC+61 LuuEy0BjxGm30X/DpCPWTHBu/E+ieBawPAZ57DlfcGKlBptNtgl6 X-Authority-Analysis: v=2.4 cv=ZZYt8MVA c=1 sm=1 tr=0 ts=6a7dcd7d cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=Z0pTeXoby7EwIRygza74:22 a=gAnH3GRIAAAA:8 a=VwQbUJbxAAAA:8 a=oqaN6P3t42WLEIsmr8gA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA5OSBTYWx0ZWRfX1/racxBy+Eg4 5wCAYj/lorvrtgmeKMTjHQm7WNE6GsGddmD+YIMkqRP2diB8PZa3xXJsFJGjoqUST6OvmnvnwOJ enm82Fs+c1xi4fGwgY0vuFKjI1wODlfXsYUfKemCU2AmKWaZ8NUVFwDMES8zJ8dhFyjU+91+BlO 7z+y4dKVXXtMGJbNbuW5FWs/CVNgn7UhmWRex29t/cz36fUTT2gmkR4txemrtm9r7mRlWvuNwwF 2lgIj2Eot2YC1Gf7NlZVp8dYYLYOA8y1btlmyqDHuF3TyEG2I8ItmKdH0Bsxgx4S5u5NJ/MKSk7 pxINHM9ECQo+g3c6evJpvJuIBxfJkV/JV77jbrTwKgr4IFeOdEi3gjrSv8E+BJ+ofmg+pzwRm6L UEEDa3LFxp3ndSR0YBw0wo8cqu6cJdM+oudRWLED0RFCPobtLIaAv0zg+zntzQv1PNSqh2x2w/6 fcs5cOkJT64tSEXknqQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130099 Add driver documentation for AD7768. Signed-off-by: Janani Sunil --- Documentation/iio/ad7768.rst | 240 +++++++++++++++++++++++++++++++++++++++= ++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 242 insertions(+) diff --git a/Documentation/iio/ad7768.rst b/Documentation/iio/ad7768.rst new file mode 100644 index 000000000000..7c97179ff905 --- /dev/null +++ b/Documentation/iio/ad7768.rst @@ -0,0 +1,240 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +AD7768 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +ADC driver for Analog Devices Inc. AD7768 and AD7768-4 devices. The module= name +is ``ad7768``. + +Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following chips are supported by this driver: + +* `AD7768 `_ - + 8-channel, 24-bit simultaneous sampling ADC +* `AD7768-4 `_ - + 4-channel, 24-bit simultaneous sampling ADC + +Supported features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Power modes +----------- + +The AD7768 family supports three power and performance modes: + +* **Low power mode** - Optimized for lowest power consumption +* **Median mode** - Balanced power and performance +* **Fast mode** - Highest performance with maximum sampling rates + +The driver initializes the device in fast mode and uses the maximum fast-m= ode +output data rate as the default sampling frequency. + +When buffered capture starts, the driver selects the lowest-noise mode tha= t can +produce the requested output data rates for all enabled channels. Where ou= tput +data rates overlap, fast mode is preferred over median mode, and median mo= de is +preferred over low power mode. This prioritizes the lower RMS noise and hi= gher +dynamic range offered by a faster mode at the same output data rate. + +Data output configuration +------------------------- + +The devices support flexible serial data output configurations: + +AD7768 data lines +^^^^^^^^^^^^^^^^^ + +* 1 data line (DOUT0) - Standard single-lane output +* 2 data lines (DOUT0, DOUT1) - Dual-lane output for higher throughput +* 8 data lines (DOUT0-DOUT7) - Maximum throughput, one line per channel + +AD7768-4 data lines +^^^^^^^^^^^^^^^^^^^ + +* 1 data line (DOUT0) - Standard single-lane output +* 4 data lines (DOUT0-DOUT3) - Maximum throughput, one line per channel + +The number of data lines can be configured via the ``adi,data-lines-number= `` +device tree property. If omitted, the driver uses the maximum supported by= the +selected variant: eight lines for AD7768 and four lines for AD7768-4. + +Channel configuration +--------------------- + +Each channel can be individually configured with: + +Channel modes +^^^^^^^^^^^^^ + +* **Mode A** - First set of filter and decimation settings +* **Mode B** - Second set of filter and decimation settings + +The hardware provides two mode profiles (A and B), each holding one +(frequency, filter) combination. When buffered capture is started, +enabled channels are grouped by their configured (frequency, filter) +pair. Up to two distinct groups are supported; the driver automatically +assigns each group to a mode slot and programs the hardware accordingly. + +Precharge and reference buffers +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Per-channel buffer control for optimal signal integrity: + +* Positive input precharge buffer (``adi,prechargebuf-pos-enable``) +* Negative input precharge buffer (``adi,prechargebuf-neg-enable``) +* Positive reference buffer (``adi,refbuf-pos-enable``) +* Negative reference buffer (``adi,refbuf-neg-enable``) + +Common mode voltage +------------------- + +The VCM pin provides a buffered common-mode voltage output used to bias +the analog inputs. The driver exposes this as a standard voltage regulator +provider under a ``regulators`` subnode in the device tree. Supported +output voltage levels are: + +* (AVDD1 - AVSS) / 2 - Mid-supply (hardware default), reported as half the + voltage provided by ``avdd1-supply`` +* 1,650,000 =C2=B5V - 1.65V +* 2,500,000 =C2=B5V - 2.5V +* 2,140,000 =C2=B5V - 2.14V + +The regulator can be enabled and disabled at runtime using the standard +regulator framework interfaces. + +The VCM circuitry is associated with channel 0. When VCM is used externall= y, +``channel@0`` must be present in the device tree and channel 0 must remain +enabled in the active scan mask. Placing channel 0 in standby disables the= VCM +output. + +Filter types +------------ + +Two digital filter types are available: + +* **Wideband** - Optimized for wide bandwidth applications +* **Sinc5** - Fifth-order sinc filter for high rejection of out-of-band no= ise + +IIO backend support +------------------- + +The driver integrates with IIO backends (e.g., AXI ADC) for high-speed data +capture and DMA operations. Features include: + +* Automatic channel enable/disable based on scan mask +* CRC on data interface. CRC replaces the header every 4th output sample. +* High-throughput buffered data acquisition + +GPIO controller +--------------- + +The AD7768 includes a 5-pin GPIO controller for auxiliary digital I/O +operations. The GPIO pins can be configured as inputs or outputs. + +Device attributes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following IIO attributes are available for each enabled channel: + +Sampling frequency +------------------ + +.. list-table:: + :header-rows: 1 + :widths: 40 60 + + * - Attribute + - Description + * - ``in_voltage_sampling_frequency`` + - Requested sampling frequency in Hz for channel N. Enabled channels = are + grouped into up to two profiles at capture time. + * - ``in_voltage_sampling_frequency_available`` + - Available sampling frequencies in Hz for channel N across all power + modes, based on the master clock frequency. Buffer setup fails if no + single power mode supports the frequencies requested by all enabled + channels. + +Filter configuration +--------------------- + +.. list-table:: + :header-rows: 1 + :widths: 40 60 + + * - Attribute + - Description + * - ``in_voltage_filter_type`` + - Requested filter type for channel N: "wideband" or "sinc5". It is + grouped with sampling frequency at capture time. + * - ``in_voltage_filter_type_available`` + - Available filter types for channel N: "wideband sinc5". + +Per-channel calibration +----------------------- + +.. list-table:: + :header-rows: 1 + :widths: 40 60 + + * - Attribute + - Description + * - ``in_voltage_calibbias`` + - Raw unsigned 24-bit channel offset register value. + * - ``in_voltage_calibscale`` + - Raw unsigned 24-bit channel gain register value. + * - ``in_voltage_convdelay`` + - Per-channel conversion delay. The driver exposes the sync phase off= set + value in seconds with picosecond precision. Resolution and valid ra= nge + depend on the decimation ratio in use (see datasheet + Table 30). + +Device buffers +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This driver supports IIO buffered data acquisition through IIO backends. +When used with compatible backends like the AXI ADC, it provides: + +* High-speed simultaneous sampling across all enabled channels +* Hardware-driven data capture +* DMA-based data transfer for minimal CPU overhead +* CRC error detection + +See :doc:`iio_devbuf` for more information about IIO device buffers. + +Example usage +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +.. code-block:: bash + + # Read current sampling frequency for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_sampling_frequency + + # Update sampling frequency for channel 0 + echo 8000 > /sys/bus/iio/devices/iio:device0/in_voltage0_sampling_frequen= cy + + # Read current filter type for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_filter_type + + # List available filter types for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_filter_type_available + + # Update filter type for channel 0 to wideband + echo wideband > /sys/bus/iio/devices/iio:device0/in_voltage0_filter_type + + # Buffer setup fails if enabled channels request more than two distinct + # (sampling frequency, filter type) combinations. + + # Read calibration scale for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_calibscale + + # Read conversion delay for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_convdelay + + +Unimplemented features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* CRC message every 16 samples (CRC_SEL configuration) - currently only + supports CRC every 4 samples diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index b02b879b053a..73c58cec7620 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -29,6 +29,7 @@ Industrial I/O Kernel Drivers ad7380 ad7606 ad7625 + ad7768 ad7944 ade9000 adf41513 diff --git a/MAINTAINERS b/MAINTAINERS index 3de7ebcc4ee7..b93c77d3a4c3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1639,6 +1639,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml +F: Documentation/iio/ad7768.rst F: drivers/gpio/gpio-ad7768.c F: drivers/iio/adc/ad7768.c =20 --=20 2.43.0