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Wed, 12 Aug 2026 05:21:56 -0700 (PDT) From: Yu-Chien Peter Lin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org, dfustini@oss.tenstorrent.com, michal.simek@amd.com, junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com, akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com, robin.randhawa@sifive.com, scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com, anup@brainfault.org, pawandeep.oza@oss.qualcomm.com, Yu-Chien Peter Lin Subject: [RFC PATCH v3 1/3] dt-bindings: riscv: Add Worlds ISA extensions Date: Wed, 12 Aug 2026 20:21:29 +0800 Message-ID: <20260812122131.1534906-2-peter.lin@sifive.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20260812122131.1534906-1-peter.lin@sifive.com> References: <20260812122131.1534906-1-peter.lin@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT bindings for RISC-V Worlds ISA extensions (Smwid, Smlwidlist, Smlwid, Smwiddeleg, Sswid) and enforce their architectural dependency rules in the schema. Signed-off-by: Yu-Chien Peter Lin --- Changes v2->v3: - Add extension dependency rules - Fix alphabetical order --- .../devicetree/bindings/riscv/extensions.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 5ffc40d599c0..0408d1116527 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -181,6 +181,18 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. =20 + - const: smlwid + description: | + The standard Smlwid extension for M-mode control of lower + privilege World ID via the mlwid CSR as ratified at commit + TBD ("TBD") of riscv-worlds. + + - const: smlwidlist + description: | + The standard Smlwidlist extension for M-mode control of lower + privilege World IDs via the mlwidlist CSR as ratified at commit + TBD ("TBD") of riscv-worlds. + - const: smmpm description: | The standard Smmpm extension for M-mode pointer masking as @@ -199,6 +211,17 @@ properties: added by other RISC-V extensions in H/S/VS/U/VU modes and as ratified at commit a28bfae (Ratified (#7)) of riscv-state-enab= le. =20 + - const: smwid + description: | + The standard Smwid extension for M-mode World ID control via t= he + mwid CSR as ratified at commit TBD ("TBD") of riscv-worlds. + + - const: smwiddeleg + description: | + The standard Smwiddeleg extension for M-mode delegation of low= er + privilege World ID control to S-mode via the mwiddeleg CSR, as + ratified at commit TBD ("TBD") of riscv-worlds. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced @@ -262,6 +285,12 @@ properties: ratified in RISC-V Profiles Version 1.0, with commit b1d806605= f87 ("Updated to ratified state.") =20 + - const: sswid + description: | + The standard Sswid extension for S-mode control of lower + privilege World IDs via the slwid CSR as ratified at commit + TBD ("TBD") of riscv-worlds. + - const: supm description: | The standard Supm extension for pointer masking support in user @@ -924,6 +953,30 @@ properties: then: contains: const: b + # Smlwidlist depends on Smwid and Smlwid + - if: + contains: + const: smlwidlist + then: + allOf: + - contains: + const: smwid + - contains: + const: smlwid + # Smwiddeleg depends on Smlwid + - if: + contains: + const: smwiddeleg + then: + contains: + const: smlwid + # Sswid depends on Smwiddeleg + - if: + contains: + const: sswid + then: + contains: + const: smwiddeleg # Supm depends on Smnpm or Ssnpm - if: contains: --=20 2.43.7 From nobody Tue Sep 29 04:42:43 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5840440A2F for ; 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Wed, 12 Aug 2026 05:22:06 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aaa5d04sm65858905e9.2.2026.08.12.05.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Aug 2026 05:22:05 -0700 (PDT) From: Yu-Chien Peter Lin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org, dfustini@oss.tenstorrent.com, michal.simek@amd.com, junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com, akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com, robin.randhawa@sifive.com, scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com, anup@brainfault.org, pawandeep.oza@oss.qualcomm.com, Yu-Chien Peter Lin Subject: [RFC PATCH v3 2/3] dt-bindings: riscv: Add Worlds per-hart properties Date: Wed, 12 Aug 2026 20:21:30 +0800 Message-ID: <20260812122131.1534906-3-peter.lin@sifive.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20260812122131.1534906-1-peter.lin@sifive.com> References: <20260812122131.1534906-1-peter.lin@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add per-hart DT properties for the RISC-V Worlds architecture: riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These platform-defined values are primarily used by M-mode firmware to configure World ID CSRs and restrict WID usage across privilege levels. Also add schema validation rules to enforce valid property combinations based on the ISA extensions present. Signed-off-by: Yu-Chien Peter Lin --- Changes v2->v3: - Drop riscv,nworlds property - Drop 'required' check for riscv,pmwid --- .../devicetree/bindings/riscv/cpus.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 5feeb2203050..326b68398b90 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,26 @@ allOf: properties: thead,vlenb: false =20 + - if: + properties: + riscv,isa-extensions: + not: + contains: + const: smwid + then: + properties: + riscv,pmwidlist: false + + - if: + properties: + riscv,isa-extensions: + not: + contains: + const: smlwid + then: + properties: + riscv,pmlwidlist: false + properties: compatible: oneOf: @@ -113,6 +133,30 @@ properties: description: The blocksize in bytes for the Zicboz cache operations. =20 + riscv,pmlwidlist: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Optional bitmask of WIDs available for S-mode and U-mode use on this + hart; each set bit N indicates WID N is available. Firmware may read + this to select platform authorized WIDs for lower-privilege modes. + + riscv,pmwid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + M-mode World ID (WID) for this hart, M-mode firmware may read this + property to identify the WID for M-mode. For a Worlds-aware platform + without any Worlds ISA implemented, this is the WID for all privilege + modes. + minimum: 0 + maximum: 63 + + riscv,pmwidlist: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Optional bitmask of WIDs available for M-mode use on this hart; each + set bit N indicates WID N is available. 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Wed, 12 Aug 2026 05:22:14 -0700 (PDT) From: Yu-Chien Peter Lin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org, dfustini@oss.tenstorrent.com, michal.simek@amd.com, junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com, akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com, robin.randhawa@sifive.com, scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com, anup@brainfault.org, pawandeep.oza@oss.qualcomm.com, Yu-Chien Peter Lin Subject: [RFC PATCH v3 3/3] dt-bindings: access-controllers: Add SiFive WorldGuard Checker Date: Wed, 12 Aug 2026 20:21:31 +0800 Message-ID: <20260812122131.1534906-4-peter.lin@sifive.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20260812122131.1534906-1-peter.lin@sifive.com> References: <20260812122131.1534906-1-peter.lin@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add binding for the SiFive wgChecker, a programmable access controller integrated in the interconnect fabric of RISC-V Worlds-capable SoCs. At this initial stage, the binding is designed for M-mode firmware to configure wgChecker partitions during platform initialization. Linux typically runs as an untrusted World and does not require a wgChecker driver; instead, it operates within the constraints enforced by firmware-configured partitions. wgChecker acts as an access-controllers provider, with consumers (protected devices) referencing it via the standard access-controllers phandle to declare their access requirements. Link: https://github.com/riscvarchive/security/blob/main/papers/worldguard%= 20proposal.pdf Signed-off-by: Yu-Chien Peter Lin --- Changes v2->v3: - Drop sifive,trustedwid property - Reposition YAML file to bindings/access-controllers (Krzysztof) - Fix compatible string (Krzysztof and Conor) - Drop unneed description from stardard property (Krzysztof) - Use consistent quotes (Krzysztof) - Keep access controller provider node only (Krzysztof) - Fix node name (Conor) - Rename sifive,protected-region to sifive,wg-region --- .../access-controllers/sifive,wgchecker2.yaml | 178 ++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/access-controllers/si= five,wgchecker2.yaml diff --git a/Documentation/devicetree/bindings/access-controllers/sifive,wg= checker2.yaml b/Documentation/devicetree/bindings/access-controllers/sifive= ,wgchecker2.yaml new file mode 100644 index 000000000000..23ff7d6ef08e --- /dev/null +++ b/Documentation/devicetree/bindings/access-controllers/sifive,wgchecker= 2.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2026 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/access-controllers/sifive,wgchecker2.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive WorldGuard Checker + +maintainers: + - Yu-Chien Peter Lin + +description: | + The RISC-V Worlds ISA extension defines World IDs (WIDs) as architectural + identifiers that tag each system transaction with its originating contex= t. + System integrators assign WIDs to execution contexts such as privilege + modes, trusted execution environments, or other isolation boundaries. + + The SiFive WorldGuard Checker is a hardware firewall positioned in the + system interconnect fabric. It supports up to 32 WIDs and inspects every + transaction, evaluating the WID against access control policies encoded + in checker slots for each protected resource. Transactions from + unauthorized WIDs are blocked and reported as bus errors, interrupts, or + both. + + This enables spatial partitioning of memory regions and memory-mapped + devices across execution contexts. Different address ranges can enforce + distinct policies, allowing isolated workloads to coexist with + hardware-enforced protection. + + The wgChecker acts as an access-controller provider as defined in the + access-controllers framework. Protected devices are consumers that + declare their access policy via the access-controllers property. + +allOf: + - $ref: /schemas/access-controllers/access-controllers.yaml# + +properties: + compatible: + items: + - enum: + - qemu,wgchecker2 + - const: sifive,wgchecker2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: + Interrupt line asserted when a WID access violation is detected and + interrupt reporting is enabled in the slot configuration (IR or IW + bits set). + + "#access-controller-cells": + const: 1 + description: | + Specifies the partition identifier to reference a partition child + node that defines the access control region, WID permissions, and + access failure configuration. The special ID 0xFFFFFFFF indicates + unprotected mode, granting unrestricted access to the device. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^partition@[0-9a-f]+$": + type: object + additionalProperties: false + + properties: + reg: + maximum: 0xFFFFFFFE + description: + Partition identifier. Must be unique within the wgChecker node. + The value 0xFFFFFFFF is reserved for unprotected mode and must + not be used. + + sifive,wg-region: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Protected memory region encoded as a base address and size. + items: + - description: Upper 32 bits of the base address + - description: Lower 32 bits of the base address + - description: Upper 32 bits of the region size + - description: Lower 32 bits of the region size + + sifive,slot-permissions: + $ref: /schemas/types.yaml#/definitions/uint64 + description: | + 64-bit WID permission bitmap. Each WID N uses two consecutive bi= ts: + - bit[2*N] : Read permission for WID N + - bit[2*N+1]: Write permission for WID N + Set bits grant access. + + sifive,slot-config: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x1F + description: | + Access failure configuration flags for this slot: + bit[0] (ER): report read violations as bus errors + bit[1] (EW): report write violations as bus errors + bit[2] (IR): report read violations via interrupt + bit[3] (IW): report write violations via interrupt + bit[4] (L) : lock this slot against further modification + Bits[5:31] are reserved and must be zero. + + required: + - reg + - sifive,wg-region + - sifive,slot-permissions + - sifive,slot-config + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#access-controller-cells" + +additionalProperties: false + +examples: + - | + // Example 1: Peripheral device protection + + access-controller@c1000 { + compatible =3D "qemu,wgchecker2", "sifive,wgchecker2"; + reg =3D <0xc1000 0x1000>; + #access-controller-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <80 4>; + + partition@0 { + reg =3D <0>; + sifive,wg-region =3D <0x0 0x000c0000 0x0 0x00001000>; + sifive,slot-permissions =3D <0x0 0x000000c3>; + sifive,slot-config =3D <0x0f>; + }; + }; + + - | + // Example 2: DRAM partitioning with multiple regions + + access-controller@40000000 { + compatible =3D "qemu,wgchecker2", "sifive,wgchecker2"; + reg =3D <0x40000000 0x1000>; + #access-controller-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <82 4>; + + partition@0 { + reg =3D <0>; + sifive,wg-region =3D <0x0 0x80000000 0x0 0x40000000>; + sifive,slot-permissions =3D <0x0 0x000000cf>; + sifive,slot-config =3D <0x0f>; + }; + + partition@1 { + reg =3D <1>; + sifive,wg-region =3D <0x0 0xc0000000 0x0 0x01000000>; + sifive,slot-permissions =3D <0x0 0x000000cc>; + sifive,slot-config =3D <0x0f>; + }; + + partition@2 { + reg =3D <2>; + sifive,wg-region =3D <0x0 0xc1000000 0x0 0x3f000000>; + sifive,slot-permissions =3D <0x0 0x000000cf>; + sifive,slot-config =3D <0x0f>; + }; + }; --=20 2.43.7