From nobody Tue Sep 29 05:34:07 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08A7519CC0F; Wed, 12 Aug 2026 01:02:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496563; cv=none; b=CNFVzOSZv1XuWC/5XkZzR4KEmHgjslSGzypzx5CGKGJEADJbD7az3v1eOVWriTS1AOb9jkrtJhGYSw/PAJVVMO45N06TjoUsbWWNuxANJQPtVlxJa/boMxuLSECkmdHW6JIWiz/shCJqElL/4P4IP71NDzI/3Wy2oHubpUUfXS4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496563; c=relaxed/simple; bh=pfUsyoLoHAX8g8NNT9OCZLozcs6hQaR9JvPwdpfxa98=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Vbc2blTQtGUGlHi+jBTVaQolCz+s+vfwtsJOcPCb0/j/g/vJ3CZn4c7loPQcrWeScTbqaoyK/kcIFWOo1mNKUGpCP9mZzT/LmlbyVImI+5WGNcoobCe6eUt2gbSzI53e7kCs4qt2mqlr2c9KqL9EieUwYfjneiJGJTusLSdyjiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=H1EsvCaa; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="H1EsvCaa" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B341D11A0F7; Wed, 12 Aug 2026 03:02:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786496554; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=abWDjsJ7MsHebe5ntsIcqA1aci2Halsj83iswXsJtc4=; b=H1EsvCaaoRHgFznR+XCmsmsslT45Kre7HxxJyi6Y8Oq/4ZSuY4dgAKmCk0hoXaXQUJLS8X YYoB0bsgP1F8zuELGXr4LjXk9Rx40DYwGAN+GgLT0J4DmWFECTiOsuMIyTiM2mq5shYrm0 zLNuzMRJ4ZlH8BD9LTm3G7JGPXyqrkMArBh/d6O1G9r4MxzFOmEon0As/sdOh41Xm0DzXg TELgugOCTWQQxpx2mLdCPCihv2CkePJ0lci/wEFy/CeMKJBMhvRBAdzdL+9Pq0n37W2LtG KXYTL/s4+NwLqyLj806PXfW1YvuaABIMDgaex8n/Bf9CzYvy1c1Fk/r3YVVMMQ== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Pankaj Dev , =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= , Fabrice Gasnier , Marek Vasut , Rahul Kumar , Alexandre Torgue , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/8] dt-bindings: phy: Document ST STM32MP25 USB2-FEMTO PHY Date: Wed, 12 Aug 2026 02:55:41 +0200 Message-ID: <20260812010157.1772849-2-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260812010157.1772849-1-marex@nabladev.com> References: <20260812010157.1772849-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 From: Pankaj Dev Document USB2 PHY for STM32MP25 USB2 controllers, which includes the USB2.0 host-only controller and USB 2.0 part of the DWC3 controller. Two such PHYs in total are present in STM32MP25 SoC, they both are slightly different, therefore they use different compatible string to discern them. Signed-off-by: Cl=C3=A9ment Le Goffic Signed-off-by: Fabrice Gasnier Signed-off-by: Marek Vasut Signed-off-by: Pankaj Dev Signed-off-by: Rahul Kumar --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- .../bindings/phy/st,stm32-usb2phy.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/st,stm32-usb2phy.= yaml diff --git a/Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml b/= Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml new file mode 100644 index 0000000000000..ca9fc3b87383c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/st,stm32-usb2phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 MPU High-Speed USB PHY + +description: + USB2 PHY block in STM32 is attached to USB 2.0 Host controller and + USB 2.0 side of DWC3 DRD controller, and provides the USB LS/FS/HS + connectivity. + +maintainers: + - Fabrice Gasnier + - Marek Vasut + - Pankaj Dev + +properties: + compatible: + enum: + - st,stm32mp25-usb2phy1 + - st,stm32mp25-usb2phy2 + + "#phy-cells": + const: 0 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + vdd33-supply: + description: Phandle to regulator providing 3V3 power supply to the US= B2 HS PHY + + st,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Phandle to system configuration controller. + items: + - items: + - description: phandle to syscfg + - description: USB2PHY control offset within syscfg + + "#clock-cells": + const: 0 + +required: + - compatible + - "#clock-cells" + - "#phy-cells" + - clocks + - resets + - st,syscfg + - vdd33-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + + usb2_phy2: usb-phy { + compatible =3D "st,stm32mp25-usb2phy"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + clocks =3D <&rcc CK_KER_USB2PHY2>; + resets =3D <&rcc USB2PHY2_R>; + st,syscfg =3D <&syscfg 0x2800>; + vdd33-supply =3D <&vdd33usb>; + }; --=20 2.53.0 From nobody Tue Sep 29 05:34:07 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BE9119CC0F; Wed, 12 Aug 2026 01:02:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496568; cv=none; b=KzuRAyn28BynXoXms0kZLFl+A2eQMV4gWtngBauVqllBGHhiAAwRoxe459M1WyEBWcjuFlbw1MOdTO9IcJuFvs976v0GpD+zRt0LajfwUIdFdp3zsmaiYULeSo9o1xCSrE1dzEx+/HnyxZWIGkp1Qt6fPd7xcEH6Qvz4OVDRNTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496568; c=relaxed/simple; bh=Q37VI9VkNh1tiUmaLYg5nQyvcXYWhRCSRud1KsuLHuI=; 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a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786496560; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=z8pZrf4Gtk8+ekwt54vGpwfhfI6JebdT3Yg7Td3HQdc=; b=CGz+ZNWBMgE9RvIW3hu+FtrZ8o74enZFYYt11xvA9w0/D7+KU8J2t0QKlEkVJitChfuf5D +iGoHw+S4JTxEhOB4KgQfJ9is1Djdw6BTgA02R+0xe6fl18Wofzi+tzhV4XoSBbLQKw29g olzy0Mbrhe1Io4vQL9sBkvN6Azc/4FsPuvimvlSNj4vFt8ahkLCW/Vi7iSzAz63L+Rypyb LeKTDgQHcZdVxS5v0JVM+vt8qXZF/n9ZJf9lIGicYVHPiD8EPaXvPjK7S7V26bRGTrtD6o wXbPdMGmNqwFltx61ups/w/U0a6LMHF2UMl6yLemKc40u2c6jutCtDGyAk780g== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Pankaj Dev , Christian Bruel , Fabrice Gasnier , Marek Vasut , Rahul Kumar , Alexandre Torgue , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/8] phy: stm32: Add support for ST STM32MP25 USB2-FEMTO PHY Date: Wed, 12 Aug 2026 02:55:42 +0200 Message-ID: <20260812010157.1772849-3-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260812010157.1772849-1-marex@nabladev.com> References: <20260812010157.1772849-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Pankaj Dev Add USB2 PHY driver for STM32MP25 USB2 controllers, which includes the USB2.0 host-only controller and USB 2.0 part of the DWC3 controller. Two such PHYs in total are present in STM32MP25 SoC, they both are slightly different, therefore they use different compatible string to discern them. Signed-off-by: Christian Bruel Signed-off-by: Fabrice Gasnier Signed-off-by: Marek Vasut Signed-off-by: Pankaj Dev Signed-off-by: Rahul Kumar --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- drivers/phy/st/Kconfig | 10 + drivers/phy/st/Makefile | 1 + drivers/phy/st/phy-stm32-usb2phy.c | 356 +++++++++++++++++++++++++++++ 3 files changed, 367 insertions(+) create mode 100644 drivers/phy/st/phy-stm32-usb2phy.c diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig index 49206185e5633..2835bb67bca9e 100644 --- a/drivers/phy/st/Kconfig +++ b/drivers/phy/st/Kconfig @@ -58,3 +58,13 @@ config PHY_STM32_USBPHYC used by an HS USB Host controller, and the second one is shared between an HS USB OTG controller and an HS USB Host controller, selected by a USB switch. + +config PHY_STM32_USB2PHY + tristate "STMicroelectronics STM32MP25 USB2.0 PHY Controller driver" + depends on ARCH_STM32 || COMPILE_TEST + depends on COMMON_CLK + select GENERIC_PHY + help + Enable this to support the High-Speed USB 2.0 transceivers that are + part of the STMicroelectronics STM32MP25 SoCs. The PHY itself is a + Synopsys FEMTO-PHY. diff --git a/drivers/phy/st/Makefile b/drivers/phy/st/Makefile index cb80e954ea9f0..4945df5ed78a8 100644 --- a/drivers/phy/st/Makefile +++ b/drivers/phy/st/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) +=3D phy-spear1340-mip= hy.o obj-$(CONFIG_PHY_STIH407_USB) +=3D phy-stih407-usb.o obj-$(CONFIG_PHY_STM32_COMBOPHY) +=3D phy-stm32-combophy.o obj-$(CONFIG_PHY_STM32_USBPHYC) +=3D phy-stm32-usbphyc.o +obj-$(CONFIG_PHY_STM32_USB2PHY) +=3D phy-stm32-usb2phy.o diff --git a/drivers/phy/st/phy-stm32-usb2phy.c b/drivers/phy/st/phy-stm32-= usb2phy.c new file mode 100644 index 0000000000000..d902354f88b69 --- /dev/null +++ b/drivers/phy/st/phy-stm32-usb2phy.c @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics STM32 USB2 PHY Controller driver + * Currently Only supported for STM32MP25 + * + * Copyright (C) 2022 STMicroelectronics + * Author(s): Pankaj Dev . + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCFG_USB2PHY2CR_USB2PHY2CMN BIT(2) +#define SYSCFG_USB2PHY2CR_VBUSVALID BIT(4) +#define SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL BIT(5) +#define SYSCFG_USB2PHY2CR_VBUSVLDEXT BIT(6) + +struct stm32_usb2phy { + struct phy *phy; + struct regmap *regmap; + struct device *dev; + struct reset_control *rstc; + struct clk *phyref; + struct regulator *vdd33; + struct clk_hw clk48_hw; + const struct stm32mp2_usb2phy_hw_data *hw_data; + atomic_t en_refcnt; + enum phy_mode mode; + u32 cr_offset; + bool is_init; +}; + +struct stm32mp2_usb2phy_hw_data { + u32 phyrefsel_mask; + bool is_usb2_host_only; +}; + +static int stm32_usb2phy_enable(struct stm32_usb2phy *phy_dev) +{ + const struct stm32mp2_usb2phy_hw_data *phy_data =3D phy_dev->hw_data; + unsigned long rate; + int refsel, ret; + + /* Check if a phy is already init or clk48 in use */ + if (atomic_inc_return(&phy_dev->en_refcnt) > 1) + return 0; + + rate =3D clk_get_rate(phy_dev->phyref); + if (rate =3D=3D 19200000) + refsel =3D 0; + else if (rate =3D=3D 20000000) + refsel =3D 1; + else if (rate =3D=3D 24000000) + refsel =3D 2; + else + return -EINVAL; + + ret =3D regmap_update_bits(phy_dev->regmap, + phy_dev->cr_offset, + phy_data->phyrefsel_mask, + field_prep(phy_data->phyrefsel_mask, refsel)); + if (ret) + return ret; + + if (phy_data->is_usb2_host_only) { + /* + * The clock should default to active after standby, as it is + * needed when resuming OHCI to access its registers. + * CMN is default reset to 1, so enforce it is cleared, when the + * clock enable request from OHCI driver comes at resume time. + */ + ret =3D regmap_clear_bits(phy_dev->regmap, phy_dev->cr_offset, + SYSCFG_USB2PHY2CR_USB2PHY2CMN); + if (ret) + return ret; + } + + ret =3D regulator_enable(phy_dev->vdd33); + if (ret) + return ret; + + ret =3D clk_prepare_enable(phy_dev->phyref); + if (ret) + goto error_regdis; + + ret =3D reset_control_deassert(phy_dev->rstc); + if (ret) + goto error_clkdis; + + return 0; + +error_clkdis: + clk_disable_unprepare(phy_dev->phyref); +error_regdis: + regulator_disable(phy_dev->vdd33); + + return ret; +} + +static int stm32_usb2phy_disable(struct stm32_usb2phy *phy_dev) +{ + int ret; + + /* Check if a phy is still init or clk48 in use */ + if (atomic_dec_return(&phy_dev->en_refcnt) > 0) + return 0; + + ret =3D reset_control_assert(phy_dev->rstc); + if (ret) + return ret; + + clk_disable_unprepare(phy_dev->phyref); + + return regulator_disable(phy_dev->vdd33); +} + +static int stm32_usb2phy_set_mode(struct phy *phy, enum phy_mode mode, int= submode) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + const struct stm32mp2_usb2phy_hw_data *phy_data =3D phy_dev->hw_data; + u32 val, mask =3D SYSCFG_USB2PHY2CR_USB2PHY2CMN; + int ret; + + if (mode =3D=3D PHY_MODE_USB_HOST) { + val =3D 0; + if (!phy_data->is_usb2_host_only) { + mask |=3D SYSCFG_USB2PHY2CR_VBUSVLDEXT | + SYSCFG_USB2PHY2CR_VBUSVALID; + if (submode !=3D USB_ROLE_NONE) + val |=3D SYSCFG_USB2PHY2CR_VBUSVALID; + } + } else if (mode =3D=3D PHY_MODE_USB_DEVICE) { + val =3D SYSCFG_USB2PHY2CR_USB2PHY2CMN | + SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL; + mask |=3D SYSCFG_USB2PHY2CR_VBUSVALID | + SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL | + SYSCFG_USB2PHY2CR_VBUSVLDEXT; + if (submode !=3D USB_ROLE_NONE) + val |=3D SYSCFG_USB2PHY2CR_VBUSVLDEXT; + } else { + return -EINVAL; + } + + ret =3D regmap_update_bits(phy_dev->regmap, phy_dev->cr_offset, mask, val= ); + if (ret) + return ret; + + phy_dev->mode =3D mode; + + return 0; +} + +static int stm32_usb2phy_init(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + int ret; + + ret =3D stm32_usb2phy_enable(phy_dev); + if (ret) + return ret; + + if (phy_dev->mode !=3D PHY_MODE_INVALID) { + ret =3D stm32_usb2phy_set_mode(phy, phy_dev->mode, USB_ROLE_NONE); + if (ret) { + stm32_usb2phy_disable(phy_dev); + return ret; + } + } + + phy_dev->is_init =3D true; + + return 0; +} + +static int stm32_usb2phy_exit(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + int ret; + + ret =3D stm32_usb2phy_disable(phy_dev); + if (ret) + return ret; + + phy_dev->is_init =3D false; + + return 0; +} + +static const struct phy_ops stm32_usb2phy_data =3D { + .init =3D stm32_usb2phy_init, + .exit =3D stm32_usb2phy_exit, + .set_mode =3D stm32_usb2phy_set_mode, + .owner =3D THIS_MODULE, +}; + +static int stm32_usb2phy_clk48_prepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev =3D container_of(hw, struct stm32_usb2phy, + clk48_hw); + + return stm32_usb2phy_enable(phy_dev); +} + +static void stm32_usb2phy_clk48_unprepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev =3D container_of(hw, struct stm32_usb2phy, + clk48_hw); + + stm32_usb2phy_disable(phy_dev); +} + +static unsigned long stm32_usb2phy_clk48_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 48000000; +} + +static const struct clk_ops stm32_usb2phy_clk48_ops =3D { + .prepare =3D stm32_usb2phy_clk48_prepare, + .unprepare =3D stm32_usb2phy_clk48_unprepare, + .recalc_rate =3D stm32_usb2phy_clk48_recalc_rate, +}; + +static int stm32_usb2phy_probe(struct platform_device *pdev) +{ + struct clk_init_data init =3D { .ops =3D &stm32_usb2phy_clk48_ops }; + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + struct stm32_usb2phy *phy_dev; + struct phy *phy; + int ret; + + phy_dev =3D devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL); + if (!phy_dev) + return -ENOMEM; + + phy_dev->dev =3D dev; + dev_set_drvdata(dev, phy_dev); + + phy_dev->rstc =3D devm_reset_control_get(dev, NULL); + if (IS_ERR(phy_dev->rstc)) + return dev_err_probe(dev, PTR_ERR(phy_dev->rstc), "Failed to get USB2PHY= reset\n"); + + phy_dev->phyref =3D devm_clk_get(dev, NULL); + if (IS_ERR(phy_dev->phyref)) + return dev_err_probe(dev, PTR_ERR(phy_dev->phyref), "Failed to get phyre= f clk\n"); + + phy_dev->vdd33 =3D devm_regulator_get_optional(dev, "vdd33"); + if (IS_ERR(phy_dev->vdd33)) + return dev_err_probe(dev, PTR_ERR(phy_dev->vdd33), "Failed to get vdd3v3= supply\n"); + + phy_dev->regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, "s= t,syscfg", 1, + &phy_dev->cr_offset); + if (IS_ERR(phy_dev->regmap)) { + return dev_err_probe(dev, PTR_ERR(phy_dev->regmap), + "No st,syscfg phandle specified\n"); + } + + phy_dev->hw_data =3D device_get_match_data(dev); + + phy =3D devm_phy_create(dev, NULL, &stm32_usb2phy_data); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), "Failed to create PHY\n"); + + phy_dev->phy =3D phy; + phy_set_drvdata(phy, phy_dev); + + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + init.name =3D devm_kasprintf(dev, GFP_KERNEL, "clk_%s_48m", + of_node_full_name(dev->of_node)); + if (!init.name) + return -ENOMEM; + + phy_dev->clk48_hw.init =3D &init; + + ret =3D devm_clk_hw_register(phy_dev->dev, &phy_dev->clk48_hw); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to register 48 MHz clock= \n"); + + ret =3D devm_of_clk_add_hw_provider(phy_dev->dev, of_clk_hw_simple_get, &= phy_dev->clk48_hw); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to add 48 MHz clock prov= ider\n"); + + return 0; +} + +static int stm32_usb2phy_suspend(struct device *dev) +{ + struct stm32_usb2phy *phy_dev =3D dev_get_drvdata(dev); + + if (phy_dev->is_init) + return stm32_usb2phy_disable(phy_dev); + + return 0; +} + +static int stm32_usb2phy_resume(struct device *dev) +{ + struct stm32_usb2phy *phy_dev =3D dev_get_drvdata(dev); + + if (phy_dev->is_init) + return stm32_usb2phy_enable(phy_dev); + + return 0; +} + +/* STM32MP25xx USB 2.0 PHY attached to USB 2.0 Host controller */ +static const struct stm32mp2_usb2phy_hw_data stm32mp25_usb2phy1_hwdata =3D= { + .phyrefsel_mask =3D GENMASK(6, 4), + .is_usb2_host_only =3D true, +}; + +/* STM32MP25xx USB 2.0 PHY attached to USB 2.0 part of DWC3 controller */ +static const struct stm32mp2_usb2phy_hw_data stm32mp25_usb2phy2_hwdata =3D= { + .phyrefsel_mask =3D GENMASK(14, 12), + .is_usb2_host_only =3D false, +}; + +static const struct of_device_id stm32_usb2phy_of_match[] =3D { + { .compatible =3D "st,stm32mp25-usb2phy1", .data =3D &stm32mp25_usb2phy1_= hwdata }, + { .compatible =3D "st,stm32mp25-usb2phy2", .data =3D &stm32mp25_usb2phy2_= hwdata }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, stm32_usb2phy_of_match); + +static DEFINE_SIMPLE_DEV_PM_OPS(stm32_usb2phy_pm_ops, + stm32_usb2phy_suspend, stm32_usb2phy_resume); + +static struct platform_driver stm32_usb2phy_driver =3D { + .probe =3D stm32_usb2phy_probe, + .driver =3D { + .name =3D "stm32-usb2phy", + .of_match_table =3D stm32_usb2phy_of_match, + .pm =3D pm_sleep_ptr(&stm32_usb2phy_pm_ops) + } +}; + +module_platform_driver(stm32_usb2phy_driver); + +MODULE_AUTHOR("Pankaj Dev "); +MODULE_DESCRIPTION("STMicroelectronics Generic USB2PHY driver for stm32"); +MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Tue Sep 29 05:34:07 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A70BF36606E; Wed, 12 Aug 2026 01:02:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496573; cv=none; b=Yagx3qlfxuuqMdF4N8WTgLJ2Ps06JbDeEWzzxKW1l5r4VPqeAXt4mz/zi10LtpS2IZ1hCqsCWKSXEAdkaDVxYokoEKyIMBGISVC814ovcJfJvPFseUi2yvKATmA9DiXRfLCKzob86krvTJLyGq+fS2soJwemby9o2qX4g5dkPnw= ARC-Message-Signature: i=1; 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Wed, 12 Aug 2026 03:02:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786496565; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=7IfkV4fMeV55auykFK/hP+/pINz7v15ZIHYcteus4q4=; b=fKHZvYG75qLff5mhyphMc1eG+wnbCDw3rnTgMNWlKymuWWMO2u1EREioIqHYn/eUDrY5iQ KAo+C70+sJywPrIls1wToTLbmDOD/GKZtG840kDWElGGHJ15nVD0+TXtXqWGtSjgy9boLj wZFNY/iUsPG60PYhmO92lJobeASbOc6n+DnQTrCOcI72vVJ8KQm5xlhbR2wGQPs/ZRp6nb tO92Kg8/lNxZHX3yighcaZmgsLxDctBepYK3Xm6GnVBlMpWwR7+10PqCCmBN7F2P7qI198 /eBwO8sbeVuJuwJHyQqjGzsTTW/JEIjldrZWlaLd667TSYYJ3h1bzT/ycX+irw== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 3/8] dt-bindings: usb: generic-ehci: Document access-controllers property Date: Wed, 12 Aug 2026 02:55:43 +0200 Message-ID: <20260812010157.1772849-4-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260812010157.1772849-1-marex@nabladev.com> References: <20260812010157.1772849-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Document the access-controllers for EHCI USB controllers in case access checks need to be performed to use them. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ehci.yaml index ae9fb70d0212c..6bca56681cdfe 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -80,6 +80,9 @@ properties: minItems: 1 maxItems: 2 =20 + access-controllers: + maxItems: 1 + dma-coherent: true =20 interrupts: --=20 2.53.0 From nobody Tue Sep 29 05:34:07 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB63C364042; Wed, 12 Aug 2026 01:02:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496578; cv=none; b=SGi9TIWBNmyTSUFzdeXxIB0q82E3gC0l1pllhZ2pDptlyLT/Z09XHTpcPzu3W/nK/2AMDzXhn/fToiGzoz5Jw3wjzWf3DojP2smiJVCSKJs6qMXp/gDKtCs2roig8ZOk07tSYWUD7KQa3eWb9p/wrilPEs9uV2qSuNd/Z26F6KY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496578; c=relaxed/simple; bh=JLPFvhcyV1Ejg92++ch63Jk8yT0B5Vd6UjuTGjnhJAU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rGCYhZUdQ5pwQQAAMwo7Cg/S4PoIV1C2xB4yEtigq+YEwsSQ89duoTi65SqH84NbQtKU/ju75dZAofFrSIzoq/PmS9gKlyv+CQD9KRkRri1BpC2CNrFMErhsE2ySC+g031d14WYd8hAl8TfIqnlPoH+ijGwUD5ioUmCYT4/RsTQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=LRTsjnwg; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="LRTsjnwg" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CF53611A15A; Wed, 12 Aug 2026 03:02:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786496570; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=m88qCHy/S/Vbp27qirkj4TXf6QFGGR91roqySjh99AY=; b=LRTsjnwgSvcVDHJACTPkpyfQfHee1RsjW9/6P8qXrL/HRs65DCnrsz7Sayon00uBXlpChL GJBH0TvLi59z4PccCxDJ3IFT6li0r/OUytgtWp+MHc4M8tOViCjwUwR2OJ0sC+SgdJNeSm 7rtORDmchymT9QSNxzck2MDTZJilVvtzam3XPWRQgkGiUmxJNKUC5YvssX8J1eLsUexZ3l 8ZzipBF5AM+W3nTqgnOHH+3WAJCbqhnmxu8M1+hsyZv/+PDnFYkpqWRHzjJ8+o941RrFVS 0CHzMMXoMpcwXb9+Qu5M88rngXYsFE5fO2gZT2CUpU6kAIUBwxQC5duJUdpH5Q== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 4/8] dt-bindings: usb: generic-ohci: Document access-controllers property Date: Wed, 12 Aug 2026 02:55:44 +0200 Message-ID: <20260812010157.1772849-5-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260812010157.1772849-1-marex@nabladev.com> References: <20260812010157.1772849-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Document the access-controllers for OHCI USB controllers in case access checks need to be performed to use them. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ohci.yaml index 322808aaa2839..8e3522a3faa76 100644 --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml @@ -65,6 +65,9 @@ properties: reg: maxItems: 1 =20 + access-controllers: + maxItems: 1 + dma-coherent: true =20 interrupts: --=20 2.53.0 From nobody Tue Sep 29 05:34:07 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47650360EC9; Wed, 12 Aug 2026 01:03:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496585; cv=none; b=sYVT+uqhD2C6U2+RFvognPHo+41vDxvmtI0fY6DfDl0nSJNFkbvL492byoh8psUELYL6hDpPnLeUq3p1AdtI7g5CPdWJdjXLrFzJk9soOkKkOOV163/bIx3Cr6ErxPvbPFYvlaa3/nUrTvPlX/KSS9Bw1h0Qggk+r6cHf2zT+6E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496585; c=relaxed/simple; bh=fX/K+WGy56rEmgzy6z516EoVaXsCq69iDNcoXAw1aaY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=biuYuH3Dr7c44pmZrub0RgZc7cN34Cu6AQbUkUAO35cHeKtJNSK+wcFFQWFM3lY7pQzhQ0e1p2uyLXqjgsONmFRmGDR9O/Ag8qZuASHiY+581anl9y2zao4pXD9mQmHiwwvTPkr+XhLQmcfJ9mM/69EFZ+1z1XtaqgwiqhVEjZc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=YX6gMBqw; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="YX6gMBqw" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 207E311A0F7; Wed, 12 Aug 2026 03:02:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786496576; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Js4g4d2kZhjNnU26OaWa6DERMam0dZGdTIc+RrtobBM=; b=YX6gMBqwNKdgaMaU0zkkQo4QCOs2RRJX2iDSI1uMV+C5tLYzB701mGgnDFWqJSG3KJUczB vRhNPc8fO2H2VSzgcTqZVkyYHmkzZSd8oT050KEZ/0s6adq9g3J4FHVwCo/ypeA7EaPwUB uOeXB+ttxoL+3Yc+gXS12wXYzwIbPL+Lc7DyGXzaHhnDba8zctdrkl9GXYaik2V31novVC vLU2lVRKsYmPaZ+FWAxwUX5IBpdJVdkXX8rV6+qnq6dWD15tU2CDp3Wc9lBaGrjbXJ6qmo 6uFdHsDlt30U+03CmBOPUuI9cSVRMnZ1LWuP8j7hjSr1rDFobmOPZVtEtWt/xw== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Fabrice Gasnier , Pankaj Dev , Alexandre Torgue , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 5/8] dt-bindings: usb: dwc3: Document ST STM32MP2 DWC3 xHCI USB controller Date: Wed, 12 Aug 2026 02:55:45 +0200 Message-ID: <20260812010157.1772849-6-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260812010157.1772849-1-marex@nabladev.com> References: <20260812010157.1772849-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The ST STM32MP2 SoC contains single instance of DWC3 USB controller with glue logic wrapper around it controlled by syscon. Document the glue logic and DWC3 controller. Signed-off-by: Fabrice Gasnier Signed-off-by: Marek Vasut Signed-off-by: Pankaj Dev --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- .../bindings/usb/st,stm32mp25-dwc3.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3= .yaml diff --git a/Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml b= /Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml new file mode 100644 index 0000000000000..e377efef43503 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/st,stm32mp25-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 MPU DWC3 USB SoC controller + +description: + The STM32 MPU DWC3 USB SoC controller block supports both + Host(SS/HS/FS/LS) and Device(SS/HS/FS) mode operation + +maintainers: + - Fabrice Gasnier + - Marek Vasut + +properties: + compatible: + const: st,stm32mp25-dwc3 + + reg: + maxItems: 1 + + access-controllers: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: ref + - const: bus_early + - const: suspend + + dr_mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [host, peripheral, otg] + + interrupts: + maxItems: 1 + + phys: + minItems: 1 + maxItems: 2 + + phy-names: + minItems: 1 + items: + - const: usb2-phy + - const: usb3-phy + + resets: + minItems: 1 + + st,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Phandle to system configuration controller. + items: + - items: + - description: phandle to syscfg + - description: USB3DR control offset within syscfg + + st,enable-port-power-control: + type: boolean + description: Enable Host-Mode Port Power Control (bit-3 of capability = param HCCPARAMS) + + st,ovrcur-active-low: + type: boolean + description: Over-Current signal polarity is active-low + + st,vbusen-active-low: + type: boolean + description: VBUS-ENABLE signal polarity is active-low + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - st,syscfg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + usb3dr: usb@48300000 { + compatible =3D "st,stm32mp25-dwc3"; + reg =3D <0x48300000 0x100000>; + clocks =3D <&rcc CK_KER_USB2PHY2>, <&rcc CK_BUS_USB3DR>, <&rcc CK_= KER_USB2PHY2>; + clock-names =3D "ref", "bus_early", "suspend"; + interrupts =3D ; + phys =3D <&usb2_phy>, <&usb3_phy>; + phy-names =3D "usb2-phy", "usb3-phy"; + resets =3D <&rcc USB3DR_R>; + st,ovrcur-active-low; + st,syscfg =3D <&syscfg 0x4800>; + st,vbusen-active-low; + }; --=20 2.53.0 From nobody Tue Sep 29 05:34:07 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E75A1367B7E; Wed, 12 Aug 2026 01:03:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496589; cv=none; b=ZqGWDhMtadpi9B8G6ACIs1ahf627oqhZXu0Odw7UYaYnGg+slR/5xsp4r91ml75U4AudovAWBXDutkkEoYOVFTWzXjWzONqk48LbKJeUwd1MDraVfoyPrjxg6LDW1mPLX/JuByA324UQCImtjp4s9ECORupVYGGBZECHdK36Wcc= ARC-Message-Signature: i=1; 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Wed, 12 Aug 2026 03:03:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786496582; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ywWWWh73l0reUvhOnhGGy+QdpwP9Hf4VXVSThCJFhTo=; b=EkiQRK8yAz6As9vZYN6HkQYoFjvtv2usk2GyCnAjbzXOyN9Z4yDxdNE47KYggff0pwyrFs WW51HoHHO9iBbTX9P1OKoikQxH2Y/ANDGRQCsBF/LUUGd3rF6w7xfgTAA+xkAH0/VLjlcx 4ZToXdZUjog66gYykrOkH37CZfgHLM8B+Hn97qCKNNwTmxHCyGlQ2htko36b/5JGO2eZ0j 34pRKp1xe24fPtUiW14kRmLkuqbG+t1QxOSafu4DM4wHD79b8zJ+KO7ksvUZnM7ePE+v/V 9SIK2RrEvcmKWqCoXe2iiEWgJxYCMp3YBAX7309FzO9HRqprOFk+xPEwFhbX6Q== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 6/8] usb: dwc3: dwc3-generic-plat: Add ST STM32MP2 DWC3 xHCI USB controller glue Date: Wed, 12 Aug 2026 02:55:46 +0200 Message-ID: <20260812010157.1772849-7-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260812010157.1772849-1-marex@nabladev.com> References: <20260812010157.1772849-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The ST STM32MP2 SoC contains one instance of DWC3 USB controller with glue logic wrapper around it controlled by syscon. Extend the generic DWC3 platform driver with ST STM32MP2 glue logic specifics. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- drivers/usb/dwc3/dwc3-generic-plat.c | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-g= eneric-plat.c index ca69ac0eb07ce..0946ed61647b6 100644 --- a/drivers/usb/dwc3/dwc3-generic-plat.c +++ b/drivers/usb/dwc3/dwc3-generic-plat.c @@ -22,6 +22,12 @@ #define EIC7700_HSP_AXI_LP_XM_CSYSREQ BIT(0) #define EIC7700_HSP_AXI_LP_XS_CSYSREQ BIT(16) =20 +#define STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT BIT(0) +#define STM32MP2_USB3DRCR_OVRCUR_POLARITY BIT(1) +#define STM32MP2_USB3DRCR_VBUSEN_POLARITY BIT(2) +#define STM32MP2_USB3DRCR_USB2ONLYH BIT(3) +#define STM32MP2_USB3DRCR_USB2ONLYD BIT(4) + struct dwc3_generic { struct device *dev; struct dwc3 dwc; @@ -85,6 +91,38 @@ static int dwc3_spacemit_k1_init(struct dwc3_generic *dw= c3g) return 0; } =20 +static int dwc3_stm32mp25_init(struct dwc3_generic *dwc3g) +{ + struct device *dev =3D dwc3g->dev; + bool ovrcur_polarity_low =3D device_property_read_bool(dev, "st,ovrcur-ac= tive-low"); + bool prt_pwr_ctrl =3D device_property_read_bool(dev, "st,enable-port-powe= r-control"); + bool usb2only_conf =3D device_property_match_string(dev, "phy-names", "us= b3-phy") < 0; + bool vbusen_polarity_low =3D device_property_read_bool(dev, "st,vbusen-ac= tive-low"); + struct regmap *regmap; + u32 drcr; + + regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, "st,syscfg"= , 1, &drcr); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "No st,syscfg phandle specifi= ed\n"); + + return regmap_update_bits(regmap, drcr, + STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT | + STM32MP2_USB3DRCR_OVRCUR_POLARITY | + STM32MP2_USB3DRCR_VBUSEN_POLARITY | + STM32MP2_USB3DRCR_USB2ONLYD | + STM32MP2_USB3DRCR_USB2ONLYH, + FIELD_PREP(STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT, + prt_pwr_ctrl) | + FIELD_PREP(STM32MP2_USB3DRCR_OVRCUR_POLARITY, + ovrcur_polarity_low) | + FIELD_PREP(STM32MP2_USB3DRCR_VBUSEN_POLARITY, + vbusen_polarity_low) | + FIELD_PREP(STM32MP2_USB3DRCR_USB2ONLYD, + !!usb2only_conf) | + FIELD_PREP(STM32MP2_USB3DRCR_USB2ONLYH, + !!usb2only_conf)); +} + static int dwc3_generic_probe(struct platform_device *pdev) { const struct dwc3_generic_config *plat_config; @@ -231,12 +269,18 @@ static const struct dwc3_generic_config eic7700_dwc3 = =3D { .properties =3D DWC3_DEFAULT_PROPERTIES, }; =20 +static const struct dwc3_generic_config stm32mp25_dwc3 =3D { + .init =3D dwc3_stm32mp25_init, + .properties =3D DWC3_DEFAULT_PROPERTIES, +}; + static const struct of_device_id dwc3_generic_of_match[] =3D { { .compatible =3D "spacemit,k1-dwc3", &spacemit_k1_dwc3}, { .compatible =3D "spacemit,k3-dwc3", }, { .compatible =3D "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, { .compatible =3D "eswin,eic7700-dwc3", &eic7700_dwc3}, { .compatible =3D "starfive,jhb100-dwc3", }, + { .compatible =3D "st,stm32mp25-dwc3", &stm32mp25_dwc3 }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); --=20 2.53.0 From nobody Tue Sep 29 05:34:07 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC5D634C9A6; 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arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="MpknEq/L" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7D85D11A16E; Wed, 12 Aug 2026 03:03:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786496587; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=IbAA6pvCgsmhB06HsWXQ/egn4NMOuHY9bVEh1SlCYDo=; b=MpknEq/LD8wmGY05KGZMorJ6MJ11A4gGCvWiGrDnT8x5kgR/ApDQoG4EaRAJg80Oz/e15z nYRiNrQRFmvtTnwWNb6ghLz4Wbe5z3W/Txy6UeINDTIRAOAZUoI0QkIotK4EZvA7QszI82 0uV4iEsg3MtSns5/x6PIUsimc3IAoB4MtPYw0rKEDH5lGinh5J6AjyPwxI78Exrk+sZQF6 CH9JVvYhDqmL7z47mdnD+99AlHB7m1fllQwr+8r/Ch86YDW7mgkj/atmsttKbt95udoa17 ZevcKDgvipv0QhvuBZEOH2AscYWEQ5K8aAGHXLz3okFXKflG7ho7A/dxXLZ1jg== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Pankaj Dev , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 7/8] arm64: dts: st: Add USB nodes on stm32mp231 Date: Wed, 12 Aug 2026 02:55:47 +0200 Message-ID: <20260812010157.1772849-8-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260812010157.1772849-1-marex@nabladev.com> References: <20260812010157.1772849-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add USB controller and PHY nodes to stm32mp231 DT. This includes two USB 2.0 FEMTO PHYs, USB 2.0 host controller and DWC3 DRD controller nodes. Include missing COMBOPHY for the USB 3.0 controller. Signed-off-by: Marek Vasut Signed-off-by: Pankaj Dev --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 77 ++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index 4505fc0e3b537..b8cef81eceeb1 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include =20 / { #address-cells =3D <2>; @@ -146,6 +147,26 @@ timer { always-on; }; =20 + usb2_phy1: usb2-phy1 { + compatible =3D "st,stm32mp25-usb2phy1"; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + st,syscfg =3D <&syscfg 0x2400>; + clocks =3D <&rcc CK_KER_USB2PHY1>; + resets =3D <&rcc USB2PHY1_R>; + status =3D "disabled"; + }; + + usb2_phy2: usb2-phy2 { + compatible =3D "st,stm32mp25-usb2phy2"; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + st,syscfg =3D <&syscfg 0x2800>; + clocks =3D <&rcc CK_KER_USB2PHY2EN>; + resets =3D <&rcc USB2PHY2_R>; + status =3D "disabled"; + }; + soc@0 { compatible =3D "simple-bus"; ranges =3D <0x0 0x0 0x0 0x80000000>; @@ -769,6 +790,21 @@ dcmipp: dcmipp@48030000 { status =3D "disabled"; }; =20 + combophy: phy@480c0000 { + compatible =3D "st,stm32mp25-combophy"; + reg =3D <0x480c0000 0x1000>; + #phy-cells =3D <1>; + clocks =3D <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; + clock-names =3D "apb", "ker"; + resets =3D <&rcc USB3PCIEPHY_R>; + reset-names =3D "phy"; + access-controllers =3D <&rifsc 67>; + power-domains =3D <&cluster_pd>; + wakeup-source; + interrupts-extended =3D <&exti1 45 IRQ_TYPE_EDGE_FALLING>; + status =3D "disabled"; + }; + sdmmc1: mmc@48220000 { compatible =3D "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; reg =3D <0x48220000 0x400>, <0x44230400 0x8>; @@ -862,6 +898,47 @@ stmmac_axi_config_1: stmmac-axi-config { snps,wr_osr_lmt =3D <0x7>; }; }; + + usbh_ohci: usb@482e0000 { + compatible =3D "generic-ohci"; + reg =3D <0x482e0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1>, <&rcc CK_BUS_USB2OHCI>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usbh_ehci: usb@482f0000 { + compatible =3D "generic-ehci"; + reg =3D <0x482f0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1>, <&rcc CK_BUS_USB2EHCI>; + companion =3D <&usbh_ohci>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usb3dr: usb@48300000 { + compatible =3D "st,stm32mp25-dwc3"; + reg =3D <0x48300000 0x100000>; + access-controllers =3D <&rifsc 66>; + clocks =3D <&rcc CK_KER_USB2PHY2>, + <&rcc CK_BUS_USB3DR>, + <&rcc CK_KER_USB2PHY2>; + clock-names =3D "ref", "bus_early", "suspend"; + interrupts =3D ; + phys =3D <&usb2_phy2>, <&combophy PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + resets =3D <&rcc USB3DR_R>; + st,syscfg =3D <&syscfg 0x4800>; + status =3D "disabled"; + }; }; =20 bsec: efuse@44000000 { --=20 2.53.0 From nobody Tue Sep 29 05:34:07 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF60634C9A6; Wed, 12 Aug 2026 01:03:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786496600; cv=none; b=Vbq8D/g9Cerx/nKanDC/XUuy0ZRQd/v8E1hZogxb5PSMwt7olrt9yw2xjb2kE3LSICIfq1vM7IeO/ZR0e4aK4h2h15lnuoPURb48SDQB3hKKqaFaHriHKS0nf6nGhMCIVpQk4MRJj+O7nBwBJddvJP6oMqbNyHvv63v/0XzADYs= ARC-Message-Signature: i=1; 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Wed, 12 Aug 2026 03:03:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786496592; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=/y0h0XBkWfzpZGbn2+ONwS3q9qDmIFhWudnEFeJ59eY=; b=Ll7s98JJVQDiY0e/l4m7Dar4+0mwNdLcNkFHdSxbO3R2L3z2FL3Y3ksub1NsxeAXzDSYV6 w4NlgeKUg1KyJvPxBecY8KPcuFwEs7wDo7qsSmSWacuoM7A85y2Z3mElBGFg4qsUefLaAZ EYF1R33pNa1hoZypjLxTQ/HAVlC2W2eRUC0CT2yuaO5hZsa3JkNyfdr0ooQR7AjzdbDuqq Hh00nQ8KlkD2zcGoyjJ3eBqO9q8CsEtNwnXUwAUFOIFSh2SY4A0IKfMjb9dz1EskLn7q2L WVd5fm+WTRfLCPrL8U2OylIiIgJ0kVkdMMpTKWf9p1yjOOnmf9JskCbOx6jJeg== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Pankaj Dev , Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 8/8] arm64: dts: st: Add USB nodes on stm32mp251 Date: Wed, 12 Aug 2026 02:55:48 +0200 Message-ID: <20260812010157.1772849-9-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260812010157.1772849-1-marex@nabladev.com> References: <20260812010157.1772849-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Pankaj Dev Add USB controller and PHY nodes to stm32mp251 DT. This includes two USB 2.0 FEMTO PHYs, USB 2.0 host controller and DWC3 DRD controller nodes. Signed-off-by: Marek Vasut Signed-off-by: Pankaj Dev --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 61 ++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 6e985f115b195..c54bd4554c33a 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -168,6 +168,26 @@ timer { arm,no-tick-in-suspend; }; =20 + usb2_phy1: usb2-phy1 { + compatible =3D "st,stm32mp25-usb2phy1"; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + st,syscfg =3D <&syscfg 0x2400>; + clocks =3D <&rcc CK_KER_USB2PHY1>; + resets =3D <&rcc USB2PHY1_R>; + status =3D "disabled"; + }; + + usb2_phy2: usb2-phy2 { + compatible =3D "st,stm32mp25-usb2phy2"; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + st,syscfg =3D <&syscfg 0x2800>; + clocks =3D <&rcc CK_KER_USB2PHY2EN>; + resets =3D <&rcc USB2PHY2_R>; + status =3D "disabled"; + }; + soc@0 { compatible =3D "simple-bus"; #address-cells =3D <1>; @@ -1746,6 +1766,47 @@ stmmac_axi_config_1: stmmac-axi-config { }; }; =20 + usbh_ohci: usb@482e0000 { + compatible =3D "generic-ohci"; + reg =3D <0x482e0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1>, <&rcc CK_BUS_USB2OHCI>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usbh_ehci: usb@482f0000 { + compatible =3D "generic-ehci"; + reg =3D <0x482f0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1>, <&rcc CK_BUS_USB2EHCI>; + companion =3D <&usbh_ohci>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usb3dr: usb@48300000 { + compatible =3D "st,stm32mp25-dwc3"; + reg =3D <0x48300000 0x100000>; + access-controllers =3D <&rifsc 66>; + clocks =3D <&rcc CK_KER_USB2PHY2>, + <&rcc CK_BUS_USB3DR>, + <&rcc CK_KER_USB2PHY2>; + clock-names =3D "ref", "bus_early", "suspend"; + interrupts =3D ; + phys =3D <&usb2_phy2>, <&combophy PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + resets =3D <&rcc USB3DR_R>; + st,syscfg =3D <&syscfg 0x4800>; + status =3D "disabled"; + }; + pcie_ep: pcie-ep@48400000 { compatible =3D "st,stm32mp25-pcie-ep"; reg =3D <0x48400000 0x100000>, --=20 2.53.0