From nobody Tue Sep 29 04:43:03 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 775AE3FDBF5 for ; Wed, 12 Aug 2026 09:11:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525863; cv=none; b=smWh8xYb0SWr1ZzGBT7TbLA6X+y8pkmTTRdLsZKLbn18henhUBm7MVAtdudEFEE+F6GeVZMSJFkT/pYDBCL2IOFh2mVyHAldiG6QCu6cwbdGEP9O7h7Rftv6BZNXeUOYCt0XApu1bEhbwt8PLIUR+Q+U/GAwnUQMkLArZraj1ZA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525863; c=relaxed/simple; bh=9/b8BF0+fc6RpPfwoZEiOW+KQxHad9SBk8oL3FpzCZY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BQeFfBI9nlTCRu5aR2tF/5RogmAOiJqgFLs4QPVaBUWGTXvxioywgvut1a+68r8bepFFrA7Ggd8EAp4zG3Yt3lphRmFRpzcaIay3Eyl8lj1S+muPLw9BPw+DxKthWY8lCU5H08BYwqv9EBgnAeQtH4uqPE9DtQ0dbvK2/SPSP6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BQbiAfF0; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BQbiAfF0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E66151F00A3A; Wed, 12 Aug 2026 09:10:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786525859; bh=lhvJ8Eik80LP8a8sp3r1jlq/XIlZIGTy2Q7808FitFE=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=BQbiAfF0bwsuIUbKdsqDjpMVxLrUMFiD0H3KYfJYvNRSd8UuMErUIb6zHeqJZCfIY nkwEGj6s30WfLU3wEn+1g6aQXlabLRjx0riU+Zl7a8ZKtIyhMFuxi++w8YlwUIrNMj xiUL/C1f2A3LF4BceJo2Q34BsTay2dtjsZ9HigK/DSPPJ8VB+QvfON83O7e471WHwO a+vuJxfMU/e+x0XO4p5hiSoOcNeaahzmCMEYAJoq0+QYIAaRZBoAI0wSAh5RJ6bNjT U+HF3kiAjTJvgEamm4gItFSwJTmpifJCP7jWSUOKCHayvJWe4y+KtMTeMAv9t2EqdF 2PB6S4EVNGGQQ== From: Lorenzo Pieralisi Date: Wed, 12 Aug 2026 11:10:29 +0200 Subject: [PATCH 1/7] irqchip/gic-v5: Check get_logical_index() return value in MADT IAFFID parsing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-gicv5-7-2-fixes-v1-1-3743e82c69a4@kernel.org> References: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> In-Reply-To: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> To: Marc Zyngier , Thomas Gleixner , Jonathan Cameron , "Rafael J. Wysocki" , Sascha Bischoff , Timothy Hayes Cc: Sascha Bischoff , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15.2 In gic_acpi_parse_iaffid() a given MADT GICC entry might not correspond to a logical cpu recognized by the kernel, resulting in the cpu variable initialization to an error value. Currently, the get_logical_index() return value is not checked for failure, which might result in out-of-bounds memory corruption while trying to index a per_cpu variable array. Add a check to evaluate get_logical_index() return value. Fixes: 35866efa52fe ("irqchip/gic-v5: Add ACPI IRS probing") Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier Link: https://sashiko.dev/#/message/20260810104747.E5CE71F000E9%40smtp.kern= el.org --- drivers/irqchip/irq-gic-v5-irs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-= irs.c index 3028a8bbbf68..0bd9ae9ae12e 100644 --- a/drivers/irqchip/irq-gic-v5-irs.c +++ b/drivers/irqchip/irq-gic-v5-irs.c @@ -874,6 +874,8 @@ static int __init gic_acpi_parse_iaffid(union acpi_subt= able_headers *header, return 0; =20 cpu =3D get_logical_index(gicc->arm_mpidr); + if (cpu < 0) + return 0; =20 if (gicc->iaffid & ~GENMASK(current_iaffid_bits - 1, 0)) { pr_warn("CPU %d iaffid 0x%x exceeds IRS iaffid bits\n", cpu, gicc->iaffi= d); --=20 2.53.0 From nobody Tue Sep 29 04:43:03 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC0D23FDC05 for ; Wed, 12 Aug 2026 09:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525866; cv=none; b=JaKX6VbW949KD2C5QHV6m0Q89g+tc889kaBlPLk59VE9MYQLt/2nA9I5KX4/+4NLy0wipwwed8VepgwP24aq0a2TfKYeGCwm/d2ZXId/VaEV/EDlIBzZCSB3lG96uzzKgr/3F+ZNy1KOgkVME269REmxNuSx3vCuEJbTENd0Hxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525866; c=relaxed/simple; bh=YI2nIPo0A3KngY5evzYrIkY1E744Hf1NJcQQfZjlgBg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H0C5zrH7dMDZ/ymOuev6SY9LmgUG9kWiq4ndUKA45MLZpQby40vleSpgO1sQoKaohCI7CmrBnWhpwcjdcb2GCsI6SIz45ttqgAm5PzHPvix/kjaxjzUUcoH7XKJyztId2obMfIj+9+TIxgoSagWzc2L06k8GqCMZE6hGt2e2Kcc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QV3hZCv9; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QV3hZCv9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A94181F00A3D; Wed, 12 Aug 2026 09:10:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786525861; bh=JYHsvdmwB6LBVn/lo/Dc78wau1kWBwcyiNhyqF3yfF0=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=QV3hZCv9W9ozngTNEmqvCtO+vmwkc9M1p5x3jsbO8++rUEaOWrKrYpDc6jwH5xzwb s60pzkr8yoyEZGZy7dfHfgg6/pQQIN4FabmMuwHiZClGCorjLAkIteItZm0kpUfwkO OAO30S3xeMmZyAJ6QcMERVk648Wk/B/owUc6mh6jUSd4D9xUfu2dEdkqu6rULdLnW0 rNRCzHlmUnTfdnOt5Rx/VPhX1mvSFJsqwpGyJMkbLRM+mGjkDJ1arNDV4BCdaFu6/9 aqIQZzqhZqBQ1g7aE95Yg+o+whWEVkFWeQQySbU3hUuDugs6wm0Ot155SzmtxhgPb0 HJjILQdv/JRAw== From: Lorenzo Pieralisi Date: Wed, 12 Aug 2026 11:10:30 +0200 Subject: [PATCH 2/7] irqchip/gic-v5: Check for NULL LPI domain on domain teardown Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-gicv5-7-2-fixes-v1-2-3743e82c69a4@kernel.org> References: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> In-Reply-To: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> To: Marc Zyngier , Thomas Gleixner , Jonathan Cameron , "Rafael J. Wysocki" , Sascha Bischoff , Timothy Hayes Cc: Sascha Bischoff , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15.2 In gicv5_free_lpi_domain() the LPI domain being freed can be NULL. Check it and return before trying to free it if it is. Fixes: 0f0101325876 ("irqchip/gic-v5: Add GICv5 LPI/IPI support") Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier Link: https://sashiko.dev/#/message/20260810104747.E5CE71F000E9%40smtp.kern= el.org --- drivers/irqchip/irq-gic-v5.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index 6a99c541b559..a7fae93e993e 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -862,6 +862,9 @@ void __init gicv5_init_lpi_domain(void) =20 void __init gicv5_free_lpi_domain(void) { + if (!gicv5_global_data.lpi_domain) + return; + irq_domain_remove(gicv5_global_data.lpi_domain); gicv5_global_data.lpi_domain =3D NULL; } --=20 2.53.0 From nobody Tue Sep 29 04:43:03 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BBBC3AD52A for ; Wed, 12 Aug 2026 09:11:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525869; cv=none; b=JSiprE0OJmrdENnj7o4WGr2oJlzlRdIQ6DM695VxpVlXY8BmS5EPGDA1TCtUAAYuLwnRCx65ppiqb97H7bOf87GZiKxMSaR0edWMp2CcU1V2uOhtWTIh3ITFONIXe7SXxD4uJnE0LLHLposeacgoxksNfa39avOuqVwXdzrgavg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525869; c=relaxed/simple; bh=dhMpYSMQPlZbZXpmTaJdQAsXKoMLBhRLVprHAhQYlGE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YldasuEBkaI2W8DotumWRPMtu0SvKSONnKfRffAIqeLbXfJ/Avx8yQ9bM1WBsuA5mw6y5cHLeQnRlGZCJuJfId9nr5htrrG9ng9ruT3cqPn6iHQg5eJngE+rw74OYHCIDri4yigwC7osP25nQsU+tmde3fYSqxZ9UtKEgpy78SM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JkWFy7LQ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JkWFy7LQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 707FD1F000E9; Wed, 12 Aug 2026 09:11:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786525864; bh=xWgwrJeQwM87bLzVkHyeUPqK874plAM7uWk/D/Ey/lw=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=JkWFy7LQgQ7KbUGbSf4woplA1Kb4UiLrTb0KVmFLdnjfgEwCaDSm1OuzloOlXHhF3 8Wg0rOcbYhpM9UrL2ra26GUD5uS+3SZxOas2k8DkkjHlIu9SiugmxSk8Q1duRv9g4/ mBC8LCkm4v94YNzFs8HHF18/Uri93Aiix0B+osVQcbC+WaU/TY0VNaCl7JWGyBVz/h ImIEnczQYOs1JH8+Ys3XFkvqZ1tnkxUOMVCtIGdnhUU6XgItbtk+sTLEuXivt0kFn6 EIEiU1k0+HUzaoXQpaEk3Ali1XoI5qV+ucAwu0RqkVWvaZ3GRTgLDvdNaRSMH4BTru g47IZGzG5AcWA== From: Lorenzo Pieralisi Date: Wed, 12 Aug 2026 11:10:31 +0200 Subject: [PATCH 3/7] irqchip/gic-v5: Disable IRSes on probe failures Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-gicv5-7-2-fixes-v1-3-3743e82c69a4@kernel.org> References: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> In-Reply-To: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> To: Marc Zyngier , Thomas Gleixner , Jonathan Cameron , "Rafael J. Wysocki" , Sascha Bischoff , Timothy Hayes Cc: Sascha Bischoff , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15.2 GICv5 driver probe failures cause IRSes initialized by the kernel to be unmapped and their data structures to be destroyed but the current driver leaves the probed IRSes enabled, whereas they should be disabled. Disable IRSes on driver probe failures so that the IRSes are brought back to their quiescent HW state. Fixes: 5cb1b6dab2de ("irqchip/gic-v5: Add GICv5 IRS/SPI support") Fixes: 35866efa52fe ("irqchip/gic-v5: Add ACPI IRS probing") Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier Link: https://sashiko.dev/#/message/20260810104747.E5CE71F000E9%40smtp.kern= el.org --- drivers/irqchip/irq-gic-v5-irs.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-= irs.c index 0bd9ae9ae12e..9d25ce8bfd8c 100644 --- a/drivers/irqchip/irq-gic-v5-irs.c +++ b/drivers/irqchip/irq-gic-v5-irs.c @@ -488,6 +488,12 @@ static int gicv5_irs_wait_for_idle(struct gicv5_irs_ch= ip_data *irs_data) GICV5_IRS_CR0_IDLE, NULL); } =20 +static void __init gicv5_irs_disable(struct gicv5_irs_chip_data *irs_data) +{ + irs_writel_relaxed(irs_data, 0, GICV5_IRS_CR0); + gicv5_irs_wait_for_idle(irs_data); +} + void gicv5_irs_syncr(void) { struct gicv5_irs_chip_data *irs_data; @@ -786,6 +792,7 @@ static int __init gicv5_irs_of_init(struct device_node = *node) =20 out_iomem: gicv5_irs_clear_affinity(irs_data); + gicv5_irs_disable(irs_data); iounmap(irs_base); out_err: kfree(irs_data); @@ -801,6 +808,7 @@ void __init gicv5_irs_remove(void) =20 list_for_each_entry_safe(irs_data, tmp_data, &irs_nodes, entry) { gicv5_irs_clear_affinity(irs_data); + gicv5_irs_disable(irs_data); iounmap(irs_data->irs_base); list_del(&irs_data->entry); kfree(irs_data); @@ -968,6 +976,7 @@ static int __init gic_acpi_parse_madt_irs(union acpi_su= btable_headers *header, =20 out_map: gicv5_irs_clear_affinity(irs_data); + gicv5_irs_disable(irs_data); iounmap(irs_base); out_release: release_mem_region(r->start, resource_size(r)); --=20 2.53.0 From nobody Tue Sep 29 04:43:03 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E8A33161BF for ; Wed, 12 Aug 2026 09:11:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525871; cv=none; b=iDy4raMGZde7PJNPE3fGEfkTDl/cHB337Al+DVHV9dU0ICTlm5O6AC+ACFYOJeMU/DJ7LNHTlV434qZLi1elatc4X+76G+yjuQJDWD941jX+opfpXkO5OFmah16fEjGVia4lyLQNjkz9QWLiQdxWrE6OmPqTia0dF8rKl3KI6bk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525871; c=relaxed/simple; bh=w+sHkBI+4ZFb3yiZ50aUcTMxHShO3Vqh+g59t2qBg14=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uRMvapNrxMBNqpc7K4oLvAqnW2p/pTx7At7KfIPzhiUni0QupsXixghyjfTS6Uwa2npHGCLriGu2CsTotxLZcf6zBt8KT6lqqaQVmxTIKtCFk8+5UWzXezvZTphEgIjDvAWCwIQlOoJJ7RZS8TByRcSmkzrNmj67/cSKhUr4RFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dyUIywoe; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dyUIywoe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 359961F00A3A; Wed, 12 Aug 2026 09:11:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786525867; bh=45oTmQP1SXYA+aGwK18rImau8rHNkkL/xftpEJkoGYs=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=dyUIywoeERVqJLkAEmKO9UCxXJTHMtXsYjvPcCLllEEb8Ax0jdPzEMfgfFvRanYSl /AstqOMriUWtD38LIeqne12q8CGYFUO95ktGUjWIRcbho/PzHD8OqM8s/Zdw6pQMiF 1/gT+/7U3AbQUkxzeR9zLgbuMO7VHbXxQgY4jts2uRlFpvsEb2g1fr13YsOM7gDK2E DKIaQMk88Xo7j6XsNGkHZ0pqhn8nTkj2a9rWnR4IErwVEVjvqZ1tygtIgAyqwGKnVU 6cVK0QVJxvvUGBxqvEj7l2teFEpuhR/VWFeZIOhKcZKDuqfPaACTVHGzFkoZZ/3fw8 AG41qgvbie1Fw== From: Lorenzo Pieralisi Date: Wed, 12 Aug 2026 11:10:32 +0200 Subject: [PATCH 4/7] irqchip/gic-v5: Fix gicv5_init_common() error paths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-gicv5-7-2-fixes-v1-4-3743e82c69a4@kernel.org> References: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> In-Reply-To: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> To: Marc Zyngier , Thomas Gleixner , Jonathan Cameron , "Rafael J. Wysocki" , Sascha Bischoff , Timothy Hayes Cc: Sascha Bischoff , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15.2 Current code fails to disable interrupts on gicv5_starting_cpu() failure and to set the handle_arch_irq pointer to NULL if gicv5_irs_enable() fails. Update the respective error paths to fix them. Fixes: 7ec80fb3f025 ("irqchip/gic-v5: Add GICv5 PPI support") Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v5.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index a7fae93e993e..4f5d1eebb4fa 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -1174,7 +1174,7 @@ static int __init gicv5_init_common(struct fwnode_han= dle *parent_domain) =20 ret =3D gicv5_starting_cpu(smp_processor_id()); if (ret) - goto out_dom; + goto out_int; =20 ret =3D set_handle_irq(gicv5_handle_irq); if (ret) @@ -1182,16 +1182,17 @@ static int __init gicv5_init_common(struct fwnode_h= andle *parent_domain) =20 ret =3D gicv5_irs_enable(); if (ret) - goto out_int; + goto out_handle; =20 gicv5_smp_init(); =20 gicv5_irs_its_probe(); return 0; =20 +out_handle: + set_handle_irq(NULL); out_int: gicv5_cpu_disable_interrupts(); -out_dom: gicv5_free_domains(); return ret; } --=20 2.53.0 From nobody Tue Sep 29 04:43:03 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 227F93FCB1C for ; Wed, 12 Aug 2026 09:11:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525874; cv=none; b=HLpq/UXoIdWpIvvHWdGXM9/nMQE9AQ+Mf96q+UZ3remr9zaC7vu4q2p5vG0vizaxA/T8pzkMroRJOQIDUpn40rloA8feGU1koLKAhdxrIEytKN5VEnnxeaw9qBd6TqztRBLhp1Oq27bZJPoqipoUqQ6HoXjZVAxytKQIpu5zmg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525874; c=relaxed/simple; bh=83e0fF6IONgopZA9JbBvRFoaSsoH7VD4M3KPq6Vf9Dg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BWhi0SdhDV95izjo/w1nJXvimaft7sznMrm0198TEs5WpuwqrC39lyFLSRAZMaHQauYxWJJMEODvJXc0yUu03yp3Gnhc8PgLbUBs+VCmAVVs1r0ctNIy4zrR0rLdDTze4wc61o4hlsQ28tZs78FGEM9DUsTSUmYdugH+Lj7f5oU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bHWaS+pe; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bHWaS+pe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED0DE1F00A3D; Wed, 12 Aug 2026 09:11:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786525870; bh=6pTgz0DwXr00MMfnrP29fVFPwkvrVf5WWN8ziQhZvNw=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=bHWaS+pe+PGo4w02tTxnqsEfAcujAyPCKixf0RwpPhU+bRLQukzY/CXJ+9gvxaawG bucgvPGs+vNJkJ31JbdaZV6U6eQLoqe7/927QZ40A1udLxucbwWRb3Vx1a95w9Ve/b XGUJSkCoZyNmIAH72gjbSZ3hfkKqODX9GaMxJQ3DiOXEQGRl+NkSE/iNAIqzYEBqmd 0CkZUxdnd/UTmHDPFCzRxYvIBlgjuxzhTz58fhhIOiiDVjKdcNuIb2wGplmlQT83pj +WI1U7bnCdvW0UOmz+8Lyarg0l4D3pKUDi7c7LF00QRLxI36YjBfJ0TCA4rf1SyOke yApQA0gaU176w== From: Lorenzo Pieralisi Date: Wed, 12 Aug 2026 11:10:33 +0200 Subject: [PATCH 5/7] irqchip/gic-v5: Release IRS iomem region on driver init failure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-gicv5-7-2-fixes-v1-5-3743e82c69a4@kernel.org> References: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> In-Reply-To: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> To: Marc Zyngier , Thomas Gleixner , Jonathan Cameron , "Rafael J. Wysocki" , Sascha Bischoff , Timothy Hayes Cc: Sascha Bischoff , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15.2 In gicv5_irs_of_init(), an IRS is set-up using of_io_request_and_map() to request its memory region (corresponding to the configuration frame) and map the IRS configuration frame. On gicv5_irs_of_init() failure, the driver unmaps the IRS iomem region but does not release the requested memory region leaving it allocated in the iomem resource tree. Fix it by releasing the iomem region on gicv5_irs_of_init() probe failure. Likewise, on both OF and ACPI driver init failure, IRS iomem regions are requested but never released in gicv5_irs_remove(). Stash a copy of the IRS iomem region in a struct resource in struct gicv5_irs_chip_data and use it to release the requested region in gicv5_irs_remove() if the driver probe fails. Fixes: 5cb1b6dab2de ("irqchip/gic-v5: Add GICv5 IRS/SPI support") Fixes: 35866efa52fe ("irqchip/gic-v5: Add ACPI IRS probing") Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier Link: https://sashiko.dev/#/message/20260810104747.E5CE71F000E9%40smtp.kern= el.org --- drivers/irqchip/irq-gic-v5-irs.c | 10 ++++++++++ include/linux/irqchip/arm-gic-v5.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-= irs.c index 9d25ce8bfd8c..86da9f82a7b0 100644 --- a/drivers/irqchip/irq-gic-v5-irs.c +++ b/drivers/irqchip/irq-gic-v5-irs.c @@ -740,6 +740,7 @@ static int __init gicv5_irs_init(struct gicv5_irs_chip_= data *irs_data) static int __init gicv5_irs_of_init(struct device_node *node) { struct gicv5_irs_chip_data *irs_data; + struct resource res; void __iomem *irs_base; u8 iaffid_bits; u32 idr; @@ -757,6 +758,11 @@ static int __init gicv5_irs_of_init(struct device_node= *node) goto out_err; } =20 + if (of_address_to_resource(node, ret, &res)) { + ret =3D -EINVAL; + goto out_err; + } + irs_base =3D of_io_request_and_map(node, ret, of_node_full_name(node)); if (IS_ERR(irs_base)) { pr_err("%pOF: unable to map GICv5 IRS registers\n", node); @@ -765,6 +771,7 @@ static int __init gicv5_irs_of_init(struct device_node = *node) } =20 irs_data->fwnode =3D of_fwnode_handle(node); + irs_data->res =3D res; gicv5_irs_init_bases(irs_data, irs_base, of_property_read_bool(node, "dma= -noncoherent")); =20 idr =3D irs_readl_relaxed(irs_data, GICV5_IRS_IDR1); @@ -794,6 +801,7 @@ static int __init gicv5_irs_of_init(struct device_node = *node) gicv5_irs_clear_affinity(irs_data); gicv5_irs_disable(irs_data); iounmap(irs_base); + release_mem_region(res.start, resource_size(&res)); out_err: kfree(irs_data); return ret; @@ -810,6 +818,7 @@ void __init gicv5_irs_remove(void) gicv5_irs_clear_affinity(irs_data); gicv5_irs_disable(irs_data); iounmap(irs_data->irs_base); + release_mem_region(irs_data->res.start, resource_size(&irs_data->res)); list_del(&irs_data->entry); kfree(irs_data); } @@ -958,6 +967,7 @@ static int __init gic_acpi_parse_madt_irs(union acpi_su= btable_headers *header, } =20 gicv5_irs_init_bases(irs_data, irs_base, irs->flags & ACPI_MADT_IRS_NON_C= OHERENT); + irs_data->res =3D *r; =20 gicv5_irs_acpi_init_affinity(irs->irs_id, irs_data); =20 diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm= -gic-v5.h index f78787e654f4..2c2fb39f049c 100644 --- a/include/linux/irqchip/arm-gic-v5.h +++ b/include/linux/irqchip/arm-gic-v5.h @@ -6,6 +6,7 @@ #define __LINUX_IRQCHIP_ARM_GIC_V5_H =20 #include +#include =20 #include #include @@ -324,6 +325,7 @@ struct gicv5_irs_chip_data { struct list_head entry; struct fwnode_handle *fwnode; void __iomem *irs_base; + struct resource res; u32 flags; u32 spi_min; u32 spi_range; --=20 2.53.0 From nobody Tue Sep 29 04:43:03 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DD784028E8 for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kA+kaDCt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B0CF71F00A3F; Wed, 12 Aug 2026 09:11:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786525873; bh=MvazE23f8HbO9Hml0EoomjcFYwH5DF1NlDQc34IZPO4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=kA+kaDCt0+N1ZeV0yvog50Gvju6gxEOR1X100qjD0pJbFMFgqoOhlUT3d1Dw0X10v /c5xFBNLJ2PgPNCY47gd9YuE1h80SzFO+uctV14GEcVMWBzyosQdE1A32e9k6AJogX 2opdeT2UlzadgxAFlnb+pinDOMyawTSuZHFrL14Vm/mIqGtNCERsJuQ2aavdGc0sav 9ifFdyhLC4JRX/3Y4GDk4gPtVKefVdKpI6svl8SwbOwbXq+sELNnahr7eolqI36mpF C0G1LhUFRJ0K7l1ywSFmhntuTFwu4ibsVL2GXrkSD46RZ16/CNaY7Y3XvRsH8sPk0q fLY4V8I/wy5lw== From: Lorenzo Pieralisi Date: Wed, 12 Aug 2026 11:10:34 +0200 Subject: [PATCH 6/7] irqchip/gic-v5: Use logical cpu 0 irs_data for dynamic IST allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-gicv5-7-2-fixes-v1-6-3743e82c69a4@kernel.org> References: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> In-Reply-To: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> To: Marc Zyngier , Thomas Gleixner , Jonathan Cameron , "Rafael J. Wysocki" , Sascha Bischoff , Timothy Hayes Cc: Sascha Bischoff , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15.2 In set-ups with a 2-level IST, L1 table entries are created dynamically when LPIs are allocated. The L1 allocation and mapping, implemented in gicv5_irs_iste_alloc() is carried out in preemtible context and can be carried out on any IRS in the system. Current code indexes the per_cpu_irs_data per cpu array using smp_processor_id() to retrieve the IRS that is local to the core executing gicv5_irs_iste_alloc(). Since that's preemptible context, the core executing that function can change on preemption. Given that every IRS in the system is equivalent to each core, this is not really an issue in that even if the thread is preempted and resumed on a different cpu, the table allocation and mapping to an IRS would work seamlessly regardless. On the other hand, smp_processor_id() spits a legitimate splat on DEBUG_PREEMPT kernels when used in preemtible context and this should be fixed. Given that all IRSes are equivalent from a core perspective in terms of IST initialization, always choose as a policy the IRS local to logical cpu 0, preventing the smp_processor_id() splat. Fixes: 0f0101325876 ("irqchip/gic-v5: Add GICv5 LPI/IPI support") Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier Link: https://sashiko.dev/#/message/20260810104747.E5CE71F000E9%40smtp.kern= el.org --- drivers/irqchip/irq-gic-v5-irs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-= irs.c index 86da9f82a7b0..b3feb6340b59 100644 --- a/drivers/irqchip/irq-gic-v5-irs.c +++ b/drivers/irqchip/irq-gic-v5-irs.c @@ -199,7 +199,7 @@ int gicv5_irs_iste_alloc(const u32 lpi) if (!gicv5_global_data.ist.l2) return 0; =20 - irs_data =3D per_cpu(per_cpu_irs_data, smp_processor_id()); + irs_data =3D per_cpu(per_cpu_irs_data, 0); if (!irs_data) return -ENOENT; =20 --=20 2.53.0 From nobody Tue Sep 29 04:43:03 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB4E840099A for ; Wed, 12 Aug 2026 09:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525890; cv=none; b=jwmI8ODTsQMINdlXLvOR8IiiTjPgUprIbB9UkDOT5CYUHsp5R0Rz5WPkBy2ffwQawnKhMlqBj5TE23V6CkP9wFomRSAA2tHa70QnjFaRznQllgsJvObOj+QbtIurpwxqBw/CvxYkkd9bSSazzmrFht9lI1EUHaHzg8+GWiQjivE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786525890; c=relaxed/simple; bh=E/qDvxPW2xqlpDK95W6l0TiiI0/FRsBc2FRxnegSDvQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sWCP05OqQF+DljSR3eIPnXChEocLI0FS93YZDn5OtnqT4/Mo2wSSu+iK+bUrl0OhHCPeGKhNl44Qz2WlIGh8ARECKLv55vkqOFEKhmYzv15qLem31BJ8hyK8diQocwIdt1f7pTDyrzGsTV9fKkH7CnZ2UAKoLzjZ116NVxC0kCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KBBexxHg; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KBBexxHg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 749161F000E9; Wed, 12 Aug 2026 09:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786525875; bh=mEfxlBtxrbaLrgUXYDELE17F7DruhVXebdfJf8wUCzg=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=KBBexxHgL85faEuuhGNfw6RFVKkk8XhVW4qKW3pzmXauhlU8zfeVMPK3A9t5LUwNe qeknXexw2aVWHulQyOyQxOrtq04wYDhpcohRvgQpZW4c2jpJl6UFsr2qU3AB10XZPK nRDbQfyPkYtmEVoNdNRwVtDUEOy327JQsPV3BvTCeBIBQ1cAI6ghJ8NKlTdrO1yck2 VsM2MfvKFYnNmDpYkjUCfzSrLOD4OwjAQ29gdLyVz7l9HiQFtzExCoNVcyXX/L+aS2 Gsez98bpwXxVcu8o4F8GwdAT+FyTcM0f24RPduLLXgZDXZCxdWZCW6xQk77p7HIQOn g6O1bf97MJCNg== From: Lorenzo Pieralisi Date: Wed, 12 Aug 2026 11:10:35 +0200 Subject: [PATCH 7/7] irqchip/gic-v5: Defer default SPI and LPI IAFFID programming Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-gicv5-7-2-fixes-v1-7-3743e82c69a4@kernel.org> References: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> In-Reply-To: <20260812-gicv5-7-2-fixes-v1-0-3743e82c69a4@kernel.org> To: Marc Zyngier , Thomas Gleixner , Jonathan Cameron , "Rafael J. Wysocki" , Sascha Bischoff , Timothy Hayes Cc: Sascha Bischoff , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15.2 SPI and LPI interrupts do not have an architected default value for their IAFFID (interrupt affinity ID) - the property that determines an IRQ affinity. Current code awkwardly tries to set a default IAFFID value corresponding to the logical cpu executing the gicv5_hwirq_init() function at SPI/LPI allocation time. There are two issues with this approach: - gicv5_hwirq_init() is called in preemptible context and current code uses smp_processor_id() to check the logical cpu executing the function. Whilst that's harmless, it can spit a splat on DEBUG_PREEMPT kernels - Setting the default SPI/LPI IAFFID to the one belonging to the cpu executing the IRQ allocation is a completely arbitrary choice It is saner to remove the SPI/LPI IAFFID set-up in the SPI/LPI domain IRQ allocation code and flag SPI/LPI irqchips as IRQCHIP_AFFINITY_PRE_STARTUP so that the SPI/LPI affinity is initialized by IRQ core to a sane value before an IRQ is started up using the respective irq_chip irq_set_affinity() callback. Fixes: 5cb1b6dab2de ("irqchip/gic-v5: Add GICv5 IRS/SPI support") Fixes: 0f0101325876 ("irqchip/gic-v5: Add GICv5 LPI/IPI support") Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v5.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index 4f5d1eebb4fa..d6f1c0c8b747 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -87,25 +87,13 @@ static void gicv5_ppi_priority_init(void) =20 static void gicv5_hwirq_init(irq_hw_number_t hwirq, u8 priority, u8 hwirq_= type) { - u64 cdpri, cdaff; - u16 iaffid; - int ret; + u64 cdpri; =20 if (hwirq_type =3D=3D GICV5_HWIRQ_TYPE_LPI || hwirq_type =3D=3D GICV5_HWI= RQ_TYPE_SPI) { cdpri =3D FIELD_PREP(GICV5_GIC_CDPRI_PRIORITY_MASK, priority) | FIELD_PREP(GICV5_GIC_CDPRI_TYPE_MASK, hwirq_type) | FIELD_PREP(GICV5_GIC_CDPRI_ID_MASK, hwirq); gic_insn(cdpri, CDPRI); - - ret =3D gicv5_irs_cpu_to_iaffid(smp_processor_id(), &iaffid); - - if (WARN_ON_ONCE(ret)) - return; - - cdaff =3D FIELD_PREP(GICV5_GIC_CDAFF_IAFFID_MASK, iaffid) | - FIELD_PREP(GICV5_GIC_CDAFF_TYPE_MASK, hwirq_type) | - FIELD_PREP(GICV5_GIC_CDAFF_ID_MASK, hwirq); - gic_insn(cdaff, CDAFF); } } =20 @@ -548,6 +536,7 @@ static const struct irq_chip gicv5_spi_irq_chip =3D { .irq_get_irqchip_state =3D gicv5_spi_irq_get_irqchip_state, .irq_set_irqchip_state =3D gicv5_spi_irq_set_irqchip_state, .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_AFFINITY_PRE_STARTUP | IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, }; @@ -561,7 +550,8 @@ static const struct irq_chip gicv5_lpi_irq_chip =3D { .irq_retrigger =3D gicv5_lpi_irq_retrigger, .irq_get_irqchip_state =3D gicv5_lpi_irq_get_irqchip_state, .irq_set_irqchip_state =3D gicv5_lpi_irq_set_irqchip_state, - .flags =3D IRQCHIP_SKIP_SET_WAKE | + .flags =3D IRQCHIP_AFFINITY_PRE_STARTUP | + IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, }; =20 --=20 2.53.0