From nobody Tue Sep 29 05:35:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4B58386453; Wed, 12 Aug 2026 03:24:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786505046; cv=none; b=dQiIC8lG4+McSsSCM3ovsQKdylBKUc+Rblep7zVp49vf3o8IjLBupX26pLDLMj3w2TAN/TCtZv+MkUMvOe/qeFI+08Bl+6gC7Mouishu0wBlAgj2H85/iGZQhXfH6bXvAAD+Zte/cTBJ7QtDMdYyCkaoVJ4sc/7qO7FlPRgvDJo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786505046; c=relaxed/simple; bh=kgoSJfCQHW0+Dg62ei7S7n3mzCu8wyzu0Bm2onZRb/E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ec7qcGAvkZZ41lXl9iyTKQXaU65Syle6TF2ViYHAoAF0Qcz5/isSf+WmUhmSwM7xSvcar9tLWvZ1Quod4EIVE3ytIk8PizCedQ3vdAqibkaUXGssy4ctTj8tFSR++mE5HcUlDlppOetGoMmhVK+eKLK+9ACX8uxYg1Zrt7mGlws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=W88hO110; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="W88hO110" Received: by smtp.kernel.org (Postfix) with ESMTPS id 50BD1C2BCF5; Wed, 12 Aug 2026 03:24:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786505046; bh=kgoSJfCQHW0+Dg62ei7S7n3mzCu8wyzu0Bm2onZRb/E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=W88hO110mV2R9+DkHRAdklqrnq66sZ+V3IRCNl0nLkFcz2viWwfH6wdTbgq5Zyozm bMcutLiJLWk9vscKbGRMsZ2sOAz+SYaUWGr/Oi0cG5b73VXN6vdRxm6A71dI9LHSQP HKwl+AGJvisJ/LZBHGPQs3iff3t3Iq/txDGVxMuSZmx76HxzftUiWT3TbOcgRQx66K irmKwVbyFAANVt9ePIsez8JLZjjaD7g49VCu1fIme32TxZuS5kjhtoWQ5bak7btCWF m+B9BA5vmEawKM9mQ8EbHqorCHz5aEO1efZ2bUA/qmI/QMriDZGGBaYUOQXWfSkZlz OzDbAiapDIBEg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4026DC5B567; Wed, 12 Aug 2026 03:24:06 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Wed, 12 Aug 2026 11:24:04 +0800 Subject: [PATCH v7 1/3] dt-bindings: pwm: add support for AE350 PWM controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-andes-pwm-v7-1-a806da8185d1@andestech.com> References: <20260812-andes-pwm-v7-0-a806da8185d1@andestech.com> In-Reply-To: <20260812-andes-pwm-v7-0-a806da8185d1@andestech.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ben Zong-You Xie X-Mailer: b4 0.15-dev-09770 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786505045; l=2621; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=AlnVaPc7CqtbKonPziakNqedexQPh0xwvAlumniDgw0=; b=Uven+JtvvWPDfRJ8NXATFqn9rZkWQE3ntU9nH4nlQQnqgfENI06Kpb7/Ppbww/jh+smbFxwos b17UCUZVzWoAAJqDjK5H6vnO57Kl7+dtHezvg774//+PGiIA5j5/yw/ X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie The ATCPIT100 is a set of compact multi-function timers, which can be used as pulse width modulators (PWM) as well as simple timers. ATCPIT100 supports up to 4 PIT channels, and each PIT channel may be configured as a simple timer or PWM, or a combination of the timer and the PWM. This IP block is a core component of the Andes AE350 platform, which serves as a reference architecture for SoC designs. The QiLai SoC also integrates this controller. The binding introduces the following compatible strings: - "andestech,qilai-pwm": For the implementation integrated into the Andes QiLai SoC. - "andestech,ae350-pwm": As a fallback compatible string representing the base IP design used across the AE350 platform architecture. Reviewed-by: Rob Herring (Arm) Signed-off-by: Ben Zong-You Xie --- .../bindings/pwm/andestech,ae350-pwm.yaml | 61 ++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml= b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml new file mode 100644 index 000000000000..287f3c62965f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/andestech,ae350-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes PWM controller on AE350 platform + +description: + This controller has 4 channels and two clock sources. Each channel can + switch the clock source by programming the corresponding register. + +maintainers: + - Ben Zong-You Xie + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - andestech,qilai-pwm + - const: andestech,ae350-pwm + - const: andestech,ae350-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: APB bus clock + - description: External clock + + clock-names: + items: + - const: pclk + - const: extclk + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + pwm@f0400000 { + compatible =3D "andestech,ae350-pwm"; + reg =3D <0xf0400000 0x100000>; + #pwm-cells =3D <3>; + clocks =3D <&pclk>, <&extclk>; + clock-names =3D "pclk", "extclk"; + }; --=20 2.34.1 From nobody Tue Sep 29 05:35:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA5A7386541; Wed, 12 Aug 2026 03:24:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786505046; cv=none; b=Ti6jYifoZWHKpUACY5JUXZKpMYoqeVTQwKvM1V0NYa0Rj7XPSbV70Zd73LgdkBlWLCX8Upd7k1wSfuGTDpilGYRS7AYYkzaxuuueV6R+o6GhubbsIUqwfuMMgsGaFVBtnwxH2eOohadXKaKKDeTMfQYjA1KJrWex3MV4KV/PsZE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786505046; c=relaxed/simple; bh=ioU/hbCFG8yIaAeOGPNGcosT5GfrMc7nNnnmPPftIl4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A2VyCbkHix30IS/VUbQOPuvxzdDS5z0656FdjBEGPUytjef36Or6Wh88HzKwJaR/93TtqjM0MU8+HiKga4Lz6zo9K+MjZwv9riixQBgTTOU4lD5/gxDbUp2Z2O0lq69twNDSK/Suq/t4C7zLWWjFT2TZ0HRqztOIBWmjDVbnXCU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZhajeDUS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZhajeDUS" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5C9E6C2BCFA; Wed, 12 Aug 2026 03:24:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786505046; bh=ioU/hbCFG8yIaAeOGPNGcosT5GfrMc7nNnnmPPftIl4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZhajeDUS+D3VAlL4kP9qOXpYzywrtjDtZNZRnXXo/47WLYXnyNqy4IKlpOYIG614u ORCNzdI9LXcNuIq05oKdo9roAHoS6QmnAzGu2oFsV15G8NlnnOJag9elh0rZc0yvdc 0+9kS+KyyWuCRAslPyBc21bKEvpe084GyojJc16F/eI/mYJRnOHgLVwplrMeMBpLZe Xergyuh2qJZm3kqgAR+GcaN1V+g7y5w5Uhi4r8Nx4Ynm1+nd0ugEOskAkUpP9bLAQm PHueYBDgk5EV2BTJrNQgIVr9k9di3LbJO0YlA20fgfwL789I9gQKNC+NyVZYYNqBU1 2jXqjV5LcNQYA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E296C5AD5A; Wed, 12 Aug 2026 03:24:06 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Wed, 12 Aug 2026 11:24:05 +0800 Subject: [PATCH v7 2/3] pwm: add Andes PWM driver support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-andes-pwm-v7-2-a806da8185d1@andestech.com> References: <20260812-andes-pwm-v7-0-a806da8185d1@andestech.com> In-Reply-To: <20260812-andes-pwm-v7-0-a806da8185d1@andestech.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ben Zong-You Xie X-Mailer: b4 0.15-dev-09770 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786505045; l=14373; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=bu9Gtg3ujoOBVbkuR2qeKO7xGUSfCtQdq/4AdlyCYQQ=; b=TzApsJE0euDNJgioLoc/iYtGzc9kC+f+mmfAwYNnO3u6LLp7YMeiV0OnwXORXUxFMHYh7FDuT Ngj+EYgOW5VAka5o7oqGTOlOCKGHPp3Stbyx9rRJ4cj+xp0whs0WRQq X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie Add a driver for the PWM controller found in Andes AE350 platforms and QiLai SoCs. The Andes PWM controller features: - 4 independent channels. - Dual clock source support (APB clock and external clock) to provide a flexible range of frequencies. - Support for normal and inversed polarity. The driver implements the .apply() and .get_state() callbacks. Since the clock source of each channel can be selected by programming the register, clock selection logic is implemented to prioritize the external clock to maximize the supported period range, falling back to the APB clock for higher frequency requirements. Signed-off-by: Ben Zong-You Xie --- drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-andes.c | 365 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 378 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 729776086879..4b5d7d037284 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -73,6 +73,18 @@ config PWM_AIROHA To compile this driver as a module, choose M here: the module will be called pwm-airoha. =20 +config PWM_ANDES + tristate "Andes PWM support" + depends on ARCH_ANDES || COMPILE_TEST + depends on HAS_IOMEM && COMMON_CLK + select REGMAP_MMIO + help + Generic PWM framework driver for Andes platform, such as QiLai SoC + and AE350 platform. + + To compile this driver as a module, choose M here: the module + will be called pwm-andes. + config PWM_APPLE tristate "Apple SoC PWM support" depends on ARCH_APPLE || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5630a521a7cf..c92369ee251d 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PWM) +=3D core.o obj-$(CONFIG_PWM_AB8500) +=3D pwm-ab8500.o obj-$(CONFIG_PWM_ADP5585) +=3D pwm-adp5585.o obj-$(CONFIG_PWM_AIROHA) +=3D pwm-airoha.o +obj-$(CONFIG_PWM_ANDES) +=3D pwm-andes.o obj-$(CONFIG_PWM_APPLE) +=3D pwm-apple.o obj-$(CONFIG_PWM_ARGON_FAN_HAT) +=3D pwm-argon-fan-hat.o obj-$(CONFIG_PWM_ATMEL) +=3D pwm-atmel.o diff --git a/drivers/pwm/pwm-andes.c b/drivers/pwm/pwm-andes.c new file mode 100644 index 000000000000..8dafce7c467c --- /dev/null +++ b/drivers/pwm/pwm-andes.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Andes PWM, used in Andes AE350 platform and QiLai SoC + * + * Copyright (C) 2026 Andes Technology Corporation. + * + * Limitations: + * - When disabling a channel, the current period is not completed and the + * output is driven to the PARK level (low when ANDES_PWM_CH_CTRL_PARK is + * clear, high when it is set). + * - A change of clock source takes effect immediately, modifying the curr= ent + * output. Otherwise there is no glitch as the currently running period = is + * completed before the new settings take effect. + * - The hardware cannot run a 0% or 100% relative duty cycle; the driver + * emulates these by disabling the channel and parking the output at the + * constant level. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ANDES_PWM_CH_ENABLE 0x1C +#define ANDES_PWM_CH_ENABLE_PWM(ch) BIT(3 + (4 * (ch))) + +#define ANDES_PWM_CH_CTRL(ch) (0x20 + (0x10 * (ch))) +#define ANDES_PWM_CH_CTRL_MODE_PWM BIT(2) +#define ANDES_PWM_CH_CTRL_CLK BIT(3) +#define ANDES_PWM_CH_CTRL_PARK BIT(4) +#define ANDES_PWM_CH_CTRL_MASK GENMASK(4, 0) + +#define ANDES_PWM_CH_RELOAD(ch) (0x24 + (0x10 * (ch))) +#define ANDES_PWM_CH_RELOAD_HIGH GENMASK(31, 16) +#define ANDES_PWM_CH_RELOAD_LOW GENMASK(15, 0) + +#define ANDES_PWM_CH_COUNTER(ch) (0x28 + (0x10 * (ch))) + +#define ANDES_PWM_CH_MAX 4 +#define ANDES_PWM_CYCLE_MIN 1 +#define ANDES_PWM_CYCLE_MAX 0x10000 + +struct andes_pwm { + struct regmap *regmap; + struct clk *pclk; + struct clk *extclk; + unsigned int pclk_rate; + unsigned int extclk_rate; +}; + +static const struct regmap_config andes_pwm_regmap_config =3D { + .name =3D "andes_pwm", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .pad_bits =3D 0, + .max_register =3D ANDES_PWM_CH_COUNTER(ANDES_PWM_CH_MAX - 1), + .cache_type =3D REGCACHE_NONE, +}; + +static inline struct andes_pwm *andes_pwm_from_chip(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static int andes_pwm_enable(struct pwm_chip *chip, unsigned int channel, + bool enable) +{ + struct andes_pwm *ap =3D andes_pwm_from_chip(chip); + + return regmap_assign_bits(ap->regmap, ANDES_PWM_CH_ENABLE, + ANDES_PWM_CH_ENABLE_PWM(channel), enable); +} + +/* + * Hold the output at a constant level by parking the disabled channel. A + * disabled channel drives its output to the PARK level (low when @high is + * false, high when @high is true), which is used to emulate a 0% or 100% + * relative duty cycle. + */ +static int andes_pwm_park(struct pwm_chip *chip, unsigned int channel, + bool high) +{ + struct andes_pwm *ap =3D andes_pwm_from_chip(chip); + int ret; + + ret =3D regmap_assign_bits(ap->regmap, ANDES_PWM_CH_CTRL(channel), + ANDES_PWM_CH_CTRL_PARK, high); + if (ret) + return ret; + + return andes_pwm_enable(chip, channel, false); +} + +static int andes_pwm_config(struct pwm_chip *chip, unsigned int channel, + const struct pwm_state *state) +{ + struct andes_pwm *ap =3D andes_pwm_from_chip(chip); + unsigned int clk_rate =3D ap->extclk_rate; + unsigned int ctrl =3D ANDES_PWM_CH_CTRL_MODE_PWM; + bool use_pclk =3D false; + u64 high_cycles; + u64 low_cycles; + u64 period_cycles; + u64 duty_cycles; + u32 reload; + + /* + * Reload register for PWM mode: + * + * 31 : 16 15 : 0 + * PWM16_Hi | PWM16_Lo + * + * The high duration is (PWM16_Hi + 1) cycles and the low duration is + * (PWM16_Lo + 1) cycles, so each phase spans ANDES_PWM_CYCLE_MIN to + * ANDES_PWM_CYCLE_MAX cycles. The hardware period (their sum) can reach + * 2 * ANDES_PWM_CYCLE_MAX cycles, but the PWM core requires the period + * to be chosen from the requested period alone, independent of the duty + * cycle. That holds only while both phases stay within + * ANDES_PWM_CYCLE_MAX for every duty split, so the usable period is + * capped at ANDES_PWM_CYCLE_MAX + ANDES_PWM_CYCLE_MIN cycles. + * + * The controller has two clock sources, the APB clock and an external + * clock. Since the external clock frequency must be slower than the APB + * clock, it is tried first for its wider period range; the APB clock is + * used only when the external clock resolves fewer than two cycles (or + * is absent) and is itself usable. + */ + period_cycles =3D mul_u64_u64_div_u64(clk_rate, state->period, + NSEC_PER_SEC); + if (period_cycles < 2 * ANDES_PWM_CYCLE_MIN && ap->pclk_rate) { + use_pclk =3D true; + clk_rate =3D ap->pclk_rate; + period_cycles =3D mul_u64_u64_div_u64(clk_rate, state->period, + NSEC_PER_SEC); + } + + /* + * A single cycle is still usable: the duty cycle can then only be zero + * or one cycle, and both are emitted by parking the channel below. + */ + if (!period_cycles) + return -EINVAL; + + /* + * Round the period down to the largest value representable for every + * duty cycle, so the chosen period depends on the requested period + * alone. With both phases capped at ANDES_PWM_CYCLE_MAX, that bound is + * ANDES_PWM_CYCLE_MAX + ANDES_PWM_CYCLE_MIN cycles. + */ + period_cycles =3D min_t(u64, period_cycles, + ANDES_PWM_CYCLE_MAX + ANDES_PWM_CYCLE_MIN); + + /* The duty cycle cannot exceed the (possibly clamped) period. */ + duty_cycles =3D mul_u64_u64_div_u64(clk_rate, state->duty_cycle, + NSEC_PER_SEC); + duty_cycles =3D min_t(u64, duty_cycles, period_cycles); + + if (state->polarity =3D=3D PWM_POLARITY_INVERSED) { + low_cycles =3D duty_cycles; + high_cycles =3D period_cycles - low_cycles; + } else { + high_cycles =3D duty_cycles; + low_cycles =3D period_cycles - high_cycles; + } + + /* + * A zero-length phase means a 0% or 100% relative duty cycle, which the + * hardware cannot run. Emit the matching constant level by parking the + * channel: high_cycles =3D=3D 0 stays low, low_cycles =3D=3D 0 stays hig= h. + */ + if (!high_cycles) + return andes_pwm_park(chip, channel, false); + if (!low_cycles) + return andes_pwm_park(chip, channel, true); + + /* + * A change of clock source takes effect immediately, modifying the + * current output. Otherwise there is no glitch as the currently running + * period is completed before the new settings take effect. + */ + ctrl |=3D use_pclk ? ANDES_PWM_CH_CTRL_CLK : 0; + ctrl |=3D (state->polarity =3D=3D PWM_POLARITY_INVERSED) ? + ANDES_PWM_CH_CTRL_PARK : 0; + regmap_update_bits(ap->regmap, ANDES_PWM_CH_CTRL(channel), + ANDES_PWM_CH_CTRL_MASK, ctrl); + reload =3D FIELD_PREP(ANDES_PWM_CH_RELOAD_HIGH, high_cycles - 1) | + FIELD_PREP(ANDES_PWM_CH_RELOAD_LOW, low_cycles - 1); + regmap_write(ap->regmap, ANDES_PWM_CH_RELOAD(channel), reload); + + return andes_pwm_enable(chip, channel, true); +} + +static int andes_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + unsigned int channel =3D pwm->hwpwm; + + if (!state->enabled) { + if (pwm->state.enabled) + andes_pwm_enable(chip, channel, false); + + return 0; + } + + return andes_pwm_config(chip, channel, state); +} + +static int andes_pwm_get_state(struct pwm_chip *chip, struct pwm_device *p= wm, + struct pwm_state *state) +{ + struct andes_pwm *ap =3D andes_pwm_from_chip(chip); + unsigned int channel =3D pwm->hwpwm; + unsigned int ctrl; + unsigned int clk_rate; + unsigned int reload; + u64 high_cycles; + u64 low_cycles; + u64 duty_cycles; + + regmap_read(ap->regmap, ANDES_PWM_CH_CTRL(channel), &ctrl); + state->polarity =3D FIELD_GET(ANDES_PWM_CH_CTRL_PARK, ctrl) ? + PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + + clk_rate =3D FIELD_GET(ANDES_PWM_CH_CTRL_CLK, ctrl) ? ap->pclk_rate + : ap->extclk_rate; + if (!clk_rate) { + /* + * The selected clock source is unavailable, so the channel + * cannot be running; report it as disabled and avoid the + * division by zero below. + */ + state->enabled =3D false; + state->period =3D 0; + state->duty_cycle =3D 0; + + return 0; + } + + state->enabled =3D regmap_test_bits(ap->regmap, ANDES_PWM_CH_ENABLE, + ANDES_PWM_CH_ENABLE_PWM(channel)) > 0; + regmap_read(ap->regmap, ANDES_PWM_CH_RELOAD(channel), &reload); + high_cycles =3D FIELD_GET(ANDES_PWM_CH_RELOAD_HIGH, reload) + 1; + low_cycles =3D FIELD_GET(ANDES_PWM_CH_RELOAD_LOW, reload) + 1; + + if (state->polarity =3D=3D PWM_POLARITY_INVERSED) + duty_cycles =3D low_cycles; + else + duty_cycles =3D high_cycles; + + /* + * high_cycles and low_cycles are each at most ANDES_PWM_CYCLE_MAX + * (0x10000, 17 bits) and NSEC_PER_SEC is below 2^30, so the products + * below are safe from 64-bit overflow. + */ + state->duty_cycle =3D DIV_ROUND_UP_ULL(duty_cycles * NSEC_PER_SEC, + clk_rate); + state->period =3D DIV_ROUND_UP_ULL((high_cycles + low_cycles) * + NSEC_PER_SEC, clk_rate); + + return 0; +} + +static const struct pwm_ops andes_pwm_ops =3D { + .apply =3D andes_pwm_apply, + .get_state =3D andes_pwm_get_state, +}; + +static int andes_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pwm_chip *chip; + struct andes_pwm *ap; + void __iomem *reg_base; + unsigned long pclk_rate; + unsigned long extclk_rate; + int ret; + + chip =3D devm_pwmchip_alloc(dev, ANDES_PWM_CH_MAX, sizeof(*ap)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + ap =3D andes_pwm_from_chip(chip); + reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg_base)) + return dev_err_probe(dev, PTR_ERR(reg_base), + "Failed to map I/O space\n"); + + ap->pclk =3D devm_clk_get_enabled(dev, "pclk"); + if (IS_ERR(ap->pclk)) + return dev_err_probe(dev, PTR_ERR(ap->pclk), + "Failed to get APB clock\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, ap->pclk); + if (ret) + return dev_err_probe(dev, ret, + "Failed to lock APB clock rate\n"); + + ap->extclk =3D devm_clk_get_optional_enabled(dev, "extclk"); + if (IS_ERR(ap->extclk)) + return dev_err_probe(dev, PTR_ERR(ap->extclk), + "Failed to get external clock\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, ap->extclk); + if (ret) + return dev_err_probe(dev, ret, + "Failed to lock external clock rate\n"); + + /* + * If the clock rate is greater than 10^9, there may be an overflow when + * calculating the cycles in andes_pwm_config() + */ + pclk_rate =3D clk_get_rate(ap->pclk); + extclk_rate =3D clk_get_rate(ap->extclk); + + ap->pclk_rate =3D pclk_rate > NSEC_PER_SEC ? 0 : pclk_rate; + ap->extclk_rate =3D extclk_rate > NSEC_PER_SEC ? 0 : extclk_rate; + + if (!ap->pclk_rate && !ap->extclk_rate) + return dev_err_probe(dev, -EINVAL, + "No usable clock: pclk %lu Hz, extclk %lu Hz\n", + pclk_rate, extclk_rate); + + ap->regmap =3D devm_regmap_init_mmio(dev, reg_base, + &andes_pwm_regmap_config); + if (IS_ERR(ap->regmap)) + return dev_err_probe(dev, PTR_ERR(ap->regmap), + "Failed to initialize regmap\n"); + + chip->ops =3D &andes_pwm_ops; + chip->atomic =3D true; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret) + return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); + + return 0; +} + +static const struct of_device_id andes_pwm_of_match[] =3D { + { .compatible =3D "andestech,ae350-pwm" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, andes_pwm_of_match); + +static struct platform_driver andes_pwm_driver =3D { + .driver =3D { + .name =3D "andes_pwm", + .of_match_table =3D andes_pwm_of_match, + }, + .probe =3D andes_pwm_probe, +}; +module_platform_driver(andes_pwm_driver); + +MODULE_AUTHOR("Ben Zong-You Xie "); +MODULE_DESCRIPTION("Andes PWM driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Tue Sep 29 05:35:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC91E38735D; Wed, 12 Aug 2026 03:24:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786505046; cv=none; b=jO7f+0dCHqEL5FsrRxwFGaO5QV+HtE1HO2GRRNHUPqq8nsjOQTIo3YYA8X5g8naZ1oVVGCuD59+1Iw2bjHH3Q2Oqus/wTjmOhbgNvkFUG7fUkzNr9X0r0pqo+pEDKc2M/BMikMFyfu9ZLGbCQkra2/SbDu9u2PKJNeyKeTAua0M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786505046; c=relaxed/simple; bh=koF5tRe0d+hPSJInPiYXuK5p+J7czy7mQN0ECKniOcc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LGwIMzwlVEmhxoOvJ73gXQ2BmfoGChtLfUdBVoW3f+gf2aQ6GZxuoVo8d96knRpK8Fg65HD8vWEk1bEsJsCS9X7iYB1coHMSxdK5jh5RjnZGpI0G2W5b0aQ7x+jhhPIg7eOIfk3Pv0fDRHsrtamdDFQCnZYU2vGaWR5aVnGwTgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lGGQrXXL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lGGQrXXL" Received: by smtp.kernel.org (Postfix) with ESMTPS id 85537C2BD05; Wed, 12 Aug 2026 03:24:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786505046; bh=koF5tRe0d+hPSJInPiYXuK5p+J7czy7mQN0ECKniOcc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lGGQrXXLzoynzhJwH+mhg08cDon7OIrrks1SeMy3DrrwfXJZ5EJLmWpKwwn1nf22E mYqboeBIFZsbGTnSlloAN+ve3G7HktdMSZfwfLAlttVY9Vd53wbtzDIcvNeHfYtiyT nruNsEHemsr7exySzzLN7b+R8ZTv41gBsW2eIa/mdHHYcszZ+USW7NB3ybYXC3fLZG kPKRjXjFJh+LZDgta+eIfjFLfZ0hCCa2YVGHcjAoM+eD7W0lvYo8gqqBR2MWBPoEj1 Mh6I09OwN8Ss6dbDNHWpRGnOn5yrJGweUSdH1sUXAmyMpvqBvH0CCkhaUQ5LBX8FRN cTrvoTR0662Wg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73F54C5B567; Wed, 12 Aug 2026 03:24:06 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Wed, 12 Aug 2026 11:24:06 +0800 Subject: [PATCH v7 3/3] MAINTAINERS: add an entry for Andes PWM driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260812-andes-pwm-v7-3-a806da8185d1@andestech.com> References: <20260812-andes-pwm-v7-0-a806da8185d1@andestech.com> In-Reply-To: <20260812-andes-pwm-v7-0-a806da8185d1@andestech.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ben Zong-You Xie X-Mailer: b4 0.15-dev-09770 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786505045; l=764; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=gjO6IZe5Ik4Z5BEicWOc/F1VbekVfs+WHY+c4FTLRSM=; b=wJ+LQWuuwY7kOate1QP4hWImy2xdHaluN1e2FeIkIeGyTo1DYF4fQSmp958EGGWqU5yKyH1wT hmIRtz+XJzSD8RWJ+n0pzIt2RqDDbUoq0qu147d40XqqpQlj8ZfPu4P X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie Add an entry for the Andes PWM driver to the MAINTAINERS file. Signed-off-by: Ben Zong-You Xie --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 15011f5752a9..dcf16c40a99e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1938,6 +1938,12 @@ S: Supported F: Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml F: drivers/watchdog/atcwdt200_wdt.c =20 +ANDES PWM DRIVER +M: Ben Zong-You Xie +S: Supported +F: Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml +F: drivers/pwm/pwm-andes.c + ANDROID DRIVERS M: Greg Kroah-Hartman M: Arve Hj=C3=B8nnev=C3=A5g --=20 2.34.1