From nobody Tue Sep 29 06:06:38 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D59B942C51D; Tue, 11 Aug 2026 23:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786491607; cv=none; b=MrMuO5tKCwOPnGVhU0tWaADDyUcjUxKPCJm1XTNx/2HNBM/qV2Tmfb6dw7s8OULTvr7KKTlmHvN1d4wsdIABulJeoN5H63ZTTTgrvdpNG0xQPSjHdhu0asdhSG4Bw5JPlY3hTe/V9CPwSpVScWfOG/r+xu3m9I4tSiZewZbrvGc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786491607; c=relaxed/simple; bh=3wLxYcxDRIIarwWq35LeGf/oxOrii9Ju1xrb9oIUx1g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GEB5Th9J6cHbguIVAPIyHDuO4pzCoNBaQoB5YbZ7z/1LEpTfEnoKqrJ1m8ZLCjfdNvUtiLaoWtYvCPzYmW/7y3MT8WQGuSp/w/pjL5Q5qCptps260DxAhO2cNTfJHaxr8tuumNCoo/eKVTn9G/BtjXijD9FCoz5EVdzH/hIFVdk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HQqkS4b9; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HQqkS4b9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC4EF1F00A3A; Tue, 11 Aug 2026 23:40:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786491605; bh=8IGmQrLEypuzyWOq4KvdNpRNse0H9fRot9r9BRdJXbA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HQqkS4b9lPTAJAUHUGeX38qcNhbO0B6wFZYzvQu1DER8F8WM/eqPAVOUCDdCNF3hw dSGERX/etz8Bus8D6M9gTqlUimwG2Ny2hk9q0C4cluIUzWEiQieYa+v7O3vSLnep2m pj4pChAPnO4pUbJWuMF3J/mPzpQR3DYdf7l91HleCNh7cEVesUy2mHKxxwrEzy0tEr 3JABqtPvJ49bCNXgbDZVjVYFUYKY+eSd6ra9mPhnu2f2qSxTGQ5ZF7kJUmWp2aFmNY 3my/Ze7YqXWOc3kp2/D/btB8dGIilmNdF+btkmsFIFtXN4fqMIxiaJ73Z3cmXfqBP0 bVRZFHSKk0jdw== From: Danilo Krummrich To: bhelgaas@google.com, dakr@kernel.org, kwilczynski@kernel.org, aliceryhl@google.com, daniel.almeida@collabora.com, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu, tamird@kernel.org, acourbot@nvidia.com, work@onurozkan.dev, jhubbard@nvidia.com, ttabi@nvidia.com, apopple@nvidia.com, ecourtney@nvidia.com, shashanks@nvidia.com, zhiw@nvidia.com Cc: driver-core@lists.linux.dev, linux-pci@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] rust: pci: convert IrqVectorRegistration to a lifetime-managed owning type Date: Wed, 12 Aug 2026 01:39:32 +0200 Message-ID: <20260811233952.3000968-2-dakr@kernel.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260811233952.3000968-1-dakr@kernel.org> References: <20260811233952.3000968-1-dakr@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert IrqVectorRegistration from a devres-managed internal type to a lifetime-annotated type that owns the PCI interrupt vector allocation. Dropping it frees the vectors. IrqVector gains a reference to the IrqVectorRegistration it was derived from. Since vector() borrows the registration, the compiler prevents the allocation from being dropped while any IrqVector (and hence any irq::Registration built from it) is still live. alloc_irq_vectors() returns IrqVectorRegistration<'_> directly, giving drivers explicit control over the allocation lifetime, which is needed by net and block drivers that re-allocate vectors at runtime, e.g. during queue reconfiguration or device recovery. Signed-off-by: Danilo Krummrich Tested-by: John Hubbard --- rust/kernel/pci.rs | 3 +- rust/kernel/pci/irq.rs | 127 ++++++++++++++++++++++------------------- 2 files changed, 69 insertions(+), 61 deletions(-) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index c6417af2bb17..2757a0cc0f11 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -51,7 +51,8 @@ pub use self::irq::{ IrqType, IrqTypes, - IrqVector, // + IrqVector, + IrqVectorRegistration, // }; =20 /// An adapter for the registration of PCI drivers. diff --git a/rust/kernel/pci/irq.rs b/rust/kernel/pci/irq.rs index fea484dcf9cf..8e0651587829 100644 --- a/rust/kernel/pci/irq.rs +++ b/rust/kernel/pci/irq.rs @@ -7,17 +7,14 @@ bindings, device, device::Bound, - devres, error::to_result, irq::{ self, IrqRequest, // }, - prelude::*, - str::CStr, - sync::aref::ARef, // + prelude::*, // }; -use core::ops::RangeInclusive; +use core::num::NonZero; =20 /// IRQ type flags for PCI interrupt allocation. #[derive(Debug, Clone, Copy)] @@ -78,6 +75,7 @@ const fn as_raw(self) -> u32 { #[derive(Clone, Copy)] pub struct IrqVector<'a> { dev: &'a Device, + reg: &'a IrqVectorRegistration<'a>, index: u32, } =20 @@ -86,87 +84,81 @@ impl<'a> IrqVector<'a> { /// /// # Safety /// - /// - `index` must be a valid IRQ vector index for `dev`. - /// - `dev` must point to a [`Device`] that has successfully allocated= IRQ vectors. - unsafe fn new(dev: &'a Device, index: u32) -> Self { - Self { dev, index } + /// - `index` must be a valid IRQ vector index for `reg`. + /// - `dev` must be the device `reg` was allocated from. + #[inline] + unsafe fn new(dev: &'a Device, reg: &'a IrqVectorRegistration<'= a>, index: u32) -> Self { + Self { dev, reg, index } } =20 /// Returns the raw vector index. fn index(&self) -> u32 { self.index } + + /// Returns the [`IrqVectorRegistration`] this vector was derived from. + pub fn vectors(&self) -> &'a IrqVectorRegistration<'a> { + self.reg + } } =20 impl<'a> TryInto> for IrqVector<'a> { type Error =3D Error; =20 fn try_into(self) -> Result> { - // SAFETY: `self.as_raw` returns a valid pointer to a `struct pci_= dev`. + // SAFETY: `self.dev.as_raw()` returns a valid pointer to a `struc= t pci_dev`. let irq =3D unsafe { bindings::pci_irq_vector(self.dev.as_raw(), s= elf.index()) }; if irq < 0 { return Err(crate::error::Error::from_errno(irq)); } - // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `self.= dev`. Ok(unsafe { IrqRequest::new(self.dev.as_ref(), irq as u32) }) } } =20 -/// Represents an IRQ vector allocation for a PCI device. +/// An allocation of PCI interrupt vectors for a device. /// -/// This type ensures that IRQ vectors are properly allocated and freed by -/// tying the allocation to the lifetime of this registration object. +/// This type owns the vector allocation; dropping it frees the vectors. I= RQ handlers borrow from +/// this registration and must be dropped before it is. /// /// # Invariants /// -/// The [`Device`] has successfully allocated IRQ vectors. -struct IrqVectorRegistration { - dev: ARef, +/// `dev` has an allocation of `count` interrupt vectors. +pub struct IrqVectorRegistration<'a> { + dev: &'a Device, + count: NonZero, } =20 -impl IrqVectorRegistration { - /// Allocate and register IRQ vectors for the given PCI device. +impl<'a> IrqVectorRegistration<'a> { + /// Returns the number of allocated vectors. /// - /// Allocates IRQ vectors and registers them with devres for automatic= cleanup. - /// Returns a range of valid IRQ vectors. - fn register<'a>( - dev: &'a Device, - min_vecs: u32, - max_vecs: u32, - irq_types: IrqTypes, - ) -> Result>> { - // SAFETY: - // - `dev.as_raw()` is guaranteed to be a valid pointer to a `stru= ct pci_dev` - // by the type invariant of `Device`. - // - `pci_alloc_irq_vectors` internally validates all other parame= ters - // and returns error codes. - let ret =3D unsafe { - bindings::pci_alloc_irq_vectors(dev.as_raw(), min_vecs, max_ve= cs, irq_types.as_raw()) - }; - - to_result(ret)?; - let count =3D ret as u32; - - // SAFETY: - // - `pci_alloc_irq_vectors` returns the number of allocated vecto= rs on success. - // - Vectors are 0-based, so valid indices are [0, count-1]. - // - `pci_alloc_irq_vectors` guarantees `count >=3D min_vecs > 0`,= so both `0` and - // `count - 1` are valid IRQ vector indices for `dev`. - let range =3D unsafe { IrqVector::new(dev, 0)..=3DIrqVector::new(d= ev, count - 1) }; + /// This is at least the `min_vecs` that [`Device::alloc_irq_vectors`]= was asked for. + #[inline] + pub fn vector_count(&self) -> usize { + self.count.get() + } =20 - // INVARIANT: The IRQ vector allocation for `dev` above was succes= sful. - let irq_vecs =3D Self { dev: dev.into() }; - devres::register(dev.as_ref(), irq_vecs, GFP_KERNEL)?; + /// Returns the [`IrqVector`] at `index`. + /// + /// The returned [`IrqVector`] borrows from this registration, ensurin= g the vector allocation + /// remains live while any handler is registered on it. + #[inline] + pub fn vector(&self, index: usize) -> Result> { + if index >=3D self.count.get() { + return Err(EINVAL); + } =20 - Ok(range) + // SAFETY: `index` is within bounds of this registration's allocat= ion, and `self.dev` is + // the device it was allocated from. + Ok(unsafe { IrqVector::new(self.dev, self, index as u32) }) } } =20 -impl Drop for IrqVectorRegistration { +impl Drop for IrqVectorRegistration<'_> { + #[inline] fn drop(&mut self) { - // SAFETY: - // - By the type invariant, `self.dev.as_raw()` is a valid pointer= to a `struct pci_dev`. - // - `self.dev` has successfully allocated IRQ vectors. + // SAFETY: By the type invariant, `self.dev.as_raw()` is a valid p= ointer to a + // `struct pci_dev` that has successfully allocated IRQ vectors. unsafe { bindings::pci_free_irq_vectors(self.dev.as_raw()) }; } } @@ -214,15 +206,16 @@ pub unsafe fn request_threaded_irq<'a, T: crate::irq:= :ThreadedHandler + 'a>( }) } =20 - /// Allocate IRQ vectors for this PCI device with automatic cleanup. + /// Allocate IRQ vectors for this PCI device. /// /// Allocates between `min_vecs` and `max_vecs` interrupt vectors for = the device. /// The allocation will use MSI-X, MSI, or INTx interrupts based on th= e `irq_types` /// parameter and hardware capabilities. When multiple types are speci= fied, the kernel /// will try them in order of preference: MSI-X first, then MSI, then = INTx interrupts. /// - /// The allocated vectors are automatically freed when the device is u= nbound, using the - /// devres (device resource management) system. + /// The allocated vectors are freed when the returned [`IrqVectorRegis= tration`] is dropped. + /// IRQ handlers registered via [`Self::request_irq`] or [`Self::reque= st_threaded_irq`] + /// borrow from the registration, so the compiler ensures they are fre= ed first. /// /// # Arguments /// @@ -232,8 +225,8 @@ pub unsafe fn request_threaded_irq<'a, T: crate::irq::T= hreadedHandler + 'a>( /// /// # Returns /// - /// Returns a range of IRQ vectors that were successfully allocated, o= r an error if the - /// allocation fails or cannot meet the minimum requirement. + /// Returns the IRQ vector registration, or an error if `min_vecs` vec= tors cannot be + /// allocated. /// /// # Examples /// @@ -256,7 +249,21 @@ pub fn alloc_irq_vectors( min_vecs: u32, max_vecs: u32, irq_types: IrqTypes, - ) -> Result>> { - IrqVectorRegistration::register(self, min_vecs, max_vecs, irq_type= s) + ) -> Result> { + // SAFETY: + // - `self.as_raw()` is guaranteed to be a valid pointer to a `str= uct pci_dev` + // by the type invariant of `Device`. + // - `pci_alloc_irq_vectors` internally validates all other parame= ters + // and returns error codes. + let ret =3D unsafe { + bindings::pci_alloc_irq_vectors(self.as_raw(), min_vecs, max_v= ecs, irq_types.as_raw()) + }; + + to_result(ret)?; + + let count =3D NonZero::new(ret as usize).ok_or(EINVAL)?; + + // INVARIANT: `pci_alloc_irq_vectors()` allocated `count` vectors = for `self`. + Ok(IrqVectorRegistration { dev: self, count }) } } --=20 2.55.0 From nobody Tue Sep 29 06:06:38 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB0D743B6F3; Tue, 11 Aug 2026 23:40:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786491612; cv=none; b=dpccP/mY9kBZcEBIFM6+S0Pd2gjWm+Ug6pytTri2oNvOCuL0oCvuA6P7xwgU58Bbhp7h83eCkAuUcgght5hCArTWSQPLBjy8Bi8lE1HVAiN/lM+YH23T/E7TAxplqiXqoJ6tDChpVlkhpupbuOZ+REKyOT4DFYfNx7I0ea419hU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786491612; c=relaxed/simple; bh=LuIZpXt3LYtHQWbNbsIpJMzmdp5Su9S36JY4bvbi1QA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CyuVbFk3UqbSWye6vAPCuoeGwxsyWIv+JItCh4q02YqDpX9hVpjQU9ELAEj1RIy7ahZ1IePjOEv/8BGkkdnUGwseFbKqtL6woepc0+i1qgVtD/K/N//5IzkggXlE+IhvXEupjIgxxwW0a64DlswR54fwTtdqGeftiK5PEtaaJdQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nRttyq1I; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nRttyq1I" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E15771F000E9; Tue, 11 Aug 2026 23:40:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786491610; bh=xLWO9FzBt+MuDdgpLZKkGWMPfByZxM3sqppm2elb0es=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=nRttyq1I08OtbtvaJg1f33Riq5t2uHo7oLqV1NeqZm8GsYOCcZr5d95d6VVW+u0u1 qk4MLDnznp8/e1/flxa6E1eXMeB6CBBfMALWN4/FWt63cKdEzrOJEtwhWeLp31oIJP 18/4y2x9TLmoAMVRh3cv1pGnBaGGLUGn5BFAgh+nTHwVo1ypBqKrv9Tf1oirJZNCYF KKFpuiBbadFvH4aod+yN1VlQk1iejEreimYoFinegtpfchuh6bwjuWJpZ6BJwTH/LK s9Apz5EhXlJ+LPA36ZYf5lmKvAhuotZEAG7wTlBXPia3i5fe+Is0LdXGKjE5YUBFcP RX+3+lXiIKf/Q== From: Danilo Krummrich To: bhelgaas@google.com, dakr@kernel.org, kwilczynski@kernel.org, aliceryhl@google.com, daniel.almeida@collabora.com, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu, tamird@kernel.org, acourbot@nvidia.com, work@onurozkan.dev, jhubbard@nvidia.com, ttabi@nvidia.com, apopple@nvidia.com, ecourtney@nvidia.com, shashanks@nvidia.com, zhiw@nvidia.com Cc: driver-core@lists.linux.dev, linux-pci@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] rust: pci: resolve IRQ in vector() and embed IrqRequest in IrqVector Date: Wed, 12 Aug 2026 01:39:33 +0200 Message-ID: <20260811233952.3000968-3-dakr@kernel.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260811233952.3000968-1-dakr@kernel.org> References: <20260811233952.3000968-1-dakr@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the pci_irq_vector() call from the TryInto impl into IrqVectorRegistration::vector(), so the IRQ number is resolved eagerly. IrqVector now embeds the resolved IrqRequest and the vector index. The conversion to IrqRequest is infallible (From instead of TryInto), which removes the need for pin_init_scope in request_irq/request_threaded_irq. Inspired-by: John Hubbard Link: https://lore.kernel.org/all/20260808031120.363869-3-jhubbard@nvidia.c= om/ Signed-off-by: Danilo Krummrich Tested-by: John Hubbard --- rust/kernel/pci/irq.rs | 77 ++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 40 deletions(-) diff --git a/rust/kernel/pci/irq.rs b/rust/kernel/pci/irq.rs index 8e0651587829..305701440114 100644 --- a/rust/kernel/pci/irq.rs +++ b/rust/kernel/pci/irq.rs @@ -68,31 +68,39 @@ const fn as_raw(self) -> u32 { } } =20 -/// Represents an allocated IRQ vector for a specific PCI device. +/// A resolved IRQ vector from a PCI interrupt vector allocation. /// -/// This type ties an IRQ vector to the device it was allocated for, -/// ensuring the vector is only used with the correct device. -#[derive(Clone, Copy)] +/// Created by [`IrqVectorRegistration::vector`] and consumed by [`Device:= :request_irq`] or +/// [`Device::request_threaded_irq`]. Borrows the [`IrqVectorRegistration`= ] it was derived from, +/// so the allocation stays live until the handler is freed. pub struct IrqVector<'a> { - dev: &'a Device, + request: IrqRequest<'a>, reg: &'a IrqVectorRegistration<'a>, - index: u32, + index: usize, } =20 impl<'a> IrqVector<'a> { - /// Creates a new [`IrqVector`] for the given device and index. + /// Creates a new [`IrqVector`] with an already resolved [`IrqRequest`= ]. /// /// # Safety /// - /// - `index` must be a valid IRQ vector index for `reg`. - /// - `dev` must be the device `reg` was allocated from. + /// `request` must have been resolved from `reg`. #[inline] - unsafe fn new(dev: &'a Device, reg: &'a IrqVectorRegistration<'= a>, index: u32) -> Self { - Self { dev, reg, index } + unsafe fn new( + request: IrqRequest<'a>, + reg: &'a IrqVectorRegistration<'a>, + index: usize, + ) -> Self { + Self { + request, + reg, + index, + } } =20 - /// Returns the raw vector index. - fn index(&self) -> u32 { + /// Returns the vector index within the allocation. + #[inline] + pub fn index(&self) -> usize { self.index } =20 @@ -102,17 +110,10 @@ pub fn vectors(&self) -> &'a IrqVectorRegistration<'a= > { } } =20 -impl<'a> TryInto> for IrqVector<'a> { - type Error =3D Error; - - fn try_into(self) -> Result> { - // SAFETY: `self.dev.as_raw()` returns a valid pointer to a `struc= t pci_dev`. - let irq =3D unsafe { bindings::pci_irq_vector(self.dev.as_raw(), s= elf.index()) }; - if irq < 0 { - return Err(crate::error::Error::from_errno(irq)); - } - // SAFETY: `irq` is guaranteed to be a valid IRQ number for `self.= dev`. - Ok(unsafe { IrqRequest::new(self.dev.as_ref(), irq as u32) }) +impl<'a> From> for IrqRequest<'a> { + #[inline] + fn from(vector: IrqVector<'a>) -> Self { + vector.request } } =20 @@ -142,15 +143,19 @@ pub fn vector_count(&self) -> usize { /// /// The returned [`IrqVector`] borrows from this registration, ensurin= g the vector allocation /// remains live while any handler is registered on it. - #[inline] pub fn vector(&self, index: usize) -> Result> { if index >=3D self.count.get() { return Err(EINVAL); } =20 - // SAFETY: `index` is within bounds of this registration's allocat= ion, and `self.dev` is - // the device it was allocated from. - Ok(unsafe { IrqVector::new(self.dev, self, index as u32) }) + // SAFETY: `self.dev.as_raw()` is a valid pointer to a `struct pci= _dev`. + let irq =3D unsafe { bindings::pci_irq_vector(self.dev.as_raw(), i= ndex as u32) }; + if irq < 0 { + return Err(Error::from_errno(irq)); + } + + // SAFETY: `irq` is a valid IRQ number for `self.dev`, resolved fr= om this registration. + Ok(unsafe { IrqVector::new(IrqRequest::new(self.dev.as_ref(), irq = as u32), self, index) }) } } =20 @@ -177,12 +182,8 @@ pub unsafe fn request_irq<'a, T: crate::irq::Handler += 'a>( name: &'static CStr, handler: impl PinInit + 'a, ) -> impl PinInit, Error> + 'a { - pin_init::pin_init_scope(move || { - let request =3D vector.try_into()?; - - // SAFETY: Caller guarantees the Registration will not be leak= ed. - Ok(unsafe { irq::Registration::::new(request, flags, name, = handler) }) - }) + // SAFETY: Caller guarantees the Registration will not be leaked. + unsafe { irq::Registration::::new(vector.into(), flags, name, h= andler) } } =20 /// Returns a [`kernel::irq::ThreadedRegistration`] for the given IRQ = vector. @@ -198,12 +199,8 @@ pub unsafe fn request_threaded_irq<'a, T: crate::irq::= ThreadedHandler + 'a>( name: &'static CStr, handler: impl PinInit + 'a, ) -> impl PinInit, Error> + 'a { - pin_init::pin_init_scope(move || { - let request =3D vector.try_into()?; - - // SAFETY: Caller guarantees the Registration will not be leak= ed. - Ok(unsafe { irq::ThreadedRegistration::::new(request, flags= , name, handler) }) - }) + // SAFETY: Caller guarantees the Registration will not be leaked. + unsafe { irq::ThreadedRegistration::::new(vector.into(), flags,= name, handler) } } =20 /// Allocate IRQ vectors for this PCI device. --=20 2.55.0 From nobody Tue Sep 29 06:06:38 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C944E438499; Tue, 11 Aug 2026 23:40:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786491617; cv=none; b=cCkyLEIyrZ6M9yABV/0GhoVnmG9eIZIdy8RGJ/BRoGASYc4jb320HJ9hIp1cX50SKnKEbW9S3f5a3nPuKID9X9Lsm6O1PMAWGMuoE+qB8qWJ8WdI/8qfChIA/QFkcsTf5HQLHSsIo7maL1HAs4IG3rA7VisYi69nv6qDNyZ7P3Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786491617; c=relaxed/simple; bh=4/hxo/KFhuiiLAHDJGcEHJ8QKsRDXYCtObffmXj2gBc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OHvYyYGvWccgzjJ0rHDq2XrEMric7uQZyd4YlJiBvah7HKaGqBm7f02NOSs6Y/+LwzbdiryCe+HHdx0fw0WaS7NjZNUbR5NydyaRGGIGvM4lzAjz+hyiTIOaw9wgWIhmlyN0/qSQwhVso/p65uE0VZunqQm8fDtuQ3jd8EudIZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l4C5op87; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l4C5op87" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D0DFB1F00A3A; Tue, 11 Aug 2026 23:40:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786491615; bh=Et6jvRde03qX5l8BhSg3TWpD9qWGcYu/EHrQQaM36Zs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=l4C5op87uxYqeKnYwobAmbMOGGPHnCNN0qH7haoRHUm+U6Fvs+lPW7ozeivc8it8Y 8wETeI2x+QNvmC1cz3B/5qsZKIOseop85Rrz8NGIPjOP4pBw81pGaMt9XwAiKNNtxW UaWmQyqa4IWdXwBEeqBo6VuxQ7vq7BeEFhlNlHsX+yJI2j+bzszscJyFr+sZ1emB+H LS2sR7q6MmIsVUytxipvfMZFDeLR4qBGjTnjPDjimzI/jurRsFpXaBIU+gruBso6QU MPO7iBRTiP9m5ilo5K4q7e1pawmQysHMEZ/MNbp9CS0xMJimqD4MS2A9FWCGwMwRy3 UmlKftAy9NDfg== From: Danilo Krummrich To: bhelgaas@google.com, dakr@kernel.org, kwilczynski@kernel.org, aliceryhl@google.com, daniel.almeida@collabora.com, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu, tamird@kernel.org, acourbot@nvidia.com, work@onurozkan.dev, jhubbard@nvidia.com, ttabi@nvidia.com, apopple@nvidia.com, ecourtney@nvidia.com, shashanks@nvidia.com, zhiw@nvidia.com Cc: driver-core@lists.linux.dev, linux-pci@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] rust: pci: remove request_irq() and request_threaded_irq() from Device Date: Wed, 12 Aug 2026 01:39:34 +0200 Message-ID: <20260811233952.3000968-4-dakr@kernel.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260811233952.3000968-1-dakr@kernel.org> References: <20260811233952.3000968-1-dakr@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the thin wrappers on Device that only forwarded to irq::Registration::new() and irq::ThreadedRegistration::new(). With IrqVector embedding a resolved IrqRequest, the conversion is infallible and drivers call irq::Registration::new(vector.into(), ...) directly. Unlike the platform equivalents, which combine a fallible IRQ lookup with handler registration, the PCI wrappers add no value beyond namespacing. They also introduce a redundant device reference. IrqVector already carries a device borrow through its embedded IrqRequest, yet the wrappers required a second, potentially unrelated, &self receiver. Signed-off-by: Danilo Krummrich Tested-by: John Hubbard --- rust/kernel/pci/irq.rs | 50 ++++++------------------------------------ 1 file changed, 7 insertions(+), 43 deletions(-) diff --git a/rust/kernel/pci/irq.rs b/rust/kernel/pci/irq.rs index 305701440114..b3dce5b49d57 100644 --- a/rust/kernel/pci/irq.rs +++ b/rust/kernel/pci/irq.rs @@ -8,10 +8,7 @@ device, device::Bound, error::to_result, - irq::{ - self, - IrqRequest, // - }, + irq::IrqRequest, prelude::*, // }; use core::num::NonZero; @@ -70,9 +67,10 @@ const fn as_raw(self) -> u32 { =20 /// A resolved IRQ vector from a PCI interrupt vector allocation. /// -/// Created by [`IrqVectorRegistration::vector`] and consumed by [`Device:= :request_irq`] or -/// [`Device::request_threaded_irq`]. Borrows the [`IrqVectorRegistration`= ] it was derived from, -/// so the allocation stays live until the handler is freed. +/// Created by [`IrqVectorRegistration::vector`]. Convert to [`IrqRequest`= ] via [`From`] to register +/// a handler with [`irq::Registration::new`](crate::irq::Registration::ne= w). Borrows the +/// [`IrqVectorRegistration`] it was derived from, so the allocation stays= live until the handler is +/// freed. pub struct IrqVector<'a> { request: IrqRequest<'a>, reg: &'a IrqVectorRegistration<'a>, @@ -169,40 +167,6 @@ fn drop(&mut self) { } =20 impl Device { - /// Returns a [`kernel::irq::Registration`] for the given IRQ vector. - /// - /// # Safety - /// - /// Callers must not `mem::forget()` the resulting [`irq::Registration= `] or otherwise prevent - /// its [`Drop`] implementation from running. - pub unsafe fn request_irq<'a, T: crate::irq::Handler + 'a>( - &'a self, - vector: IrqVector<'a>, - flags: irq::Flags, - name: &'static CStr, - handler: impl PinInit + 'a, - ) -> impl PinInit, Error> + 'a { - // SAFETY: Caller guarantees the Registration will not be leaked. - unsafe { irq::Registration::::new(vector.into(), flags, name, h= andler) } - } - - /// Returns a [`kernel::irq::ThreadedRegistration`] for the given IRQ = vector. - /// - /// # Safety - /// - /// Callers must not `mem::forget()` the resulting [`irq::ThreadedRegi= stration`] or otherwise - /// prevent its [`Drop`] implementation from running. - pub unsafe fn request_threaded_irq<'a, T: crate::irq::ThreadedHandler = + 'a>( - &'a self, - vector: IrqVector<'a>, - flags: irq::Flags, - name: &'static CStr, - handler: impl PinInit + 'a, - ) -> impl PinInit, Error> + 'a { - // SAFETY: Caller guarantees the Registration will not be leaked. - unsafe { irq::ThreadedRegistration::::new(vector.into(), flags,= name, handler) } - } - /// Allocate IRQ vectors for this PCI device. /// /// Allocates between `min_vecs` and `max_vecs` interrupt vectors for = the device. @@ -211,8 +175,8 @@ pub unsafe fn request_threaded_irq<'a, T: crate::irq::T= hreadedHandler + 'a>( /// will try them in order of preference: MSI-X first, then MSI, then = INTx interrupts. /// /// The allocated vectors are freed when the returned [`IrqVectorRegis= tration`] is dropped. - /// IRQ handlers registered via [`Self::request_irq`] or [`Self::reque= st_threaded_irq`] - /// borrow from the registration, so the compiler ensures they are fre= ed first. + /// Use [`IrqVectorRegistration::vector`] to obtain an [`IrqVector`] f= or a given vector + /// index. /// /// # Arguments /// --=20 2.55.0 From nobody Tue Sep 29 06:06:38 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED90847ECC5; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GbCr7PuN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BFD801F000E9; Tue, 11 Aug 2026 23:40:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786491620; bh=dP/Ow6CSJlTxIV+PgdIArvTtqly361pVDQMqZe4fFsY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=GbCr7PuNbocBK0oBKjarp2z4Sfp0jLP32jTM4Uovvj7LppoerVctrPklLCw3XOa9C 2Mfctl6Be+fgOXomnEFhxewMF4ysTyTdSt7b7e06YsZD1D9HDwQwfog9VklGihwqpx g1/d5aIyRI9G3Nq0+8tOhDmT3P6fCp45Nvun1DSXJ+yq9urFkQV7VkIOeCfUTdt9Gf HgGkg+er0lK1lzk03uIZZKMuzmt1YDVouGs+GSYvIRdrez9fzraeFhoFvtDrjtKazS A5LdmjEt0prPq2KpXuXbPsnWX/ktn2Nt8F71eq+w+Vivrne9yZYNbih4PIuP3kU59M GcF14iVq8R40A== From: Danilo Krummrich To: bhelgaas@google.com, dakr@kernel.org, kwilczynski@kernel.org, aliceryhl@google.com, daniel.almeida@collabora.com, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu, tamird@kernel.org, acourbot@nvidia.com, work@onurozkan.dev, jhubbard@nvidia.com, ttabi@nvidia.com, apopple@nvidia.com, ecourtney@nvidia.com, shashanks@nvidia.com, zhiw@nvidia.com Cc: driver-core@lists.linux.dev, linux-pci@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] PCI: Add pci_irq_type() to query the allocated interrupt type Date: Wed, 12 Aug 2026 01:39:35 +0200 Message-ID: <20260811233952.3000968-5-dakr@kernel.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260811233952.3000968-1-dakr@kernel.org> References: <20260811233952.3000968-1-dakr@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a helper that returns PCI_IRQ_MSIX, PCI_IRQ_MSI, or PCI_IRQ_INTX based on the interrupt type the PCI core selected after pci_alloc_irq_vectors(). Several drivers already open-code this check against pdev->msix_enabled and pdev->msi_enabled, or even open code this helper [1]. A common helper avoids the duplication and keeps drivers from accessing the bitfield directly (see also [2]). Acked-by: Bjorn Helgaas Link: https://elixir.bootlin.com/linux/v7.1/source/drivers/net/ethernet/aqu= antia/atlantic/aq_pci_func.c#L196 [1] Inspired-by: John Hubbard Link: https://lore.kernel.org/all/DKKG2QM3YJYB.Z2H2B2UXJ75N@kernel.org/ [2] Signed-off-by: Danilo Krummrich Tested-by: John Hubbard --- include/linux/pci.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 64b308b6e61c..80b8561b5be0 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1783,6 +1783,26 @@ void pci_free_irq_vectors(struct pci_dev *dev); int pci_irq_vector(struct pci_dev *dev, unsigned int nr); const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); =20 +/** + * pci_irq_type - Get the interrupt type of a PCI device + * @pdev: the PCI device to operate on + * + * Discriminate the interrupt type the PCI core selected for this device + * after a successful pci_alloc_irq_vectors() call. + * + * Return: %PCI_IRQ_MSIX, %PCI_IRQ_MSI, or %PCI_IRQ_INTX. + */ +static inline unsigned int pci_irq_type(struct pci_dev *pdev) +{ + if (pdev->msix_enabled) + return PCI_IRQ_MSIX; + + if (pdev->msi_enabled) + return PCI_IRQ_MSI; + + return PCI_IRQ_INTX; +} + #else static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS;= } static inline void pci_disable_msi(struct pci_dev *dev) { } @@ -1845,6 +1865,11 @@ static inline const struct cpumask *pci_irq_get_affi= nity(struct pci_dev *pdev, { return cpu_possible_mask; } + +static inline unsigned int pci_irq_type(struct pci_dev *pdev) +{ + return PCI_IRQ_INTX; +} #endif =20 /** --=20 2.55.0 From nobody Tue Sep 29 06:06:38 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90CC9432E6F; Tue, 11 Aug 2026 23:40:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786491626; cv=none; b=cQK5v+XSLorFRoV0Tcz/QcqyVh29J9ai5INW/e76NKl7yEwtg8MvrgTNhOrOLxYxzncHkG/EUINba4FZ2Co58v5lTq/a/xeFraFF7kW+Gc5/ZoG0HToUVuDR6wLd/xzPxc4r/Di3dGLfD+G0oLA3GExFHxw6Rt+7ZPAd0gC6+gw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786491626; c=relaxed/simple; bh=F3xDwx9RXkfN9aqmpjv4XwQeNvoYEzjQQAwVjG6j/to=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YSXbIybSNOUrbEyfI3515dY8bvdQcKRgv07bk7JAeB5vLW69wbuk7igJQu2TmO96WDoq4vLMRANBt1twtlT/AD8EwGWB9bqIdoSiVhG20mFmKHQjhJubFYngSZy8uZy+lvGJK79qqAMAsQOzaySEKQUAJGP7or1eQ2qbygpD09o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Td7a9W5q; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Td7a9W5q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AED801F00A3A; Tue, 11 Aug 2026 23:40:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786491625; bh=IlVtep7DDzI4H03ENDQUeTtt1UMkSbhkQnvi+Gh7hMg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Td7a9W5quWBbBRzMvye4EQIKclUWNiEzNpRtRhLPx+TR0fUuQuyf4qcipuQI4Q/lL sODohtV9Foz0MCU8JFRMlpIMjBx1lZKnPTjn/625L6iIILo49ePUfKLBmmSn74Jbc8 TBvnY5oGI380CmPQKWQsSFtgjy8u8v87yYm/Nt2bYRvHbY5EsaVNiV2UYYyck1AWXu PQAw3QRw1SLX7G1fnD9mfVusPp0wetgj4ajAjyt5l7lo2EsWo0Rb061xdDdo3Yl/Yk s5mw+p+HdnsVTb6IweCUGGBbx7W7geX472CY7USgZdJrZb/y+jB6kbU5Xj0scnS20e Mc9XAZAd/EDug== From: Danilo Krummrich To: bhelgaas@google.com, dakr@kernel.org, kwilczynski@kernel.org, aliceryhl@google.com, daniel.almeida@collabora.com, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu, tamird@kernel.org, acourbot@nvidia.com, work@onurozkan.dev, jhubbard@nvidia.com, ttabi@nvidia.com, apopple@nvidia.com, ecourtney@nvidia.com, shashanks@nvidia.com, zhiw@nvidia.com Cc: driver-core@lists.linux.dev, linux-pci@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] rust: pci: expose the allocated interrupt type Date: Wed, 12 Aug 2026 01:39:36 +0200 Message-ID: <20260811233952.3000968-6-dakr@kernel.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260811233952.3000968-1-dakr@kernel.org> References: <20260811233952.3000968-1-dakr@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add irq_type() on IrqVectorRegistration and IrqVector, wrapping the new pci_irq_type() C function. A driver whose interrupt acknowledgment depends on the type (MSI-X vs MSI vs INTx) queries it here rather than assuming which type the PCI core selected. Suggested-by: John Hubbard Link: https://lore.kernel.org/all/20260808031120.363869-4-jhubbard@nvidia.c= om/ Signed-off-by: Danilo Krummrich Tested-by: John Hubbard --- rust/helpers/pci.c | 5 +++++ rust/kernel/pci/irq.rs | 22 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c index e44905317d75..23b06becb448 100644 --- a/rust/helpers/pci.c +++ b/rust/helpers/pci.c @@ -24,6 +24,11 @@ __rust_helper bool rust_helper_dev_is_pci(const struct d= evice *dev) return dev_is_pci(dev); } =20 +__rust_helper unsigned int rust_helper_pci_irq_type(struct pci_dev *pdev) +{ + return pci_irq_type(pdev); +} + #ifndef CONFIG_PCI_MSI __rust_helper int rust_helper_pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, diff --git a/rust/kernel/pci/irq.rs b/rust/kernel/pci/irq.rs index b3dce5b49d57..41059b922492 100644 --- a/rust/kernel/pci/irq.rs +++ b/rust/kernel/pci/irq.rs @@ -33,6 +33,16 @@ const fn as_raw(self) -> u32 { IrqType::MsiX =3D> bindings::PCI_IRQ_MSIX, } } + + /// Construct from raw value. + #[inline] + const fn from_raw(raw: u32) -> Self { + match raw { + bindings::PCI_IRQ_MSIX =3D> IrqType::MsiX, + bindings::PCI_IRQ_MSI =3D> IrqType::Msi, + _ =3D> IrqType::Intx, + } + } } =20 /// Set of IRQ types that can be used for PCI interrupt allocation. @@ -106,6 +116,11 @@ pub fn index(&self) -> usize { pub fn vectors(&self) -> &'a IrqVectorRegistration<'a> { self.reg } + + /// Returns the interrupt type the PCI core selected for this vector's= allocation. + pub fn irq_type(&self) -> IrqType { + self.reg.irq_type() + } } =20 impl<'a> From> for IrqRequest<'a> { @@ -137,6 +152,13 @@ pub fn vector_count(&self) -> usize { self.count.get() } =20 + /// Returns the interrupt type the PCI core selected for this allocati= on. + #[inline] + pub fn irq_type(&self) -> IrqType { + // SAFETY: `self.dev.as_raw()` is a valid pointer to a `struct pci= _dev`. + IrqType::from_raw(unsafe { bindings::pci_irq_type(self.dev.as_raw(= )) }) + } + /// Returns the [`IrqVector`] at `index`. /// /// The returned [`IrqVector`] borrows from this registration, ensurin= g the vector allocation --=20 2.55.0