From nobody Tue Sep 29 06:06:53 2026 Received: from out-172.mta0.migadu.com (out-172.mta0.migadu.com [91.218.175.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 833393FF8B9 for ; Tue, 11 Aug 2026 23:03:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786489423; cv=none; b=g7JCI/aySJzw5vpKps1f4XN8VMOZN6c1YvcM3AIDjIJIiPM/w5J7ZRYeqDOyBGAVDpLbdJp2KgimwEQwMqMuS5nvZgbtsN+nV3pL/otMYDO2SlwQmZxO3ISms2Wmkx/9UQduUcPqTNY0dS8LMNFrq8jO8FUvWSTJa3jjPyYIO0o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786489423; c=relaxed/simple; bh=wwIC3eX7Fml2Q+kjJARL44tlkprsNjlDDjhJKw7k/rY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YSWXlWKlfJUMPsWUBA8tcY55WLSPvYuI3ZoTNYRklqucQDJTH0feI2bC9oSQ8++TTDTJnochi1Ce5qQUKlDWQLFQG4Fy6x3Hc4FvKrOaKIGfeeQAc6ED41kwZXUEAgt0wIhUNq6kpjCjshK24Ud721pdpqQpbHtOHjeBUiYaQM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=aKmFALIB; arc=none smtp.client-ip=91.218.175.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="aKmFALIB" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1786489417; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OUZulxlEFenT7RvZakt+p4GE/qxIk5ggsq3u1CDIY8o=; b=aKmFALIBIEB1UhNbRDH6xre7z0bcw6q8Ll+3mDGOOS2KPmUD8CLCAFcA8G3EXol/OGGNDu wlpUfjHFYoTy5Gj4sA4rxm5R4E6VWWtdUuFRsJMQwHircRbYKaIXL4SQtGnM1/Roc4E7DK V0Hg1NBCvboosZvc0nzGC6JqeJ6Y3go= From: Jinyu Tang To: Anup Patel , Anup Patel , Paolo Bonzini , Sean Christopherson Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra , Paul Walmsley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Conor Dooley , Yong-Xuan Wang , Nutty Liu , Jinyu Tang , Jinyu Tang Subject: [PATCH v2 1/3] KVM: riscv: Implement KVM_PRE_FAULT_MEMORY Date: Wed, 12 Aug 2026 07:03:14 +0800 Message-ID: <20260811230316.218770-2-jinyu.tang@linux.dev> In-Reply-To: <20260811230316.218770-1-jinyu.tang@linux.dev> References: <20260811230316.218770-1-jinyu.tang@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The generic KVM_PRE_FAULT_MEMORY ioctl lets userspace populate KVM page tables before running a vCPU over a GPA range. x86 already supports the ioctl, but RISC-V does not expose the capability and has no arch hook. Add the RISC-V arch hook and reuse the existing G-stage fault mapping path with a read access. Report progress using the G-stage mapping returned by the map path, so the ioctl can advance by the actual leaf size that covers the requested GPA. Unlike x86, RISC-V's G-stage fault path does not return a detailed result such as RET_PF_FIXED or RET_PF_RETRY. Treat a successful call that does not return a visible G-stage mapping as no progress, instead of reporting that a page was prefaulted. Signed-off-by: Jinyu Tang --- arch/riscv/kvm/Kconfig | 1 + arch/riscv/kvm/gstage.c | 3 +++ arch/riscv/kvm/mmu.c | 33 +++++++++++++++++++++++++++++++++ arch/riscv/kvm/vm.c | 1 + 4 files changed, 38 insertions(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index ec2cee0a39e0..8ac209e8ac87 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -28,6 +28,7 @@ config KVM select KVM_COMMON select KVM_GENERIC_DIRTYLOG_READ_PROTECT select KVM_GENERIC_HARDWARE_ENABLING + select KVM_GENERIC_PRE_FAULT_MEMORY select KVM_MMIO select VIRT_XFER_TO_GUEST_WORK select SCHED_INFO diff --git a/arch/riscv/kvm/gstage.c b/arch/riscv/kvm/gstage.c index e5002cb9cbef..6bd8b8fd6ceb 100644 --- a/arch/riscv/kvm/gstage.c +++ b/arch/riscv/kvm/gstage.c @@ -280,6 +280,9 @@ int kvm_riscv_gstage_map_page(struct kvm_gstage *gstage, out_map->level, true); } else if (ALIGN_DOWN(PFN_PHYS(pte_pfn(ptep_get(ptep))), page_size) =3D= =3D hpa) { kvm_riscv_gstage_update_pte_prot(gstage, ptep_level, gpa, ptep, prot); + out_map->addr =3D ALIGN_DOWN(gpa, page_size); + out_map->level =3D ptep_level; + out_map->pte =3D ptep_get(ptep); return 0; } } diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c index 6035b5ec9503..c96e21740c91 100644 --- a/arch/riscv/kvm/mmu.c +++ b/arch/riscv/kvm/mmu.c @@ -748,6 +748,39 @@ int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kv= m_memory_slot *memslot, return ret; } =20 +long kvm_arch_vcpu_pre_fault_memory(struct kvm_vcpu *vcpu, + struct kvm_pre_fault_memory *range) +{ + struct kvm_gstage_mapping out_map =3D { 0 }; + struct kvm_memory_slot *memslot; + unsigned long map_size; + unsigned long hva; + gpa_t end; + gfn_t gfn; + int ret; + + gfn =3D gpa_to_gfn(range->gpa); + memslot =3D kvm_vcpu_gfn_to_memslot(vcpu, gfn); + if (!memslot) + return -ENOENT; + + hva =3D gfn_to_hva_memslot_prot(memslot, gfn, NULL); + if (kvm_is_error_hva(hva)) + return -ENOENT; + + ret =3D kvm_riscv_mmu_map(vcpu, memslot, range->gpa, hva, false, &out_map= ); + if (ret) + return ret; + + if (!pte_val(out_map.pte)) + return -EAGAIN; + + map_size =3D PAGE_SIZE << (out_map.level * kvm_riscv_gstage_index_bits); + end =3D ALIGN_DOWN(range->gpa, map_size) + map_size; + + return min_t(u64, range->size, end - range->gpa); +} + int kvm_riscv_mmu_alloc_pgd(struct kvm *kvm) { struct page *pgd_page; diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index a9f083feeb76..58500a19b33b 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -187,6 +187,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) case KVM_CAP_MP_STATE: case KVM_CAP_IMMEDIATE_EXIT: case KVM_CAP_SET_GUEST_DEBUG: + case KVM_CAP_PRE_FAULT_MEMORY: r =3D 1; break; case KVM_CAP_NR_VCPUS: --=20 2.43.0 From nobody Tue Sep 29 06:06:53 2026 Received: from out-184.mta0.migadu.com (out-184.mta0.migadu.com [91.218.175.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB7604307B0 for ; Tue, 11 Aug 2026 23:03:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786489430; cv=none; b=eObOQaSBWZY6BRtbRAKkSzFkbNSnDzFBpwccLMYFL1X5cQBEuAMpBFmK1vLDBJs/i/yd8b22H+w7QhLAJ1BoRX5muiRxFm3C3x8WUdlJPVdmhUwaxN+/KafC8A+A7j2ONmqJYqiE1EyfzTO2WgmYQHTI5IagEQ1hP1v5dY5deH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786489430; c=relaxed/simple; bh=Yvo9LgMLOuQSU56xXqv5p0DmtktsYza1DlVL/M+lu3U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qCgnV4hRXXA6wy/ZZwTUXbtHaRUmWwzpxu1LOqno/BJx1pzzka5GODA3m3Uc3ErRtci/D4Y/fcQdyP/2ckvp/WHKpZjSRqVNSAQ8RsD0XsX2qMl1qolE7O6vsmOmIEt868Gf209A549pg7jvdlp9A50Lkc9heJqUn4PfVZ84UsQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=sduuRLgq; arc=none smtp.client-ip=91.218.175.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="sduuRLgq" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1786489425; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nhSfHP9g04wYalHk7dBUvUUOdewrP/fVDAB8KJOgRKY=; b=sduuRLgqmPiCXoUyn5OGRz/tfB+r5Ky7gmSA3mHy31fSS+Yz7xfPDALsM/uOOm0gzOLpnO 7F6n8yUdNsxs4Spu+FBmdV3W3nERR/tzpWUSA7Pcz5KtG6S87GocABKRYVL8ngSaFmpcKB VuGClGWJE+uzk0+csXlizPPaisOp5l8= From: Jinyu Tang To: Anup Patel , Anup Patel , Paolo Bonzini , Sean Christopherson Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra , Paul Walmsley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Conor Dooley , Yong-Xuan Wang , Nutty Liu , Jinyu Tang , Jinyu Tang Subject: [PATCH v2 2/3] KVM: selftests: Add RISC-V Sv57 page table indexing Date: Wed, 12 Aug 2026 07:03:15 +0800 Message-ID: <20260811230316.218770-3-jinyu.tang@linux.dev> In-Reply-To: <20260811230316.218770-1-jinyu.tang@linux.dev> References: <20260811230316.218770-1-jinyu.tang@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" RISC-V selftests can create guests with five page-table levels, for example when the selected guest mode is Sv57. The RISC-V page-table walker only had index arrays for levels 0 through 3, so virt_arch_pg_map() indexed past the end of the arrays when level 4 was used. Add the missing L4 index mask and shift so selftests can build guest page tables for Sv57 VMs. Signed-off-by: Jinyu Tang --- tools/testing/selftests/kvm/include/riscv/processor.h | 3 +++ tools/testing/selftests/kvm/lib/riscv/processor.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index e3acf2ae9881..abde3c71c891 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -127,6 +127,9 @@ void vm_install_exception_handler(struct kvm_vm *vm, in= t vector, exception_handl =20 void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn = handler); =20 +/* L4 index Bit[56:48] */ +#define PGTBL_L4_INDEX_MASK 0x01FF000000000000ULL +#define PGTBL_L4_INDEX_SHIFT 48 /* L3 index Bit[47:39] */ #define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL #define PGTBL_L3_INDEX_SHIFT 39 diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/test= ing/selftests/kvm/lib/riscv/processor.c index ded5429f3448..b4d41a407553 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -43,6 +43,7 @@ static u64 pte_index_mask[] =3D { PGTBL_L1_INDEX_MASK, PGTBL_L2_INDEX_MASK, PGTBL_L3_INDEX_MASK, + PGTBL_L4_INDEX_MASK, }; =20 static u32 pte_index_shift[] =3D { @@ -50,6 +51,7 @@ static u32 pte_index_shift[] =3D { PGTBL_L1_INDEX_SHIFT, PGTBL_L2_INDEX_SHIFT, PGTBL_L3_INDEX_SHIFT, + PGTBL_L4_INDEX_SHIFT, }; =20 static u64 pte_index(struct kvm_vm *vm, gva_t gva, int level) --=20 2.43.0 From nobody Tue Sep 29 06:06:53 2026 Received: from out-185.mta0.migadu.com (out-185.mta0.migadu.com [91.218.175.185]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 647DE36604B for ; Tue, 11 Aug 2026 23:03:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.185 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786489434; cv=none; b=J+xhO1/uYiGMx4GyOdqmZ8U8PKveTbi3CIv9QX5nk7Mxq8xyVJWAp0JrS080ysLoyQdHX/PIv5xCNNmCKW0A083MReXCWM8zhCkL4RYS2H0g+ZoeWqSDbRODSCGWLY5EtLtRLpuAGDA73hNQykwO1Ynz1i0OcLROelWe0C3k7Xk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786489434; c=relaxed/simple; bh=XyIn08WiCac5PIjwY3CazzPrW6vIHJnSZ9DAu0w7m+8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=olufUEBCtBTFalXY1JqF8cfzjnllA4YAqe/gQrS7Xf1CritvmFgMkoc9uRDevhBA/XGewv/qEpFP65VdSaWgDPz8hP5ZKg6fistjMrJfVgQq+VpFxpQjddh6jcNeq95yFJw8eiIYZeQqWoOYg4Q1hWhC19eUsm/+WvCCQ/eMAHg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=vDgshGKE; arc=none smtp.client-ip=91.218.175.185 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="vDgshGKE" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1786489431; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B0gsK+RPMVbPdBplt1NaL9W65DIA5uhK1UuwwNS0HXY=; b=vDgshGKEX7vyYjP47jciW6pM4KsjZCFm51w72WbPmdjHLIiUKn89xuTA16ycJkruA63PVN 4gnHxVCXbPHRVql09oH4kJJHXfWEvrejfOF2Yd/pC+Ki6SDPq1soSy/g5Hlj5pO8mVUQ0l b0Wluk3xk6jhpIuxsmKwF3wgTHDQTTM= From: Jinyu Tang To: Anup Patel , Anup Patel , Paolo Bonzini , Sean Christopherson Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra , Paul Walmsley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Conor Dooley , Yong-Xuan Wang , Nutty Liu , Jinyu Tang , Jinyu Tang Subject: [PATCH v2 3/3] KVM: selftests: Enable pre_fault_memory_test for RISC-V Date: Wed, 12 Aug 2026 07:03:16 +0800 Message-ID: <20260811230316.218770-4-jinyu.tang@linux.dev> In-Reply-To: <20260811230316.218770-1-jinyu.tang@linux.dev> References: <20260811230316.218770-1-jinyu.tang@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" RISC-V now supports KVM_PRE_FAULT_MEMORY, so include the generic pre_fault_memory_test in the RISC-V KVM selftest build. The test uses PAGE_SIZE from the architecture processor header. Define the normal 4K RISC-V selftest page size so the generic test can build for RISC-V. Signed-off-by: Jinyu Tang --- v1 -> v2: - Drop the per-test guest_modes_append_default() call from pre_fault_memory_test.c. RISC-V already initializes supported and default guest modes from kvm_selftest_arch_init(), which is called by the common kvm_selftest_init() constructor, as suggested by Sean. tools/testing/selftests/kvm/Makefile.kvm | 1 + tools/testing/selftests/kvm/include/riscv/processor.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 6fc34e9bf8e1..ac64ac92fd4b 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -225,6 +225,7 @@ TEST_GEN_PROGS_riscv +=3D coalesced_io_test TEST_GEN_PROGS_riscv +=3D dirty_log_perf_test TEST_GEN_PROGS_riscv +=3D get-reg-list TEST_GEN_PROGS_riscv +=3D mmu_stress_test +TEST_GEN_PROGS_riscv +=3D pre_fault_memory_test TEST_GEN_PROGS_riscv +=3D rseq_test TEST_GEN_PROGS_riscv +=3D steal_time =20 diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index abde3c71c891..70487c8ed155 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -12,6 +12,9 @@ #include #include "kvm_util.h" =20 +#define PAGE_SHIFT 12 +#define PAGE_SIZE BIT_ULL(PAGE_SHIFT) + #define INSN_OPCODE_MASK 0x007c #define INSN_OPCODE_SHIFT 2 #define INSN_OPCODE_SYSTEM 28 --=20 2.43.0