From nobody Tue Sep 29 06:59:41 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 945713F3287; Tue, 11 Aug 2026 06:29:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786429790; cv=none; b=gWfuGY/XgWe9Te4a1M4WE+wNxQhe/AE6qMIbhQ7lM7aHcHNRs+V3Sr6JaXjIuJ9NMwg1EhpgkhJUn0nJFe3tpqeB5GMgW+H2/ZhYHJd66sX7whCfN21TryGtLHX9r7TdgfdP4escgoMpESuDeacUgiod5l7o1Um2xKXC3qBZ3yg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786429790; c=relaxed/simple; bh=rxbnkO5Bo9eMuXTx/7aC8GXRAwV4Vgxstp+S/wWtRJ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ET5FRa+MCVzDdJV7KdQhxS4MQPjzWVDAy2y1KToODtJ1S764Qc79MhrH3ugFUWAstUuC6+coE+zhJpJd9mQE4AucoaRsnQYxsetujqgbimQDlDRBOFmSlqCCCoHLR9tPGf5L6vD5PJXVM9V8YQjfQ/uKIePrUqstl9yLaC+ZmCc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ff/NyR1F; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ff/NyR1F" Received: by smtp.kernel.org (Postfix) with ESMTPS id 352E9C2BCF7; Tue, 11 Aug 2026 06:29:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786429790; bh=rxbnkO5Bo9eMuXTx/7aC8GXRAwV4Vgxstp+S/wWtRJ4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Ff/NyR1FN50F4B2rrNlK4y4oUH9BwfVNRofg73n4e+xOIv+g8dgEpVg+dKoJFlwDg MGcYb5QEJvfZ8L7rW4IcYEgVjlKcnil6enhhbCRxyfl9Dm9FzKL8YQa2L4WRenuT4x ZLRc4rJLIhm8D6lE6S0Cnm1h6TiQpaKb6IMz9vD6NJ1T4YDDLVNAoiSF6AqBOy4A/K 3OiO+XxQVJk3ggn4KK7n1njwS0DSuBIyogTKIpFYZzZTG4Yw5aiXj8evHkckgyqoR/ 5IP/leX2PNpLK4sqqDrjocHSZU6k19gZ5uI6yAsX9H9ynELJBA5/wh4iSPUmnKuUaz AnUY7SZlPLmqQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22BBAC5AD7B; Tue, 11 Aug 2026 06:29:50 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Tue, 11 Aug 2026 14:29:48 +0800 Subject: [PATCH v5 1/4] dt-bindings: i2c: add support for AE350 I2C controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260811-atciic100-v5-1-1d306c21dba3@andestech.com> References: <20260811-atciic100-v5-0-1d306c21dba3@andestech.com> In-Reply-To: <20260811-atciic100-v5-0-1d306c21dba3@andestech.com> To: Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Ben Zong-You Xie , Conor Dooley X-Mailer: b4 0.15-dev-09770 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786429789; l=2147; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=bq3xzDJ/OIuUwfBkMViZX6pvpmLXUhLZ07QGmtn5ZDY=; b=jLQ0aV2x15w7MTRX/V+ERzbSHB3sC2BMYjnGoGn5kladTHrDAZW/eeYb/kKShILU4286x9sVH CWF2HlU6y4FAD3ercY0Q8wV70E6dKPeNlqeQjQI4vFtub8gJpQgiIcv X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie Document device tree bindings for the I2C controller on Andes AE350 platform. The ATCIIC100 is a dedicated I2C controller IP developed by Andes Technology. This IP block is a core component of the Andes AE350 platform, which serves as a reference architecture for SoC designs. The QiLai SoC also integrates this I2C controller. The binding introduces the following compatible strings: - "andestech,qilai-i2c": For the implementation integrated into the Andes QiLai SoC. - "andestech,ae350-i2c": As a fallback compatible string representing the base IP design used across the AE350 platform architecture. Signed-off-by: Ben Zong-You Xie Acked-by: Conor Dooley --- .../bindings/i2c/andestech,ae350-i2c.yaml | 45 ++++++++++++++++++= ++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/andestech,ae350-i2c.yaml= b/Documentation/devicetree/bindings/i2c/andestech,ae350-i2c.yaml new file mode 100644 index 000000000000..59a521fb249b --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/andestech,ae350-i2c.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/andestech,ae350-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes I2C controller on AE350 platform + +maintainers: + - Ben Zong-You Xie + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - andestech,qilai-i2c + - const: andestech,ae350-i2c + - const: andestech,ae350-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + i2c@f0a00000 { + compatible =3D "andestech,ae350-i2c"; + reg =3D <0xf0a00000 0x100000>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH>; + }; --=20 2.34.1 From nobody Tue Sep 29 06:59:41 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9460C3F3291; Tue, 11 Aug 2026 06:29:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786429790; cv=none; b=JQRmtW/6hSRf7nId/MMaejYkslmuYmi9fAbotnWB+Bbg93nVefmlEXLkhM/o7nJAlHG6zDzAOmuAGVGVE6v6XtT0aum3xMshfI/RldekX1n2cCaVcdahT50AfmNaQl1yHAcQvq0hYLWv+NSr3G00wTwywCFNCdFVEGxbERm2Ebw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786429790; c=relaxed/simple; bh=ZSPZYlnZG19PBMB/VQ/6Xt2l5W+gQnrh8Hogh8vtC1k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Tue, 11 Aug 2026 06:29:50 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Tue, 11 Aug 2026 14:29:49 +0800 Subject: [PATCH v5 2/4] i2c: add Andes I2C driver support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260811-atciic100-v5-2-1d306c21dba3@andestech.com> References: <20260811-atciic100-v5-0-1d306c21dba3@andestech.com> In-Reply-To: <20260811-atciic100-v5-0-1d306c21dba3@andestech.com> To: Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Ben Zong-You Xie X-Mailer: b4 0.15-dev-09770 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786429789; l=11439; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=anfOM9cdAboej+C0cpOCCkEAR/UEiOCs3AOuyLG0+c0=; b=bJ8IvlzyJwaGn5ET6cq3AbWhiiKNmKoW2RcUC17YdFu8xtzFrxX+huitzy8nNPwtgJ/SG6qud /TarIQlhTA6A5HQDTl4922ZOiR3o6rBAy9+kbjM+PIgOKj+NAgKq5DB X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie Add support for Andes I2C driver. Andes I2C can act as either a controller or a target, depending on the control register settings. Now, we only support controller mode. Signed-off-by: Ben Zong-You Xie --- drivers/i2c/busses/Kconfig | 10 ++ drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-andes.c | 341 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 352 insertions(+) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index d7b89508311f..73f1946bd8b7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -446,6 +446,16 @@ config I2C_AT91_SLAVE_EXPERIMENTAL - There are some mismatches with a SAMA5D4 as slave and a SAMA5D2 as master. =20 +config I2C_ANDES + tristate "Andes I2C Controller" + depends on ARCH_ANDES || COMPILE_TEST + help + If you say yes to this option, support will be included for the + Andes I2C controller. + + This support is also available as a module. If so, the module + will be called i2c-andes. + config I2C_AU1550 tristate "Au1550/Au1200/Au1300 SMBus interface" depends on MIPS_ALCHEMY diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 3755c54b3d82..6fe6ded04d2d 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_I2C_ASPEED) +=3D i2c-aspeed.o obj-$(CONFIG_I2C_AT91) +=3D i2c-at91.o i2c-at91-y :=3D i2c-at91-core.o i2c-at91-master.o i2c-at91-$(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL) +=3D i2c-at91-slave.o +obj-$(CONFIG_I2C_ANDES) +=3D i2c-andes.o obj-$(CONFIG_I2C_AU1550) +=3D i2c-au1550.o obj-$(CONFIG_I2C_AXXIA) +=3D i2c-axxia.o obj-$(CONFIG_I2C_BCM2835) +=3D i2c-bcm2835.o diff --git a/drivers/i2c/busses/i2c-andes.c b/drivers/i2c/busses/i2c-andes.c new file mode 100644 index 000000000000..5f135d8c9b13 --- /dev/null +++ b/drivers/i2c/busses/i2c-andes.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for Andes I2C controller, used in Andes AE350 platform and QiLai= SoC + * + * Copyright (C) 2026 Andes Technology Corporation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ANDES_I2C_ID_REG 0x0 +#define ANDES_I2C_ID_MASK GENMASK(31, 8) +#define ANDES_I2C_ID 0x020210 + +#define ANDES_I2C_CFG_REG 0x10 +#define ANDES_I2C_CFG_FIFOSIZE GENMASK(1, 0) + +#define ANDES_I2C_INTEN_REG 0x14 +#define ANDES_I2C_INTEN_FIFO_EMPTY BIT(0) +#define ANDES_I2C_INTEN_FIFO_FULL BIT(1) +#define ANDES_I2C_INTEN_CMPL BIT(9) + +#define ANDES_I2C_STATUS_REG 0x18 +#define ANDES_I2C_STATUS_FIFO_EMPTY BIT(0) +#define ANDES_I2C_STATUS_FIFO_FULL BIT(1) +#define ANDES_I2C_STATUS_ADDR_HIT BIT(3) +#define ANDES_I2C_STATUS_CMPL BIT(9) +#define ANDES_I2C_STATUS_W1C GENMASK(9, 3) + +#define ANDES_I2C_ADDR_REG 0x1C + +#define ANDES_I2C_DATA_REG 0x20 + +#define ANDES_I2C_CTRL_REG 0x24 +#define ANDES_I2C_CTRL_DATA_CNT GENMASK(7, 0) +#define ANDES_I2C_CTRL_DIR BIT(8) +#define ANDES_I2C_CTRL_PHASE GENMASK(12, 9) + +#define ANDES_I2C_CMD_REG 0x28 +#define ANDES_I2C_CMD_ACTION GENMASK(2, 0) +#define ANDES_I2C_CMD_TRANS BIT(0) + +#define ANDES_I2C_SETUP_REG 0x2C +#define ANDES_I2C_SETUP_IICEN BIT(0) +#define ANDES_I2C_SETUP_REQ BIT(2) + +#define ANDES_I2C_TPM_REG 0x30 + +#define ANDES_I2C_TIMEOUT_US 400000 +#define ANDES_I2C_TIMEOUT usecs_to_jiffies(ANDES_I2C_TIMEOUT_US) + +#define ANDES_I2C_MAX_DATA_LEN 256 + +struct andes_i2c { + struct i2c_adapter adap; + struct completion completion; + spinlock_t lock; + struct regmap *map; + u8 *buf; + unsigned int fifo_size; + int irq; + u16 buf_len; + bool addr_hit; + bool xfer_done; +}; + +static const struct regmap_config andes_i2c_regmap_config =3D { + .name =3D "andes_i2c", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .pad_bits =3D 0, + .max_register =3D ANDES_I2C_TPM_REG, + .cache_type =3D REGCACHE_NONE, +}; + +static void andes_i2c_xfer_common(struct andes_i2c *i2c, u32 status) +{ + unsigned long flags; + unsigned int fsize =3D i2c->fifo_size; + unsigned int val; + + spin_lock_irqsave(&i2c->lock, flags); + if (status & ANDES_I2C_STATUS_FIFO_EMPTY) { + /* Disable the FIFO empty interrupt for the last write */ + if (i2c->buf_len <=3D fsize) { + fsize =3D i2c->buf_len; + regmap_clear_bits(i2c->map, ANDES_I2C_INTEN_REG, + ANDES_I2C_INTEN_FIFO_EMPTY); + } + + while (fsize--) { + val =3D *i2c->buf++; + regmap_write(i2c->map, ANDES_I2C_DATA_REG, val); + i2c->buf_len--; + } + } else if (status & ANDES_I2C_STATUS_FIFO_FULL) { + while (fsize--) { + regmap_read(i2c->map, ANDES_I2C_DATA_REG, &val); + *i2c->buf++ =3D (u8)val; + i2c->buf_len--; + } + } + + if (status & ANDES_I2C_STATUS_CMPL) { + i2c->xfer_done =3D true; + if (status & ANDES_I2C_STATUS_ADDR_HIT) + i2c->addr_hit =3D true; + + /* Write 1 to clear the status */ + regmap_set_bits(i2c->map, ANDES_I2C_STATUS_REG, + ANDES_I2C_STATUS_W1C); + + /* For the last read, retrieve all remaining data in FIFO. */ + while (i2c->buf_len > 0) { + regmap_read(i2c->map, ANDES_I2C_DATA_REG, &val); + *i2c->buf++ =3D (u8)val; + i2c->buf_len--; + } + } + + spin_unlock_irqrestore(&i2c->lock, flags); +} + +static irqreturn_t andes_i2c_irq_handler(int irq, void *data) +{ + struct andes_i2c *i2c =3D data; + u32 i2c_status; + + regmap_read(i2c->map, ANDES_I2C_STATUS_REG, &i2c_status); + andes_i2c_xfer_common(i2c, i2c_status); + if (i2c->xfer_done) + complete(&i2c->completion); + + return IRQ_HANDLED; +} + +static int andes_i2c_xfer_wait(struct andes_i2c *i2c, struct i2c_msg *msg) +{ + unsigned int mask; + unsigned int i2c_ctrl; + + /* + * Set the data count. If there are 256 bytes to be transmitted, write + * zero to the data count field. + */ + regmap_update_bits(i2c->map, ANDES_I2C_CTRL_REG, + ANDES_I2C_CTRL_DATA_CNT, + FIELD_PREP(ANDES_I2C_CTRL_DATA_CNT, i2c->buf_len)); + + regmap_set_bits(i2c->map, ANDES_I2C_CTRL_REG, ANDES_I2C_CTRL_PHASE); + if (msg->flags & I2C_M_RD) + regmap_set_bits(i2c->map, ANDES_I2C_CTRL_REG, + ANDES_I2C_CTRL_DIR); + else + regmap_clear_bits(i2c->map, ANDES_I2C_CTRL_REG, + ANDES_I2C_CTRL_DIR); + + regmap_write(i2c->map, ANDES_I2C_ADDR_REG, msg->addr); + + if (i2c->irq >=3D 0) { + mask =3D ANDES_I2C_INTEN_CMPL; + mask |=3D (msg->flags & I2C_M_RD) ? ANDES_I2C_INTEN_FIFO_FULL + : ANDES_I2C_INTEN_FIFO_EMPTY; + regmap_set_bits(i2c->map, ANDES_I2C_INTEN_REG, mask); + } + + regmap_set_bits(i2c->map, ANDES_I2C_CMD_REG, ANDES_I2C_CMD_TRANS); + if (i2c->irq >=3D 0) { + unsigned long time_left; + + time_left =3D wait_for_completion_timeout(&i2c->completion, + ANDES_I2C_TIMEOUT); + if (!time_left) + return -ETIMEDOUT; + + if (!i2c->addr_hit) + return -ENXIO; + + regmap_write(i2c->map, ANDES_I2C_INTEN_REG, 0); + reinit_completion(&i2c->completion); + } else { + unsigned int val; + int ret; + + mask =3D ANDES_I2C_STATUS_CMPL; + mask |=3D (msg->flags & I2C_M_RD) ? ANDES_I2C_STATUS_FIFO_FULL + : ANDES_I2C_STATUS_FIFO_EMPTY; + while (!i2c->xfer_done) { + ret =3D regmap_read_poll_timeout(i2c->map, + ANDES_I2C_STATUS_REG, + val, val & mask, 2000, + ANDES_I2C_TIMEOUT_US); + if (ret) + return ret; + + andes_i2c_xfer_common(i2c, val); + } + + if (!i2c->addr_hit) + return -ENXIO; + } + + /* Check if all data is successfully transmitted */ + regmap_read(i2c->map, ANDES_I2C_CTRL_REG, &i2c_ctrl); + if (FIELD_GET(ANDES_I2C_CTRL_DATA_CNT, i2c_ctrl)) + return -EIO; + + return 0; +} + +static int andes_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, + int num) +{ + int i; + struct i2c_msg *m; + struct andes_i2c *i2c =3D i2c_get_adapdata(adap); + int ret; + + for (i =3D 0; i < num; i++) { + m =3D &msg[i]; + i2c->addr_hit =3D false; + i2c->buf =3D m->buf; + i2c->buf_len =3D m->len; + i2c->xfer_done =3D false; + ret =3D andes_i2c_xfer_wait(i2c, m); + if (ret < 0) + return ret; + } + + return num; +} + +static u32 andes_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static struct i2c_algorithm andes_i2c_algo =3D { + .xfer =3D andes_i2c_xfer, + .functionality =3D andes_i2c_func, +}; + +static const struct i2c_adapter_quirks andes_i2c_quirks =3D { + .flags =3D I2C_AQ_NO_ZERO_LEN, + .max_write_len =3D ANDES_I2C_MAX_DATA_LEN, + .max_read_len =3D ANDES_I2C_MAX_DATA_LEN, +}; + +static int andes_i2c_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct andes_i2c *i2c; + void __iomem *reg_base; + u32 i2c_id; + int ret; + struct i2c_adapter *adap; + + i2c =3D devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg_base)) + return dev_err_probe(dev, PTR_ERR(reg_base), + "failed to map I/O space\n"); + + i2c->map =3D devm_regmap_init_mmio(dev, reg_base, + &andes_i2c_regmap_config); + if (IS_ERR(i2c->map)) + return dev_err_probe(dev, PTR_ERR(i2c->map), + "failed to initialize regmap\n"); + + regmap_read(i2c->map, ANDES_I2C_ID_REG, &i2c_id); + if (FIELD_GET(ANDES_I2C_ID_MASK, i2c_id) !=3D ANDES_I2C_ID) + return dev_err_probe(dev, -ENODEV, "unmatched hardware ID 0x%x\n", + i2c_id); + + i2c->irq =3D platform_get_irq(pdev, 0); + if (i2c->irq >=3D 0) { + ret =3D devm_request_irq(dev, i2c->irq, andes_i2c_irq_handler, 0, + dev_name(dev), i2c); + if (ret < 0) + return dev_err_probe(dev, ret, "unable to request IRQ %d\n", + i2c->irq); + } else { + dev_warn(dev, "no IRQ resource, falling back to poll mode\n"); + } + + spin_lock_init(&i2c->lock); + init_completion(&i2c->completion); + adap =3D &i2c->adap; + strscpy(adap->name, pdev->name, sizeof(adap->name)); + adap->algo =3D &andes_i2c_algo; + adap->class =3D I2C_CLASS_HWMON; + adap->dev.parent =3D dev; + adap->dev.of_node =3D dev->of_node; + adap->owner =3D THIS_MODULE; + adap->quirks =3D &andes_i2c_quirks; + adap->retries =3D 1; + adap->timeout =3D ANDES_I2C_TIMEOUT; + i2c_set_adapdata(adap, i2c); + platform_set_drvdata(pdev, i2c); + ret =3D devm_i2c_add_adapter(dev, adap); + if (ret) + return dev_err_probe(dev, ret, "failed to add adapter\n"); + + regmap_read(i2c->map, ANDES_I2C_CFG_REG, &i2c->fifo_size); + i2c->fifo_size =3D 2 << FIELD_GET(ANDES_I2C_CFG_FIFOSIZE, i2c->fifo_size); + + regmap_set_bits(i2c->map, ANDES_I2C_SETUP_REG, + ANDES_I2C_SETUP_IICEN | ANDES_I2C_SETUP_REQ); + return 0; +} + +static const struct of_device_id andes_i2c_of_match[] =3D { + { .compatible =3D "andestech,ae350-i2c" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, andes_i2c_of_match); + +static struct platform_driver andes_i2c_platform_driver =3D { + .driver =3D { + .name =3D "andes_i2c", + .of_match_table =3D andes_i2c_of_match, + }, + .probe =3D andes_i2c_probe, +}; + +module_platform_driver(andes_i2c_platform_driver); + +MODULE_AUTHOR("Ben Zong-You Xie "); +MODULE_DESCRIPTION("Andes I2C controller driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Tue Sep 29 06:59:41 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97BB23F3293; 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Signed-off-by: Ben Zong-You Xie --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 15011f5752a9..d1727fd0e83e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1938,6 +1938,12 @@ S: Supported F: Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml F: drivers/watchdog/atcwdt200_wdt.c =20 +ANDES I2C DRIVER +M: Ben Zong-You Xie +S: Supported +F: Documentation/devicetree/bindings/i2c/andestech,ae350-i2c.yaml +F: drivers/i2c/busses/i2c-andes.c + ANDROID DRIVERS M: Greg Kroah-Hartman M: Arve Hj=C3=B8nnev=C3=A5g --=20 2.34.1 From nobody Tue Sep 29 06:59:41 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A04643F39CB; Tue, 11 Aug 2026 06:29:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786429790; cv=none; b=guqiI9XHIBG5jJHxxunSf9Wy3p8zOmGMQhR0j+MzJ/acqQ7WIQ3rDVp1oLVMkzRIeskkxU9eh2kxxnVn7yUcDCJhWFNqGbm6Wyk3mkU8CvTo7FceLoKBqMFrsQUa+YeS9M09HVWrBa6+kpvDEWcbHCABJKONmkwCn21VAR5DV6o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786429790; c=relaxed/simple; bh=YUyTnratnqlECwzSAzk6FREP35eA7ZpjXULZWweNn00=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XlSoD/gyBaNoTADJtqBeAJCn05Ug4xrqboF/ZnO5lcYkfzsPSYQ7trWF4R0Oj4/7nycAA5fkmcyCRK2ScdUk1AHbYIKGhLnSK0kr6rEXhWDBjNeWua/hFvbsS8J852UeUqYgyYWgREdLbbqttNyNz+bqJ7BFreInrnSdDBrjBqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qegK+1IY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qegK+1IY" Received: by smtp.kernel.org (Postfix) with ESMTPS id 636CDC2BCFD; Tue, 11 Aug 2026 06:29:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786429790; bh=YUyTnratnqlECwzSAzk6FREP35eA7ZpjXULZWweNn00=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qegK+1IYLJRmJs1FNoA0zUkyYS/g7nJ+HWHBOgrj8pVKZKrZ4GTxftJaLXznYjTqF Ehth2vgSYI6jge/7n0WF/4oi1zdA3jtaFVgjPLYsVKTjZsunQbYpOifzsoTZ60kB2g FPylP6RNMnFv67CGWtysULNjSuZgDLwOpTE2Cwooqaj9MfNhoaxdsANqO4pcyJ5qPK m/054y+unWcCI7VV6sw8opxsx7K0QveXKpsWGJAhSvt6Ou7r3q/JPEYGDEYIAFfl8C DKGxpde7ijMp3NylUDKpfzKH0LsCoQdI7DO1amnpJ5uQUq/WMvo+akrrP25S/ZBM2t E64p67DWSAb9g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 492E4C5B573; Tue, 11 Aug 2026 06:29:50 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Tue, 11 Aug 2026 14:29:51 +0800 Subject: [PATCH v5 4/4] riscv: dts: andes: qilai: add I2C controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260811-atciic100-v5-4-1d306c21dba3@andestech.com> References: <20260811-atciic100-v5-0-1d306c21dba3@andestech.com> In-Reply-To: <20260811-atciic100-v5-0-1d306c21dba3@andestech.com> To: Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Ben Zong-You Xie X-Mailer: b4 0.15-dev-09770 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786429789; l=723; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=lHt2jE6+LDmM/nXD6n9TCCx5A6rJ3cqG+Q1RYfyMh24=; b=7qBBUukN4Q697T7Q52OnZqnGftXQt9gJBiL/RXCNLMZnybjenZ/TxkgbyDH8lSLYgHYtZQqlc MAGN2U/1Z84ClDt+A1AmpCbVus6K5zL+IfG5Zf1F3Oiy2C4kRgQxsIZ X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie Add the I2C node to QiLai DTS. Signed-off-by: Ben Zong-You Xie --- arch/riscv/boot/dts/andes/qilai.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/and= es/qilai.dtsi index de3de32f8c39..8b40f4d7f8d5 100644 --- a/arch/riscv/boot/dts/andes/qilai.dtsi +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -182,5 +182,12 @@ uart0: serial@30300000 { reg-io-width =3D <4>; no-loopback-test; }; + + i2c: i2c@30800000 { + compatible =3D "andestech,qilai-i2c", + "andestech,ae350-i2c"; + reg =3D <0x0 0x30800000 0x0 0x100000>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; --=20 2.34.1