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([187.15.140.84]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080a6f414sm430309066b.17.2026.08.10.12.42.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 12:42:26 -0700 (PDT) From: Nicholas Dudar To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, tsbogend@alpha.franken.de, johan.almbladh@anyfinetworks.com, paulburton@kernel.org Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, philmd@oss.qualcomm.com, bpf@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH bpf-next v3 1/3] bpf, mips: Factor out div/mod emission helpers Date: Mon, 10 Aug 2026 15:42:13 -0400 Message-Id: <20260810194215.3754591-2-main.kalliope@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260810194215.3754591-1-main.kalliope@gmail.com> References: <20260810194215.3754591-1-main.kalliope@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Factor MIPS32 and MIPS64 division and modulo emission out of emit_alu_r() and emit_alu_r64(). This prepares the JITs to select signed or unsigned opcodes without duplicating the R6 and pre-R6 handling. No functional change intended. Suggested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Nicholas Dudar --- arch/mips/net/bpf_jit_comp.c | 36 ++++++++++++++++++++++------------ arch/mips/net/bpf_jit_comp64.c | 36 ++++++++++++++++++++++------------ 2 files changed, 48 insertions(+), 24 deletions(-) diff --git a/arch/mips/net/bpf_jit_comp.c b/arch/mips/net/bpf_jit_comp.c index 6ee4abe6a1f7..320180330fb3 100644 --- a/arch/mips/net/bpf_jit_comp.c +++ b/arch/mips/net/bpf_jit_comp.c @@ -338,6 +338,28 @@ void emit_alu_i(struct jit_context *ctx, u8 dst, s32 i= mm, u8 op) clobber_reg(ctx, dst); } =20 +/* ALU division operation (32-bit) */ +static void emit_div(struct jit_context *ctx, u8 dst, u8 src) +{ + if (cpu_has_mips32r6) { + emit(ctx, divu_r6, dst, dst, src); + } else { + emit(ctx, divu, dst, src); + emit(ctx, mflo, dst); + } +} + +/* ALU modulo operation (32-bit) */ +static void emit_mod(struct jit_context *ctx, u8 dst, u8 src) +{ + if (cpu_has_mips32r6) { + emit(ctx, modu, dst, dst, src); + } else { + emit(ctx, divu, dst, src); + emit(ctx, mfhi, dst); + } +} + /* ALU register operation (32-bit) */ void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op) { @@ -385,21 +407,11 @@ void emit_alu_r(struct jit_context *ctx, u8 dst, u8 s= rc, u8 op) break; /* dst =3D dst / src */ case BPF_DIV: - if (cpu_has_mips32r6) { - emit(ctx, divu_r6, dst, dst, src); - } else { - emit(ctx, divu, dst, src); - emit(ctx, mflo, dst); - } + emit_div(ctx, dst, src); break; /* dst =3D dst % src */ case BPF_MOD: - if (cpu_has_mips32r6) { - emit(ctx, modu, dst, dst, src); - } else { - emit(ctx, divu, dst, src); - emit(ctx, mfhi, dst); - } + emit_mod(ctx, dst, src); break; } clobber_reg(ctx, dst); diff --git a/arch/mips/net/bpf_jit_comp64.c b/arch/mips/net/bpf_jit_comp64.c index fa7e9aa37f49..2520e1db7ab7 100644 --- a/arch/mips/net/bpf_jit_comp64.c +++ b/arch/mips/net/bpf_jit_comp64.c @@ -197,6 +197,28 @@ static void emit_alu_i64(struct jit_context *ctx, u8 d= st, s32 imm, u8 op) clobber_reg(ctx, dst); } =20 +/* ALU division operation (64-bit) */ +static void emit_div64(struct jit_context *ctx, u8 dst, u8 src) +{ + if (cpu_has_mips64r6) { + emit(ctx, ddivu_r6, dst, dst, src); + } else { + emit(ctx, ddivu, dst, src); + emit(ctx, mflo, dst); + } +} + +/* ALU modulo operation (64-bit) */ +static void emit_mod64(struct jit_context *ctx, u8 dst, u8 src) +{ + if (cpu_has_mips64r6) { + emit(ctx, dmodu, dst, dst, src); + } else { + emit(ctx, ddivu, dst, src); + emit(ctx, mfhi, dst); + } +} + /* ALU register operation (64-bit) */ static void emit_alu_r64(struct jit_context *ctx, u8 dst, u8 src, u8 op) { @@ -235,21 +257,11 @@ static void emit_alu_r64(struct jit_context *ctx, u8 = dst, u8 src, u8 op) break; /* dst =3D dst / src */ case BPF_DIV: - if (cpu_has_mips64r6) { - emit(ctx, ddivu_r6, dst, dst, src); - } else { - emit(ctx, ddivu, dst, src); - emit(ctx, mflo, dst); - } + emit_div64(ctx, dst, src); break; /* dst =3D dst % src */ case BPF_MOD: - if (cpu_has_mips64r6) { - emit(ctx, dmodu, dst, dst, src); - } else { - emit(ctx, ddivu, dst, src); - emit(ctx, mfhi, dst); - } + emit_mod64(ctx, dst, src); break; default: /* Width-generic operations */ From nobody Tue Sep 29 07:39:15 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0630D44470A for ; Mon, 10 Aug 2026 19:42:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786390959; cv=none; b=UGHURJ7lOw8wsZwEWervAYIwzRP11z4HMZ3h0HSkyr8wroVWcaS3M+39IelryrRzzvcNOOXiIKAxOV+hJVrHOqwBMx8OTB1HkhlWbm5/11ZdzIOCUdNwg2GHibOE5VzUIWZ7YaNq95fXFITqdjCYZimOECTNctclgnEmVu7FARQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786390959; c=relaxed/simple; bh=W485Ps4F9bQqeQYrJN3IRGl+zarYhizxFCivRtuP0Xo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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([187.15.140.84]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080a6f414sm430309066b.17.2026.08.10.12.42.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 12:42:31 -0700 (PDT) From: Nicholas Dudar To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, tsbogend@alpha.franken.de, johan.almbladh@anyfinetworks.com, paulburton@kernel.org Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, philmd@oss.qualcomm.com, bpf@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH bpf-next v3 2/3] MIPS: uasm: Add signed div/mod emitters Date: Mon, 10 Aug 2026 15:42:14 -0400 Message-Id: <20260810194215.3754591-3-main.kalliope@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260810194215.3754591-1-main.kalliope@gmail.com> References: <20260810194215.3754591-1-main.kalliope@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add uasm emitters for the signed DIV, MOD, DDIV, and DMOD instructions. Provide both pre-R6 and R6 division forms so users can select the instruction appropriate for the target ISA. Assisted-by: Codex:gpt-5.6-sol Link: https://lore.kernel.org/bpf/CAM1=3D_QS79dDBfaaNQXnWd61AqHd1M4o9aDMMif= tnoJveNr=3DFZg@mail.gmail.com/ Signed-off-by: Nicholas Dudar --- arch/mips/include/asm/uasm.h | 6 ++++++ arch/mips/mm/uasm-mips.c | 10 ++++++++++ arch/mips/mm/uasm.c | 20 ++++++++++++++------ 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index b43bfd445252..9d3edb59efc0 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -85,15 +85,20 @@ Ip_u1u2(_ctc1); Ip_u2u1(_ctcmsa); Ip_u2u1s3(_daddiu); Ip_u3u1u2(_daddu); +Ip_u1u2(_ddiv); +Ip_u3u1u2(_ddiv_r6); Ip_u1u2(_ddivu); Ip_u3u1u2(_ddivu_r6); Ip_u1(_di); Ip_u2u1msbu3(_dins); Ip_u2u1msbu3(_dinsm); Ip_u2u1msbu3(_dinsu); +Ip_u1u2(_div); +Ip_u3u1u2(_div_r6); Ip_u1u2(_divu); Ip_u3u1u2(_divu_r6); Ip_u1u2u3(_dmfc0); +Ip_u3u1u2(_dmod); Ip_u3u1u2(_dmodu); Ip_u1u2u3(_dmtc0); Ip_u1u2(_dmultu); @@ -135,6 +140,7 @@ Ip_u1u2u3(_mfc0); Ip_u1u2u3(_mfhc0); Ip_u1(_mfhi); Ip_u1(_mflo); +Ip_u3u1u2(_mod); Ip_u3u1u2(_modu); Ip_u3u1u2(_movn); Ip_u3u1u2(_movz); diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c index e15c6700cd08..ef1a2b040070 100644 --- a/arch/mips/mm/uasm-mips.c +++ b/arch/mips/mm/uasm-mips.c @@ -75,6 +75,9 @@ static const struct insn insn_table[insn_invalid] =3D { [insn_ctcmsa] =3D {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE}, [insn_daddiu] =3D {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, [insn_daddu] =3D {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD}, + [insn_ddiv] =3D {M(spec_op, 0, 0, 0, 0, ddiv_op), RS | RT}, + [insn_ddiv_r6] =3D {M(spec_op, 0, 0, 0, ddiv_ddiv6_op, ddiv_op), + RS | RT | RD}, [insn_ddivu] =3D {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT}, [insn_ddivu_r6] =3D {M(spec_op, 0, 0, 0, ddivu_ddivu6_op, ddivu_op), RS | RT | RD}, @@ -82,10 +85,15 @@ static const struct insn insn_table[insn_invalid] =3D { [insn_dins] =3D {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE}, [insn_dinsm] =3D {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE}, [insn_dinsu] =3D {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE}, + [insn_div] =3D {M(spec_op, 0, 0, 0, 0, div_op), RS | RT}, + [insn_div_r6] =3D {M(spec_op, 0, 0, 0, div_div6_op, div_op), + RS | RT | RD}, [insn_divu] =3D {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT}, [insn_divu_r6] =3D {M(spec_op, 0, 0, 0, divu_divu6_op, divu_op), RS | RT | RD}, [insn_dmfc0] =3D {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, + [insn_dmod] =3D {M(spec_op, 0, 0, 0, ddiv_dmod_op, ddiv_op), + RS | RT | RD}, [insn_dmodu] =3D {M(spec_op, 0, 0, 0, ddivu_dmodu_op, ddivu_op), RS | RT | RD}, [insn_dmtc0] =3D {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, @@ -140,6 +148,8 @@ static const struct insn insn_table[insn_invalid] =3D { [insn_mfhc0] =3D {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET}, [insn_mfhi] =3D {M(spec_op, 0, 0, 0, 0, mfhi_op), RD}, [insn_mflo] =3D {M(spec_op, 0, 0, 0, 0, mflo_op), RD}, + [insn_mod] =3D {M(spec_op, 0, 0, 0, div_mod_op, div_op), + RS | RT | RD}, [insn_modu] =3D {M(spec_op, 0, 0, 0, divu_modu_op, divu_op), RS | RT | RD}, [insn_movn] =3D {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD}, diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 125140979d62..06d722665451 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -49,18 +49,20 @@ enum opcode { insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez, insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1, - insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu, - insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, - insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu, + insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddiv, + insn_ddiv_r6, insn_ddivu, insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, + insn_dinsu, insn_div, insn_div_r6, insn_divu, insn_divu_r6, insn_dmfc0, + insn_dmod, insn_dmodu, insn_dmtc0, insn_dmultu, insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, - insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0, - insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_no= r, - insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc, + insn_mflo, insn_mod, insn_modu, insn_movn, insn_movz, insn_mtc0, + insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, + insn_muhu, insn_nor, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, + insn_sb, insn_sc, insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll, insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, @@ -287,9 +289,12 @@ I_u1u2(_cfc1) I_u2u1(_cfcmsa) I_u1u2(_ctc1) I_u2u1(_ctcmsa) +I_u1u2(_ddiv) +I_u3u1u2(_ddiv_r6) I_u1u2(_ddivu) I_u3u1u2(_ddivu_r6) I_u1u2u3(_dmfc0) +I_u3u1u2(_dmod) I_u3u1u2(_dmodu) I_u1u2u3(_dmtc0) I_u1u2(_dmultu) @@ -297,6 +302,8 @@ I_u3u1u2(_dmulu) I_u2u1s3(_daddiu) I_u3u1u2(_daddu) I_u1(_di); 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([187.15.140.84]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080a6f414sm430309066b.17.2026.08.10.12.42.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 12:42:35 -0700 (PDT) From: Nicholas Dudar To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, tsbogend@alpha.franken.de, johan.almbladh@anyfinetworks.com, paulburton@kernel.org Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, philmd@oss.qualcomm.com, bpf@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH bpf-next v3 3/3] bpf, mips: Add support for BPF_SDIV and BPF_SMOD Date: Mon, 10 Aug 2026 15:42:15 -0400 Message-Id: <20260810194215.3754591-4-main.kalliope@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260810194215.3754591-1-main.kalliope@gmail.com> References: <20260810194215.3754591-1-main.kalliope@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MIPS JITs handle BPF_DIV and BPF_MOD without inspecting insn->off, which distinguishes BPF_SDIV and BPF_SMOD. Signed operations therefore use unsigned instructions, or unsigned helpers for ALU64 on 32-bit MIPS, and produce unsigned results for negative operands. Pass insn->off unchanged through immediate validation and register emission, and interpret it only in div/mod-specific paths. Use signed DIV/DDIV for pre-R6 and DIV/MOD/DDIV/DMOD for R6. On 32-bit MIPS, use div64_s64() and a signed remainder helper for ALU64. Keep the signed quotient signed while computing that remainder, and keep signed immediates out of the unsigned power-of-two shift/mask rewrite. check_alu_op() rejects immediate zero divisors. bpf_do_misc_fixups() rewrites signed immediate -1 and guards register divisors that are zero or, for signed operations, -1 before JIT compilation. The ALU32 paths continue to zero-extend their results. The remaining test_bpf failures are five MOVSX, eight BSWAP, three MEMSX, and one JMP32_JA. MOVSX and MEMSX will be addressed separately; Johan Almbladh is handling BSWAP and JMP32_JA. Found while auditing BPF JIT handling of signed div/mod. Assisted-by: Codex:gpt-5.6-sol Link: https://lore.kernel.org/bpf/CAM1=3D_QS79dDBfaaNQXnWd61AqHd1M4o9aDMMif= tnoJveNr=3DFZg@mail.gmail.com/ Link: https://lore.kernel.org/bpf/CAM1=3D_QQ7XiJEozaetLt_+kVn91YAXWpJK_pyfT= 9=3DpaXseW=3DwwA@mail.gmail.com/ Signed-off-by: Nicholas Dudar --- arch/mips/net/bpf_jit_comp.c | 35 ++++++++++++++++------- arch/mips/net/bpf_jit_comp.h | 4 +-- arch/mips/net/bpf_jit_comp32.c | 29 ++++++++++++------- arch/mips/net/bpf_jit_comp64.c | 51 +++++++++++++++++++++------------- 4 files changed, 78 insertions(+), 41 deletions(-) diff --git a/arch/mips/net/bpf_jit_comp.c b/arch/mips/net/bpf_jit_comp.c index 320180330fb3..f14de6d73122 100644 --- a/arch/mips/net/bpf_jit_comp.c +++ b/arch/mips/net/bpf_jit_comp.c @@ -208,7 +208,7 @@ void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src) } =20 /* Validate ALU immediate range */ -bool valid_alu_i(u8 op, s32 imm) +bool valid_alu_i(u8 op, s32 imm, s16 off) { switch (BPF_OP(op)) { case BPF_NEG: @@ -237,6 +237,9 @@ bool valid_alu_i(u8 op, s32 imm) return imm =3D=3D 0 || (imm > 0 && is_power_of_2(imm)); case BPF_DIV: case BPF_MOD: + /* Do not use unsigned shift/mask rewrites for signed div/mod. */ + if (off =3D=3D 1) + return false; /* imm must be an 17-bit power of two */ return (u32)imm <=3D 0x10000 && is_power_of_2((u32)imm); } @@ -339,29 +342,41 @@ void emit_alu_i(struct jit_context *ctx, u8 dst, s32 = imm, u8 op) } =20 /* ALU division operation (32-bit) */ -static void emit_div(struct jit_context *ctx, u8 dst, u8 src) +static void emit_div(struct jit_context *ctx, u8 dst, u8 src, s16 off) { if (cpu_has_mips32r6) { - emit(ctx, divu_r6, dst, dst, src); + if (off =3D=3D 1) + emit(ctx, div_r6, dst, dst, src); + else + emit(ctx, divu_r6, dst, dst, src); } else { - emit(ctx, divu, dst, src); + if (off =3D=3D 1) + emit(ctx, div, dst, src); + else + emit(ctx, divu, dst, src); emit(ctx, mflo, dst); } } =20 /* ALU modulo operation (32-bit) */ -static void emit_mod(struct jit_context *ctx, u8 dst, u8 src) +static void emit_mod(struct jit_context *ctx, u8 dst, u8 src, s16 off) { if (cpu_has_mips32r6) { - emit(ctx, modu, dst, dst, src); + if (off =3D=3D 1) + emit(ctx, mod, dst, dst, src); + else + emit(ctx, modu, dst, dst, src); } else { - emit(ctx, divu, dst, src); + if (off =3D=3D 1) + emit(ctx, div, dst, src); + else + emit(ctx, divu, dst, src); emit(ctx, mfhi, dst); } } =20 /* ALU register operation (32-bit) */ -void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op) +void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op, s16 off) { switch (BPF_OP(op)) { /* dst =3D dst & src */ @@ -407,11 +422,11 @@ void emit_alu_r(struct jit_context *ctx, u8 dst, u8 s= rc, u8 op) break; /* dst =3D dst / src */ case BPF_DIV: - emit_div(ctx, dst, src); + emit_div(ctx, dst, src, off); break; /* dst =3D dst % src */ case BPF_MOD: - emit_mod(ctx, dst, src); + emit_mod(ctx, dst, src, off); break; } clobber_reg(ctx, dst); diff --git a/arch/mips/net/bpf_jit_comp.h b/arch/mips/net/bpf_jit_comp.h index a37fe20818eb..0ddedb733dd1 100644 --- a/arch/mips/net/bpf_jit_comp.h +++ b/arch/mips/net/bpf_jit_comp.h @@ -163,7 +163,7 @@ void emit_mov_i(struct jit_context *ctx, u8 dst, s32 im= m); void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src); =20 /* Validate ALU/ALU64 immediate range */ -bool valid_alu_i(u8 op, s32 imm); +bool valid_alu_i(u8 op, s32 imm, s16 off); =20 /* Rewrite ALU/ALU64 immediate operation */ bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val); @@ -172,7 +172,7 @@ bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val); void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op); =20 /* ALU register operation (32-bit) */ -void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op); +void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op, s16 off); =20 /* Atomic read-modify-write (32-bit) */ void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 co= de); diff --git a/arch/mips/net/bpf_jit_comp32.c b/arch/mips/net/bpf_jit_comp32.c index 40a878b672f5..6619182b5ef3 100644 --- a/arch/mips/net/bpf_jit_comp32.c +++ b/arch/mips/net/bpf_jit_comp32.c @@ -512,7 +512,7 @@ static void emit_mul_r64(struct jit_context *ctx, clobber_reg64(ctx, dst); } =20 -/* Helper function for 64-bit modulo */ +/* Helper function for unsigned 64-bit modulo */ static u64 jit_mod64(u64 a, u64 b) { u64 rem; @@ -521,13 +521,22 @@ static u64 jit_mod64(u64 a, u64 b) return rem; } =20 +/* Helper function for signed 64-bit modulo */ +static s64 jit_smod64(s64 a, s64 b) +{ + s64 quot =3D div64_s64(a, b); + + return a - quot * b; +} + /* ALU div/mod register (64-bit) */ -static void emit_divmod_r64(struct jit_context *ctx, - const u8 dst[], const u8 src[], u8 op) +static void emit_divmod_r64(struct jit_context *ctx, const u8 dst[], + const u8 src[], u8 op, s16 off) { const u8 *r0 =3D bpf2mips32[BPF_REG_0]; /* Mapped to v0-v1 */ const u8 *r1 =3D bpf2mips32[BPF_REG_1]; /* Mapped to a0-a1 */ const u8 *r2 =3D bpf2mips32[BPF_REG_2]; /* Mapped to a2-a3 */ + bool is_signed =3D off =3D=3D 1; int exclude, k; u32 addr =3D 0; =20 @@ -546,11 +555,11 @@ static void emit_divmod_r64(struct jit_context *ctx, switch (BPF_OP(op)) { /* dst =3D dst / src */ case BPF_DIV: - addr =3D (u32)&div64_u64; + addr =3D is_signed ? (u32)&div64_s64 : (u32)&div64_u64; break; /* dst =3D dst % src */ case BPF_MOD: - addr =3D (u32)&jit_mod64; + addr =3D is_signed ? (u32)&jit_smod64 : (u32)&jit_mod64; break; } emit_mov_i(ctx, MIPS_R_T9, addr); @@ -1516,9 +1525,9 @@ int build_insn(const struct bpf_insn *insn, struct ji= t_context *ctx) case BPF_ALU | BPF_MUL | BPF_K: case BPF_ALU | BPF_DIV | BPF_K: case BPF_ALU | BPF_MOD | BPF_K: - if (!valid_alu_i(BPF_OP(code), imm)) { + if (!valid_alu_i(BPF_OP(code), imm, off)) { emit_mov_i(ctx, MIPS_R_T6, imm); - emit_alu_r(ctx, lo(dst), MIPS_R_T6, BPF_OP(code)); + emit_alu_r(ctx, lo(dst), MIPS_R_T6, BPF_OP(code), off); } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { emit_alu_i(ctx, lo(dst), val, alu); } @@ -1546,7 +1555,7 @@ int build_insn(const struct bpf_insn *insn, struct ji= t_context *ctx) case BPF_ALU | BPF_MUL | BPF_X: case BPF_ALU | BPF_DIV | BPF_X: case BPF_ALU | BPF_MOD | BPF_X: - emit_alu_r(ctx, lo(dst), lo(src), BPF_OP(code)); + emit_alu_r(ctx, lo(dst), lo(src), BPF_OP(code), off); emit_zext_ver(ctx, dst); break; /* dst =3D imm (64-bit) */ @@ -1599,7 +1608,7 @@ int build_insn(const struct bpf_insn *insn, struct ji= t_context *ctx) * and then do the operation on this register. */ emit_mov_se_i64(ctx, tmp, imm); - emit_divmod_r64(ctx, dst, tmp, BPF_OP(code)); + emit_divmod_r64(ctx, dst, tmp, BPF_OP(code), off); break; /* dst =3D dst & src (64-bit) */ /* dst =3D dst | src (64-bit) */ @@ -1629,7 +1638,7 @@ int build_insn(const struct bpf_insn *insn, struct ji= t_context *ctx) /* dst =3D dst % src (64-bit) */ case BPF_ALU64 | BPF_DIV | BPF_X: case BPF_ALU64 | BPF_MOD | BPF_X: - emit_divmod_r64(ctx, dst, src, BPF_OP(code)); + emit_divmod_r64(ctx, dst, src, BPF_OP(code), off); break; /* dst =3D htole(dst) */ /* dst =3D htobe(dst) */ diff --git a/arch/mips/net/bpf_jit_comp64.c b/arch/mips/net/bpf_jit_comp64.c index 2520e1db7ab7..db027c2d9221 100644 --- a/arch/mips/net/bpf_jit_comp64.c +++ b/arch/mips/net/bpf_jit_comp64.c @@ -198,29 +198,42 @@ static void emit_alu_i64(struct jit_context *ctx, u8 = dst, s32 imm, u8 op) } =20 /* ALU division operation (64-bit) */ -static void emit_div64(struct jit_context *ctx, u8 dst, u8 src) +static void emit_div64(struct jit_context *ctx, u8 dst, u8 src, s16 off) { if (cpu_has_mips64r6) { - emit(ctx, ddivu_r6, dst, dst, src); + if (off =3D=3D 1) + emit(ctx, ddiv_r6, dst, dst, src); + else + emit(ctx, ddivu_r6, dst, dst, src); } else { - emit(ctx, ddivu, dst, src); + if (off =3D=3D 1) + emit(ctx, ddiv, dst, src); + else + emit(ctx, ddivu, dst, src); emit(ctx, mflo, dst); } } =20 /* ALU modulo operation (64-bit) */ -static void emit_mod64(struct jit_context *ctx, u8 dst, u8 src) +static void emit_mod64(struct jit_context *ctx, u8 dst, u8 src, s16 off) { if (cpu_has_mips64r6) { - emit(ctx, dmodu, dst, dst, src); + if (off =3D=3D 1) + emit(ctx, dmod, dst, dst, src); + else + emit(ctx, dmodu, dst, dst, src); } else { - emit(ctx, ddivu, dst, src); + if (off =3D=3D 1) + emit(ctx, ddiv, dst, src); + else + emit(ctx, ddivu, dst, src); emit(ctx, mfhi, dst); } } =20 /* ALU register operation (64-bit) */ -static void emit_alu_r64(struct jit_context *ctx, u8 dst, u8 src, u8 op) +static void emit_alu_r64(struct jit_context *ctx, u8 dst, u8 src, u8 op, + s16 off) { switch (BPF_OP(op)) { /* dst =3D dst << src */ @@ -257,15 +270,15 @@ static void emit_alu_r64(struct jit_context *ctx, u8 = dst, u8 src, u8 op) break; /* dst =3D dst / src */ case BPF_DIV: - emit_div64(ctx, dst, src); + emit_div64(ctx, dst, src, off); break; /* dst =3D dst % src */ case BPF_MOD: - emit_mod64(ctx, dst, src); + emit_mod64(ctx, dst, src, off); break; default: /* Width-generic operations */ - emit_alu_r(ctx, dst, src, op); + emit_alu_r(ctx, dst, src, op, off); } clobber_reg(ctx, dst); } @@ -686,9 +699,9 @@ int build_insn(const struct bpf_insn *insn, struct jit_= context *ctx) case BPF_ALU | BPF_AND | BPF_K: case BPF_ALU | BPF_XOR | BPF_K: case BPF_ALU | BPF_LSH | BPF_K: - if (!valid_alu_i(BPF_OP(code), imm)) { + if (!valid_alu_i(BPF_OP(code), imm, off)) { emit_mov_i(ctx, MIPS_R_T4, imm); - emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); + emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code), off); } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { emit_alu_i(ctx, dst, val, alu); } @@ -708,10 +721,10 @@ int build_insn(const struct bpf_insn *insn, struct ji= t_context *ctx) case BPF_ALU | BPF_MUL | BPF_K: case BPF_ALU | BPF_DIV | BPF_K: case BPF_ALU | BPF_MOD | BPF_K: - if (!valid_alu_i(BPF_OP(code), imm)) { + if (!valid_alu_i(BPF_OP(code), imm, off)) { emit_sext(ctx, dst, dst); emit_mov_i(ctx, MIPS_R_T4, imm); - emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); + emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code), off); } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { emit_sext(ctx, dst, dst); emit_alu_i(ctx, dst, val, alu); @@ -726,7 +739,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_= context *ctx) case BPF_ALU | BPF_OR | BPF_X: case BPF_ALU | BPF_XOR | BPF_X: case BPF_ALU | BPF_LSH | BPF_X: - emit_alu_r(ctx, dst, src, BPF_OP(code)); + emit_alu_r(ctx, dst, src, BPF_OP(code), off); emit_zext_ver(ctx, dst); break; /* dst =3D dst >> src */ @@ -745,7 +758,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_= context *ctx) case BPF_ALU | BPF_MOD | BPF_X: emit_sext(ctx, dst, dst); emit_sext(ctx, MIPS_R_T4, src); - emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); + emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code), off); emit_zext_ver(ctx, dst); break; /* dst =3D imm (64-bit) */ @@ -782,9 +795,9 @@ int build_insn(const struct bpf_insn *insn, struct jit_= context *ctx) case BPF_ALU64 | BPF_MUL | BPF_K: case BPF_ALU64 | BPF_DIV | BPF_K: case BPF_ALU64 | BPF_MOD | BPF_K: - if (!valid_alu_i(BPF_OP(code), imm)) { + if (!valid_alu_i(BPF_OP(code), imm, off)) { emit_mov_i(ctx, MIPS_R_T4, imm); - emit_alu_r64(ctx, dst, MIPS_R_T4, BPF_OP(code)); + emit_alu_r64(ctx, dst, MIPS_R_T4, BPF_OP(code), off); } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { emit_alu_i64(ctx, dst, val, alu); } @@ -811,7 +824,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_= context *ctx) case BPF_ALU64 | BPF_MUL | BPF_X: case BPF_ALU64 | BPF_DIV | BPF_X: case BPF_ALU64 | BPF_MOD | BPF_X: - emit_alu_r64(ctx, dst, src, BPF_OP(code)); + emit_alu_r64(ctx, dst, src, BPF_OP(code), off); break; /* dst =3D htole(dst) */ /* dst =3D htobe(dst) */