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charset="utf-8" From: Babu Moger For Intel, the memory controller is called Integrated Memory Controller (IMC). For AMD, it is called Unified Memory Controller (UMC). Rename the variables and functions from imc (Integrated Memory Controller) to the generic mc (Memory Controller) in preparation for the support of MBM and MBA tests on AMD. No functional change intended. Assisted-by: Claude:claude-opus-4.8 Signed-off-by: Babu Moger Co-developed-by: Swapnil Sapkal Signed-off-by: Swapnil Sapkal --- v3->v4: - Rebased onto v7.2-rc7. Reworked to match the upstream resctrl_val.c refactor that reads the memory bandwidth counters into a single read-event array. - Renamed the remaining Intel specific references missed in v3: the get_mem_bw_imc() helper, the imc_counter_config comments and the 'Mem_BW' bandwidth label. (Reinette) tools/testing/selftests/resctrl/mba_test.c | 26 +- tools/testing/selftests/resctrl/mbm_test.c | 22 +- tools/testing/selftests/resctrl/resctrl.h | 4 +- tools/testing/selftests/resctrl/resctrl_val.c | 240 +++++++++--------- 4 files changed, 146 insertions(+), 146 deletions(-) diff --git a/tools/testing/selftests/resctrl/mba_test.c b/tools/testing/sel= ftests/resctrl/mba_test.c index 39cee9898359..6c6c885eba5e 100644 --- a/tools/testing/selftests/resctrl/mba_test.c +++ b/tools/testing/selftests/resctrl/mba_test.c @@ -23,7 +23,7 @@ static int mba_init(const struct resctrl_test *test, { int ret; =20 - ret =3D initialize_read_mem_bw_imc(); + ret =3D initialize_read_mem_bw_mc(); if (ret) return ret; =20 @@ -73,7 +73,7 @@ static int mba_measure(const struct user_params *uparams, return measure_read_mem_bw(uparams, param, bm_pid); } =20 -static bool show_mba_info(unsigned long *bw_imc, unsigned long *bw_resc) +static bool show_mba_info(unsigned long *bw_mc, unsigned long *bw_resc) { unsigned int allocation; bool ret =3D false; @@ -83,27 +83,27 @@ static bool show_mba_info(unsigned long *bw_imc, unsign= ed long *bw_resc) /* Memory bandwidth from 100% down to 10% */ for (allocation =3D 0; allocation < ALLOCATION_MAX / ALLOCATION_STEP; allocation++) { - unsigned long sum_bw_imc =3D 0, sum_bw_resc =3D 0; - long avg_bw_imc, avg_bw_resc; + unsigned long sum_bw_mc =3D 0, sum_bw_resc =3D 0; + long avg_bw_mc, avg_bw_resc; int avg_diff_per; float avg_diff; =20 for (runs =3D NUM_OF_RUNS * allocation; runs < NUM_OF_RUNS * allocation + NUM_OF_RUNS ; runs++) { - sum_bw_imc +=3D bw_imc[runs]; + sum_bw_mc +=3D bw_mc[runs]; sum_bw_resc +=3D bw_resc[runs]; } =20 - avg_bw_imc =3D sum_bw_imc / NUM_OF_RUNS; + avg_bw_mc =3D sum_bw_mc / NUM_OF_RUNS; avg_bw_resc =3D sum_bw_resc / NUM_OF_RUNS; - if (avg_bw_imc < THROTTLE_THRESHOLD || avg_bw_resc < THROTTLE_THRESHOLD)= { + if (avg_bw_mc < THROTTLE_THRESHOLD || avg_bw_resc < THROTTLE_THRESHOLD) { ksft_print_msg("Bandwidth below threshold (%d MiB). Dropping results fr= om MBA schemata %u.\n", THROTTLE_THRESHOLD, ALLOCATION_MIN + ALLOCATION_STEP * allocation); continue; } =20 - avg_diff =3D (float)labs(avg_bw_resc - avg_bw_imc) / avg_bw_imc; + avg_diff =3D (float)labs(avg_bw_resc - avg_bw_mc) / avg_bw_mc; avg_diff_per =3D (int)(avg_diff * 100); =20 ksft_print_msg("%s Check MBA diff within %d%% for schemata %u\n", @@ -113,7 +113,7 @@ static bool show_mba_info(unsigned long *bw_imc, unsign= ed long *bw_resc) ALLOCATION_MIN + ALLOCATION_STEP * allocation); =20 ksft_print_msg("avg_diff_per: %d%%\n", avg_diff_per); - ksft_print_msg("avg_bw_imc: %lu\n", avg_bw_imc); + ksft_print_msg("avg_bw_mc: %lu\n", avg_bw_mc); ksft_print_msg("avg_bw_resc: %lu\n", avg_bw_resc); if (avg_diff_per > MAX_DIFF_PERCENT) ret =3D true; @@ -130,7 +130,7 @@ static bool show_mba_info(unsigned long *bw_imc, unsign= ed long *bw_resc) static int check_results(void) { unsigned long bw_resc[NUM_OF_RUNS * ALLOCATION_MAX / ALLOCATION_STEP]; - unsigned long bw_imc[NUM_OF_RUNS * ALLOCATION_MAX / ALLOCATION_STEP]; + unsigned long bw_mc[NUM_OF_RUNS * ALLOCATION_MAX / ALLOCATION_STEP]; char *token_array[8], output[] =3D RESULT_FILE_NAME, temp[512]; int runs; FILE *fp; @@ -152,8 +152,8 @@ static int check_results(void) token =3D strtok(NULL, ":\t"); } =20 - /* Field 3 is perf imc value */ - bw_imc[runs] =3D strtoul(token_array[3], NULL, 0); + /* Field 3 is perf mc value */ + bw_mc[runs] =3D strtoul(token_array[3], NULL, 0); /* Field 5 is resctrl value */ bw_resc[runs] =3D strtoul(token_array[5], NULL, 0); runs++; @@ -161,7 +161,7 @@ static int check_results(void) =20 fclose(fp); =20 - return show_mba_info(bw_imc, bw_resc); + return show_mba_info(bw_mc, bw_resc); } =20 static void mba_test_cleanup(void) diff --git a/tools/testing/selftests/resctrl/mbm_test.c b/tools/testing/sel= ftests/resctrl/mbm_test.c index 6dbbc3b76003..d89f71c58335 100644 --- a/tools/testing/selftests/resctrl/mbm_test.c +++ b/tools/testing/selftests/resctrl/mbm_test.c @@ -15,21 +15,21 @@ #define NUM_OF_RUNS 5 =20 static int -show_bw_info(unsigned long *bw_imc, unsigned long *bw_resc, size_t span) +show_bw_info(unsigned long *bw_mc, unsigned long *bw_resc, size_t span) { - unsigned long sum_bw_imc =3D 0, sum_bw_resc =3D 0; - long avg_bw_imc =3D 0, avg_bw_resc =3D 0; + unsigned long sum_bw_mc =3D 0, sum_bw_resc =3D 0; + long avg_bw_mc =3D 0, avg_bw_resc =3D 0; int runs, ret, avg_diff_per; float avg_diff =3D 0; =20 for (runs =3D 0; runs < NUM_OF_RUNS; runs++) { - sum_bw_imc +=3D bw_imc[runs]; + sum_bw_mc +=3D bw_mc[runs]; sum_bw_resc +=3D bw_resc[runs]; } =20 - avg_bw_imc =3D sum_bw_imc / NUM_OF_RUNS; + avg_bw_mc =3D sum_bw_mc / NUM_OF_RUNS; avg_bw_resc =3D sum_bw_resc / NUM_OF_RUNS; - avg_diff =3D (float)labs(avg_bw_resc - avg_bw_imc) / avg_bw_imc; + avg_diff =3D (float)labs(avg_bw_resc - avg_bw_mc) / avg_bw_mc; avg_diff_per =3D (int)(avg_diff * 100); =20 ret =3D avg_diff_per > MAX_DIFF_PERCENT; @@ -38,7 +38,7 @@ show_bw_info(unsigned long *bw_imc, unsigned long *bw_res= c, size_t span) ksft_print_msg("avg_diff_per: %d%%\n", avg_diff_per); if (span) ksft_print_msg("Span (MB): %zu\n", span / MB); - ksft_print_msg("avg_bw_imc: %lu\n", avg_bw_imc); + ksft_print_msg("avg_bw_mc: %lu\n", avg_bw_mc); ksft_print_msg("avg_bw_resc: %lu\n", avg_bw_resc); =20 return ret; @@ -46,7 +46,7 @@ show_bw_info(unsigned long *bw_imc, unsigned long *bw_res= c, size_t span) =20 static int check_results(size_t span) { - unsigned long bw_imc[NUM_OF_RUNS], bw_resc[NUM_OF_RUNS]; + unsigned long bw_mc[NUM_OF_RUNS], bw_resc[NUM_OF_RUNS]; char temp[1024], *token_array[8]; char output[] =3D RESULT_FILE_NAME; int runs, ret; @@ -72,11 +72,11 @@ static int check_results(size_t span) } =20 bw_resc[runs] =3D strtoul(token_array[5], NULL, 0); - bw_imc[runs] =3D strtoul(token_array[3], NULL, 0); + bw_mc[runs] =3D strtoul(token_array[3], NULL, 0); runs++; } =20 - ret =3D show_bw_info(bw_imc, bw_resc, span); + ret =3D show_bw_info(bw_mc, bw_resc, span); =20 fclose(fp); =20 @@ -89,7 +89,7 @@ static int mbm_init(const struct resctrl_test *test, { int ret; =20 - ret =3D initialize_read_mem_bw_imc(); + ret =3D initialize_read_mem_bw_mc(); if (ret) return ret; =20 diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index 175101022bf3..a2f364a9af94 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -49,7 +49,7 @@ =20 /* * Memory bandwidth (in MiB) below which the bandwidth comparisons - * between iMC and resctrl are considered unreliable. For example RAS + * between MC and resctrl are considered unreliable. For example RAS * features or memory performance features that generate memory traffic * may drive accesses that are counted differently by performance counters * and MBM respectively, for instance generating "overhead" traffic which @@ -182,7 +182,7 @@ unsigned char *alloc_buffer(size_t buf_size, bool memfl= ush); void mem_flush(unsigned char *buf, size_t buf_size); void fill_cache_read(unsigned char *buf, size_t buf_size, bool once); ssize_t get_fill_buf_size(int cpu_no, const char *cache_type); -int initialize_read_mem_bw_imc(void); +int initialize_read_mem_bw_mc(void); int measure_read_mem_bw(const struct user_params *uparams, struct resctrl_val_param *param, pid_t bm_pid); void initialize_mem_bw_resctrl(const struct resctrl_val_param *param, diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index f20d2194c35f..bd413d2d5420 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -14,7 +14,7 @@ #define READ_FILE_NAME "cas_count_read" #define DYN_PMU_PATH "/sys/bus/event_source/devices" #define SCALE 0.00006103515625 -#define MAX_IMCS 40 +#define MAX_MCS 40 #define MAX_TOKENS 5 =20 #define CON_MBM_LOCAL_BYTES_PATH \ @@ -27,7 +27,7 @@ struct membw_read_format { __u64 id; /* if PERF_FORMAT_ID */ }; =20 -struct imc_counter_config { +struct mc_counter_config { __u32 type; __u64 event; __u64 umask; @@ -36,42 +36,42 @@ struct imc_counter_config { }; =20 static char mbm_total_path[1024]; -static int imcs; -static struct imc_counter_config imc_counters_config[MAX_IMCS]; +static int mcs; +static struct mc_counter_config mc_counters_config[MAX_MCS]; static const struct resctrl_test *current_test; =20 static void read_mem_bw_initialize_perf_event_attr(int i) { - memset(&imc_counters_config[i].pe, 0, + memset(&mc_counters_config[i].pe, 0, sizeof(struct perf_event_attr)); - imc_counters_config[i].pe.type =3D imc_counters_config[i].type; - imc_counters_config[i].pe.size =3D sizeof(struct perf_event_attr); - imc_counters_config[i].pe.disabled =3D 1; - imc_counters_config[i].pe.inherit =3D 1; - imc_counters_config[i].pe.exclude_guest =3D 0; - imc_counters_config[i].pe.config =3D - imc_counters_config[i].umask << 8 | - imc_counters_config[i].event; - imc_counters_config[i].pe.sample_type =3D PERF_SAMPLE_IDENTIFIER; - imc_counters_config[i].pe.read_format =3D + mc_counters_config[i].pe.type =3D mc_counters_config[i].type; + mc_counters_config[i].pe.size =3D sizeof(struct perf_event_attr); + mc_counters_config[i].pe.disabled =3D 1; + mc_counters_config[i].pe.inherit =3D 1; + mc_counters_config[i].pe.exclude_guest =3D 0; + mc_counters_config[i].pe.config =3D + mc_counters_config[i].umask << 8 | + mc_counters_config[i].event; + mc_counters_config[i].pe.sample_type =3D PERF_SAMPLE_IDENTIFIER; + mc_counters_config[i].pe.read_format =3D PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_TOTAL_TIME_RUNNING; } =20 static void read_mem_bw_ioctl_perf_event_ioc_reset_enable(int i) { - ioctl(imc_counters_config[i].fd, PERF_EVENT_IOC_RESET, 0); - ioctl(imc_counters_config[i].fd, PERF_EVENT_IOC_ENABLE, 0); + ioctl(mc_counters_config[i].fd, PERF_EVENT_IOC_RESET, 0); + ioctl(mc_counters_config[i].fd, PERF_EVENT_IOC_ENABLE, 0); } =20 static void read_mem_bw_ioctl_perf_event_ioc_disable(int i) { - ioctl(imc_counters_config[i].fd, PERF_EVENT_IOC_DISABLE, 0); + ioctl(mc_counters_config[i].fd, PERF_EVENT_IOC_DISABLE, 0); } =20 /* * get_read_event_and_umask: Parse config into event and umask * @cas_count_cfg: Config - * @count: iMC number + * @count: MC number */ static void get_read_event_and_umask(char *cas_count_cfg, unsigned int cou= nt) { @@ -87,21 +87,21 @@ static void get_read_event_and_umask(char *cas_count_cf= g, unsigned int count) if (!token[i]) break; if (strcmp(token[i], "event") =3D=3D 0) - imc_counters_config[count].event =3D strtol(token[i + 1], NULL, 16); + mc_counters_config[count].event =3D strtol(token[i + 1], NULL, 16); if (strcmp(token[i], "umask") =3D=3D 0) - imc_counters_config[count].umask =3D strtol(token[i + 1], NULL, 16); + mc_counters_config[count].umask =3D strtol(token[i + 1], NULL, 16); } } =20 static int open_perf_read_event(int i, int cpu_no) { - imc_counters_config[i].fd =3D - perf_event_open(&imc_counters_config[i].pe, -1, cpu_no, -1, + mc_counters_config[i].fd =3D + perf_event_open(&mc_counters_config[i].pe, -1, cpu_no, -1, PERF_FLAG_FD_CLOEXEC); =20 - if (imc_counters_config[i].fd =3D=3D -1) { + if (mc_counters_config[i].fd =3D=3D -1) { fprintf(stderr, "Error opening leader %llx\n", - imc_counters_config[i].pe.config); + mc_counters_config[i].pe.config); =20 return -1; } @@ -109,10 +109,10 @@ static int open_perf_read_event(int i, int cpu_no) return 0; } =20 -static int parse_imc_read_bw_events(char *imc_dir, unsigned int type, +static int parse_mc_read_bw_events(char *mc_dir, unsigned int type, unsigned int *count) { - char imc_events_dir[PATH_MAX], imc_counter_cfg[PATH_MAX]; + char mc_events_dir[PATH_MAX], mc_counter_cfg[PATH_MAX]; unsigned int orig_count =3D *count; char cas_count_cfg[1024]; struct dirent *ep; @@ -122,14 +122,14 @@ static int parse_imc_read_bw_events(char *imc_dir, un= signed int type, FILE *fp; DIR *dp; =20 - path_len =3D snprintf(imc_events_dir, sizeof(imc_events_dir), "%sevents", - imc_dir); - if (path_len >=3D sizeof(imc_events_dir)) { - ksft_print_msg("Unable to create path to %sevents\n", imc_dir); + path_len =3D snprintf(mc_events_dir, sizeof(mc_events_dir), "%sevents", + mc_dir); + if (path_len >=3D sizeof(mc_events_dir)) { + ksft_print_msg("Unable to create path to %sevents\n", mc_dir); return -1; } =20 - dp =3D opendir(imc_events_dir); + dp =3D opendir(mc_events_dir); if (!dp) { ksft_perror("Unable to open PMU events directory"); return -1; @@ -145,36 +145,36 @@ static int parse_imc_read_bw_events(char *imc_dir, un= signed int type, strchr(ep->d_name, '.')) continue; =20 - path_len =3D snprintf(imc_counter_cfg, sizeof(imc_counter_cfg), - "%s/%s", imc_events_dir, ep->d_name); - if (path_len >=3D sizeof(imc_counter_cfg)) { + path_len =3D snprintf(mc_counter_cfg, sizeof(mc_counter_cfg), + "%s/%s", mc_events_dir, ep->d_name); + if (path_len >=3D sizeof(mc_counter_cfg)) { ksft_print_msg("Unable to create path to %s/%s\n", - imc_events_dir, ep->d_name); + mc_events_dir, ep->d_name); goto out_close; } - fp =3D fopen(imc_counter_cfg, "r"); + fp =3D fopen(mc_counter_cfg, "r"); if (!fp) { - ksft_perror("Failed to open iMC config file"); + ksft_perror("Failed to open MC config file"); goto out_close; } num_cfg =3D fscanf(fp, "%1023s", cas_count_cfg); fclose(fp); if (num_cfg <=3D 0) { - ksft_perror("Could not get iMC cas count read"); + ksft_perror("Could not get MC cas count read"); goto out_close; } - if (*count >=3D MAX_IMCS) { - ksft_print_msg("Maximum iMC count exceeded\n"); + if (*count >=3D MAX_MCS) { + ksft_print_msg("Maximum MC count exceeded\n"); goto out_close; } =20 - imc_counters_config[*count].type =3D type; + mc_counters_config[*count].type =3D type; get_read_event_and_umask(cas_count_cfg, *count); /* Do not fail after incrementing *count. */ *count +=3D 1; } if (*count =3D=3D orig_count) { - ksft_print_msg("Unable to find events in %s\n", imc_events_dir); + ksft_print_msg("Unable to find events in %s\n", mc_events_dir); goto out_close; } ret =3D 0; @@ -183,36 +183,36 @@ static int parse_imc_read_bw_events(char *imc_dir, un= signed int type, return ret; } =20 -/* Get type and config of an iMC counter's read event. */ -static int read_from_imc_dir(char *imc_dir, unsigned int *count) +/* Get type and config of an MC counter's read event. */ +static int read_from_mc_dir(char *mc_dir, unsigned int *count) { - char imc_counter_type[PATH_MAX]; + char mc_counter_type[PATH_MAX]; unsigned int type; int path_len; FILE *fp; int ret; =20 - /* Get type of iMC counter */ - path_len =3D snprintf(imc_counter_type, sizeof(imc_counter_type), - "%s%s", imc_dir, "type"); - if (path_len >=3D sizeof(imc_counter_type)) { + /* Get type of MC counter */ + path_len =3D snprintf(mc_counter_type, sizeof(mc_counter_type), + "%s%s", mc_dir, "type"); + if (path_len >=3D sizeof(mc_counter_type)) { ksft_print_msg("Unable to create path to %s%s\n", - imc_dir, "type"); + mc_dir, "type"); return -1; } - fp =3D fopen(imc_counter_type, "r"); + fp =3D fopen(mc_counter_type, "r"); if (!fp) { - ksft_perror("Failed to open iMC counter type file"); + ksft_perror("Failed to open MC counter type file"); =20 return -1; } ret =3D fscanf(fp, "%u", &type); fclose(fp); if (ret <=3D 0) { - ksft_perror("Could not get iMC type"); + ksft_perror("Could not get MC type"); return -1; } - ret =3D parse_imc_read_bw_events(imc_dir, type, count); + ret =3D parse_mc_read_bw_events(mc_dir, type, count); if (ret) { ksft_print_msg("Unable to parse bandwidth event and umask\n"); return ret; @@ -222,10 +222,10 @@ static int read_from_imc_dir(char *imc_dir, unsigned = int *count) } =20 /* - * A system can have 'n' number of iMC (Integrated Memory Controller) + * A system can have 'n' number of MC (Memory Controller) * counters, get that 'n'. Discover the properties of the available * counters in support of needed performance measurement via perf. - * For each iMC counter get it's type and config. Also obtain each + * For each MC counter get it's type and config. Also obtain each * counter's event and umask for the memory read events that will be * measured. * @@ -233,9 +233,9 @@ static int read_from_imc_dir(char *imc_dir, unsigned in= t *count) * * Return: >=3D 0 on success. < 0 on failure. */ -static int num_of_imcs(void) +static int num_of_mem_controllers(void) { - char imc_dir[512], *temp; + char mc_dir[512], *temp; unsigned int count =3D 0; struct dirent *ep; int ret; @@ -249,7 +249,7 @@ static int num_of_imcs(void) continue; =20 /* - * imc counters are named as "uncore_imc_", hence + * mc counters are named as "uncore_imc_", hence * increment the pointer to point to . Note that * sizeof(UNCORE_IMC) would count for null character as * well and hence the last underscore character in @@ -263,9 +263,9 @@ static int num_of_imcs(void) * first character is a numerical digit or not. */ if (temp[0] >=3D '0' && temp[0] <=3D '9') { - sprintf(imc_dir, "%s/%s/", DYN_PMU_PATH, + sprintf(mc_dir, "%s/%s/", DYN_PMU_PATH, ep->d_name); - ret =3D read_from_imc_dir(imc_dir, &count); + ret =3D read_from_mc_dir(mc_dir, &count); if (ret) { closedir(dp); =20 @@ -275,7 +275,7 @@ static int num_of_imcs(void) } closedir(dp); if (count =3D=3D 0) { - ksft_print_msg("Unable to find iMC counters\n"); + ksft_print_msg("Unable to find MC counters\n"); =20 return -1; } @@ -288,46 +288,46 @@ static int num_of_imcs(void) return count; } =20 -int initialize_read_mem_bw_imc(void) +int initialize_read_mem_bw_mc(void) { - int imc; + int mc; =20 - imcs =3D num_of_imcs(); - if (imcs <=3D 0) - return imcs; + mcs =3D num_of_mem_controllers(); + if (mcs <=3D 0) + return mcs; =20 - /* Initialize perf_event_attr structures for all iMC's */ - for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_initialize_perf_event_attr(imc); + /* Initialize perf_event_attr structures for all MC's */ + for (mc =3D 0; mc < mcs; mc++) + read_mem_bw_initialize_perf_event_attr(mc); =20 return 0; } =20 -static void perf_close_imc_read_mem_bw(void) +static void perf_close_mc_read_mem_bw(void) { int mc; =20 - for (mc =3D 0; mc < imcs; mc++) { - if (imc_counters_config[mc].fd !=3D -1) - close(imc_counters_config[mc].fd); + for (mc =3D 0; mc < mcs; mc++) { + if (mc_counters_config[mc].fd !=3D -1) + close(mc_counters_config[mc].fd); } } =20 /* - * perf_open_imc_read_mem_bw - Open perf fds for IMCs + * perf_open_mc_read_mem_bw - Open perf fds for MCs * @cpu_no: CPU number that the benchmark PID is bound to * * Return: =3D 0 on success. < 0 on failure. */ -static int perf_open_imc_read_mem_bw(int cpu_no) +static int perf_open_mc_read_mem_bw(int cpu_no) { - int imc, ret; + int mc, ret; =20 - for (imc =3D 0; imc < imcs; imc++) - imc_counters_config[imc].fd =3D -1; + for (mc =3D 0; mc < mcs; mc++) + mc_counters_config[mc].fd =3D -1; =20 - for (imc =3D 0; imc < imcs; imc++) { - ret =3D open_perf_read_event(imc, cpu_no); + for (mc =3D 0; mc < mcs; mc++) { + ret =3D open_perf_read_event(mc, cpu_no); if (ret) goto close_fds; } @@ -335,56 +335,56 @@ static int perf_open_imc_read_mem_bw(int cpu_no) return 0; =20 close_fds: - perf_close_imc_read_mem_bw(); + perf_close_mc_read_mem_bw(); return -1; } =20 /* - * do_imc_read_mem_bw_test - Perform memory bandwidth test + * do_mc_read_mem_bw_test - Perform memory bandwidth test * * Runs memory bandwidth test over one second period. Also, handles starti= ng - * and stopping of the IMC perf counters around the test. + * and stopping of the MC perf counters around the test. */ -static void do_imc_read_mem_bw_test(void) +static void do_mc_read_mem_bw_test(void) { - int imc; + int mc; =20 - for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_ioctl_perf_event_ioc_reset_enable(imc); + for (mc =3D 0; mc < mcs; mc++) + read_mem_bw_ioctl_perf_event_ioc_reset_enable(mc); =20 sleep(1); =20 /* Stop counters after a second to get results. */ - for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_ioctl_perf_event_ioc_disable(imc); + for (mc =3D 0; mc < mcs; mc++) + read_mem_bw_ioctl_perf_event_ioc_disable(mc); } =20 /* - * get_read_mem_bw_imc - Memory read bandwidth as reported by iMC counters + * get_read_mem_bw_mc - Memory read bandwidth as reported by MC counters * * Memory read bandwidth utilized by a process on a socket can be calculat= ed - * using iMC counters' read events. Perf events are used to read these + * using MC counters' read events. Perf events are used to read these * counters. * * Return: =3D 0 on success. < 0 on failure. */ -static int get_read_mem_bw_imc(float *bw_imc) +static int get_read_mem_bw_mc(float *bw_mc) { float reads =3D 0, of_mul_read =3D 1; - int imc; + int mc; =20 /* - * Log read event values from all iMC counters into - * struct imc_counter_config. + * Log read event values from all MC counters into + * struct mc_counter_config. * Take overflow into consideration before calculating total bandwidth. */ - for (imc =3D 0; imc < imcs; imc++) { + for (mc =3D 0; mc < mcs; mc++) { struct membw_read_format measurement; - struct imc_counter_config *r =3D - &imc_counters_config[imc]; + struct mc_counter_config *r =3D + &mc_counters_config[mc]; =20 if (read(r->fd, &measurement, sizeof(measurement)) =3D=3D -1) { - ksft_perror("Couldn't get read bandwidth through iMC"); + ksft_perror("Couldn't get read bandwidth through MC"); return -1; } =20 @@ -398,7 +398,7 @@ static int get_read_mem_bw_imc(float *bw_imc) reads +=3D measurement.value * of_mul_read * SCALE; } =20 - *bw_imc =3D reads; + *bw_mc =3D reads; return 0; } =20 @@ -502,19 +502,19 @@ void signal_handler_unregister(void) * print_results_bw: the memory bandwidth results are stored in a file * @filename: file that stores the results * @bm_pid: child pid that runs benchmark - * @bw_imc: perf imc counter value + * @bw_mc: perf mc counter value * @bw_resc: memory bandwidth value * * Return: 0 on success, < 0 on error. */ -static int print_results_bw(char *filename, pid_t bm_pid, float bw_imc, +static int print_results_bw(char *filename, pid_t bm_pid, float bw_mc, unsigned long bw_resc) { - unsigned long diff =3D fabs(bw_imc - bw_resc); + unsigned long diff =3D fabs(bw_mc - bw_resc); FILE *fp; =20 if (strcmp(filename, "stdio") =3D=3D 0 || strcmp(filename, "stderr") =3D= =3D 0) { - printf("Pid: %d \t Mem_BW_iMC: %f \t ", (int)bm_pid, bw_imc); + printf("Pid: %d \t Mem_BW_MC: %f \t ", (int)bm_pid, bw_mc); printf("Mem_BW_resc: %lu \t Difference: %lu\n", bw_resc, diff); } else { fp =3D fopen(filename, "a"); @@ -523,8 +523,8 @@ static int print_results_bw(char *filename, pid_t bm_pi= d, float bw_imc, =20 return -1; } - if (fprintf(fp, "Pid: %d \t Mem_BW_iMC: %f \t Mem_BW_resc: %lu \t Differ= ence: %lu\n", - (int)bm_pid, bw_imc, bw_resc, diff) <=3D 0) { + if (fprintf(fp, "Pid: %d \t Mem_BW_MC: %f \t Mem_BW_resc: %lu \t Differe= nce: %lu\n", + (int)bm_pid, bw_mc, bw_resc, diff) <=3D 0) { ksft_print_msg("Could not log results\n"); fclose(fp); =20 @@ -543,7 +543,7 @@ static int print_results_bw(char *filename, pid_t bm_pi= d, float bw_imc, * @bm_pid: PID that runs the benchmark * * Measure memory bandwidth from resctrl and from another source which is - * perf imc value or could be something else if perf imc event is not + * perf mc value or could be something else if perf mc event is not * available. Compare the two values to validate resctrl value. It takes * 1 sec to measure the data. * resctrl does not distinguish between read and write operations so @@ -554,42 +554,42 @@ int measure_read_mem_bw(const struct user_params *upa= rams, { unsigned long bw_resc, bw_resc_start, bw_resc_end; FILE *mem_bw_fp; - float bw_imc; + float bw_mc; int ret; =20 mem_bw_fp =3D open_mem_bw_resctrl(mbm_total_path); if (!mem_bw_fp) return -1; =20 - ret =3D perf_open_imc_read_mem_bw(uparams->cpu); + ret =3D perf_open_mc_read_mem_bw(uparams->cpu); if (ret < 0) goto close_fp; =20 ret =3D get_mem_bw_resctrl(mem_bw_fp, &bw_resc_start); if (ret < 0) - goto close_imc; + goto close_mc; =20 rewind(mem_bw_fp); =20 - do_imc_read_mem_bw_test(); + do_mc_read_mem_bw_test(); =20 ret =3D get_mem_bw_resctrl(mem_bw_fp, &bw_resc_end); if (ret < 0) - goto close_imc; + goto close_mc; =20 - ret =3D get_read_mem_bw_imc(&bw_imc); + ret =3D get_read_mem_bw_mc(&bw_mc); if (ret < 0) - goto close_imc; + goto close_mc; =20 - perf_close_imc_read_mem_bw(); + perf_close_mc_read_mem_bw(); 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charset="utf-8" From: Babu Moger The test detects the number of memory controllers by scanning the perf sysfs (DYN_PMU_PATH) for the vendor specific memory controller PMU name. On Intel this PMU is named "uncore_imc_". Detect the vendor and select the memory controller PMU name accordingly so that the rest of the code stays generic and can be extended to other vendors. Bail out on vendors that are not yet supported. While at it, match against the full "uncore_imc_" string and use strlen() instead of sizeof() to advance past the prefix. This is clearer than relying on sizeof() counting the terminating NULL to make up for the trailing underscore. Assisted-by: Claude:claude-opus-4.8 Signed-off-by: Babu Moger Co-developed-by: Swapnil Sapkal Signed-off-by: Swapnil Sapkal --- v3->v4: - Reworded the subject and changelog (Reinette) - Dropped the local vendor variable and call get_vendor() directly (Rei= nette) tools/testing/selftests/resctrl/resctrl_val.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index bd413d2d5420..c6089c42aa7e 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -10,7 +10,7 @@ */ #include "resctrl.h" =20 -#define UNCORE_IMC "uncore_imc" +#define UNCORE_IMC "uncore_imc_" #define READ_FILE_NAME "cas_count_read" #define DYN_PMU_PATH "/sys/bus/event_source/devices" #define SCALE 0.00006103515625 @@ -238,24 +238,29 @@ static int num_of_mem_controllers(void) char mc_dir[512], *temp; unsigned int count =3D 0; struct dirent *ep; + char *sysfs_name; int ret; DIR *dp; =20 + if (get_vendor() =3D=3D ARCH_INTEL) { + sysfs_name =3D UNCORE_IMC; + } else { + ksft_print_msg("Unsupported vendor\n"); + return -1; + } + dp =3D opendir(DYN_PMU_PATH); if (dp) { while ((ep =3D readdir(dp))) { - temp =3D strstr(ep->d_name, UNCORE_IMC); + temp =3D strstr(ep->d_name, sysfs_name); if (!temp) continue; =20 /* * mc counters are named as "uncore_imc_", hence - * increment the pointer to point to . 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charset="utf-8" From: Babu Moger The MBM and MBA tests validate the resctrl memory bandwidth numbers against the memory controller performance counters. On Intel these are the iMC (Integrated Memory Controller) counters and the read event and umask are discovered from the PMU's sysfs event files. Commit 25e56847821f ("perf/x86/amd/uncore: Add memory controller support") added support for the UMC (Unified Memory Controller) perf events on AMD. Unlike Intel, the UMC PMU does not expose the CAS command events via sysfs, so program the read event directly: Number of CAS commands sent for reads: EventCode =3D 0x0a, umask =3D 0x1. Keep all the vendor detection contained in num_of_mem_controllers() and dispatch to a vendor specific routine to initialize the counter configuration. Only reading the counter's perf "type" is common to both vendors, so factor that out into a shared helper. On AMD each memory controller (UMC) is exposed as its own PMU (amd_umc_) that is tied to a specific NUMA node, whereas on Intel opening an iMC event on the benchmark CPU always resolves to the local memory controllers. A UMC PMU can only be opened from a CPU that belongs to the same node and returns -ENODEV otherwise. Since the benchmark runs on a single CPU, open the counters that are local to that CPU and skip the UMCs on remote nodes. This both avoids the perf_event_open() failure and matches the local traffic accounted by mbm_local_bytes. Assisted-by: Claude:claude-opus-4.8 Signed-off-by: Babu Moger Co-developed-by: Swapnil Sapkal Signed-off-by: Swapnil Sapkal --- v3->v4: - Contained all vendor detection in num_of_mem_controllers() and dispatched to per-vendor routines, factoring the common counter 'type' read into a shared helper. (Reinette) - Adapted to the upstream read-only bandwidth refactor. - Handled the AMD per-node UMC PMU topology: open only the UMCs local to the benchmark CPU and skip remote-node UMCs that would otherwise fail perf_event_open() with -ENODEV on multi-node systems. - Improved the perf_event_open() error reporting (print the errno with strerror()). tools/testing/selftests/resctrl/resctrl_val.c | 135 ++++++++++++++---- 1 file changed, 109 insertions(+), 26 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index c6089c42aa7e..4fce7c0c6490 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -11,6 +11,7 @@ #include "resctrl.h" =20 #define UNCORE_IMC "uncore_imc_" +#define AMD_UMC "amd_umc_" #define READ_FILE_NAME "cas_count_read" #define DYN_PMU_PATH "/sys/bus/event_source/devices" #define SCALE 0.00006103515625 @@ -99,12 +100,8 @@ static int open_perf_read_event(int i, int cpu_no) perf_event_open(&mc_counters_config[i].pe, -1, cpu_no, -1, PERF_FLAG_FD_CLOEXEC); =20 - if (mc_counters_config[i].fd =3D=3D -1) { - fprintf(stderr, "Error opening leader %llx\n", - mc_counters_config[i].pe.config); - - return -1; - } + if (mc_counters_config[i].fd =3D=3D -1) + return -errno; =20 return 0; } @@ -183,16 +180,14 @@ static int parse_mc_read_bw_events(char *mc_dir, unsi= gned int type, return ret; } =20 -/* Get type and config of an MC counter's read event. */ -static int read_from_mc_dir(char *mc_dir, unsigned int *count) +/* Get the perf "type" of a memory controller counter. Shared by all vendo= rs. */ +static int get_mc_counter_type(const char *mc_dir, unsigned int *type) { char mc_counter_type[PATH_MAX]; - unsigned int type; int path_len; FILE *fp; int ret; =20 - /* Get type of MC counter */ path_len =3D snprintf(mc_counter_type, sizeof(mc_counter_type), "%s%s", mc_dir, "type"); if (path_len >=3D sizeof(mc_counter_type)) { @@ -206,12 +201,29 @@ static int read_from_mc_dir(char *mc_dir, unsigned in= t *count) =20 return -1; } - ret =3D fscanf(fp, "%u", &type); + ret =3D fscanf(fp, "%u", type); fclose(fp); if (ret <=3D 0) { ksft_perror("Could not get MC type"); return -1; } + + return 0; +} + +/* + * Intel: get type and config of an iMC counter's read event. The read eve= nt + * and umask are discovered from the PMU's sysfs event files. + */ +static int read_from_intel_mc_dir(char *mc_dir, unsigned int *count) +{ + unsigned int type; + int ret; + + ret =3D get_mc_counter_type(mc_dir, &type); + if (ret) + return ret; + ret =3D parse_mc_read_bw_events(mc_dir, type, count); if (ret) { ksft_print_msg("Unable to parse bandwidth event and umask\n"); @@ -222,12 +234,40 @@ static int read_from_mc_dir(char *mc_dir, unsigned in= t *count) } =20 /* - * A system can have 'n' number of MC (Memory Controller) - * counters, get that 'n'. Discover the properties of the available - * counters in support of needed performance measurement via perf. - * For each MC counter get it's type and config. Also obtain each - * counter's event and umask for the memory read events that will be - * measured. + * AMD: get type and config of a UMC counter's read event. The UMC PMU does + * not expose the CAS command events via sysfs, so program them directly: + * Number of CAS commands sent for reads: EventCode =3D 0x0a, umask =3D 0x1 + */ +static int read_from_amd_mc_dir(char *mc_dir, unsigned int *count) +{ + unsigned int type; + int ret; + + ret =3D get_mc_counter_type(mc_dir, &type); + if (ret) + return ret; + + if (*count >=3D MAX_MCS) { + ksft_print_msg("Maximum MC count exceeded\n"); + return -1; + } + + mc_counters_config[*count].type =3D type; + mc_counters_config[*count].event =3D 0xa; + mc_counters_config[*count].umask =3D 0x1; + *count +=3D 1; + + return 0; +} + +/* + * A system can have 'n' number of MC (Memory Controller) counters, get + * that 'n'. On Intel the memory controller is called Integrated Memory + * Controller (iMC) and on AMD it is called Unified Memory Controller (UMC= ). + * Discover the properties of the available counters in support of needed + * performance measurement via perf. For each MC counter get it's type and + * config. Also obtain each counter's event and umask for the memory read + * events that will be measured. * * Enumerate all these details into an array of structures. * @@ -235,6 +275,7 @@ static int read_from_mc_dir(char *mc_dir, unsigned int = *count) */ static int num_of_mem_controllers(void) { + int (*read_mc_dir)(char *mc_dir, unsigned int *count); char mc_dir[512], *temp; unsigned int count =3D 0; struct dirent *ep; @@ -244,6 +285,10 @@ static int num_of_mem_controllers(void) =20 if (get_vendor() =3D=3D ARCH_INTEL) { sysfs_name =3D UNCORE_IMC; + read_mc_dir =3D read_from_intel_mc_dir; + } else if (get_vendor() =3D=3D ARCH_AMD) { + sysfs_name =3D AMD_UMC; + read_mc_dir =3D read_from_amd_mc_dir; } else { ksft_print_msg("Unsupported vendor\n"); return -1; @@ -257,8 +302,9 @@ static int num_of_mem_controllers(void) continue; =20 /* - * mc counters are named as "uncore_imc_", hence - * increment the pointer to point to . + * MC counters are named as "uncore_imc_" on Intel + * and "amd_umc_" on AMD, hence increment the pointer + * to point to . */ temp =3D temp + strlen(sysfs_name); =20 @@ -270,7 +316,7 @@ static int num_of_mem_controllers(void) if (temp[0] >=3D '0' && temp[0] <=3D '9') { sprintf(mc_dir, "%s/%s/", DYN_PMU_PATH, ep->d_name); - ret =3D read_from_mc_dir(mc_dir, &count); + ret =3D read_mc_dir(mc_dir, &count); if (ret) { closedir(dp); =20 @@ -280,7 +326,9 @@ static int num_of_mem_controllers(void) } closedir(dp); if (count =3D=3D 0) { - ksft_print_msg("Unable to find MC counters\n"); + ksft_print_msg("Unable to find memory controller counters\n"); + if (get_vendor() =3D=3D ARCH_AMD) + ksft_print_msg("Try loading amd_uncore module\n"); =20 return -1; } @@ -326,15 +374,40 @@ static void perf_close_mc_read_mem_bw(void) */ static int perf_open_mc_read_mem_bw(int cpu_no) { - int mc, ret; + int mc, ret, opened =3D 0; =20 for (mc =3D 0; mc < mcs; mc++) mc_counters_config[mc].fd =3D -1; =20 for (mc =3D 0; mc < mcs; mc++) { ret =3D open_perf_read_event(mc, cpu_no); - if (ret) - goto close_fds; + if (!ret) { + opened++; + continue; + } + + /* + * On AMD each memory controller (UMC) has its own PMU that is + * tied to a specific NUMA node, unlike Intel where opening an + * iMC event on the benchmark CPU always resolves to the local + * memory controllers. A UMC PMU can only be opened from a CPU + * that belongs to the same node and returns -ENODEV otherwise. + * The benchmark runs on a single CPU, so skip the UMCs that + * belong to remote nodes and measure only the memory + * controllers local to the benchmark. This matches what + * mbm_local_bytes accounts for on the resctrl side. + */ + if (ret =3D=3D -ENODEV && get_vendor() =3D=3D ARCH_AMD) + continue; + + ksft_print_msg("Error opening memory bandwidth performance counter: %s\n= ", + strerror(-ret)); + goto close_fds; + } + + if (!opened) { + ksft_print_msg("Could not open any memory controller counters\n"); + goto close_fds; } =20 return 0; @@ -354,14 +427,20 @@ static void do_mc_read_mem_bw_test(void) { int mc; =20 - for (mc =3D 0; mc < mcs; mc++) + for (mc =3D 0; mc < mcs; mc++) { + if (mc_counters_config[mc].fd =3D=3D -1) + continue; read_mem_bw_ioctl_perf_event_ioc_reset_enable(mc); + } =20 sleep(1); =20 /* Stop counters after a second to get results. */ - for (mc =3D 0; mc < mcs; mc++) + for (mc =3D 0; mc < mcs; mc++) { + if (mc_counters_config[mc].fd =3D=3D -1) + continue; read_mem_bw_ioctl_perf_event_ioc_disable(mc); + } } =20 /* @@ -388,6 +467,10 @@ static int get_read_mem_bw_mc(float *bw_mc) struct mc_counter_config *r =3D &mc_counters_config[mc]; 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charset="utf-8" Intel MBA (Memory Bandwidth Allocation) throttles memory bandwidth using a percentage, so the MBA test sweeps the schemata from 10% to 100% in steps of 10%. AMD MBA instead uses an absolute memory bandwidth value. Sweep the AMD MBA schemata from 4 GB/s to 40 GB/s in steps of 4 GB/s. The hardware represents these in units of 1/8 GB/s, so the test writes 32, 64, ... up to 320. The number of allocations swept (10), and hence the number of measurements, stays the same as Intel. Select the minimum, maximum and step of the sweep based on the vendor. Assisted-by: Claude:claude-opus-4.8 Signed-off-by: Swapnil Sapkal --- tools/testing/selftests/resctrl/mba_test.c | 79 ++++++++++++++++++---- 1 file changed, 66 insertions(+), 13 deletions(-) diff --git a/tools/testing/selftests/resctrl/mba_test.c b/tools/testing/sel= ftests/resctrl/mba_test.c index 6c6c885eba5e..9fcb9992c529 100644 --- a/tools/testing/selftests/resctrl/mba_test.c +++ b/tools/testing/selftests/resctrl/mba_test.c @@ -13,10 +13,51 @@ #define RESULT_FILE_NAME "result_mba" #define NUM_OF_RUNS 5 #define MAX_DIFF_PERCENT 15 + +/* Intel MBA is specified as a percentage: 10%, 20% ... 100%. */ #define ALLOCATION_MAX 100 #define ALLOCATION_MIN 10 #define ALLOCATION_STEP 10 =20 +/* + * AMD MBA is not a percentage but an absolute memory bandwidth value. The + * test sweeps the bandwidth from 4 GB/s to 40 GB/s in steps of 4 GB/s, + * which the hardware represents in units of 1/8 GB/s (i.e. 4 GB/s -> 32, + * 8 GB/s -> 64, ... 40 GB/s -> 320). + */ +#define AMD_ALLOCATION_MAX 320 +#define AMD_ALLOCATION_MIN 32 +#define AMD_ALLOCATION_STEP 32 + +/* Number of MBA schemata allocations to sweep (same for both vendors). */ +#define NUM_OF_ALLOCS (ALLOCATION_MAX / ALLOCATION_STEP) + +/* + * The fixed-size result arrays in check_results() and the aggregation loo= p in + * show_mba_info() are sized and driven by NUM_OF_ALLOCS, so each vendor's= sweep + * must produce exactly NUM_OF_ALLOCS allocations. Enforce this at build t= ime so + * that changing a vendor's min/max/step can never overflow those arrays. + */ +_Static_assert((ALLOCATION_MAX - ALLOCATION_MIN) / ALLOCATION_STEP + 1 =3D= =3D NUM_OF_ALLOCS, + "Intel MBA sweep must yield NUM_OF_ALLOCS allocations"); +_Static_assert((AMD_ALLOCATION_MAX - AMD_ALLOCATION_MIN) / AMD_ALLOCATION_= STEP + 1 =3D=3D NUM_OF_ALLOCS, + "AMD MBA sweep must yield NUM_OF_ALLOCS allocations"); + +static unsigned int mba_alloc_min(void) +{ + return get_vendor() =3D=3D ARCH_AMD ? AMD_ALLOCATION_MIN : ALLOCATION_MIN; +} + +static unsigned int mba_alloc_max(void) +{ + return get_vendor() =3D=3D ARCH_AMD ? AMD_ALLOCATION_MAX : ALLOCATION_MAX; +} + +static unsigned int mba_alloc_step(void) +{ + return get_vendor() =3D=3D ARCH_AMD ? AMD_ALLOCATION_STEP : ALLOCATION_ST= EP; +} + static int mba_init(const struct resctrl_test *test, const struct user_params *uparams, const struct resctrl_val_param *param, int domain_id) @@ -33,15 +74,17 @@ static int mba_init(const struct resctrl_test *test, } =20 /* - * Change schemata percentage from 100 to 10%. Write schemata to specified - * con_mon grp, mon_grp in resctrl FS. + * Sweep the MBA schemata from the minimum to the maximum allocation. On + * Intel the allocation is a percentage (10% .. 100%); on AMD it is an + * absolute memory bandwidth value (4 GB/s .. 40 GB/s). Write schemata to + * the specified con_mon grp, mon_grp in resctrl FS. * For each allocation, run 5 times in order to get average values. */ static int mba_setup(const struct resctrl_test *test, const struct user_params *uparams, struct resctrl_val_param *p) { - static unsigned int allocation =3D ALLOCATION_MIN; + static unsigned int allocation; static int runs_per_allocation; char allocation_str[64]; int ret; @@ -53,16 +96,20 @@ static int mba_setup(const struct resctrl_test *test, if (runs_per_allocation++ !=3D 0) return 0; =20 - if (allocation > ALLOCATION_MAX) + /* Set the initial allocation once the vendor is known. */ + if (allocation =3D=3D 0) + allocation =3D mba_alloc_min(); + + if (allocation > mba_alloc_max()) return END_OF_TESTS; =20 - sprintf(allocation_str, "%d", allocation); + sprintf(allocation_str, "%u", allocation); =20 ret =3D write_schemata(p->ctrlgrp, allocation_str, uparams->cpu, test->re= source); if (ret < 0) return ret; =20 - allocation +=3D ALLOCATION_STEP; + allocation +=3D mba_alloc_step(); =20 return 0; } @@ -75,14 +122,15 @@ static int mba_measure(const struct user_params *upara= ms, =20 static bool show_mba_info(unsigned long *bw_mc, unsigned long *bw_resc) { + unsigned int alloc_min =3D mba_alloc_min(); + unsigned int alloc_step =3D mba_alloc_step(); unsigned int allocation; bool ret =3D false; int runs; =20 ksft_print_msg("Results are displayed in (MB)\n"); - /* Memory bandwidth from 100% down to 10% */ - for (allocation =3D 0; allocation < ALLOCATION_MAX / ALLOCATION_STEP; - allocation++) { + /* Memory bandwidth for each of the swept MBA allocations */ + for (allocation =3D 0; allocation < NUM_OF_ALLOCS; allocation++) { unsigned long sum_bw_mc =3D 0, sum_bw_resc =3D 0; long avg_bw_mc, avg_bw_resc; int avg_diff_per; @@ -99,7 +147,7 @@ static bool show_mba_info(unsigned long *bw_mc, unsigned= long *bw_resc) if (avg_bw_mc < THROTTLE_THRESHOLD || avg_bw_resc < THROTTLE_THRESHOLD) { ksft_print_msg("Bandwidth below threshold (%d MiB). Dropping results fr= om MBA schemata %u.\n", THROTTLE_THRESHOLD, - ALLOCATION_MIN + ALLOCATION_STEP * allocation); + alloc_min + alloc_step * allocation); continue; } =20 @@ -110,7 +158,7 @@ static bool show_mba_info(unsigned long *bw_mc, unsigne= d long *bw_resc) avg_diff_per > MAX_DIFF_PERCENT ? "Fail:" : "Pass:", MAX_DIFF_PERCENT, - ALLOCATION_MIN + ALLOCATION_STEP * allocation); + alloc_min + alloc_step * allocation); =20 ksft_print_msg("avg_diff_per: %d%%\n", avg_diff_per); ksft_print_msg("avg_bw_mc: %lu\n", avg_bw_mc); @@ -129,8 +177,8 @@ static bool show_mba_info(unsigned long *bw_mc, unsigne= d long *bw_resc) =20 static int check_results(void) { - unsigned long bw_resc[NUM_OF_RUNS * ALLOCATION_MAX / ALLOCATION_STEP]; - unsigned long bw_mc[NUM_OF_RUNS * ALLOCATION_MAX / ALLOCATION_STEP]; + unsigned long bw_resc[NUM_OF_RUNS * NUM_OF_ALLOCS]; + unsigned long bw_mc[NUM_OF_RUNS * NUM_OF_ALLOCS]; char *token_array[8], output[] =3D RESULT_FILE_NAME, temp[512]; int runs; FILE *fp; @@ -147,6 +195,11 @@ static int check_results(void) char *token =3D strtok(temp, ":\t"); int fields =3D 0; =20 + if (runs >=3D NUM_OF_RUNS * NUM_OF_ALLOCS) { + ksft_print_msg("Got more results than expected\n"); + break; + } + while (token) { token_array[fields++] =3D token; token =3D strtok(NULL, ":\t"); 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charset="utf-8" From: Babu Moger Now that the UMC (Unified Memory Controller) perf events can be used to validate the resctrl memory bandwidth numbers on AMD, extend the vendor_specific gate of the MBM and MBA tests to also cover AMD so that they run on AMD in addition to Intel. The tests stay restricted to Intel and AMD: num_of_mem_controllers() only knows about the iMC and UMC counters, so keeping the gate (rather than making the tests universal) leaves other vendors skipped instead of failing. Assisted-by: Claude:claude-opus-4.8 Signed-off-by: Babu Moger Co-developed-by: Swapnil Sapkal Signed-off-by: Swapnil Sapkal --- v3->v4: - Rebased onto v7.2-rc7. - Extend the vendor_specific gate to ARCH_INTEL | ARCH_AMD instead of removing it, so unsupported vendors are skipped rather than reported as a failure. tools/testing/selftests/resctrl/mba_test.c | 2 +- tools/testing/selftests/resctrl/mbm_test.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/resctrl/mba_test.c b/tools/testing/sel= ftests/resctrl/mba_test.c index 9fcb9992c529..97b7d368d5a2 100644 --- a/tools/testing/selftests/resctrl/mba_test.c +++ b/tools/testing/selftests/resctrl/mba_test.c @@ -271,7 +271,7 @@ static bool mba_feature_check(const struct resctrl_test= *test) struct resctrl_test mba_test =3D { .name =3D "MBA", .resource =3D "MB", - .vendor_specific =3D ARCH_INTEL, + .vendor_specific =3D ARCH_INTEL | ARCH_AMD, .feature_check =3D mba_feature_check, .run_test =3D mba_run_test, .cleanup =3D mba_test_cleanup, diff --git a/tools/testing/selftests/resctrl/mbm_test.c b/tools/testing/sel= ftests/resctrl/mbm_test.c index d89f71c58335..515717743a61 100644 --- a/tools/testing/selftests/resctrl/mbm_test.c +++ b/tools/testing/selftests/resctrl/mbm_test.c @@ -177,7 +177,7 @@ static bool mbm_feature_check(const struct resctrl_test= *test) struct resctrl_test mbm_test =3D { .name =3D "MBM", .resource =3D "MB", - .vendor_specific =3D ARCH_INTEL, + .vendor_specific =3D ARCH_INTEL | ARCH_AMD, .feature_check =3D mbm_feature_check, .run_test =3D mbm_run_test, .cleanup =3D mbm_test_cleanup, --=20 2.43.0