From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 427333B05AF; Mon, 10 Aug 2026 12:15:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364142; cv=none; b=LR3dHIOWL3CsXB/6/OW6I43enqd2mK89iv9KHbTaoOJ2gkDxlNITCMXKzq3vN9kKIlBUqKlgbHj9dYnyeDMPViHo1+71RdLS4XX0rh9EllpRcyaRWTkX1mHJKFP7g1PWybzACNGO1Fs8jgiFXziOmqfvvWMID8unnTQQAfmpNp4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364142; c=relaxed/simple; bh=H5CEku+ITlAjoMrStPbt5ViE5yaSmu2wL1s37Eewqcs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uVuI7NmKpt/M/PslrjdG1ssv4MdrRPmmr5JEDiG/f7N2PgpXXPdX4YL0r66ivqoGOpoPOUNXy1m6ZCpA9OyOOxOzS2CZtTQH6GLO9ZKWBpydy9FgxcCFl/y4jvH4mhyRk4cDbyzraNNSn9yV8GOau5uUtTkdRWbJK1abx5y3jrY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=kmNyjS6Z; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="kmNyjS6Z" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C4480BFA89; Mon, 10 Aug 2026 15:15:35 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364137; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=FEboMO/dpKdx6T83eWgMRJEjA2wYI7OkmJwek6C81zo=; b=kmNyjS6ZWTxxxo0nLbhz9xd1F0Rds6HSjPiauQfAswFOBySIeyvXPHjKZ+Zepqj9EhJZwV brj39BsyjiXhOMGAeDBoqSWFcWSzjgm81z0sf/vkNw62iJgfN3bE2KFfl5vPEENhHLzC7Q msIxQ3mgyM+ujpwzIaqHdSDOISkkU3Cj/WJBfznSgw9JhV3FRK7+CF0jVqUzy3ru5AW/7X j5BAJSddbfJoexyaB88YC4DdT2mvEQemGiF8uqrDKWlXFztHjxm0BlSdJX0ihT5G04SBOT WPQ8T5luWIFS0VvZkT2A7kGYdTx2AXgXiC9p5CXilRV7zFOz8SIlsNXitha+Pg== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Philipp Zabel , Rob Herring Subject: [PATCH 01/25] dt-bindings: reset: Add RV1106 CRU reset definitions Date: Mon, 10 Aug 2026 15:10:52 +0300 Message-ID: <20260810121121.210040-2-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add the reset ID definitions for the Rockchip RV1106 clock and reset unit (CRU), to be used by the reset controller driver and device tree nodes. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- .../dt-bindings/reset/rockchip,rv1106-cru.h | 305 ++++++++++++++++++ 1 file changed, 305 insertions(+) create mode 100644 include/dt-bindings/reset/rockchip,rv1106-cru.h diff --git a/include/dt-bindings/reset/rockchip,rv1106-cru.h b/include/dt-b= indings/reset/rockchip,rv1106-cru.h new file mode 100644 index 000000000000..d2567ccda94e --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rv1106-cru.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RV1106_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RV1106_H + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3Dlist all of reset fields id=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ + +/* PMU-->SOFTRST_CON00 */ +#define SRST_P_I2C1 0 +#define SRST_I2C1 1 +#define SRST_H_PMU_BIU 2 +#define SRST_P_PMU_BIU 3 +#define SRST_H_PMU_SRAM 4 +#define SRST_PMU_MCU 5 +#define SRST_PMU_MCU_PWRUP 6 +#define SRST_PMU_MCU_CPU 7 +#define SRST_T_PMU_MCU_CPU 8 + +/* PMU-->SOFTRST_CON01 */ +#define SRST_P_PMU_GPIO0 9 +#define SRST_PMU_GPIO0 10 +#define SRST_PVTM_PMU 11 +#define SRST_P_PVTM_PMU 12 +#define SRST_DDR_FAIL_SAFE 13 + +/* PMU-->SOFTRST_CON02 */ +#define SRST_P_PMU_HP_TIMER 14 +#define SRST_PMU_HP_TIMER 15 +#define SRST_PMU_32K_HP_TIMER 16 +#define SRST_P_PMU_IOC 17 +#define SRST_P_PMU_CRU 18 +#define SRST_P_PMU_GRF 19 +#define SRST_P_PMU_SGRF 20 +#define SRST_P_PMU_SGRF_REMAP 21 +#define SRST_P_PMU_WDT 22 +#define SRST_T_PMU_WDT 23 +#define SRST_P_PMU_MAILBOX 24 + +/* TOP-->SOFTRST_CON02 */ +#define SRST_REF_PVTPLL_0 25 +#define SRST_REF_PVTPLL_1 26 +#define SRST_P_CRU 27 +#define SRST_P_CRU_BIU 28 + +/* PERI-->SOFTRST_CON00 */ +#define SRST_P_PERI_BIU 29 +#define SRST_A_PERI_BIU 30 +#define SRST_H_PERI_BIU 31 +#define SRST_H_BOOTROM 32 +#define SRST_P_TIMER 33 +#define SRST_TIMER0 34 +#define SRST_TIMER1 35 +#define SRST_TIMER2 36 +#define SRST_TIMER3 37 +#define SRST_TIMER4 38 +#define SRST_TIMER5 39 +#define SRST_P_STIMER 40 + +/* PERI-->SOFTRST_CON01 */ +#define SRST_STIMER0 41 +#define SRST_STIMER1 42 +#define SRST_P_WDT_NS 43 +#define SRST_T_WDT_NS 44 +#define SRST_P_WDT_S 45 +#define SRST_T_WDT_S 46 +#define SRST_P_I2C0 47 +#define SRST_I2C0 48 +#define SRST_P_I2C2 49 +#define SRST_I2C2 50 +#define SRST_P_I2C3 51 +#define SRST_I2C3 52 +#define SRST_P_I2C4 53 +#define SRST_I2C4 54 + +/* PERI-->SOFTRST_CON02 */ +#define SRST_P_GPIO4 55 +#define SRST_GPIO4 56 +#define SRST_P_PERI_IOC 57 +#define SRST_P_UART2 58 +#define SRST_S_UART2 59 +#define SRST_P_UART3 60 +#define SRST_S_UART3 61 +#define SRST_P_UART4 62 +#define SRST_S_UART4 63 +#define SRST_P_UART5 64 + +/* PERI-->SOFTRST_CON03 */ +#define SRST_S_UART5 65 +#define SRST_P_SARADC 66 +#define SRST_SARADC 67 +#define SRST_SARADC_PHY 68 +#define SRST_P_SPI1 69 +#define SRST_SPI1 70 +#define SRST_H_TRNG_NS 71 +#define SRST_H_TRNG_S 72 +#define SRST_CORE_CRYPTO 73 +#define SRST_PKA_CRYPTO 74 +#define SRST_A_CRYPTO 75 +#define SRST_H_CRYPTO 76 +#define SRST_P_PWM1_PERI 77 + +/* PERI-->SOFTRST_CON04 */ +#define SRST_PWM1_PERI 78 +#define SRST_P_PWM2_PERI 79 +#define SRST_PWM2_PERI 80 +#define SRST_P_PERI_GRF 81 +#define SRST_P_PERI_CRU 82 +#define SRST_A_USBOTG 83 +#define SRST_A_BUS_BIU 84 +#define SRST_H_EMMC 85 +#define SRST_H_SFC 86 + +/* PERI-->SOFTRST_CON05 */ +#define SRST_S_SFC 87 +#define SRST_P_USBPHY 88 +#define SRST_USBPHY_POR 89 +#define SRST_USBPHY_OTG 90 +#define SRST_A_DMAC 91 +#define SRST_A_DECOM 92 +#define SRST_P_DECOM 93 +#define SRST_D_DECOM 94 +#define SRST_P_PERI_SGRF 95 +#define SRST_H_SAI 96 +#define SRST_M_SAI 97 +#define SRST_M_I2S0_8CH_TX 98 + +/* PERI-->SOFTRST_CON06 */ +#define SRST_H_I2S0 99 +#define SRST_M_DSM 100 +#define SRST_P_DSM 101 +#define SRST_P_ACODEC 102 +#define SRST_M_I2S0_8CH_RX 103 +#define SRST_P_DFT2APB 104 +#define SRST_H_IVE 105 +#define SRST_A_IVE 106 +#define SRST_P_UART0 107 +#define SRST_S_UART0 108 +#define SRST_P_UART1 109 + +/* PERI-->SOFTRST_CON07 */ +#define SRST_S_UART1 110 +#define SRST_P_PWM0_PERI 111 +#define SRST_PWM0_PERI 112 + +/* VI-->SOFTRST_CON00 */ +#define SRST_H_VI_BIU 113 +#define SRST_A_VI_BIU 114 +#define SRST_P_VI_BIU 115 +#define SRST_CORE_ISP3P2 116 +#define SRST_D_VICAP 117 +#define SRST_P_VICAP 118 +#define SRST_A_VICAP 119 +#define SRST_H_VICAP 120 +#define SRST_VICAP_I0 121 +#define SRST_VICAP_I1 122 + +/* VI-->SOFTRST_CON01 */ +#define SRST_VICAP_RX0 123 +#define SRST_VICAP_RX1 124 +#define SRST_VICAP_ISP0 125 +#define SRST_P_CSIHOST0 126 +#define SRST_P_CSIHOST1 127 +#define SRST_H_SDMMC 128 +#define SRST_SDMMC_DETN_FLT 129 +#define SRST_P_MIPICSIPHY 130 +#define SRST_P_GPIO3 131 + +/* VI-->SOFTRST_CON02 */ +#define SRST_GPIO3 132 +#define SRST_P_VI_IOC 133 +#define SRST_P_VI_GRF 134 +#define SRST_P_VI_SGRF 135 +#define SRST_P_VI_CRU 136 +#define SRST_P_VI_RTC_TEST 137 +#define SRST_P_VI_RTC_NIU 138 + +/* NPU-->SOFTRST_CON00 */ +#define SRST_H_NPU_BIU 139 +#define SRST_A_NPU_BIU 140 +#define SRST_P_NPU_BIU 141 +#define SRST_P_NPU_CRU 142 +#define SRST_P_NPU_SGRF 143 +#define SRST_P_NPU_GRF 144 +#define SRST_H_RKNN 145 +#define SRST_A_RKNN 146 + +/* CORE-->SOFTRST_CON00 */ +#define SRST_NCOREPORESET 147 +#define SRST_NCORESET 148 +#define SRST_NDBGRESET 149 +#define SRST_NL2RESET 150 +#define SRST_A_M_CORE_BIU 151 +#define SRST_P_DBG 152 +#define SRST_POT_DBG 153 +#define SRST_NT_DBG 154 +#define SRST_P_CORE_GRF 155 +#define SRST_H_CPU_BIU 156 +#define SRST_P_CPU_BIU 157 +#define SRST_PVTM_CORE 158 +#define SRST_P_PVTM_CORE 159 + +/* CORE-->SOFTRST_CON01 */ +#define SRST_REF_PVTPLL_CORE 160 +#define SRST_CORE_MCU 161 +#define SRST_CORE_MCU_PWRUP 162 +#define SRST_CORE_MCU_CPU 163 +#define SRST_T_CORE_MCU_CPU 164 +#define SRST_MCU_BIU 165 +#define SRST_P_MAILBOX 166 +#define SRST_P_INTMUX 167 +#define SRST_P_CORE_CRU 168 +#define SRST_P_CORE_SGRF 169 +#define SRST_H_CACHE 170 + +/* VEPU-->SOFTRST_CON00 */ +#define SRST_H_VEPU_BIU 171 +#define SRST_A_VEPU_BIU 172 +#define SRST_A_VEPU_COM_BIU 173 +#define SRST_P_VEPU_BIU 174 +#define SRST_H_VEPU 175 +#define SRST_A_VEPU 176 +#define SRST_CORE_VEPU 177 +#define SRST_H_VEPU_PP 178 +#define SRST_A_VEPU_PP 179 +#define SRST_CORE_VEPU_DVBM 180 +#define SRST_P_VICAP_VEPU 181 +#define SRST_P_GPIO1 182 + +/* VEPU-->SOFTRST_CON01 */ +#define SRST_GPIO1 183 +#define SRST_P_VEPU_IOC 184 +#define SRST_P_SPI0 185 +#define SRST_SPI0 186 +#define SRST_P_VEPU_CRU 187 +#define SRST_P_VEPU_SGRF 188 +#define SRST_P_VEPU_GRF 189 +#define SRST_UART_DETN_FLT 190 + +/* VO-->SOFTRST_CON00 */ +#define SRST_A_VO_BIU 191 +#define SRST_H_VO_BIU 192 +#define SRST_H_RGA2E 193 +#define SRST_A_RGA2E 194 +#define SRST_CORE_RGA2E 195 +#define SRST_P_VO_GRF 196 +#define SRST_A_VOP_BIU 197 +#define SRST_H_VOP 198 +#define SRST_D_VOP 199 +#define SRST_A_VOP 200 + +/* VO-->SOFTRST_CON01 */ +#define SRST_P_MAC_BIU 201 +#define SRST_A_MAC_BIU 202 +#define SRST_A_MAC 203 +#define SRST_P_VO_SGRF 204 +#define SRST_P_VO_CRU 205 +#define SRST_H_SDIO 206 + +/* VO-->SOFTRST_CON02 */ +#define SRST_P_TSADC 207 +#define SRST_TSADC 208 +#define SRST_P_OTPC_NS 209 +#define SRST_SBPI_OTPC_NS 210 +#define SRST_USER_OTPC_NS 211 +#define SRST_P_OTPC_S 212 +#define SRST_SBPI_OTPC_S 213 +#define SRST_USER_OTPC_S 214 +#define SRST_OTPC_ARB 215 +#define SRST_MACPHY 216 +#define SRST_P_OTP_MASK 217 +#define SRST_PMC_OTP 218 + +/* VO-->SOFTRST_CON03 */ +#define SRST_P_GPIO2 219 +#define SRST_GPIO2 220 +#define SRST_P_VO_IOC 221 + +/* DDR-->SOFTRST_CON00 */ +#define SRST_P_DDR_BIU 222 +#define SRST_P_DDRC 223 +#define SRST_P_DDRMON 224 +#define SRST_TIMER_DDRMON 225 +#define SRST_P_DFICTRL 226 +#define SRST_A_SYS_SHRM 227 +#define SRST_A_SHRM_NIU 228 +#define SRST_P_DDR_GRF 229 + +/* DDR-->SOFTRST_CON01 */ +#define SRST_P_DDR_CRU 230 +#define SRST_P_DDR_HWLP 231 +#define SRST_P_DDRPHY 232 + +/* SUBDDR-->SOFTRST_CON00 */ +#define SRST_MSCH_BIU 233 +#define SRST_A_DDRC 234 +#define SRST_CORE_DDRC 235 +#define SRST_DDRMON 236 +#define SRST_DFICTRL 237 +#define SRST_DDR_PHY 238 + +#endif --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BB903BBFC7; Mon, 10 Aug 2026 12:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364144; cv=none; b=ePqRGesUWPyTZ8VEzjTAUp73w+xjNNNXfDJ0knny3IwnKQgglkbZ0qQRVPsPSKZ5ZfMElEi+8748vNMnR14znxjxLBTnHngfJteDdvQBzekj1fugyCfw0Ql7L94DT7X+1klnrNbzA0d1AE/GpV5lnyvK2KWQlnqV0h6/mIlIb9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364144; c=relaxed/simple; bh=LmvlOQgMC9hl07aBqHbiKQeEXzvWxYsIIDpGMPlswTM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=L65CHwJZw8iVXWW1KLcVBTFHwxT0W+lb3YnHWPdmxy++wX41218ZBg++AFxvttdrGQL+p2PYp/UMZX97TU4x65A1A+vnGvra3crTuXQP8890Pg3wmTw+tcBMkBUNbosy9WHBWV41VjjEPRWfAtUOfaKxZdJjUAQy871MvcUn3qo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=kSn9sISU; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="kSn9sISU" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3A2FAC0515; Mon, 10 Aug 2026 15:15:38 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364139; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=6a87aqRaR39IxOlf9jr04hynwmjap3BR0d8ylmCASYU=; b=kSn9sISUfU3rakYNwxDLNCno9h2PYtqJlplMujYucoqqG37V29tS4F07S39NHetrqRw76j jcentJNJR1dXHo5+v+sOf2a93/sizOPbKaMjiE3L+/rdXfHET9QJJHsN57xUS5axRLmRaj 0tA7d+p9TfvnEYWvkVmU8KxTepsBa9w5N0G433zBvDuM1eUnE3WLvyQgKHM55hsWhwCyWx n89sqJ5babzUzsjz8UIvDk7k2ACq2cvjv3R7Ybxsj9nglnbyeguhQa3TAkQvyodtmYuR8m EOjAzaHLNqPdkYdv0bOeYkznWBrZISesD4kJu/jZEq2edI3mNSLo+5ULhbZcKA== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Brian Masney , Heiko Stuebner , Michael Turquette , Stephen Boyd Subject: [PATCH 02/25] clk: rockchip: Add reset controller support for RV1106 Date: Mon, 10 Aug 2026 15:10:53 +0300 Message-ID: <20260810121121.210040-3-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Implement the reset controller for the RV1106 CRU by wiring up the software reset registers and exposing them through the reset framework. Hook the registration into clk-rv1106 and add the per-register reset lookup table in rst-rv1106.c. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- drivers/clk/rockchip/Makefile | 2 +- drivers/clk/rockchip/clk-rv1106.c | 2 + drivers/clk/rockchip/clk.h | 1 + drivers/clk/rockchip/rst-rv1106.c | 340 ++++++++++++++++++++++++++++++ 4 files changed, 344 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/rockchip/rst-rv1106.c diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 554b7eb83dc9..e511018477f3 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -19,7 +19,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) +=3D softrst.o =20 obj-$(CONFIG_CLK_PX30) +=3D clk-px30.o obj-$(CONFIG_CLK_RV1103B) +=3D clk-rv1103b.o -obj-$(CONFIG_CLK_RV1106) +=3D clk-rv1106.o +obj-$(CONFIG_CLK_RV1106) +=3D clk-rv1106.o rst-rv1106.o obj-$(CONFIG_CLK_RV110X) +=3D clk-rv1108.o obj-$(CONFIG_CLK_RV1126) +=3D clk-rv1126.o obj-$(CONFIG_CLK_RV1126B) +=3D clk-rv1126b.o rst-rv1126b.o diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-r= v1106.c index 3f26573e6cb7..1e3a110192bb 100644 --- a/drivers/clk/rockchip/clk-rv1106.c +++ b/drivers/clk/rockchip/clk-rv1106.c @@ -1077,6 +1077,8 @@ static int __init clk_rv1106_probe(struct platform_de= vice *pdev) ARRAY_SIZE(rv1106_grf_clk_branches)); } =20 + rv1106_rst_init(np, reg_base); + rockchip_register_restart_notifier(ctx, RV1106_GLB_SRST_FST, NULL); =20 rockchip_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 9e3503e2ffc2..ef258c77b243 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -1392,6 +1392,7 @@ static inline void rockchip_register_softrst(struct d= evice_node *np, return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); } =20 +void rv1106_rst_init(struct device_node *np, void __iomem *reg_base); void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base); void rk3506_rst_init(struct device_node *np, void __iomem *reg_base); void rk3528_rst_init(struct device_node *np, void __iomem *reg_base); diff --git a/drivers/clk/rockchip/rst-rv1106.c b/drivers/clk/rockchip/rst-r= v1106.c new file mode 100644 index 000000000000..5055c0a54d3f --- /dev/null +++ b/drivers/clk/rockchip/rst-rv1106.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Copyright (c) 2026 Vladislav Leonov + * Author: Vladislav Leonov + * Based on Elaine Zhang's implementation for RV1126B + */ + +#include +#include +#include +#include "clk.h" + +#define SOFTRST_CON(x) ((x) * 0x4 + 0xa00) + +/* CRU base 0x00000 (PMU) + 0x0A00 */ +#define PMUCRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x0 * 4 + reg * 16 + b= it) +/* CRU base 0x10000 (TOP) + 0x0A00 */ +#define TOPCRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x10000 * 4 + reg * 16= + bit) +/* CRU base 0x12000 (PERI) + 0x0A00 */ +#define PERICRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x12000 * 4 + reg * 1= 6 + bit) +/* CRU base 0x14000 (VI) + 0x0A00 */ +#define VICRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x14000 * 4 + reg * 16 = + bit) +/* CRU base 0x16000 (NPU) + 0x0A00 */ +#define NPUCRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x16000 * 4 + reg * 16= + bit) +/* CRU base 0x18000 (CORE) + 0x0A00 */ +#define CORECRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x18000 * 4 + reg * 1= 6 + bit) +/* CRU base 0x1a000 (VEPU) + 0x0A00 */ +#define VEPUCRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x1a000 * 4 + reg * 1= 6 + bit) +/* CRU base 0x1c000 (VO) + 0x0A00 */ +#define VOCRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x1c000 * 4 + reg * 16 = + bit) +/* CRU base 0x1e000 (DDR) + 0x0A00 */ +#define DDRCRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x1e000 * 4 + reg * 16= + bit) +/* CRU base 0x1f000 (SUBDDR) + 0x0A00 */ +#define SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] =3D (0x1f000 * 4 + reg *= 16 + bit) + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3Dmapping table for re= set ID to register offset=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D */ +static const int rv1106_register_offset[] =3D { + /* PMU-->SOFTRST_CON00 */ + PMUCRU_RESET_OFFSET(SRST_P_I2C1, 0, 3), + PMUCRU_RESET_OFFSET(SRST_I2C1, 0, 4), + PMUCRU_RESET_OFFSET(SRST_H_PMU_BIU, 0, 6), + PMUCRU_RESET_OFFSET(SRST_P_PMU_BIU, 0, 7), + PMUCRU_RESET_OFFSET(SRST_H_PMU_SRAM, 0, 8), + PMUCRU_RESET_OFFSET(SRST_PMU_MCU, 0, 9), + PMUCRU_RESET_OFFSET(SRST_PMU_MCU_PWRUP, 0, 10), + PMUCRU_RESET_OFFSET(SRST_PMU_MCU_CPU, 0, 11), + PMUCRU_RESET_OFFSET(SRST_T_PMU_MCU_CPU, 0, 12), + + /* PMU-->SOFTRST_CON01 */ + PMUCRU_RESET_OFFSET(SRST_P_PMU_GPIO0, 1, 2), + PMUCRU_RESET_OFFSET(SRST_PMU_GPIO0, 1, 3), + PMUCRU_RESET_OFFSET(SRST_PVTM_PMU, 1, 4), + PMUCRU_RESET_OFFSET(SRST_P_PVTM_PMU, 1, 5), + PMUCRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 15), + + /* PMU-->SOFTRST_CON02 */ + PMUCRU_RESET_OFFSET(SRST_P_PMU_HP_TIMER, 2, 0), + PMUCRU_RESET_OFFSET(SRST_PMU_HP_TIMER, 2, 1), + PMUCRU_RESET_OFFSET(SRST_PMU_32K_HP_TIMER, 2, 2), + PMUCRU_RESET_OFFSET(SRST_P_PMU_IOC, 2, 3), + PMUCRU_RESET_OFFSET(SRST_P_PMU_CRU, 2, 4), + PMUCRU_RESET_OFFSET(SRST_P_PMU_GRF, 2, 5), + PMUCRU_RESET_OFFSET(SRST_P_PMU_SGRF, 2, 6), + PMUCRU_RESET_OFFSET(SRST_P_PMU_SGRF_REMAP, 2, 7), + PMUCRU_RESET_OFFSET(SRST_P_PMU_WDT, 2, 8), + PMUCRU_RESET_OFFSET(SRST_T_PMU_WDT, 2, 9), + PMUCRU_RESET_OFFSET(SRST_P_PMU_MAILBOX, 2, 10), + + /* TOP-->SOFTRST_CON02 */ + TOPCRU_RESET_OFFSET(SRST_REF_PVTPLL_0, 2, 7), + TOPCRU_RESET_OFFSET(SRST_REF_PVTPLL_1, 2, 8), + TOPCRU_RESET_OFFSET(SRST_P_CRU, 2, 10), + TOPCRU_RESET_OFFSET(SRST_P_CRU_BIU, 2, 11), + + /* PERI-->SOFTRST_CON00 */ + PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 0, 4), + PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 0, 5), + PERICRU_RESET_OFFSET(SRST_H_PERI_BIU, 0, 6), + PERICRU_RESET_OFFSET(SRST_H_BOOTROM, 0, 7), + PERICRU_RESET_OFFSET(SRST_P_TIMER, 0, 8), + PERICRU_RESET_OFFSET(SRST_TIMER0, 0, 9), + PERICRU_RESET_OFFSET(SRST_TIMER1, 0, 10), + PERICRU_RESET_OFFSET(SRST_TIMER2, 0, 11), + PERICRU_RESET_OFFSET(SRST_TIMER3, 0, 12), + PERICRU_RESET_OFFSET(SRST_TIMER4, 0, 13), + PERICRU_RESET_OFFSET(SRST_TIMER5, 0, 14), + PERICRU_RESET_OFFSET(SRST_P_STIMER, 0, 15), + + /* PERI-->SOFTRST_CON01 */ + PERICRU_RESET_OFFSET(SRST_STIMER0, 1, 0), + PERICRU_RESET_OFFSET(SRST_STIMER1, 1, 1), + PERICRU_RESET_OFFSET(SRST_P_WDT_NS, 1, 2), + PERICRU_RESET_OFFSET(SRST_T_WDT_NS, 1, 3), + PERICRU_RESET_OFFSET(SRST_P_WDT_S, 1, 4), + PERICRU_RESET_OFFSET(SRST_T_WDT_S, 1, 5), + PERICRU_RESET_OFFSET(SRST_P_I2C0, 1, 6), + PERICRU_RESET_OFFSET(SRST_I2C0, 1, 7), + PERICRU_RESET_OFFSET(SRST_P_I2C2, 1, 10), + PERICRU_RESET_OFFSET(SRST_I2C2, 1, 11), + PERICRU_RESET_OFFSET(SRST_P_I2C3, 1, 12), + PERICRU_RESET_OFFSET(SRST_I2C3, 1, 13), + PERICRU_RESET_OFFSET(SRST_P_I2C4, 1, 14), + PERICRU_RESET_OFFSET(SRST_I2C4, 1, 15), + + /* PERI-->SOFTRST_CON02 */ + PERICRU_RESET_OFFSET(SRST_P_GPIO4, 2, 0), + PERICRU_RESET_OFFSET(SRST_GPIO4, 2, 1), + PERICRU_RESET_OFFSET(SRST_P_PERI_IOC, 2, 2), + PERICRU_RESET_OFFSET(SRST_P_UART2, 2, 3), + PERICRU_RESET_OFFSET(SRST_S_UART2, 2, 6), + PERICRU_RESET_OFFSET(SRST_P_UART3, 2, 7), + PERICRU_RESET_OFFSET(SRST_S_UART3, 2, 10), + PERICRU_RESET_OFFSET(SRST_P_UART4, 2, 11), + PERICRU_RESET_OFFSET(SRST_S_UART4, 2, 14), + PERICRU_RESET_OFFSET(SRST_P_UART5, 2, 15), + + /* PERI-->SOFTRST_CON03 */ + PERICRU_RESET_OFFSET(SRST_S_UART5, 3, 2), + PERICRU_RESET_OFFSET(SRST_P_SARADC, 3, 3), + PERICRU_RESET_OFFSET(SRST_SARADC, 3, 4), + PERICRU_RESET_OFFSET(SRST_SARADC_PHY, 3, 5), + PERICRU_RESET_OFFSET(SRST_P_SPI1, 3, 6), + PERICRU_RESET_OFFSET(SRST_SPI1, 3, 7), + PERICRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 9), + PERICRU_RESET_OFFSET(SRST_H_TRNG_S, 3, 10), + PERICRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 11), + PERICRU_RESET_OFFSET(SRST_PKA_CRYPTO, 3, 12), + PERICRU_RESET_OFFSET(SRST_A_CRYPTO, 3, 13), + PERICRU_RESET_OFFSET(SRST_H_CRYPTO, 3, 14), + PERICRU_RESET_OFFSET(SRST_P_PWM1_PERI, 3, 15), + + /* PERI-->SOFTRST_CON04 */ + PERICRU_RESET_OFFSET(SRST_PWM1_PERI, 4, 0), + PERICRU_RESET_OFFSET(SRST_P_PWM2_PERI, 4, 2), + PERICRU_RESET_OFFSET(SRST_PWM2_PERI, 4, 3), + PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 4, 5), + PERICRU_RESET_OFFSET(SRST_P_PERI_CRU, 4, 6), + PERICRU_RESET_OFFSET(SRST_A_USBOTG, 4, 7), + PERICRU_RESET_OFFSET(SRST_A_BUS_BIU, 4, 10), + PERICRU_RESET_OFFSET(SRST_H_EMMC, 4, 13), + PERICRU_RESET_OFFSET(SRST_H_SFC, 4, 14), + + /* PERI-->SOFTRST_CON05 */ + PERICRU_RESET_OFFSET(SRST_S_SFC, 5, 0), + PERICRU_RESET_OFFSET(SRST_P_USBPHY, 5, 1), + PERICRU_RESET_OFFSET(SRST_USBPHY_POR, 5, 2), + PERICRU_RESET_OFFSET(SRST_USBPHY_OTG, 5, 3), + PERICRU_RESET_OFFSET(SRST_A_DMAC, 5, 8), + PERICRU_RESET_OFFSET(SRST_A_DECOM, 5, 9), + PERICRU_RESET_OFFSET(SRST_P_DECOM, 5, 10), + PERICRU_RESET_OFFSET(SRST_D_DECOM, 5, 11), + PERICRU_RESET_OFFSET(SRST_P_PERI_SGRF, 5, 12), + PERICRU_RESET_OFFSET(SRST_H_SAI, 5, 13), + PERICRU_RESET_OFFSET(SRST_M_SAI, 5, 14), + PERICRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 5, 15), + + /* PERI-->SOFTRST_CON06 */ + PERICRU_RESET_OFFSET(SRST_H_I2S0, 6, 0), + PERICRU_RESET_OFFSET(SRST_M_DSM, 6, 1), + PERICRU_RESET_OFFSET(SRST_P_DSM, 6, 2), + PERICRU_RESET_OFFSET(SRST_P_ACODEC, 6, 3), + PERICRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 6, 6), + PERICRU_RESET_OFFSET(SRST_P_DFT2APB, 6, 7), + PERICRU_RESET_OFFSET(SRST_H_IVE, 6, 9), + PERICRU_RESET_OFFSET(SRST_A_IVE, 6, 10), + PERICRU_RESET_OFFSET(SRST_P_UART0, 6, 11), + PERICRU_RESET_OFFSET(SRST_S_UART0, 6, 14), + PERICRU_RESET_OFFSET(SRST_P_UART1, 6, 15), + + /* PERI-->SOFTRST_CON07 */ + PERICRU_RESET_OFFSET(SRST_S_UART1, 7, 2), + PERICRU_RESET_OFFSET(SRST_P_PWM0_PERI, 7, 3), + PERICRU_RESET_OFFSET(SRST_PWM0_PERI, 7, 4), + + /* VI-->SOFTRST_CON00 */ + VICRU_RESET_OFFSET(SRST_H_VI_BIU, 0, 4), + VICRU_RESET_OFFSET(SRST_A_VI_BIU, 0, 5), + VICRU_RESET_OFFSET(SRST_P_VI_BIU, 0, 6), + VICRU_RESET_OFFSET(SRST_CORE_ISP3P2, 0, 9), + VICRU_RESET_OFFSET(SRST_D_VICAP, 0, 10), + VICRU_RESET_OFFSET(SRST_P_VICAP, 0, 11), + VICRU_RESET_OFFSET(SRST_A_VICAP, 0, 12), + VICRU_RESET_OFFSET(SRST_H_VICAP, 0, 13), + VICRU_RESET_OFFSET(SRST_VICAP_I0, 0, 14), + VICRU_RESET_OFFSET(SRST_VICAP_I1, 0, 15), + + /* VI-->SOFTRST_CON01 */ + VICRU_RESET_OFFSET(SRST_VICAP_RX0, 1, 0), + VICRU_RESET_OFFSET(SRST_VICAP_RX1, 1, 1), + VICRU_RESET_OFFSET(SRST_VICAP_ISP0, 1, 2), + VICRU_RESET_OFFSET(SRST_P_CSIHOST0, 1, 4), + VICRU_RESET_OFFSET(SRST_P_CSIHOST1, 1, 6), + VICRU_RESET_OFFSET(SRST_H_SDMMC, 1, 12), + VICRU_RESET_OFFSET(SRST_SDMMC_DETN_FLT, 1, 13), + VICRU_RESET_OFFSET(SRST_P_MIPICSIPHY, 1, 14), + VICRU_RESET_OFFSET(SRST_P_GPIO3, 1, 15), + + /* VI-->SOFTRST_CON02 */ + VICRU_RESET_OFFSET(SRST_GPIO3, 2, 0), + VICRU_RESET_OFFSET(SRST_P_VI_IOC, 2, 1), + VICRU_RESET_OFFSET(SRST_P_VI_GRF, 2, 2), + VICRU_RESET_OFFSET(SRST_P_VI_SGRF, 2, 3), + VICRU_RESET_OFFSET(SRST_P_VI_CRU, 2, 4), + VICRU_RESET_OFFSET(SRST_P_VI_RTC_TEST, 2, 5), + VICRU_RESET_OFFSET(SRST_P_VI_RTC_NIU, 2, 7), + + /* NPU-->SOFTRST_CON00 */ + NPUCRU_RESET_OFFSET(SRST_H_NPU_BIU, 0, 3), + NPUCRU_RESET_OFFSET(SRST_A_NPU_BIU, 0, 4), + NPUCRU_RESET_OFFSET(SRST_P_NPU_BIU, 0, 5), + NPUCRU_RESET_OFFSET(SRST_P_NPU_CRU, 0, 6), + NPUCRU_RESET_OFFSET(SRST_P_NPU_SGRF, 0, 7), + NPUCRU_RESET_OFFSET(SRST_P_NPU_GRF, 0, 8), + NPUCRU_RESET_OFFSET(SRST_H_RKNN, 0, 9), + NPUCRU_RESET_OFFSET(SRST_A_RKNN, 0, 10), + + /* CORE-->SOFTRST_CON00 */ + CORECRU_RESET_OFFSET(SRST_NCOREPORESET, 0, 1), + CORECRU_RESET_OFFSET(SRST_NCORESET, 0, 2), + CORECRU_RESET_OFFSET(SRST_NDBGRESET, 0, 3), + CORECRU_RESET_OFFSET(SRST_NL2RESET, 0, 4), + CORECRU_RESET_OFFSET(SRST_A_M_CORE_BIU, 0, 5), + CORECRU_RESET_OFFSET(SRST_P_DBG, 0, 6), + CORECRU_RESET_OFFSET(SRST_POT_DBG, 0, 7), + CORECRU_RESET_OFFSET(SRST_NT_DBG, 0, 8), + CORECRU_RESET_OFFSET(SRST_P_CORE_GRF, 0, 11), + CORECRU_RESET_OFFSET(SRST_H_CPU_BIU, 0, 12), + CORECRU_RESET_OFFSET(SRST_P_CPU_BIU, 0, 13), + CORECRU_RESET_OFFSET(SRST_PVTM_CORE, 0, 14), + CORECRU_RESET_OFFSET(SRST_P_PVTM_CORE, 0, 15), + + /* CORE-->SOFTRST_CON01 */ + CORECRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 1, 0), + CORECRU_RESET_OFFSET(SRST_CORE_MCU, 1, 1), + CORECRU_RESET_OFFSET(SRST_CORE_MCU_PWRUP, 1, 2), + CORECRU_RESET_OFFSET(SRST_CORE_MCU_CPU, 1, 3), + CORECRU_RESET_OFFSET(SRST_T_CORE_MCU_CPU, 1, 4), + CORECRU_RESET_OFFSET(SRST_MCU_BIU, 1, 5), + CORECRU_RESET_OFFSET(SRST_P_MAILBOX, 1, 8), + CORECRU_RESET_OFFSET(SRST_P_INTMUX, 1, 9), + CORECRU_RESET_OFFSET(SRST_P_CORE_CRU, 1, 10), + CORECRU_RESET_OFFSET(SRST_P_CORE_SGRF, 1, 11), + CORECRU_RESET_OFFSET(SRST_H_CACHE, 1, 12), + + /* VEPU-->SOFTRST_CON00 */ + VEPUCRU_RESET_OFFSET(SRST_H_VEPU_BIU, 0, 4), + VEPUCRU_RESET_OFFSET(SRST_A_VEPU_BIU, 0, 5), + VEPUCRU_RESET_OFFSET(SRST_A_VEPU_COM_BIU, 0, 6), + VEPUCRU_RESET_OFFSET(SRST_P_VEPU_BIU, 0, 7), + VEPUCRU_RESET_OFFSET(SRST_H_VEPU, 0, 8), + VEPUCRU_RESET_OFFSET(SRST_A_VEPU, 0, 9), + VEPUCRU_RESET_OFFSET(SRST_CORE_VEPU, 0, 10), + VEPUCRU_RESET_OFFSET(SRST_H_VEPU_PP, 0, 11), + VEPUCRU_RESET_OFFSET(SRST_A_VEPU_PP, 0, 12), + VEPUCRU_RESET_OFFSET(SRST_CORE_VEPU_DVBM, 0, 13), + VEPUCRU_RESET_OFFSET(SRST_P_VICAP_VEPU, 0, 14), + VEPUCRU_RESET_OFFSET(SRST_P_GPIO1, 0, 15), + + /* VEPU-->SOFTRST_CON01 */ + VEPUCRU_RESET_OFFSET(SRST_GPIO1, 1, 0), + VEPUCRU_RESET_OFFSET(SRST_P_VEPU_IOC, 1, 1), + VEPUCRU_RESET_OFFSET(SRST_P_SPI0, 1, 2), + VEPUCRU_RESET_OFFSET(SRST_SPI0, 1, 3), + VEPUCRU_RESET_OFFSET(SRST_P_VEPU_CRU, 1, 5), + VEPUCRU_RESET_OFFSET(SRST_P_VEPU_SGRF, 1, 6), + VEPUCRU_RESET_OFFSET(SRST_P_VEPU_GRF, 1, 7), + VEPUCRU_RESET_OFFSET(SRST_UART_DETN_FLT, 1, 8), + + /* VO-->SOFTRST_CON00 */ + VOCRU_RESET_OFFSET(SRST_A_VO_BIU, 0, 3), + VOCRU_RESET_OFFSET(SRST_H_VO_BIU, 0, 4), + VOCRU_RESET_OFFSET(SRST_H_RGA2E, 0, 7), + VOCRU_RESET_OFFSET(SRST_A_RGA2E, 0, 8), + VOCRU_RESET_OFFSET(SRST_CORE_RGA2E, 0, 9), + VOCRU_RESET_OFFSET(SRST_P_VO_GRF, 0, 10), + VOCRU_RESET_OFFSET(SRST_A_VOP_BIU, 0, 12), + VOCRU_RESET_OFFSET(SRST_H_VOP, 0, 13), + VOCRU_RESET_OFFSET(SRST_D_VOP, 0, 14), + VOCRU_RESET_OFFSET(SRST_A_VOP, 0, 15), + + /* VO-->SOFTRST_CON01 */ + VOCRU_RESET_OFFSET(SRST_P_MAC_BIU, 1, 6), + VOCRU_RESET_OFFSET(SRST_A_MAC_BIU, 1, 7), + VOCRU_RESET_OFFSET(SRST_A_MAC, 1, 8), + VOCRU_RESET_OFFSET(SRST_P_VO_SGRF, 1, 12), + VOCRU_RESET_OFFSET(SRST_P_VO_CRU, 1, 13), + VOCRU_RESET_OFFSET(SRST_H_SDIO, 1, 15), + + /* VO-->SOFTRST_CON02 */ + VOCRU_RESET_OFFSET(SRST_P_TSADC, 2, 0), + VOCRU_RESET_OFFSET(SRST_TSADC, 2, 1), + VOCRU_RESET_OFFSET(SRST_P_OTPC_NS, 2, 3), + VOCRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 2, 5), + VOCRU_RESET_OFFSET(SRST_USER_OTPC_NS, 2, 6), + VOCRU_RESET_OFFSET(SRST_P_OTPC_S, 2, 7), + VOCRU_RESET_OFFSET(SRST_SBPI_OTPC_S, 2, 9), + VOCRU_RESET_OFFSET(SRST_USER_OTPC_S, 2, 10), + VOCRU_RESET_OFFSET(SRST_OTPC_ARB, 2, 11), + VOCRU_RESET_OFFSET(SRST_MACPHY, 2, 13), + VOCRU_RESET_OFFSET(SRST_P_OTP_MASK, 2, 14), + VOCRU_RESET_OFFSET(SRST_PMC_OTP, 2, 15), + + /* VO-->SOFTRST_CON03 */ + VOCRU_RESET_OFFSET(SRST_P_GPIO2, 3, 0), + VOCRU_RESET_OFFSET(SRST_GPIO2, 3, 1), + VOCRU_RESET_OFFSET(SRST_P_VO_IOC, 3, 2), + + /* DDR-->SOFTRST_CON00 */ + DDRCRU_RESET_OFFSET(SRST_P_DDR_BIU, 0, 2), + DDRCRU_RESET_OFFSET(SRST_P_DDRC, 0, 5), + DDRCRU_RESET_OFFSET(SRST_P_DDRMON, 0, 7), + DDRCRU_RESET_OFFSET(SRST_TIMER_DDRMON, 0, 8), + DDRCRU_RESET_OFFSET(SRST_P_DFICTRL, 0, 11), + DDRCRU_RESET_OFFSET(SRST_A_SYS_SHRM, 0, 13), + DDRCRU_RESET_OFFSET(SRST_A_SHRM_NIU, 0, 14), + DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 0, 15), + + /* DDR-->SOFTRST_CON01 */ + DDRCRU_RESET_OFFSET(SRST_P_DDR_CRU, 1, 0), + DDRCRU_RESET_OFFSET(SRST_P_DDR_HWLP, 1, 2), + DDRCRU_RESET_OFFSET(SRST_P_DDRPHY, 1, 3), + + /* SUBDDR-->SOFTRST_CON00 */ + SUBDDRCRU_RESET_OFFSET(SRST_MSCH_BIU, 0, 0), + SUBDDRCRU_RESET_OFFSET(SRST_A_DDRC, 0, 1), + SUBDDRCRU_RESET_OFFSET(SRST_CORE_DDRC, 0, 3), + SUBDDRCRU_RESET_OFFSET(SRST_DDRMON, 0, 4), + SUBDDRCRU_RESET_OFFSET(SRST_DFICTRL, 0, 5), + SUBDDRCRU_RESET_OFFSET(SRST_DDR_PHY, 0, 6), +}; + +void rv1106_rst_init(struct device_node *np, void __iomem *reg_base) +{ + rockchip_register_softrst_lut(np, + rv1106_register_offset, + ARRAY_SIZE(rv1106_register_offset), + reg_base + SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); +} --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48E753D969B; Mon, 10 Aug 2026 12:15:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364146; cv=none; b=d6YGT6hxvGg8X3K7Kri2kXugUfNVhV6JD7OMkDUakLKOBiW/elTqLjwLpbHiEnU7ZBVfFddrMvM6FDWRYQVdRzHVUdOYCxlW1TEINpfp5TNNIx5p60dNJ2z1QGM+3WGhwcmyvuMVFhodnoST7MyjyXfd2ouJLZvPWKgLQSotigQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364146; c=relaxed/simple; bh=9kpZc3zCVYNc7OjO/sbGTOXmDC+Zl9ah6ei6e88BSKw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=grZWsfsg6jDRAVxwrTohnMsnMW60z2Nw5SincUsvndrga2kwZmpYjeeXT5Km9EPZXSOILLDzFXsSDkW9QYWF+tBNIzbMC8AbQNEQUoxLmALAma9jw3nPV8Qws1XmdGx5WXP8xdvg5OKfnKrhCYH9RySS28UpR4l5t/t+q+rY5tI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=jd2e4Mtb; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="jd2e4Mtb" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7CB72C0516; Mon, 10 Aug 2026 15:15:40 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364141; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=v1XLSf6ZDB/wEqrRtkdlR8YK8IVnmgU/VbtIqk1IzZk=; b=jd2e4MtboCVn2w1QPDe/Im5f/LMETb6HuTl6ESnZ4NMjl7H/x6TkM3szAKfDAbQDrU1S0r Xoj2sdSLWDJFDtqPT9hlfMiPQpSH1EQhU04PyARXyehUa4SvzGMVy/ayGzXO8FT2uBKMVF VJLEJSXxNbYUcuOUMrz5UYjOedsXukd440taUfpf1sMxTLEeXCAf1l5DOLKSrVwEIRH2Y+ 6I7LJLeiW3fa5alzAf1ASqUUYkL4OAk+LykgL7P30kq3l75MerT4ShUdS61brB1xIBc4LK 8zHWxqTy4JACFR+c+4XL3g0a0MiNoNlKuquogslOVgqcqjoPCQJm9hua47Kg3Q== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 03/25] ARM: dts: rockchip: Add reset bindings to RV1106 Date: Mon, 10 Aug 2026 15:10:54 +0300 Message-ID: <20260810121121.210040-4-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Include the RV1106 CRU reset-ID header so device tree nodes can reference reset lines by name, matching the reset controller support added in the previous commit. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index 70d3da6bd03e..fa5d0d7f4dcb 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9B3E3DA5AF; Mon, 10 Aug 2026 12:15:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364149; cv=none; b=HBU9uapcVrqF2yw161MSvNsBnz8jWMEI1aE2Dn/3TawDPjZHLfHmRzCbVZUEMrLO0qOq5vj0QXTQi0hc8CfuBX5kPJLjCjXwWUTp2Fz6F/Gp08/nodd4qUOMYDkgN3oTMwI/CCdjg2CHyTc1nfQqcd7E/IKNFhsTq5Nu0bLRF5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364149; c=relaxed/simple; bh=M1FEvrydZ3cAT5N5FfbTHX7UZCogZ/FJ8FFgL2S3Yl4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EtqFx1ImFllw5peKdtAGS73GewG0TkSZ+ik/4sYJgUaW4rsIW3l2RnOPqSWnt2tpWPF4SqA988nMQLTxsnKa6L2npQxzLVAEXAB9Hyg/Ka24IpGoCs7WOSSwM9Nic17o0/tuwOe5c/4CzClYiXsIygp5yBV0QRZrKh3xf4VLB2k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=UeIEk5zM; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="UeIEk5zM" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id BB833BFA89; Mon, 10 Aug 2026 15:15:42 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364144; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Hf3hq9uUQWUEz8YvFbiRVgRTtJAkRTrXQ6MRYpIYIEw=; b=UeIEk5zMajwNW4r8+weqNaNRWkDcX2R+4atx7y05y44m8kQkfK4J0lgfbgNpBSgxIOE/jV gDX1GEexBCpwzJ1mllZ9trQnv7mjFLGJ5ArO7FYqnWxcbizrpnUzbZUk3l4/W+JN6pNUHw A1dfYLT8jDIf5gCCTsbiP275HG8GFp6rJOEfjTneZqocPnbC49wvnftdmeg2iZiEemi54O CwwgmNseusKz7usvNoa7dhbEzLG/lX2EawL5RONj0oViXHKOWq94hFMdHBMqxsaKt8rDaJ kK2UbRp3MYteDJoxE6M5iE4S/1fJ9Xedf4jtwwwqxtMLmUy6+wuaHyb0Mv5XNQ== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Andrew Lunn , Conor Dooley , "David S. Miller" , David Wu , Eric Dumazet , Heiko Stuebner , Jakub Kicinski , Krzysztof Kozlowski , Paolo Abeni , Rob Herring , netdev@vger.kernel.org Subject: [PATCH 04/25] dt-bindings: net: rockchip-dwmac: add RV1106 compatible Date: Mon, 10 Aug 2026 15:10:55 +0300 Message-ID: <20260810121121.210040-5-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add compatible string for RV1106 gmac, and constrain it to be compatible with Synopsys dwmac 4.20a. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- Documentation/devicetree/bindings/net/rockchip-dwmac.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Do= cumentation/devicetree/bindings/net/rockchip-dwmac.yaml index 80c252845349..65eee45f7d7e 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml @@ -29,6 +29,7 @@ select: - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac + - rockchip,rv1106-gmac - rockchip,rv1108-gmac - rockchip,rv1126-gmac required: @@ -56,6 +57,7 @@ properties: - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac + - rockchip,rv1106-gmac - rockchip,rv1126-gmac - const: snps,dwmac-4.20a =20 --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02BE53D8901; Mon, 10 Aug 2026 12:15:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364152; cv=none; b=pWLNj8OC886sOnJtp+JnwM82dn1Dotn3UOj57Ratzq25jQJCcy9e+0jdzrrrohTw8PgKO9UJFv/rE97wehpOS9fEaGvOUvQl1NgTXxXBclap9qoY08NQqVcEoRwuLA+t77xYOGKeauq+KsJleGJFAMx/DaxEsz0M5p1Zi39gQO4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364152; c=relaxed/simple; bh=NQyJJlcPFAO0sM7qXsqPILz7OOJlZWfyA8v7GbUfGq8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iS+hESI5e5GzGADS4b8GGo1ropFhtS31ps5chYKZOb1jLSN78/FRWEsF1eLlacKwaFXk8TsptXb47Ah8Xq9RV1ii/8a4MGMzPv7BrmGPuggxaSCLLxL/aGTv/ihWzpQYMnj2Fj6zHRuK5W7KXADpT8TYF2lz7avKZ0rw0eBihE0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=EupqziQl; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="EupqziQl" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9BB7BC0517; Mon, 10 Aug 2026 15:15:46 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364149; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ja3ddn8Iyrr0BPUQgL0q4vghx18v/jp3QyN5ZHrPqoo=; b=EupqziQltR4M0MziVrus8tmeNouchv6VjiDPgtVw/CnZ/Xkk5OjmGmZKXQgQxjIxe5sQ3e ghMdgnPty6SMJghCBu5sFgnJBpBB3ytSkam3ttej8Ax8rPYzoXvNwQqPqhUj3nVGHxT0j5 X50lCTYYm3IvMiw+xO/yRsIG56vxB/Xf5KC5jNT7xBxN4asHahNXGu4Njv8e/LATX3II68 67fwUFva8u3F81TvAh7WFmqcpKI5q3R3a1klP/uG4ji2cz+/WwEFY1AgwW50dwgLVt1s4y 99rn7TEuKNIKNc97tgyM/URj99DByOIcWvuR++LmxFwPcZfhNxQPQQCUpB19NA== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Alexandre Torgue , Andrew Lunn , "David S. Miller" , Eric Dumazet , Heiko Stuebner , Jakub Kicinski , Maxime Chevallier , Maxime Coquelin , Paolo Abeni , linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org Subject: [PATCH 05/25] net: ethernet: stmicro: stmmac: dwmac-rk: Add RV1106 support Date: Mon, 10 Aug 2026 15:10:56 +0300 Message-ID: <20260810121121.210040-6-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Rockchip RV1106 GMAC 10/100 ethernet controller. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/e= thernet/stmicro/stmmac/dwmac-rk.c index 8d7042e68926..a1bf545467cc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -1034,6 +1034,60 @@ static const struct rk_gmac_ops rk3588_ops =3D { }, }; =20 +#define RV1106_VOGRF_GMAC_CLK_CON 0X60004 + +#define RV1106_VOGRF_MACPHY_RMII_MODE GRF_BIT(0) +#define RV1106_VOGRF_GMAC_CLK_RMII_DIV2 GRF_BIT(2) +#define RV1106_VOGRF_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(2) + +#define RV1106_VOGRF_MACPHY_CON0 0X60028 + +static void rv1106_set_to_rmii(struct rk_priv_data *bsp_priv) +{ + regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON, + RV1106_VOGRF_MACPHY_RMII_MODE | + RV1106_VOGRF_GMAC_CLK_RMII_DIV2); +} + +static int rv1106_set_speed(struct rk_priv_data *bsp_priv, + phy_interface_t interface, int speed) +{ + unsigned int val; + + if (interface !=3D PHY_INTERFACE_MODE_RMII) + return 0; + + if (speed =3D=3D SPEED_10) + val =3D RV1106_VOGRF_GMAC_CLK_RMII_DIV20; + else if (speed =3D=3D SPEED_100) + val =3D RV1106_VOGRF_GMAC_CLK_RMII_DIV2; + else + return -EINVAL; + + regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON, val); + + return 0; +} + +static void rv1106_integrated_phy_powerup(struct rk_priv_data *bsp_priv) +{ + rk_gmac_integrated_fephy_powerup(bsp_priv, RV1106_VOGRF_MACPHY_CON0); +} + +static void rv1106_integrated_phy_powerdown(struct rk_priv_data *bsp_priv) +{ + rk_gmac_integrated_fephy_powerdown(bsp_priv, RV1106_VOGRF_MACPHY_CON0); +} + +static const struct rk_gmac_ops rv1106_ops =3D { + .set_to_rmii =3D rv1106_set_to_rmii, + .set_speed =3D rv1106_set_speed, + .integrated_phy_powerup =3D rv1106_integrated_phy_powerup, + .integrated_phy_powerdown =3D rv1106_integrated_phy_powerdown, + + .supports_rmii =3D true, +}; + #define RV1108_GRF_GMAC_CON0 0X0900 =20 /* RV1108_GRF_GMAC_CON0 */ @@ -1628,6 +1682,7 @@ static const struct of_device_id rk_gmac_dwmac_match[= ] =3D { { .compatible =3D "rockchip,rk3568-gmac", .data =3D &rk3568_ops }, { .compatible =3D "rockchip,rk3576-gmac", .data =3D &rk3576_ops }, { .compatible =3D "rockchip,rk3588-gmac", .data =3D &rk3588_ops }, + { .compatible =3D "rockchip,rv1106-gmac", .data =3D &rv1106_ops }, { .compatible =3D "rockchip,rv1108-gmac", .data =3D &rv1108_ops }, { .compatible =3D "rockchip,rv1126-gmac", .data =3D &rv1126_ops }, { } --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4982B3DB64D; Mon, 10 Aug 2026 12:15:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364154; cv=none; b=a0tA3UM8+61Pwqpy3dv5b39MJANcac8foxvKnptniB10P+PtJehLaQF02wLbvJT/tsu3sezP1JirP9JmhNvEKG40hftTTHYynE1I2raYLqe8rsfevrmT106Y7U4SFPt91E5+Il8HIcADzlnAqBCPD6rF0XAXQIYZLQekuA6b0ls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364154; c=relaxed/simple; bh=4Awjjf/du7R9fcJrkoKbpT1I7fR1jX8vL8nrj3muPpE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CmuAReQ3YA9oEGedM8U4Ui1G5zt7Ey7P/Cg+Iz9XdAexylSTaGUlCXvNYU671dZNQdXDULpzrSwVGbD8bpOzD88vVf3pETntDiT1gzBQyOGCMoYEgAZYwx6yFwOLpvidJEJY8ITyXCqJ4M2Npetj8eRt3ECeM5043JSGyTg8794= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=GmwWXZvW; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="GmwWXZvW" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0EDBDC0516; Mon, 10 Aug 2026 15:15:49 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364151; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=aUtZrsjC3vglTeNLq8+cauC4JI68XDzlA8yNJ7+9MYA=; b=GmwWXZvWIVElYjcS897Vd4n2aK5EH6DTVsk6T6F6FVblshSJnhnBZgCNCzTWB042R9hJ7c sJeZk6DUMxFmIK390lHlCctnYe5q1zyDKau+BFtjQnpEPtzy40qiCrFjwfbDzJ+m7ZIBXb wnfxLoo3Lhai4WEqi1D1T8Cm4M4iqPkHeYbx2KwSUl5u+qEh/O42V16E8qP+JY5dX1Re4/ i9nHG+dSM4Nmqfmdy653ArubspI/FSsT7wAiU/mMNyS4TxVTitvqRlfJ78t1/RGDAH4tHo KSFktaA07aQVVCnMCZvDAhgxntfFobsvC6f1eLJB7EY38FXb5catkHDaeQi5tw== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 06/25] ARM: dts: rockchip: Add Ethernet GMAC node for RV1106 Date: Mon, 10 Aug 2026 15:10:57 +0300 Message-ID: <20260810121121.210040-7-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Rockchip RV1106 has GMAC 10/100 ethernet controller. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 62 ++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index fa5d0d7f4dcb..71dd3dcc386c 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -19,6 +19,7 @@ / { interrupt-parent =3D <&gic>; =20 aliases { + ethernet0 =3D &gmac; gpio0 =3D &gpio0; gpio1 =3D &gpio1; gpio2 =3D &gpio2; @@ -282,6 +283,67 @@ system_sram: sram@ff6c0000 { ranges =3D <0 0xff6c0000 0x40000>; }; =20 + gmac: ethernet@ffa80000 { + compatible =3D "rockchip,rv1106-gmac", "snps,dwmac-4.20a"; + reg =3D <0xffa80000 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_wake_irq"; + rockchip,grf =3D <&grf>; + clocks =3D <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>, + <&cru ACLK_MAC>, <&cru PCLK_MAC>; + clock-names =3D "stmmaceth", "clk_mac_ref", + "aclk_mac", "pclk_mac"; + resets =3D <&cru SRST_A_MAC>; + reset-names =3D "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + + phy-mode =3D "rmii"; + clock_in_out =3D "input"; + phy-handle =3D <&rmii_phy>; + + status =3D "disabled"; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + rmii_phy: ethernet-phy@2 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <2>; + clocks =3D <&cru CLK_MACPHY>; + resets =3D <&cru SRST_MACPHY>; + phy-is-integrated; + }; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <4>; + snps,rd_osr_lmt =3D <8>; + snps,blen =3D <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + queue0 { + status =3D "okay"; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + queue0 { + status =3D "okay"; + }; + }; + }; + emmc: mmc@ffa90000 { compatible =3D "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; reg =3D <0xffa90000 0x4000>; --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64E563DD50D; Mon, 10 Aug 2026 12:15:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364157; cv=none; b=DH3B4NR7NLrBBUhNByg9UUNVSR2Gi8qVtz0CIHRGBpxP7L9n5svOfeupNuK3kiT+PvRaovdlJgZTn9DttfBaCe41OhcQ61W89UM35KzfbXKZNVjOIytxCvqhyE2g4A+Ptk5l/F8iEMlh0gCGOMxIxUW0WObEjr2OOsWuepQoDXw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364157; c=relaxed/simple; bh=OLkbaDWgp4ipL02gZisJWTsKREQw8A4zBnKtceIU6U0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WOmTm2Y/8DcYGDx/dVpZ3nANl25N0bLLlz8iFiO705RIS1GBSFu3pmdLU7PEILmgnH45NfmIkiQAlxP3nC0Z7gpAc9vQG3IkZjlSiJ3Yf0OoUX374scZIpdQqz3IDmNS0U1+v6BaQnXqR499SlR83p0rWsXGcgMiMoUAPUYMGSg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=nnuhJ48/; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="nnuhJ48/" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5A5D2C0519; Mon, 10 Aug 2026 15:15:52 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364154; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=cDtG0QjaIvwPANkpMnYor9ZJCrij1s8L69sJNuEhQRw=; b=nnuhJ48/kMqZtnMtY0k5ZMoQmuIJec10u3anCmK4xdzZX4yufAnkC1zsUpbZe9T/xGMzQ3 5IHfQYI1O+whLQNflzFD9CLBonOzqQPwK7p0BA8EezpQeaKjHWyKJQBm3kqBKQ49F/GH+x 3ddMnyDyUeS7l7aSCR1mKDNIb7/b0zr1+Erka+leg12BkR+0SEfWqR1rfd7xZQ3k9V7KXC ao+D0T7DuKOlrurGy9KcYevfpIzzx+RObgZrNnlvRvCM7wk5p9SOdU5/aXCjeJ1w94CWyD fMtWao7pPtZ/pUs7oHcEY/fCiDa9gbF1LH8iXKOOwUrNmFs3W/jmBHvEgqPm4g== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Neil Armstrong , Rob Herring , Vinod Koul , linux-phy@lists.infradead.org Subject: [PATCH 07/25] dt-bindings: phy: rockchip,inno-usb2phy: Add RV1106 compatible Date: Mon, 10 Aug 2026 15:10:58 +0300 Message-ID: <20260810121121.210040-8-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The RV1106 has a single USB2 PHY with only an OTG port. Its OTG port also exposes a "disconnect" interrupt in addition to the existing otg-bvalid/otg-id/linestate, needed for reliable HS device unplug detection, so allow up to 4 interrupts for that variant. Add the "rockchip,rv1106-usb2phy" compatible and require "rockchip,usbgrf" for it, matching the other Rockchip PHYs that need GRF access. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- .../devicetree/bindings/phy/rockchip,inno-usb2phy.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.ya= ml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml index f50fc69fbbe4..4bc418376b18 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml @@ -25,6 +25,7 @@ properties: - rockchip,rk3568-usb2phy - rockchip,rk3576-usb2phy - rockchip,rk3588-usb2phy + - rockchip,rv1106-usb2phy - rockchip,rv1108-usb2phy =20 reg: @@ -121,7 +122,7 @@ properties: =20 interrupts: minItems: 1 - maxItems: 3 + maxItems: 4 =20 interrupt-names: oneOf: @@ -131,6 +132,11 @@ properties: - const: otg-bvalid - const: otg-id - const: linestate + - items: + - const: otg-bvalid + - const: otg-id + - const: linestate + - const: disconnect =20 phy-supply: description: @@ -160,6 +166,7 @@ allOf: enum: - rockchip,rk3528-usb2phy - rockchip,rk3568-usb2phy + - rockchip,rv1106-usb2phy - rockchip,rv1108-usb2phy then: required: --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44D1E3D6485; Mon, 10 Aug 2026 12:15:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364160; cv=none; b=QhZYRrVz0LsLp6YPH5QNCeiOgupxI2H4rZtJ1kYyide3ybjD5xRkhX6THxGZUTgl8+iqs5UqY/V9paLgS/gqnEOC05Ppo2dla22jz9oRTNiF9NRKc4B5lhxCIWF9aocTImS+RZGhTmt9j6RCdRA/N8bxhdtSmvoI54tQdxPUPtg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364160; c=relaxed/simple; bh=gkLbLbqn9POYmI7xz286NeF2c4v8eoSTSq1XUHNTNhY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NPNV7RurStRHv4dzGkNC8JL27YJLdXhypDziYuqENzqTeBlbYLR3PBcvCm1OkeFx8w5xzqGqQulSS6lmiSsXZGCn4M8uwfDyC64Qk1Df08NhSiBvi0vzRCkaOvygdxY9VxJoz4pXwPwq1ttZJ4tuVayXR889AudSr/69d2rCRpc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=FFft6+Da; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="FFft6+Da" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3A3CCC0518; Mon, 10 Aug 2026 15:15:55 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364156; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=/IfKtls+le+9BtiQy6PvVE/vxklhPQZSTDxsy6J1Qqo=; b=FFft6+DamO6uqBIaV1j4bG9OPKSXmQMbA8epNg8w4oJqnuxpSl9D9MDtP/1EZSMgSBQ1tq sy4lLhZJow2WOyuWHYuGkqpNqikZBCp4izHL2QP5PVVfjYiL5CZmK/RZdaKWqmrJpopbjP uQvC9BNHwk0LnOBipT1Hc4T3SH0XS3We6lj+J7oOILiUO/Y1XkxKn8rOwVFcsVVwNcj1XD MvLw0/6BP43TM0ysFWzCPPjAj8+TUK7UWn4EFd5gn5mFmI0kLjrMUFyEOBcZ84E0q4aa7+ M7FZBPqOXIHPGYtq6UNJ1DC4fsdP93W6NXkHWarS5JsqUXF6G+XUGnOL2dydfg== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Heiko Stuebner , Neil Armstrong , Vinod Koul , linux-phy@lists.infradead.org Subject: [PATCH 08/25] phy: rockchip: inno-usb2: Add support for RV1106 Date: Mon, 10 Aug 2026 15:10:59 +0300 Message-ID: <20260810121121.210040-9-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The RV1106 has a single USB2 PHY with only an OTG port, so add its phy_cfgs entry with the OTG port's control/status/detect bit offsets and charger-detection register layout. Also add rv1106_usb2phy_tuning() to apply the vendor HS PHY tuning: enable pre-emphasis in all line states, raise the Tx pre-emphasis strength and eye height, increase the 45ohm HS ODT drive strength, lower the Rx squelch trigger point, bypass squelch detector calibration, disable the differential receiver to save power, and switch the HS disconnect detector to single-ended mode (needed for reliable unplug detection). The register offsets and values are ported from the Rockchip vendor BSP kernel; one difference is that the BSP driver additionally lowered the Tx pre-emphasis strength on newer chip revisions via rockchip_get_cpu_version(), which has no mainline equivalent, so only the new revision's tuning value is kept here. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/ro= ckchip/phy-rockchip-inno-usb2.c index 7d8a533f24ae..ee24382a732a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -1617,6 +1617,38 @@ static int rk3588_usb2phy_tuning(struct rockchip_usb= 2phy *rphy) return ret; } =20 +static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy) +{ + int ret; + + /* Always enable pre-emphasis in SOF & EOP & chirp & non-chirp state */ + ret =3D regmap_update_bits(rphy->phy_base, 0x30, GENMASK(2, 0), 0x07); + + /* Set Tx HS pre_emphasize strength to 3'b001 */ + ret |=3D regmap_update_bits(rphy->phy_base, 0x40, GENMASK(5, 3), 0x01 << = 3); + + /* Set RX Squelch trigger point configure to 4'b0000 (112.5 mV) */ + ret |=3D regmap_update_bits(rphy->phy_base, 0x64, GENMASK(6, 3), 0x00 << = 3); + + /* Turn off differential receiver by default to save power */ + ret |=3D regmap_update_bits(rphy->phy_base, 0x100, BIT(6), 0); + + /* Set 45ohm HS ODT value to 5'b10111 to increase driver strength */ + ret |=3D regmap_update_bits(rphy->phy_base, 0x11c, GENMASK(4, 0), 0x17); + + /* Set Tx HS eye height tuning to 3'b011 (462 mV) */ + ret |=3D regmap_update_bits(rphy->phy_base, 0x124, GENMASK(4, 2), 0x03 <<= 2); + + /* Bypass Squelch detector calibration */ + ret |=3D regmap_update_bits(rphy->phy_base, 0x1a4, GENMASK(7, 4), 0x01 <<= 4); + ret |=3D regmap_update_bits(rphy->phy_base, 0x1b4, GENMASK(7, 4), 0x01 <<= 4); + + /* Set HS disconnect detect mode to single ended detect mode */ + ret |=3D regmap_update_bits(rphy->phy_base, 0x70, BIT(2), BIT(2)); + + return ret; +} + static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] =3D { { .reg =3D 0x17c, @@ -2324,6 +2356,49 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_= cfgs[] =3D { { /* sentinel */ } }; =20 +static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] =3D { + { + .reg =3D 0xff3e0000, + .num_ports =3D 1, + .phy_tuning =3D rv1106_usb2phy_tuning, + .clkout_ctl =3D { 0x0058, 4, 4, 1, 0 }, + .port_cfgs =3D { + [USB2PHY_PORT_OTG] =3D { + .phy_sus =3D { 0x0050, 8, 0, 0, 0x1d1 }, + .bvalid_det_en =3D { 0x0100, 2, 2, 0, 1 }, + .bvalid_det_st =3D { 0x0104, 2, 2, 0, 1 }, + .bvalid_det_clr =3D { 0x0108, 2, 2, 0, 1 }, + .idfall_det_en =3D { 0x0100, 5, 5, 0, 1 }, + .idfall_det_st =3D { 0x0104, 5, 5, 0, 1 }, + .idfall_det_clr =3D { 0x0108, 5, 5, 0, 1 }, + .idrise_det_en =3D { 0x0100, 4, 4, 0, 1 }, + .idrise_det_st =3D { 0x0104, 4, 4, 0, 1 }, + .idrise_det_clr =3D { 0x0108, 4, 4, 0, 1 }, + .ls_det_en =3D { 0x0100, 0, 0, 0, 1 }, + .ls_det_st =3D { 0x0104, 0, 0, 0, 1 }, + .ls_det_clr =3D { 0x0108, 0, 0, 0, 1 }, + .utmi_avalid =3D { 0x0060, 10, 10, 0, 1 }, + .utmi_bvalid =3D { 0x0060, 9, 9, 0, 1 }, + .utmi_id =3D { 0x0060, 6, 6, 0, 1 }, + .utmi_ls =3D { 0x0060, 5, 4, 0, 1 }, + }, + }, + .chg_det =3D { + .opmode =3D { 0x0050, 8, 0, 0, 0x1d7 }, + .cp_det =3D { 0x0060, 13, 13, 0, 1 }, + .dcp_det =3D { 0x0060, 12, 12, 0, 1 }, + .dp_det =3D { 0x0060, 14, 14, 0, 1 }, + .idm_sink_en =3D { 0x0058, 8, 8, 0, 1 }, + .idp_sink_en =3D { 0x0058, 7, 7, 0, 1 }, + .idp_src_en =3D { 0x0058, 9, 9, 0, 1 }, + .rdm_pdwn_en =3D { 0x0058, 10, 10, 0, 1 }, + .vdm_src_en =3D { 0x0058, 12, 12, 0, 1 }, + .vdp_src_en =3D { 0x0058, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] =3D { { .reg =3D 0x100, @@ -2380,6 +2455,7 @@ static const struct of_device_id rockchip_usb2phy_dt_= match[] =3D { { .compatible =3D "rockchip,rk3568-usb2phy", .data =3D &rk3568_phy_cfgs }, { .compatible =3D "rockchip,rk3576-usb2phy", .data =3D &rk3576_phy_cfgs }, { .compatible =3D "rockchip,rk3588-usb2phy", .data =3D &rk3588_phy_cfgs }, + { .compatible =3D "rockchip,rv1106-usb2phy", .data =3D &rv1106_phy_cfgs }, { .compatible =3D "rockchip,rv1108-usb2phy", .data =3D &rv1108_phy_cfgs }, {} }; --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A44EB3E0241; Mon, 10 Aug 2026 12:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364163; cv=none; b=beOUdfJCp27jBLLRs9TLdPNOlmCWb8tXn+tkMP/ZnZt1hYYfJmUWB9LzU396sZrJ3ZXlnuvKCXORcE4IHOa66b+ZZ0bqa2e9tWUupy3plD1xvNzQ99Uo2/iKQytotXtbM02ShhYlw+jzkW+NItU58COYULYsNSObAqUqGkMs3LU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364163; c=relaxed/simple; bh=bYGrXRj8Po9cz3ohfc2Ovi9o70pqezxvdpfAPljBFgE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PvKzoY22NO3gFG41bR6eOJ7jTCHaAp7+t+y+mjE5L873pzbdL8zA3A+6C1RMWCrRsW9YI100QSJ8U5oxT4HQU2Uyw596yGcSWC+kitUg8gr/5L2FHz0TBKn8LxTpTG9oaktYEJ1nclDwgJ5UrejYYd93mS8eR7jYXyS5NMwzoKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=nxvNEE11; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="nxvNEE11" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 74A56BFAEB; Mon, 10 Aug 2026 15:15:57 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364159; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=j1MZTVd373in/IMAt/QC2whUgnWuRGxEI5v6pl6Py28=; b=nxvNEE11H9zqz15OnmCrMYQYJVUrhuPfJ5WkRponEciyDxEGANuP/9yOFyEFfIWBkA5H+Y rhyiOhKu9RCPNXrgS+nlqgxfPzuRwmquKr0w7KjBpVK+osankuAWfKo5PuQUmOa+P4nK0m w9apiw8iaV4D+HMO9JwYh2L5bwDoEOaO0NaKsSOiygJdqzdeI70fuaTWFuwLcyfkPZTf0w 8y3KLG8li42QO64gtlqg0m6k9LWGaxibGnllWZA4a2v2u5rin77joC4pgN7pUz64Np+jjO US+kLFL4fZ8GKVC/842mXTb2z5Liz5pCxe4uDh5PADrikeImrigtcXAGCQs0eg== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Greg Kroah-Hartman , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring , linux-usb@vger.kernel.org Subject: [PATCH 09/25] dt-bindings: usb: rockchip,dwc3: add RV1106 SoC support Date: Mon, 10 Aug 2026 15:11:00 +0300 Message-ID: <20260810121121.210040-10-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Document the DWC3 USB controller found on the Rockchip RV1106 SoC. The RV1106 has a USB2-only (high-speed) OTG controller. Unlike the other supported SoCs it has no dedicated suspend clock: it only needs the 24 MHz reference clock, the AXI bus clock and the UTMI clock. Since the top-level clock-names list enforces a fixed order with "suspend_clk" as the second entry, relax the second and third entries to enums so that the RV1106 clock set (ref_clk, bus_clk, utmi) can be expressed, and add a per-SoC clause constraining RV1106 to exactly these three clocks. The relaxation is required rather than cosmetic: every other compatible's own clause already agrees with the shared tuple position-by-position, but RV1106 genuinely reorders it (bus_clk before utmi, no suspend_clk), and allOf branches are ANDed, so without loosening the shared entries the two clauses would be unsatisfiable together. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- .../bindings/usb/rockchip,dwc3.yaml | 35 ++++++++++++++++--- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Doc= umentation/devicetree/bindings/usb/rockchip,dwc3.yaml index 0554dbc4b854..86e00f251bdb 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -31,6 +31,7 @@ select: - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 - rockchip,rk3588-dwc3 + - rockchip,rv1106-dwc3 required: - compatible =20 @@ -44,6 +45,7 @@ properties: - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 - rockchip,rk3588-dwc3 + - rockchip,rv1106-dwc3 - const: snps,dwc3 =20 reg: @@ -58,10 +60,11 @@ properties: - description: Controller reference clock, must to be 24 MHz - description: - Controller suspend clock, must to be 24 MHz or 32 KHz + Controller suspend clock (must to be 24 MHz or 32 KHz) or + Master/Core clock - description: Master/Core clock, must to be >=3D 62.5 MHz for SS - operation and >=3D 30MHz for HS operation + operation and >=3D 30MHz for HS operation, or UTMI clock - description: Controller grf clock OR UTMI clock - description: @@ -71,8 +74,12 @@ properties: minItems: 3 items: - const: ref_clk - - const: suspend_clk - - const: bus_clk + - enum: + - suspend_clk + - bus_clk + - enum: + - bus_clk + - utmi - enum: - grf_clk - utmi @@ -145,7 +152,10 @@ allOf: clocks: maxItems: 3 clock-names: - maxItems: 3 + items: + - const: ref_clk + - const: suspend_clk + - const: bus_clk - if: properties: compatible: @@ -161,6 +171,21 @@ allOf: - const: bus_clk - const: utmi - const: pipe + - if: + properties: + compatible: + contains: + const: rockchip,rv1106-dwc3 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: ref_clk + - const: bus_clk + - const: utmi =20 examples: - | --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B42E23E1204; Mon, 10 Aug 2026 12:16:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364166; cv=none; b=Szlshy4btmce5kzshawv8RnXGdxjCcPom/TLTPjyz2KyuRbPnQJX7MRd9ztW55ljw4rtw9Eoq+LdP8JAKMuNlfxROGusiXicDI1g3va2kpwX9tuA0QDbdNh5x17/YZQzY23s65DrBahDVkGZxJkKQuuBg+D9Ur63s9U/G8saqLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364166; c=relaxed/simple; bh=27Dy8S0A0xEFr+M0asXkwaHrlOHrD5IjSfrmKSDKhWM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eNQazia5VVy8g5wxEXKcLi73jTZDV2Iz3D3F+f7yc1285F6FHdJHhHL9MR7ia6y75uBvF5fxmCytigMeQQMnWA53Re+KxLFMNhhZ6R/SrU/VJwDnJHo5QSs9FpvWwMaiclplFncvSA1bEeWh96NFHQ1AvJ29+gJAf+2mIpfVcfk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=hmCIc8Vy; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="hmCIc8Vy" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A87B2C0516; Mon, 10 Aug 2026 15:16:00 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364162; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=BzpzWg1RUAwQmycNuzrv0GryxIk9OCzfL2FG5/H+8bQ=; b=hmCIc8VyewX65zNXEnQc9R+YNR9iwvyDg8Q3h9nb5IiNtN2DZeK4Ke5ikInUEOvoy1qMvW zqUvDCLNwWkIwy0ZVIym/3eTbZHYgOvBnVIcRCjFZLExGV41ehjeAX/W9NgfbuRFLEppKT Od7zqgHUKettwyfBVj59gPU9qf5ZHSvxDasS6uD0xDMpk2Qah3P/7WZPomichYc2h9UIzo 4LwaNN76yddbVUQhGadfxY4DZZDgYYEDO24jj04b/RGX4SJNny9+wyRKJHaxODQzT9ZZzK 8sBZqCDDmpPIBkDyo689VwEHp19c04Yatl+/iIeDnlBDIya2S1Zh8s4Sl8nl7A== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 10/25] ARM: dts: rockchip: Add USB2 PHY and USB3-OTG (DWC3) nodes for RV1106 Date: Mon, 10 Aug 2026 15:11:01 +0300 Message-ID: <20260810121121.210040-11-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add the u2phy node with its otg-port child, using the disconnect interrupt in addition to otg-bvalid/otg-id/linestate. Also add the usbdrd/usbdrd_dwc3 nodes for the DWC3 controller behind the PHY, reusing the "rockchip,rk3399-dwc3" glue compatible and the snps quirks already used by other Rockchip DWC3 platforms, since RV1106 does not need a dedicated glue driver. Both nodes default to status =3D "disabled" and are enabled per-board. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 48 ++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index 71dd3dcc386c..43db3b1dd4b8 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -180,6 +180,30 @@ saradc: adc@ff3c0000 { status =3D "disabled"; }; =20 + u2phy: usb2-phy@ff3e0000 { + compatible =3D "rockchip,rv1106-usb2phy"; + reg =3D <0xff3e0000 0x8000>; + clocks =3D <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; + clock-names =3D "phyclk", "pclk"; + resets =3D <&cru SRST_USBPHY_POR>, <&cru SRST_P_USBPHY>; + reset-names =3D "phy", "apb"; + rockchip,usbgrf =3D <&grf>; + #clock-cells =3D <0>; + clock-output-names =3D "usb480m_phy"; + status =3D "disabled"; + + u2phy_otg: otg-port { + interrupts =3D , + , + , + ; + interrupt-names =3D "otg-bvalid", "otg-id", + "linestate", "disconnect"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + }; + uart0: serial@ff4a0000 { compatible =3D "rockchip,rv1106-uart", "snps,dw-apb-uart"; reg =3D <0xff4a0000 0x100>; @@ -378,6 +402,30 @@ sfc: spi@ffac0000 { #size-cells =3D <0>; status =3D "disabled"; }; + + usbdrd_dwc3: usb@ffb00000 { + compatible =3D "rockchip,rv1106-dwc3", "snps,dwc3"; + reg =3D <0xffb00000 0x100000>; + interrupts =3D ; + clocks =3D <&cru CLK_REF_USBOTG>, <&cru ACLK_USBOTG>, + <&cru CLK_UTMI_USBOTG>; + clock-names =3D "ref_clk", "bus_clk", "utmi"; + resets =3D <&cru SRST_A_USBOTG>; + dr_mode =3D "otg"; + maximum-speed =3D "high-speed"; + phys =3D <&u2phy_otg>; + phy-names =3D "usb2-phy"; + phy_type =3D "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + snps,parkmode-disable-hs-quirk; + status =3D "disabled"; + }; }; }; =20 --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 874CF3E1D02; Mon, 10 Aug 2026 12:16:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364168; cv=none; b=Fbq6AxofnnTMoviubK892qdGbDJDWW97O4DrMuFPBgA7IfxrYKiUE4CzPRSwY/MeOu52lXQ5OwTbMmUH5TM+yB9tQgMLS+Pux0XEHyqVdXYTxJT2//PvseqmMGVOg6m4vafsiVV4nYgtsaTzZoB3INaR8cF0AIfiCqLiKIOrPhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364168; c=relaxed/simple; bh=6LzwL3IWqV4HqkMFFNnP2FrxGIQZwrFxRU2U+HKlC+w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eA1aT3DLt9BV8WgX2gunR/Oy8BjiSYFbGaGEWqCgqNDRfXOXpjJhCmrIM3l+x5MbIb8NmVZZlKNbtvjVTMB5fJgH0hLiB+5zvQC1Y/NA/SE3gVJpcEnP3ve//u5iQNHqFCY5aBU9a+GhVqHY3JebixFR1Z5xP3xkEuHsrcyeneA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=Kod5Do55; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="Kod5Do55" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E3AE4C0518; Mon, 10 Aug 2026 15:16:02 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364164; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=GvvdDodrLnIavxk43AjnGgAOmbOYW9Z/Zj0W0n2gWow=; b=Kod5Do550IVo7LWhEaB8L2sfV2wNaEScyjaGkk0HvDWI+D2Nwn9PG2gA+CsjT6oacLEh/d wf40NxixC9QkyWCb7h09712kDvNPdbL3HEcUMjoDCzpC2JZ/1TV0hq3R2kuA5ZsePXarYF SLvui/daxQaezMenAriTQI+WhhrUabxiPmvY41/MrSyiiRQunVBcnT1PJ8ZvrxznY2+Rvn vGMDUaCUY+BKXmJK2PDu6sF3bw/gRN0oaRvBcFKoXQ3sSnC0W11E5GK9ZKNT5gubmRHe2q trhbT0mH5yJ+d9kIceiVnyAk54bW59dHYJ2CHrbjHrX0Ad1mYuvG2zk7sPEIvQ== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Andi Shyti , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring , linux-i2c@vger.kernel.org Subject: [PATCH 11/25] dt-bindings: i2c: rk3x: Add RV1106 compatible Date: Mon, 10 Aug 2026 15:11:02 +0300 Message-ID: <20260810121121.210040-12-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The RV1106 I2C controller is compatible with the one found on RK3399, so add the "rockchip,rv1106-i2c" compatible to the list of variants that fall back to "rockchip,rk3399-i2c". Signed-off-by: Vladislav Leonov Acked-by: Krzysztof Kozlowski Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Document= ation/devicetree/bindings/i2c/i2c-rk3x.yaml index 91805fe8f393..725a58a35df7 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml @@ -43,6 +43,7 @@ properties: - rockchip,rk3568-i2c - rockchip,rk3576-i2c - rockchip,rk3588-i2c + - rockchip,rv1106-i2c - rockchip,rv1126-i2c - const: rockchip,rk3399-i2c =20 --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E88013E3166; Mon, 10 Aug 2026 12:16:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364170; cv=none; b=CKsF+Zcr7dvm8VrORBhAvha2D5rSTaEPyBNLsxdrU1Uhq5pYa5ON3fPEs8ki5ZAH7z0Y7mAFiAuP1jupLYnpUq4icEHMR4S5uCgP7innzY9P2BekQBcG9SCRRB3nScvmnsUjWWkSZfdMXWXK2qh7jVlAAW9MuGtPf7skuf3x25U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364170; c=relaxed/simple; bh=35jxSxXms7xlHnkMfDcTwH+OoyM5QeqxevVg1cD6bC0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tVMloBrojW3JzC9/kk6uC9Wxr8YdZ/U1slZJapx5hqUGAGV20l0LtqwjbQOd1j0ultHIUbzUTaNbLpVd+NiX+2e0vTJ4qK0/dAvoE5F8ITaBYO1kEP5j+bj004tJUN039+7EF+V1SqZYEgc+/yBQ8DdPdXKiJzjkWYIjCbO9A6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=ZiAL5w2U; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="ZiAL5w2U" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6506BC0519; Mon, 10 Aug 2026 15:16:05 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364166; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Y9l5G6RkfJNGl6CnVwssyReWh7AHu+6IehUiBWk/o3A=; b=ZiAL5w2Ugmi20YSJg6mtqwFHgXOxL4/kYEDiVU/y3GghFCCs4p5DncpBLmVIRK4xA7Fohm vfho6lQLJJZqlTsZG4LkyEb8HvY/5sUttyFKPtr1ZTCLhEaaM4wk1nHM93xQ8TsmaYm9mc C8SfJUVp0lhWQ53GpKa5Ps8ai5SAbRS2dEc/AF3drcrHgcUKkHPXI42Z2m7J9mMOx+sd0R fvKiJejwy8YXO7ItjtjqL0dXDi+sfqs/XvcXo5zyH45gMvlBeFIxcRJENxnX3bL2bc65lr mnBdPfTFV0OzUlJbP1NDIUU5yZ3QsFSb+0Tvg88YP+DJlqjVNEDp03pENpR1Nw== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 12/25] ARM: dts: rockchip: Add I2C nodes for RV1106 Date: Mon, 10 Aug 2026 15:11:03 +0300 Message-ID: <20260810121121.210040-13-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Rockchip RV1106 has five I2C controllers. Add the i2c0-i2c4 nodes together with their aliases, using the m0 pinmux by default. All nodes default to status =3D "disabled" and are enabled per-board. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 70 ++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index 43db3b1dd4b8..43d992e3e2d6 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -25,6 +25,11 @@ aliases { gpio2 =3D &gpio2; gpio3 =3D &gpio3; gpio4 =3D &gpio4; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; }; =20 cpus { @@ -155,6 +160,32 @@ gic: interrupt-controller@ff1f0000 { #address-cells =3D <0>; }; =20 + i2c0: i2c@ff310000 { + compatible =3D "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg =3D <0xff310000 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names =3D "i2c", "pclk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0m0_xfer>; + status =3D "disabled"; + }; + + i2c1: i2c@ff320000 { + compatible =3D "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg =3D <0xff320000 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names =3D "i2c", "pclk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1m0_xfer>; + status =3D "disabled"; + }; + gpio0_ioc: syscon@ff388000 { compatible =3D "rockchip,rv1106-gpio0-ioc", "syscon"; reg =3D <0xff388000 0x8000>; @@ -204,6 +235,45 @@ u2phy_otg: otg-port { }; }; =20 + i2c2: i2c@ff450000 { + compatible =3D "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg =3D <0xff450000 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names =3D "i2c", "pclk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2m0_xfer>; + status =3D "disabled"; + }; + + i2c3: i2c@ff460000 { + compatible =3D "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg =3D <0xff460000 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names =3D "i2c", "pclk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3m0_xfer>; + status =3D "disabled"; + }; + + i2c4: i2c@ff470000 { + compatible =3D "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg =3D <0xff470000 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names =3D "i2c", "pclk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4m0_xfer>; + status =3D "disabled"; + }; + uart0: serial@ff4a0000 { compatible =3D "rockchip,rv1106-uart", "snps,dw-apb-uart"; reg =3D <0xff4a0000 0x100>; --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CBA63E3D95; Mon, 10 Aug 2026 12:16:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364173; cv=none; b=QGNh88lACe3axATVdc+pWHvwE+/8la7wRhVzybHMCheKpvQJ+kJp+ebU6kCgUUx/Oj04wwrNa0vJm6UgrYmE6oM8bHu0HhV9ztA14xpe7AkcnuqTOX4nQBoTh/LWamn/MMQcKDe9OPE8opHy0w2KGZ1KCxaza8EaDzQwUunAr30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364173; c=relaxed/simple; bh=EwKoWzxvDb5lS4G45Dto+QJmOfcdYoSvXcSRxB560Iw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iDiFsl/PUK7OantKy9uHLQGkSzgw08pFS1vJ8xky+LhfkyY9aV193Lruv56Qs0knMSlmCOnwQEHc0n86PNfrmkqNsjus1zVcIoe3pHHuxmJYPVCr+qZUI+z+CnDiWcs7DWOtGABYO/BockayS+WlY48p/3y0HxN5P1HTNHqJMcg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=Gx68abnp; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="Gx68abnp" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id BB488C051B; Mon, 10 Aug 2026 15:16:07 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364169; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=35Y1Mvqm3PQ758mkGyOjdGnkGXdHZYwPhqgHLSP43Hg=; b=Gx68abnpQU5Lp0EKxuXN1cc0xMlytXhI2rmEwQfBATpwZs6Rfk2GOdbep2obCGjzjeouRt k9s+rCU4ZzOvKn6ckL23ULBJrOH25KUTKzt1nrBqnauejqvTDUdwmc5kGloiXkhLaYiRLc Gy/v9urBQ7DFNZBIS2+yQZDkVsePckZzxbSKb/2VIqcCBDYEgPatZmolJRcIEC644pZVnq WUUFb+M/bIY2Mx+CWUgDv9S/lpyEHzeVPPZvgTdAlpO4iAZfScUYDtFszzBtmJyXEcOZRD 59aft1pDiFvpoBuU0pKpoBzBkQyOxJNEP243mgOj/0JP2s1CL2ETJ66CCXbIjw== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 13/25] ARM: dts: rockchip: Add DMAC node for RV1106 Date: Mon, 10 Aug 2026 15:11:04 +0300 Message-ID: <20260810121121.210040-14-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Rockchip RV1106 has a single ARM PL330 DMA controller with 8 channels, shared by the peripherals. Add the dmac node with its 8 event interrupts plus the abort interrupt. The controller needs arm,pl330-periph-burst to use burst transfers for peripheral requests, as on the other Rockchip PL330 platforms. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index 43d992e3e2d6..4abc333ab370 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -235,6 +235,24 @@ u2phy_otg: otg-port { }; }; =20 + dmac: dma-controller@ff420000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0xff420000 0x4000>; + interrupts =3D , + , + , + , + , + , + , + , + ; + #dma-cells =3D <1>; + clocks =3D <&cru ACLK_DMAC>; + clock-names =3D "apb_pclk"; + arm,pl330-periph-burst; + }; + i2c2: i2c@ff450000 { compatible =3D "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; reg =3D <0xff450000 0x1000>; --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 827ED3D88F2; Mon, 10 Aug 2026 12:16:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364175; cv=none; b=eBNoouOOGgmLC/LOxw3eQRdWCNo9Q7YGU91ZCYwdtU6cgGZ8pgUGpgrbNQgtGjeKfN5ZKbtRLui4bMTixr++exdFtlAQOr03rUJya3xXDtmkUYWgtiwivr5vgaxiULAgjylk+A8ATjlBZRTlnmt0X+BnYTHpHjC2WTq567KuPdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364175; c=relaxed/simple; bh=hta0Pp4rfzoS/Aevnu0xZ0RRZRyH3gGeB9Rml6eHOVA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oqF6qnTJ4IH0Ei+t/hBbZHNNRStajKhnl05marXpeXQSH8lGAY5mPmfmCJGj4TF7hT5mkWQBR1CA49yJWD7L+32YtgOSoVL/d90V931285ZfnLb/UXkCzXxThLz8ad50VvhZ5e9X7ar3Nl4iCmRSWESFtKfw3ILfHpu+ftOF0H0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=FEA1uvjJ; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="FEA1uvjJ" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7956EC051C; Mon, 10 Aug 2026 15:16:10 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364171; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=y76GiRMrYgaa2B8p3vMOOGelYc4wcU4Ng2CgUWCP/+8=; b=FEA1uvjJ/gAdaqCdVA4iEr3nLxsWN3Y3LAraMdFZ4L0eCPIiHBAeALZMI7HcxZjdA3k9Co CttneTiVFmFUDc3VtV5PZwUFjQ0tasP4h4y7xtt7LrWZpBOpNI3CHW/p9rnlgYO1on6jTX ikFubHptQqlHkDovSK47DX+lWriCWk68cX719kqFWQOdjMdQ3Agk3fE3YG4k5uw2uonMed wyWoRJyBSHNTGmBdthldBZlvLPgFjS8pN3rRMSkYR/LDKqEXV8sk4SNgH9gobKQE2svOup ejL9N76BuRjN9eNS9kyj69hUWcLV8c6iuPRHfT7M53oJXNoX8yi1eJ3KUMIG3w== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 14/25] ARM: dts: rockchip: Add DMA support to UART nodes Date: Mon, 10 Aug 2026 15:11:05 +0300 Message-ID: <20260810121121.210040-15-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add dmas/dma-names properties to uart0-uart5 so the dw-abp-uart driver can use the RV1106 DMAC for TX/RX. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index 4abc333ab370..58ac297e4d75 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -298,6 +298,8 @@ uart0: serial@ff4a0000 { interrupts =3D ; reg-shift =3D <2>; reg-io-width =3D <4>; + dmas =3D <&dmac 7>, <&dmac 6>; + dma-names =3D "tx", "rx"; clocks =3D <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names =3D "baudclk", "apb_pclk"; status =3D "disabled"; @@ -309,6 +311,8 @@ uart1: serial@ff4b0000 { interrupts =3D ; reg-shift =3D <2>; reg-io-width =3D <4>; + dmas =3D <&dmac 9>, <&dmac 8>; + dma-names =3D "tx", "rx"; clocks =3D <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names =3D "baudclk", "apb_pclk"; status =3D "disabled"; @@ -320,6 +324,8 @@ uart2: serial@ff4c0000 { interrupts =3D ; reg-shift =3D <2>; reg-io-width =3D <4>; + dmas =3D <&dmac 11>, <&dmac 10>; + dma-names =3D "tx", "rx"; clocks =3D <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names =3D "baudclk", "apb_pclk"; status =3D "disabled"; @@ -331,6 +337,8 @@ uart3: serial@ff4d0000 { interrupts =3D ; reg-shift =3D <2>; reg-io-width =3D <4>; + dmas =3D <&dmac 13>, <&dmac 12>; + dma-names =3D "tx", "rx"; clocks =3D <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names =3D "baudclk", "apb_pclk"; status =3D "disabled"; @@ -342,6 +350,8 @@ uart4: serial@ff4e0000 { interrupts =3D ; reg-shift =3D <2>; reg-io-width =3D <4>; + dmas =3D <&dmac 15>, <&dmac 14>; + dma-names =3D "tx", "rx"; clocks =3D <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names =3D "baudclk", "apb_pclk"; status =3D "disabled"; @@ -353,6 +363,8 @@ uart5: serial@ff4f0000 { interrupts =3D ; reg-shift =3D <2>; reg-io-width =3D <4>; + dmas =3D <&dmac 17>, <&dmac 16>; + dma-names =3D "tx", "rx"; clocks =3D <&cru SCLK_UART5>, <&cru PCLK_UART5>; clock-names =3D "baudclk", "apb_pclk"; status =3D "disabled"; --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CB993DAAB0; Mon, 10 Aug 2026 12:16:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364177; cv=none; b=UNL5h74HgoGZkdfnAd6DnTOpMem7Egec3GMmakxqsa6/9hGVjcSxmfnjgpcEbbhtX5rQw22Ev+43lI2aaZe7cbYv/x8X/otykVgMD0zjjYzK1dmfPko4qlaHowb6A+iFrhX2612ff5i0oWR8rKwF6I8cW6wNXkkiZlyuMFTfiio= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364177; c=relaxed/simple; bh=fBbBFCfL1qnbIrz+YRMXQG931bBeLwr3NZ5iAIymmy0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZcZG8gKFI1DF/WfPqrBZ6NydZRTQ+ujGHsxKAw47ltDC3q+tkO7bRTwmHtuCKez1bLkvMWMlo8Y97wCFi6TFWSYTo5fkxIIpRSEIelXiP7/vdda8McRwj5/ZZtFpXGioXxVfmQOvDlLlVoBwWGcynkitKYWkwy9fP5yWSdmenVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=p3lpEu4Y; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="p3lpEu4Y" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7E28FBFAEB; Mon, 10 Aug 2026 15:16:12 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364174; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=P4h8dquu6slcO6eGmqY9QueeVQuamfZ2A7/alu4byEQ=; b=p3lpEu4YgBYMt+wFTdv6GcHxB2FgHpdNIsekfb3e0VR8ElDPJ5k6G4qGQJv04ZwbYKHXEs JqUMLMZbWVb9b81EemukQjlFHeq7FzgvuSnGTh4ArOsYZbUZJyqfbouyImWXGEeqqc4Y9r NJz5+EuQXz09JVf9jf2uTGllt3zoetxrHsiuEfjM+kiQ1XcCV2vtC9nayPxCov7wqVK60A tPoQfpQ0kPgi/cuP861AAHAdq7os26PvgLxzVQkAoZrRYBGHnTsSOUOC2KQe4qu8ePbr8U rTIZTN7j66KshiBYvadQPI7rhuKThzVmfhQfcl0HemlEVdNuokFc89d5I2kFOA== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Brian Masney , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Michael Turquette , Rob Herring , Stephen Boyd Subject: [PATCH 15/25] dt-bindings: clock: rockchip: Add SCLK_IN_SPI1 for RV1106 Date: Mon, 10 Aug 2026 15:11:06 +0300 Message-ID: <20260810121121.210040-16-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add the clock ID for SCLK_IN_SPI1. This gate exists per the RV1106 TRM but is missing in the Rockchip BSP kernel. SCLK_IN_SPI0 already has a binding, so add the SPI1 counterpart for consistency. Signed-off-by: Vladislav Leonov Acked-by: Krzysztof Kozlowski Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- include/dt-bindings/clock/rockchip,rv1106-cru.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rockchip,rv1106-cru.h b/include/dt-b= indings/clock/rockchip,rv1106-cru.h index 80244988e139..ec6e7cd36f08 100644 --- a/include/dt-bindings/clock/rockchip,rv1106-cru.h +++ b/include/dt-bindings/clock/rockchip,rv1106-cru.h @@ -303,4 +303,6 @@ #define PCLK_CPU_ROOT 286 #define CLK_RTC32K_FRAC 287 =20 +#define SCLK_IN_SPI1 288 + #endif --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61B963E5EEA; Mon, 10 Aug 2026 12:16:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364179; cv=none; b=hcnnM7/GlW8pSnBUVcBUyNHef8c7hHzCIN3eSrEco/QCeIgFEEGS8AVIrW7JbNHLe8NZkGPaORvT3GYWqXFWCndrhVl7dupcd6vM0I7VqPFvewDEQAbFnoi5t4QepnfyOy/W5X9Bx2x3LROJ/Sbi9k52aetb7EwmMElEojoM91s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364179; c=relaxed/simple; bh=s/5lgSlePgYYOK7g09Mf9z3bNr7jAVXO40yfhYktGik=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lehzhJaX14mp9bqP2bgXI7LFUaupID4nf0ysL8f7i7TGUOZbmMwHMpi8Iw6TelcksBTmxjmL9nvckALV17m6X+Qe59ZoaLWTHM2wdz6gP3NBjAsSRSL3W3xC8ZyUD6ru5MA63yAVMKyTjejEhg7MBuUZl+27xFKlL+IGYlqgFq4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=iPD02Zdf; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="iPD02Zdf" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 36C5DC0516; Mon, 10 Aug 2026 15:16:15 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364176; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=3Hl1hvKOm1E58LS9l2PpGKlwAtOA5MDxmR8+JN0pJaI=; b=iPD02ZdfQxc+vaH1TjGukoKGpootB6Auc1YOxLOZUzGJvf+1121tcio/JCRCW2x8bzyPIj TG/DSX26HOk9a2ulZskkSreLj1ZiVVVsLu3VZrI1CNP2ZisAObbCJAn7b+lGExxVlU2dyY VVQi9BTdp6geQAI+upa/PEQDPc4Jw6X+1DV4GNmMg6AUhUPrdQu6QpAnf06Wq1czkMuLMA p/4k02H8PZIfkIbDy1jwc0uEa04o/QjnZ+F+Ffl1HCck0eCLmhdDHYCKta14EcBTWGma0N US723+GC5ND6Tg3CpzAPbeMbHapo7eVR1wiRADk1alYDkgYhSXOCMexRBfx6nw== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Brian Masney , Heiko Stuebner , Michael Turquette , Stephen Boyd Subject: [PATCH 16/25] clk: rockchip: Add SCLK_IN_SPI1 gate for RV1106 Date: Mon, 10 Aug 2026 15:11:07 +0300 Message-ID: <20260810121121.210040-17-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Register the SCLK_IN_SPI1 clock gate (PERICLKGATE_CON3, bit 8), mirroring the existing SCLK_IN_SPI0 gate. This clock is documented in the RV1106 TRM but was missing in the Rockchip BSP kernel. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- drivers/clk/rockchip/clk-rv1106.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-r= v1106.c index 1e3a110192bb..236159157c7e 100644 --- a/drivers/clk/rockchip/clk-rv1106.c +++ b/drivers/clk/rockchip/clk-rv1106.c @@ -976,6 +976,8 @@ static struct rockchip_clk_branch rv1106_clk_branches[]= __initdata =3D { RV1106_VEPUCLKGATE_CON(0), 14, GFLAGS), GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0, RV1106_VEPUCLKGATE_CON(1), 4, GFLAGS), + GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0, + RV1106_PERICLKGATE_CON(3), 8, GFLAGS), =20 GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0, RV1106_PERICLKGATE_CON(4), 9, GFLAGS), --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBF683D902E; Mon, 10 Aug 2026 12:16:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364182; cv=none; b=CIXbevNI/nrGllyPA9HsZV9tkQK1zb1f8YocZBhTRVFrtHhE1NqF863GHFrue7gQYpY/H8ZxmmzaXVqqNCjQ6FED8CuwrprUERFXbzLHBKkIRnTl5lnCInJUg9HMjPyQWQTC7i9wl5FGIh8bjB6dzUxiWIn3uyPMp+TUfrOI/eY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364182; c=relaxed/simple; bh=JjxwpskZzfY+fNYf5+RTD7bFPDdPRRtJ9X84JgCx9KM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eqa7GjHfE0vhqr42pBe0iolYfA4nBCtB7pEi50Przr+ULteC9MWMFUKY8rVPGSxaKSzsulmqf9ixR5dvF9YyeaD81T1uQp9n6PiFwttkjdM7OIzlCimkS4bIoo09vPpXfHLOWvs363VoEVcwrJGR1K/VstdmgVa5bQHVdjISE+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=LB68WSLB; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="LB68WSLB" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 58964C0518; Mon, 10 Aug 2026 15:16:17 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364178; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=jyXAV2W+9WeUgVtJKmGxJKoFTEPe3bQ/W+GJ1vmEbr0=; b=LB68WSLB067autQFFTfw9lgzVXbCwzWc761plBR1sHe3XnwXuVCep6nY8u/9Pm5IoK6sX8 oyL3K1K6ywdU9lA/8a/vzaLnwnAVLV9jUFmiMLS+8HNAOb3BBxnkFh4Do/GJAXkkGcjjOf x/z6BhRy82c2vnLmm1ALIcg1z7DIRizpU5XD1eD9W+z0wrJMvTz7ov6OtW2QB3fd4GG67Z rcVzXGK2U+UyuGbXLuC6cpiEpeNDDXVBEgevjhuc/UrjIKIjtLvcYV7am+BE8LNlNK7/Aq 1N8lwb0qM3Vy+qgDAz5hysEHHSAUUMAcFPaTlgWQ6kRwO46cbzqXX5M/es0S3A== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Mark Brown , Rob Herring , linux-spi@vger.kernel.org Subject: [PATCH 17/25] dt-bindings: spi: rockchip: Add RV1106 compatible Date: Mon, 10 Aug 2026 15:11:08 +0300 Message-ID: <20260810121121.210040-18-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The RV1106 SPI controller is compatible with the one found on RK3066, so add the "rockchip,rv1106-spi" compatible to the list of variants that fall back to "rockchip,rk3066-spi". The RV1106 SPI controller also has an additional external slave clock input (sclk_in), so extend clocks/clock-names with a third, description/const entry for it. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- Documentation/devicetree/bindings/spi/spi-rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml b/Docu= mentation/devicetree/bindings/spi/spi-rockchip.yaml index ce6762c92fda..159111d143f2 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml @@ -40,6 +40,7 @@ properties: - rockchip,rk3568-spi - rockchip,rk3576-spi - rockchip,rk3588-spi + - rockchip,rv1106-spi - rockchip,rv1126-spi - const: rockchip,rk3066-spi =20 @@ -50,14 +51,18 @@ properties: maxItems: 1 =20 clocks: + minItems: 2 items: - description: transfer-clock - description: peripheral clock + - description: slave clock =20 clock-names: + minItems: 2 items: - const: spiclk - const: apb_pclk + - const: sclk_in =20 dmas: items: --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 216503DB339; Mon, 10 Aug 2026 12:16:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364184; cv=none; b=OX7EKE+Iv4HqNkqZ6FhsmcXOT9GT6tCveTAXvMkWWY/1oD67DvnhlO1CexEBZ908hkvDrehLOKqoTGCYaFHNnJiv9AElDXeFWYlSOp3szcG0bVWsXdXu3Zr3pHEG6p+YDl6fs7tVZitZ9F2wUJnvyOKWmSWUiP4RkL9rFDJ9zjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364184; c=relaxed/simple; bh=MrSpY5EZAN3FEtuBbH+EmJm2SMcGm7j0LyDLHqnge94=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VuBC+YS+zt6J5zP+SxRu65kuAje9O67iIOlcEQlMs6GTswyv7TwW24iMXcclV3rT/ocTEdMvhmgQwt4jaAY80AqmpxGmFzjobyEDiAjHoeRqIoWVSX7Fby/OEjhawSl+l257bdpqEcCxfwwDL7o2n8XIdGdHHAUU+kbhA59ZGa8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=N2+uw0Yr; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="N2+uw0Yr" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D023AC0519; Mon, 10 Aug 2026 15:16:19 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364181; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ljDGBtz+ECPARFnAYybal9Xk5SoydAvNr02UpW+gUnU=; b=N2+uw0YrWpAznT6QUje+zq98tMayjw1+FZqN5pbWXi9R0wli+JgY4WMlGZBfyHcQK4HX/N jW3oexTHLs0xyfKuBQCEXvnOPAv3/6XPqV/chabvBcuq7/LQFlMlpaho3TZKhCpjryGJDK ZOS09MhJoaE808AOguXunn5CWqhCiWVjK6r7YADwGPi4QSmNuRbg+lTyzyyDSBYaMFRrrc HXXY1GVE7RFe6odL+odm1Shz2+kJBVSJmw6qGYqh+edD1dvUD+3Oq4yhwmM7YfLpL1xuLq kum8Si7YxSkdfv8FapPG+RfpPMkSuKLFN+THmvQSyDPcn3rS7iLndXjw6QRmFA== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Heiko Stuebner , Mark Brown , linux-spi@vger.kernel.org Subject: [PATCH 18/25] spi: rockchip: Add support for RV1106 Date: Mon, 10 Aug 2026 15:11:09 +0300 Message-ID: <20260810121121.210040-19-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add the "rockchip,rv1106-spi" compatible to the match table. No driver changes are needed beyond that, since the controller behaves like the other Rockchip variants already handled by the driver. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- drivers/spi/spi-rockchip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 231fbcf0e7aa..447e6ff47c53 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -1021,6 +1021,7 @@ static const struct of_device_id rockchip_spi_dt_matc= h[] =3D { { .compatible =3D "rockchip,rk3328-spi", }, { .compatible =3D "rockchip,rk3368-spi", }, { .compatible =3D "rockchip,rk3399-spi", }, + { .compatible =3D "rockchip,rv1106-spi", }, { .compatible =3D "rockchip,rv1108-spi", }, { .compatible =3D "rockchip,rv1126-spi", }, { }, --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2062F3EB0E2; Mon, 10 Aug 2026 12:16:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364186; cv=none; b=qc/twIwbV0bvF7A2JcPYsfGByuoWLbT5fjf/m0zaIiUKTNBhZGqRFteSBd2n4sjwZiqM9xZQGfpcWGneIGSFmQG4gA/gAjrzNtilVks7SVDZeUo35EnrPbCoWj4yJwXcSiat+/7f6Bq5o9u4RHr+NDVMoKyPcRrBGmDAMz5ABEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364186; c=relaxed/simple; bh=RoQUuHMRBOlUT6PMXmijPBzse7gY96zfByIiX3DLl2g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Qa5AQEurbSDMo1pq1N0gE2rT4qRbyBtYg7lz7+u7EEumjRfQ9ieItc3zFvoPZHEy79Ysf9/c8x4lnTkUnbYhzmZk/tjaWpYVhiI+j+NuCMJNBQokviAbxWeDJRJh3NRnhY+DaiS5P8xyuf3eo3zREqCbWB6MFvf7wE4GGukfsvg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=gP+S9Yoa; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="gP+S9Yoa" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1C870C0514; Mon, 10 Aug 2026 15:16:21 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364183; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=PjpXsUWuH/r9E8s8lUfUdg5PLs7m5CliRJpnNLInJrI=; b=gP+S9Yoax+x4I/pvI/7/l8RziF3Wh1xJY/9F+IBe/aiziSieWgj1PjbSrlmdHgpINK9/ur ojW4UQ7TKnmZlPW6z9o7fSPuma/8WSnPdW0txTOI8ysyjVlMqfWLhmtRV7WFJhLZKURKYp z37wYXPacIYGb2jVFV1uNRfrHWJ8AVp9/VVqr5659ry8v+GYEoSGLExVvhde8y5gkddOIa mLsp73El1xT49aklCBSXtnQvGRQ/03i6W2w9zPzKJortrM4TYqFflsnrwqwxeaKm4xIbn9 fk4HYtE4xKdp9g2M+165tMF/kv8aKieQYYVTDcXChVaMhiYlIyD7vrHi/97laA== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 19/25] ARM: dts: rockchip: Add SPI nodes for RV1106 Date: Mon, 10 Aug 2026 15:11:10 +0300 Message-ID: <20260810121121.210040-20-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Rockchip RV1106 has two SPI controllers. Add the spi0 and spi1 nodes together with their aliases, using the m0 pinmux and the DMA channels of the single DMAC. Compared to Rockchip BSP kernel add missing SCLK_IN_SPI1 to spi1 node. Both nodes default to status =3D "disabled" and are enabled per-board. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index 58ac297e4d75..ce2f169b1acd 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -30,6 +30,8 @@ aliases { i2c2 =3D &i2c2; i2c3 =3D &i2c3; i2c4 =3D &i2c4; + spi0 =3D &spi0; + spi1 =3D &spi1; }; =20 cpus { @@ -370,6 +372,38 @@ uart5: serial@ff4f0000 { status =3D "disabled"; }; =20 + spi0: spi@ff500000 { + compatible =3D "rockchip,rv1106-spi", "rockchip,rk3066-spi"; + reg =3D <0xff500000 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>; + clock-names =3D "spiclk", "apb_pclk", "sclk_in"; + dmas =3D <&dmac 1>, <&dmac 0>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + status =3D "disabled"; + }; + + spi1: spi@ff510000 { + compatible =3D "rockchip,rv1106-spi", "rockchip,rk3066-spi"; + reg =3D <0xff510000 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_SPI1>, <&cru PCLK_SPI1>, <&cru SCLK_IN_SPI1>; + clock-names =3D "spiclk", "apb_pclk", "sclk_in"; + dmas =3D <&dmac 3>, <&dmac 2>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; + status =3D "disabled"; + }; + gpio1_ioc: syscon@ff538000 { compatible =3D "rockchip,rv1106-gpio1-ioc", "syscon"; reg =3D <0xff538000 0x8000>; --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 777C53DC4B6; Mon, 10 Aug 2026 12:16:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364189; cv=none; b=bJL5NES5bAg6htszfy33xeaKmt8NvyGbP5PPAChUIO1D6Xa+OeGVdn+6dNm85T1Wyw9CQaH9jzaICnMFb/j8Q/iDUTD9iwRimwQBpnUt9Tu0eY36p41NlvG8n7DolhaiqU+wECQoJUeLaJZ3SowFealHll7JA9szKedx8aNWMNE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364189; c=relaxed/simple; bh=t91XblPqoV6PdJaJMiKtKZWFOUj+j7FoahLhW23CxDA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bM4Wk8PTE+8tdfvXZFvD3hJOY8WsNlvbW/A5XJnIl3+KXBunsOe+ml5iGGOjNLYP4pvTgCgG5wp+C1cYmWUd1qnvI1QdgmrvIspOsWCQulD9s2jpv5bF+KT1iZNNI1laFcYmZRHp4ny02amjIkrW0X9RhgqJBExESX0y6ik/duE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=nFuLd717; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="nFuLd717" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4EC63C0518; Mon, 10 Aug 2026 15:16:24 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364186; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=lOe5l9utNgT7rnp1te/CrBZS1W64mKYVhM5GuNKN2to=; b=nFuLd717My9K/2HTU5k1GvZJr8IbjhdkNZTwa0rR081ukM0y7pRzaCclLFR25Os905OgqI c6o6mwtDaf+6mi02TDhDEXbeFYnXSGx+UQQlLB7lR9Rx2FZy6tmqZcqrGVeHaYc9ma4KRJ Zk6zNpKdAQN7kjMzuTMwzdkyX10QQM/QVbCwaR6zSL3ceY2zhqx1Z1H/DE9me6wiFORduy 4WNmbKQquo5xf1V4hPd+9pp+nJJ1yxNdcMfGgZVyWum5DzF2PFGgM/TpQCeXau2JvJcVLZ RJQkSfTF2ChmyDoT1FxMsXUAnjZT3FcmeGNeXqXAslDVOp67nJbo8Z+OOVOkMg== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Aurelien Jarno , Conor Dooley , Daniel Golle , Heiko Stuebner , Herbert Xu , Krzysztof Kozlowski , Nicolas Frattaroli , Olivia Mackall , Rob Herring , linux-crypto@vger.kernel.org Subject: [PATCH 20/25] dt-bindings: rng: rockchip: Add RV1106 compatible Date: Mon, 10 Aug 2026 15:11:11 +0300 Message-ID: <20260810121121.210040-21-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add rockchip,rv1106-rng as a variant of rockchip,rk3588-rng, following the pattern used for fallback compatibles in the schema (an items list with an enum and a matching const fallback), so RV1106 can reuse the existing rk3588-rng driver bindings. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- .../devicetree/bindings/rng/rockchip,rk3588-rng.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml= b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml index fcc5be80142d..60ceac2697c0 100644 --- a/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml +++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml @@ -13,10 +13,13 @@ maintainers: =20 properties: compatible: - enum: - - rockchip,rk3576-rng - - rockchip,rk3588-rng - + oneOf: + - const: rockchip,rk3576-rng + - const: rockchip,rk3588-rng + - items: + - enum: + - rockchip,rv1106-rng + - const: rockchip,rk3588-rng reg: maxItems: 1 =20 --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 557753EC816; Mon, 10 Aug 2026 12:16:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364192; cv=none; b=AlxxnMjggwG9OtmlL4SsRr6KnEe3yS1WSt5Pd7EzUalTOnVXtmxBFoAZGRKGsrQReIAIjRwVKeZxQ7oi7iuATxUtdnFww6i2iEDyHj8pJ7cLPg9olyYiVtlc/x52SlGTAy8YI8rUit6jgwZgN+OHMHM196V3z3Lo5Kkp2/TpXIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364192; c=relaxed/simple; bh=Hlb3zGiE/jTTbqr6GH01A5CdzLPFhNzjLR7B2UM6ijY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KEQtfo/Vwg5dTx6yzyskaCEOvA5qgwg21Ao86r5Y/UwGHQXc9+aNlzfa3ZdAPSGibziA2bFJ4xCplzOkWgPZzLNbhfskCypAKdnCje+RZzQb53zd8Yv/fACOrF1H+i8IZWniJhoew57d8I7c3R6/viWkxeGP6WT72sgEhZAKtC8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=pyg4r4ZO; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="pyg4r4ZO" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E46DEC0519; Mon, 10 Aug 2026 15:16:27 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364189; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=zmEzOagfD/gxsGiGWHAJSJv8bTNucnmIbKN5W/YS2eo=; b=pyg4r4ZOIP9A/e3kdcpDnIlTXtmyR5dwMrmgno9ZP5ew3iEcFwaZVfRNk7YOiaZyLQtYCb rzNSDfG6tyrz/kCInE5gSG2ccLOdw2WGGZAEdIAkCJ+c3kI9H18aLFHKl54NtX0xijNA/R JosPeXsGO+0aMDEM99TwER0f+2rH8oiPgEq8eYfH0lFCFxYXI4WVKtkmdqwDFv/FmJg6Gf LFhaImskTfnvKKDQZuAfBsT9Lf194h04ZYTMnultP+paLeSH2zIA+rCJy11tNsVKQro8wR I5E22s/S55vXFpAjM/+smuqrwfBnBuc8hiSYRQX/BnSFiBTUkbW4Px0p8uujIg== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 21/25] ARM: dts: rockchip: Add RNG node for RV1106 Date: Mon, 10 Aug 2026 15:11:12 +0300 Message-ID: <20260810121121.210040-22-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add the true random number generator (TRNG) node for RV1106, compatible with rockchip,rk3588-rng. The node is left disabled by default and can be enabled in board dts files. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index ce2f169b1acd..5db640a6ba90 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -255,6 +255,15 @@ dmac: dma-controller@ff420000 { arm,pl330-periph-burst; }; =20 + rng: rng@ff448000 { + compatible =3D "rockchip,rv1106-rng", "rockchip,rk3588-rng"; + reg =3D <0xff448000 0x200>; + interrupts =3D ; + clocks =3D <&cru HCLK_TRNG_NS>; + resets =3D <&cru SRST_H_TRNG_NS>; + status =3D "disabled"; + }; + i2c2: i2c@ff450000 { compatible =3D "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; reg =3D <0xff450000 0x1000>; --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D50A83EC823; Mon, 10 Aug 2026 12:16:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364194; cv=none; b=Vps6TAfn6BS1QfnYZVjqqTJbAn8PZPxSfaG1/VMAywtlluRMWsLu9OwQaOL2KMrCG8+4dxAQY6FGJODNRBgD8rmbW9LT11Dxldkiz9R5Ju2JXo2Lnyogx2LW0pllwZQb3cqgT/SrFLZi8qRHg9vFBu+YpTs1ZCmcmEmDOcC9kDI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364194; c=relaxed/simple; bh=//5Luhk7Q1co+UT8/FPgq+Wn0X0axEbKWWcBwfkbrmM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=grCW/Iqa9glo88m00yUtkTyRQeh8mq1Y+WqrOYRO4+tlzpQwpPPIO3sdgl+WgrLF/fqDxIdp4QvYveYM0k3moq+wPNVtDLa/NPsFyXvYsJ8dlf31O+8sGZobqKngYheiYxdANvEMCytUvwdyv6urNcwVU4WwYWZxWoZGL86/848= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=X6r2N0uv; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="X6r2N0uv" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 11777C0514; Mon, 10 Aug 2026 15:16:29 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364191; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=9cR5q9c8zxs0kvDwMYx9QuXfsTPCggxiJ1S/eoJFxgg=; b=X6r2N0uvMlSwPEGhnKwGUJ9gpJSyCW7rZGh9JrII3qrGjaYx12Es1+zGl7DT0Irs15qKxq Q8HSAn9Le8rI3AnqF6eL0VMGneMiiVVlRvKMyTQfMHJk0N5Blct8kMOSb8G0HQyOh7BisR dDkMEkYDsvyk4BrHF0jxaQp9jxitD9uK9E/ZzKi0nlFn67vZfbfkuSW3eqOWKuqqtxsQFC tZrSVzfMeo5vBTLq3hTKGLhrtZmVqBRngbb4v/Z3zbj8RDYHD4tqTQcrcj7ViGfT1Vn/hR VQBq6aGJHxSAinGUW1X9gd4rSXaCxsnE7wvsup3tNTJlft/q+lBz3smJMg9D6g== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 22/25] ARM: dts: rockchip: Add SDMMC1 node for RV1106 Date: Mon, 10 Aug 2026 15:11:13 +0300 Message-ID: <20260810121121.210040-23-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add the SDMMC1 controller node, compatible with rockchip,rk3288-dw-mshc, matching the existing eMMC and SD card controller nodes on this SoC. The node is left disabled by default and can be enabled in board dts files. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index 5db640a6ba90..b31cdb1c19d4 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -450,6 +450,18 @@ system_sram: sram@ff6c0000 { ranges =3D <0 0xff6c0000 0x40000>; }; =20 + sdmmc1: mmc@ff9a0000 { + compatible =3D "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg =3D <0xff9a0000 0x4000>; + interrupts =3D ; + clocks =3D <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth =3D <0x100>; + max-frequency =3D <200000000>; + status =3D "disabled"; + }; + gmac: ethernet@ffa80000 { compatible =3D "rockchip,rv1106-gmac", "snps,dwmac-4.20a"; reg =3D <0xffa80000 0x10000>; --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ED763EE1F8; Mon, 10 Aug 2026 12:16:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364196; cv=none; b=SOB0LUmUpD6j8QOsHNs4J4PjO/tbBXLUuedMf6P+TUlCdLwfmD1Wnn+v1mB2N2aPc9ljrR84lyNdoA6kbqVrpnOXnDLMny+YqwBHV42VVw1tNF8fjYF3SocIUfYyMJsoHRrtqUukJBk9LOXXe71u5Rp0qPznDlXhXwSwlqnma7Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364196; c=relaxed/simple; bh=Ficm7zonXC2aFb96eSapE8xIhmoLZMdMHaf+Xcg6rTo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vl+xSCceQDAv9i279O46gbeqSU6yi+XGuFv4fFhoneXhRzoAb0Dn5tOlJ8bWZiFKQWKNm+7urb5pAgObQlRqmR9WfVuAUPkvUhAKiwENPYAEeXd2XKbe7SV1X67DykX62iNDhgoqinfg/51RjROgbhMeT/BozXlqqham6fqzZpE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=JeHLCWyE; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="JeHLCWyE" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1B805C051C; Mon, 10 Aug 2026 15:16:31 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364193; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=sqrx4ikcXrAn8DGvjuumVqDdeyjA818dinNYnkqF66s=; b=JeHLCWyEUzzhHs8YZrYxBVZDt9I5y/H0XdVxW7IbEtBBvy9UQlYyOojVFdCXNNjEb8EhrP XusHB38mUu7EQQ1Ri/qjlpuFqT9FDcEqeUdi5fqF4if6vUaLzBR/7tMISPY+qXk1Yrd27F sm+wVdTndkmE2SwY4EZ2hnOOc/Wdj3WZ/MvSKlQO7Ulcv6gshB352lLiY3QR4ZbKYFq06Z u0dApIKvxvIW197GjLABJdfy4M/dT8gV8Owel0NmYAxYek+txN0G0ieKix5UX3xUJoIkka ld44GQTG7wbDJLE/Y/oA4kLIz7VcXSsIVXVj4KWz3gw+ZwJTYEIYvBGd5Hfa2g== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 23/25] ARM: dts: rockchip: add arm,cpu-registers-not-fw-configured to RV1106 timer node Date: Mon, 10 Aug 2026 15:11:14 +0300 Message-ID: <20260810121121.210040-24-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The firmware on RV1106 does not initialize CNTVOFF, so the virtual counter may have a bogus offset relative to the physical one. Add the arm,cpu-registers-not-fw-configured property to the arch timer node so the kernel does not trust firmware-configured timer registers and uses the physical timer instead of the virtual one. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index b31cdb1c19d4..12e87d25c72b 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -57,6 +57,7 @@ timer { clock-frequency =3D <24000000>; interrupts =3D , ; + arm,cpu-registers-not-fw-configured; }; =20 xin24m: oscillator { --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AEF03F0AB7; Mon, 10 Aug 2026 12:16:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364199; cv=none; b=K1lOjdX9n3DuCA1aMmh4Cl0D5CO5qaxpyUZmEmpBajuAnzf/d8Yuw3lxbXs9x7Nyi9rk5XB6a6+bmhfpVrHRXmOFskTNnI8iuTkdCXPf8KVcUL/WuKVTETVjOm8Wi0hAJGfe34kDkthrPavHVv6R0h9SJxa6raQiZuN0QPQ4n5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364199; c=relaxed/simple; bh=gFT3B4iLUq9Fto1vIW5ndfyqUd7uv4MvIQnYb1oy2oE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=F5lE9t0cBFV+Gm/oEowDAkEcWvWHT08gm97xmRZ4eqJXfk9oitozfncEVzLP74+GceGD7lfqZdxZc967msnj0bGNFbMfL5zMNVWWS7Ni3uxT6hqdHo9vebuT5D5/qeqjYfmyRpnT0GUNLKf88bnFow4frtP8g+R7hJY1vAN86mA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=QoQQGobm; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="QoQQGobm" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A4944C0519; Mon, 10 Aug 2026 15:16:34 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364196; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ycaA4zP669aUiie8zKyoviwsLCosDdRQ+6HaaafWNQs=; b=QoQQGobmRzM3gxEeKdVkx2BgbCm09kZqHISI75T8RbTj4qaJ3BY6BF5BZKwsEg36M9na7D SvTi9kaRdRhu5km1rWvfGMezx7UOeENFCSxyiox/L+6HkzGKtkviPS+fDRwJvlplMQhrbW 2H280posq3dZNoh2sl3a+zgh+rMsGQI0bgQPpSexjjKgiW1Lzc903n+j0IqcSewXKoN8Ld lHVl3XqwzS1oYW2oUjXjyohuZlxRUZNbcwd0ClvEmTUhN2ZFTxTfVfxTgZj98X30WPlNLl yLp01qdmZiR6CdWnbw9MQvvR1sLr2VTvts41TNVhKiOqk9FhWu31WNPhXNdv6Q== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org Subject: [PATCH 24/25] dt-bindings: pwm: rockchip: Add RV1106 compatible Date: Mon, 10 Aug 2026 15:11:15 +0300 Message-ID: <20260810121121.210040-25-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add the compatible for the PWM of the RV1106 which is compatible with RK3328 vatiant. RV1106 PWM channels also wire up an interrupt line each, with the channel that supports capture mode using a second one for that. Add "interrupts" to the schema to describe this. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml b/Docu= mentation/devicetree/bindings/pwm/pwm-rockchip.yaml index c8cdfb723336..8fa75cabf025 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml @@ -34,12 +34,20 @@ properties: - rockchip,rk3562-pwm - rockchip,rk3568-pwm - rockchip,rk3588-pwm + - rockchip,rv1106-pwm - rockchip,rv1126-pwm - const: rockchip,rk3328-pwm =20 reg: maxItems: 1 =20 + interrupts: + minItems: 1 + maxItems: 2 + description: + Some PWM channels (e.g. on rockchip,rv1106-pwm) additionally + support capture mode and use a second interrupt for that. + clocks: minItems: 1 maxItems: 2 --=20 2.47.3 From nobody Tue Sep 29 09:09:00 2026 Received: from mail.zlab.su (mail.zlab.su [109.73.193.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA6493F1AB7; Mon, 10 Aug 2026 12:16:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.73.193.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364202; cv=none; b=Qh5qDPH2IEzqifhYq2pAZP7nCQx2bDtNPvIPk6+W8on5kY7hRWdb+LvGzRzH6x3G+hBwpu7Y+ul4m9zgZFoMk+zYHMLLcbyvpiijj2EzoBthtpHd2n1fNY3nSiGK4OzASc6KocBx46VC7Oe6y1q/mfhJgzsnpfQj0tzr8RNgKCs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786364202; c=relaxed/simple; bh=5T/RgXnHHK3myJWdBsYk4LYGHqbI09TkFKPeTwOpLGw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YjSfL7ttnbct7muU5MJFg1ROhw36EBvRECLw5ZY5Y0IOnhSIJPJ1xikS/AsdAOSId6pvSArkv+GxOQONaSJo9Fgvyfb4HJsly7gJ96PPou1GAK+f4+Do6wxHwMXI3V4xXelD/SBglGFGB7Jz2LSFGpfCsOod3aHYYy9N1aotNuM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su; spf=pass smtp.mailfrom=zlab.su; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b=a7PyVENF; arc=none smtp.client-ip=109.73.193.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=zlab.su Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zlab.su Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zlab.su header.i=@zlab.su header.b="a7PyVENF" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 820D4C0514; Mon, 10 Aug 2026 15:16:37 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zlab.su; s=dkim; t=1786364198; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=kn221FDOcVW/vtJXVqj4m4sWcXwUTAwENBaWLbgbIbw=; b=a7PyVENFaH2HN71sVwO4XD1+ej1znLtCwGJIJojakVvCll3nvzOQzFGw5XPyzUocE1G7xS Vsa3FywK6Nfc4Ojh++/FUkWzRnwRKY4ttmOsSaG3DL+ngJkBJLLDXrRXh5kl8pBo1H8uhn 5NsTevWZACBzA5RuT+8KxWA39nqTiClOdJDeTpd7qG+3nhZlBHHBMewjWq+l+5xNXO52IH EqT+AedNJO+ouxeVF01tIBSwyW+f6yCmx6auSqkjz2ZFTc2op7zoFIXjrkq+nlrlyJ+ccs NW4xVQ9sV3kP8BO3bQ0+A82cz8aU6HGCkG9cFc8ondVy/seoAQ+qbSi+EZhCqQ== From: Vladislav Leonov To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Simon Glass , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladislav Leonov , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 25/25] ARM: dts: rockchip: Add PWM nodes for RV1106 Date: Mon, 10 Aug 2026 15:11:16 +0300 Message-ID: <20260810121121.210040-26-vlad@zlab.su> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260810121121.210040-1-vlad@zlab.su> References: <20260810121121.210040-1-vlad@zlab.su> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add the 12 PWM controller nodes (pwm0-pwm11) for RV1106, along with their aliases. Signed-off-by: Vladislav Leonov Tested-by: Simon Glass # Luckfox Pico Mini B (RV1103) --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 159 +++++++++++++++++++++++++ 1 file changed, 159 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/roc= kchip/rv1106.dtsi index 12e87d25c72b..d7959158f8a0 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -30,6 +30,18 @@ aliases { i2c2 =3D &i2c2; i2c3 =3D &i2c3; i2c4 =3D &i2c4; + pwm0 =3D &pwm0; + pwm1 =3D &pwm1; + pwm2 =3D &pwm2; + pwm3 =3D &pwm3; + pwm4 =3D &pwm4; + pwm5 =3D &pwm5; + pwm6 =3D &pwm6; + pwm7 =3D &pwm7; + pwm8 =3D &pwm8; + pwm9 =3D &pwm9; + pwm10 =3D &pwm10; + pwm11 =3D &pwm11; spi0 =3D &spi0; spi1 =3D &spi1; }; @@ -189,6 +201,104 @@ i2c1: i2c@ff320000 { status =3D "disabled"; }; =20 + pwm0: pwm@ff350000 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff350000 0x10>; + interrupts =3D ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm0m0_pins>; + clocks =3D <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm1: pwm@ff350010 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff350010 0x10>; + interrupts =3D ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm1m0_pins>; + clocks =3D <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm2: pwm@ff350020 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff350020 0x10>; + interrupts =3D ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm2m0_pins>; + clocks =3D <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm3: pwm@ff350030 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff350030 0x10>; + interrupts =3D , + ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm3m0_pins>; + clocks =3D <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm4: pwm@ff360000 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff360000 0x10>; + interrupts =3D ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm4m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm5: pwm@ff360010 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff360010 0x10>; + interrupts =3D ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm5m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm6: pwm@ff360020 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff360020 0x10>; + interrupts =3D ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm6m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm7: pwm@ff360030 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff360030 0x10>; + interrupts =3D , + ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm7m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + gpio0_ioc: syscon@ff388000 { compatible =3D "rockchip,rv1106-gpio0-ioc", "syscon"; reg =3D <0xff388000 0x8000>; @@ -304,6 +414,55 @@ i2c4: i2c@ff470000 { status =3D "disabled"; }; =20 + pwm8: pwm@ff490000 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff490000 0x10>; + interrupts =3D ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm8m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm9: pwm@ff490010 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff490010 0x10>; + interrupts =3D ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm9m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm10: pwm@ff490020 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff490020 0x10>; + interrupts =3D ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm10m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm11: pwm@ff490030 { + compatible =3D "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; + reg =3D <0xff490030 0x10>; + interrupts =3D , + ; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm11m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + uart0: serial@ff4a0000 { compatible =3D "rockchip,rv1106-uart", "snps,dw-apb-uart"; reg =3D <0xff4a0000 0x100>; --=20 2.47.3