From nobody Tue Sep 29 08:26:40 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E453F40861B for ; Mon, 10 Aug 2026 15:11:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786374675; cv=none; b=MpmeiF/oJ76z1DSm2lDcMZFEhhdCCPpo/S/o/8Ewm8vvl/L7Rj212Gzm+TL+Z0Ug0koBx3yEhQq0RAPzAm/asVzH3NVYK+6548FdfHFyYha5Te0y835ep5aKcHoAit4gz+Xj/euBkb0wfJrYk4lp5Ng2XJQBa7QPuFW2LonZSeg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786374675; c=relaxed/simple; bh=i/G1An0VHWTu6Kk1L/fgdDQndh5AbgnUyrA5Wx6vERE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=X4nihafEsrRbPzc4/4WVD7Z4vkqONHwcMWHlTH/FeUeCG1S/XkOMmg1r15OXgvrc752Z9N5mxWoculNds9dcYc9F8dxU68gieEM8dWVchG3Rb521lkAN4QejoG6sw56+qO7H1T2aZZtBGtJgYpL/RAvikM5N5G8TfNrEv5mi0I8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=v+uGeFwD; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="v+uGeFwD" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 305D01A1533; Mon, 10 Aug 2026 15:11:11 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 052136033B; Mon, 10 Aug 2026 15:11:11 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2228A11C4A9F4; Mon, 10 Aug 2026 17:11:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1786374666; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=dPbz9BIgZZPw7WZpzE8qr59XBu7j/hRKKLXb1kSnc50=; b=v+uGeFwDr2kTSpl5iGYfde2p2uhZAztahPlzAOUcV/fERhFSO4pB5rkqoTXk3oanJrC3rJ tiW+ws2aufZyo1XnCP44yVa8NKwWTAA45VPPug8WpziMHonhrYGFLIzYuSJK7t51dtmQgX enkZtKR0O5pO4ktjLzrKaRo+ZklEvao1c2iEzX3bq2vpvZvageZ2EdBsCtR4wjuJVHQBeR lTzQ5ZnwW5QK2uYVqyIaPmYL9EhkLxP8sQrIQBK0/4TO5QZL7eszONVEx90yikl6emE9iO aaPW+XDj1ICQ28Bz7y7kuUOP270iDaHghIbR5YFHGbMjyGHQsmR7zK2+COIbzw== From: Miquel Raynal Date: Mon, 10 Aug 2026 17:10:42 +0200 Subject: [PATCH v3 1/3] spi: spi-mem: Flag DQS capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260810-winbond-nand-next-phy-tuning-v3-1-a97c3a61e675@bootlin.com> References: <20260810-winbond-nand-next-phy-tuning-v3-0-a97c3a61e675@bootlin.com> In-Reply-To: <20260810-winbond-nand-next-phy-tuning-v3-0-a97c3a61e675@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 DQS is a typical SPI memory signal used to help with reading the data on the bus at high speeds (especially in DTR mode) by avoiding clock skews. The chip generates a clock signal synchronized with its data output fronts, also called data strobe. SPI NOR and SPI NAND cores must set this flag in order to indicate to other layers that DQS is available. Create a getter and a setter to reach this capability. Signed-off-by: Miquel Raynal Acked-by: Mark Brown --- drivers/spi/spi-mem.c | 32 ++++++++++++++++++++++++++++++++ include/linux/spi/spi-mem.h | 4 ++++ 2 files changed, 36 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index a88b9f038356..5f973ebfb8b6 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -541,6 +541,38 @@ const char *spi_mem_get_name(struct spi_mem *mem) } EXPORT_SYMBOL_GPL(spi_mem_get_name); =20 +/** + * spi_mem_set_dqs() - Mark DQS as being available + * @mem: the SPI memory + * + * When reading at high frequencies (> 100MHz), especially when DTR is ena= bled, + * transfer speed is limited due to clock skews. In particular, the contro= ller + * does not know the board propagation delay nor the memory chip internal = delay + * (clock in to data out) and thus cannot optimize its sampling points. + * Mitigating this limitation is possible with the addition of a data stro= be + * signal, commonly named DQS. + * + * Set the DQS boolean if the feature is available and configured at the c= hip + * level. Controllers may query this value. + */ +void spi_mem_set_dqs(struct spi_mem *mem) +{ + mem->dqs =3D true; +} +EXPORT_SYMBOL_GPL(spi_mem_set_dqs); + +/** + * spi_mem_has_dqs() - Query whether the DQS is available or not + * @mem: the SPI memory + * + * Return: a boolean indicating whether the DQS signal is available or not. + */ +bool spi_mem_has_dqs(struct spi_mem *mem) +{ + return mem->dqs; +} +EXPORT_SYMBOL_GPL(spi_mem_has_dqs); + /** * spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation = to * match controller limitations diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index f660bb2e9f85..0cce6b57242a 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -275,6 +275,7 @@ struct spi_mem_dirmap_desc { * @spi: the underlying SPI device * @drvpriv: spi_mem_driver private data * @name: name of the SPI memory device + * @dqs: extra data trobe pin available for high frequency read operations * * Extra information that describe the SPI memory device and may be needed= by * the controller to properly handle this device should be placed here. @@ -286,6 +287,7 @@ struct spi_mem { struct spi_device *spi; void *drvpriv; const char *name; + bool dqs; }; =20 /** @@ -461,6 +463,8 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, } #endif /* CONFIG_SPI_MEM */ =20 +void spi_mem_set_dqs(struct spi_mem *mem); +bool spi_mem_has_dqs(struct spi_mem *mem); int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op); u64 spi_mem_calc_op_duration(struct spi_mem *mem, struct spi_mem_op *op); --=20 2.54.0 From nobody Tue Sep 29 08:26:40 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADA9D23393E for ; Mon, 10 Aug 2026 15:11:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786374680; cv=none; b=o2W5tHl6MDCkby3Hhv/MmAx2eM9t7FpHwd9VjnlAJpcSja8yIFZ+nEul1GeH3bmwyMlHlFZoqJNxJmefeyRZ0oM9ffSLi/hlwnR8IZCdzRVbS8LT+YxGjm13LCQysk47y31TT6Zoa3LT3bU2NFB6ZoGoTJQhMvs4CSGp9XHjESg= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260810-winbond-nand-next-phy-tuning-v3-2-a97c3a61e675@bootlin.com> References: <20260810-winbond-nand-next-phy-tuning-v3-0-a97c3a61e675@bootlin.com> In-Reply-To: <20260810-winbond-nand-next-phy-tuning-v3-0-a97c3a61e675@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Check whether the NAND is capable of generating a DQS signal and set the flag accordingly. Not wiring the DQS signal on a DQS capable chip that will be used at frequency requiring this signal may be considered a hardware bug, so let's assume this line will be routed "in most cases". If/when we get issues with this assumption, a DT property describing the lacking line in the routing can be created. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 4 ++++ include/linux/mtd/spinand.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 74bb5ee83b31..b54f7a1dae85 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -2050,6 +2050,10 @@ static int spinand_probe(struct spi_mem *mem) if (ret) return ret; =20 + /* Assume manufacturer drivers will enable the DQS pin if it is available= */ + if (spinand->flags & SPINAND_HAS_DQS) + spi_mem_set_dqs(mem); + ret =3D mtd_device_register(mtd, NULL, 0); if (ret) goto err_spinand_cleanup; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index ec6efcfeef83..fe05b477afef 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -490,6 +490,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3) #define SPINAND_NO_RAW_ACCESS BIT(4) #define SPINAND_ODTR_PACKED_PAGE_READ BIT(5) +#define SPINAND_HAS_DQS BIT(6) =20 /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine stru= cture --=20 2.54.0 From nobody Tue Sep 29 08:26:40 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14CB03F9F45 for ; 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bh=Zn32rgRm94l4EzfC6PqAkGOthXJmT/0MRbdxmTrZ2XE=; b=E7Jy+3vM3oEC0H6s3G1rWMwlk/mH23SOr8oj9nZyFa9q8ABYi5bpP/ZO7WmqO1/rObYy4+ kUel5txeGDVWAv4RXG+QInGakvHLk42uud+UZCZJ2BTzcfWDWFj0Z8+iGQ5LNWV58895lS kjSrW5/f/2FWQbRyUvzxjlGwDuFpa9skF7M9TRTiV6n8IaXI37RlZCNKi9ePDc1Nr+ajsa tC8jqCjvfFY+ZAKMcNSwmX+Gk9Kw3eSDln1gDBQX/UC5kWcfYuU+gwLRQd74afLCuk5ZjJ R0MpHqRsFEF/jSQ/yyw+Srq2jjtohriD/7w6oKEt43v3YoCnWTmyfEGDYaQj8A== From: Miquel Raynal Date: Mon, 10 Aug 2026 17:10:44 +0200 Subject: [PATCH v3 3/3] mtd: spi-nand: winbond: Enable the DQS pin on W35N**JW series Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260810-winbond-nand-next-phy-tuning-v3-3-a97c3a61e675@bootlin.com> References: <20260810-winbond-nand-next-phy-tuning-v3-0-a97c3a61e675@bootlin.com> In-Reply-To: <20260810-winbond-nand-next-phy-tuning-v3-0-a97c3a61e675@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 These chips have a DQS pin, enable it by default in DTR mode because there is apparently no issue in setting it for lower frequencies, and the extra power consumption seems very low compared to the current drawn by the NAND array itself while operating. This setting will be required for high speed I/O transfers (with PHY tuning). Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 9b78c1e6cbc9..8209b214e594 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -607,7 +607,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and, else if (!single && !dtr) io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_SDR; else if (!single && dtr) - io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR; + io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR_DS; else return -EINVAL; =20 @@ -689,7 +689,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants, &cont_read_cache_octal_variants), - 0, + SPINAND_HAS_DQS, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg), @@ -744,7 +744,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants, &cont_read_cache_octal_variants), - SPINAND_ODTR_PACKED_PAGE_READ, + SPINAND_ODTR_PACKED_PAGE_READ | SPINAND_HAS_DQS, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg), @@ -776,7 +776,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants, &cont_read_cache_octal_variants), - SPINAND_ODTR_PACKED_PAGE_READ, + SPINAND_ODTR_PACKED_PAGE_READ | SPINAND_HAS_DQS, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg), --=20 2.54.0