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[87.20.3.207]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4995ea3361esm194506475e9.15.2026.08.09.05.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Aug 2026 05:15:04 -0700 (PDT) From: Christian Marangi To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Christian Marangi , Benjamin Larsson , John Ogness , Manuel Lauss , Jacques Nilo , Rong Zhang , Jiaxun Yang , Randy Dunlap , Gerhard Engleder , Binbin Zhou , Lubomir Rintel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Conor Dooley Subject: [PATCH v4 1/2] dt-bindings: serial: 8250: Add Airoha compatibles Date: Sun, 9 Aug 2026 14:14:46 +0200 Message-ID: <20260809121449.574277-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260809121449.574277-1-ansuelsmth@gmail.com> References: <20260809121449.574277-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Benjamin Larsson The Airoha SoC family have a mostly 16550-compatible UART and High-Speed UART hardware with the exception of custom baud rate settings register. Signed-off-by: Benjamin Larsson Signed-off-by: Christian Marangi Acked-by: Conor Dooley --- Documentation/devicetree/bindings/serial/8250.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documenta= tion/devicetree/bindings/serial/8250.yaml index bb7b9c87a807..b6f7e093d8d7 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -110,6 +110,11 @@ properties: - const: mrvl,pxa-uart - const: nuvoton,wpcm450-uart - const: nuvoton,npcm750-uart + - const: airoha,en7523-uart + - items: + - const: airoha,an7581-uart + - const: airoha,en7523-uart + - const: airoha,an7581-hsuart - const: nvidia,tegra20-uart - const: nxp,lpc3220-uart - items: --=20 2.53.0 From nobody Tue Sep 29 09:46:21 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 013863C0602 for ; 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[87.20.3.207]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4995ea3361esm194506475e9.15.2026.08.09.05.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Aug 2026 05:15:06 -0700 (PDT) From: Christian Marangi To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Christian Marangi , Benjamin Larsson , John Ogness , Manuel Lauss , Jacques Nilo , Rong Zhang , Jiaxun Yang , Randy Dunlap , Gerhard Engleder , Binbin Zhou , Lubomir Rintel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v4 2/2] serial: 8250: Add Airoha SoC UART and HSUART support Date: Sun, 9 Aug 2026 14:14:47 +0200 Message-ID: <20260809121449.574277-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260809121449.574277-1-ansuelsmth@gmail.com> References: <20260809121449.574277-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Airoha AN7523 UART and AN7581 HSUART. These implement a standard 16550 UART with only some custom logic for baud rate handling. Co-developed-by: Benjamin Larsson Signed-off-by: Benjamin Larsson Reviewed-by: Andy Shevchenko Signed-off-by: Christian Marangi --- drivers/tty/serial/8250/8250.h | 6 + drivers/tty/serial/8250/8250_airoha.c | 187 ++++++++++++++++++++++++++ drivers/tty/serial/8250/8250_port.c | 16 +++ drivers/tty/serial/8250/Kconfig | 11 ++ drivers/tty/serial/8250/Makefile | 1 + 5 files changed, 221 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_airoha.c diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h index 77fe0588fd6b..e6b2b9431229 100644 --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h @@ -73,6 +73,12 @@ struct serial8250_config { unsigned int flags; }; =20 +enum uart_port_type { + /* Internal 8250 only */ + UART_PORT_AIROHA =3D 124, + UART_PORT_AIROHA_HS =3D 125, +}; + #define UART_CAP_FIFO BIT(8) /* UART has FIFO */ #define UART_CAP_EFR BIT(9) /* UART has EFR */ #define UART_CAP_SLEEP BIT(10) /* UART has IER sleep */ diff --git a/drivers/tty/serial/8250/8250_airoha.c b/drivers/tty/serial/825= 0/8250_airoha.c new file mode 100644 index 000000000000..fe72a39561c2 --- /dev/null +++ b/drivers/tty/serial/8250/8250_airoha.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Airoha UART driver + * + * Copyright (c) 2025 Genexis Sweden AB + * Author: Benjamin Larsson + * Christian Marangi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "8250.h" + +#define UART_AIROHA_XINCLKDR 10 +#define UART_AIROHA_XYD 11 +#define UART_AIROHA_XYD_X GENMASK(31, 16) +#define UART_AIROHA_XYD_Y GENMASK(15, 0) + +struct airoha_8250_priv { + int line; +}; + +#define UART_BRD_20M 0x0001 + +#define XINDIV_CLOCK (20 * HZ_PER_MHZ) +#define XYD_Y 65000 + +static const unsigned int airoha_clk_divs[] =3D { 2, 4, 10 }; + +static unsigned int airoha_get_divisor(struct uart_port *port, + unsigned int baud, + unsigned int *frac) +{ + /* Hardware always uses BRDIV =3D 1. */ + *frac =3D 0; + + return UART_BRD_20M; +} + +/* + * Airoha UART baud rate calculation logic + * + * crystal_clock =3D 20 MHz (fixed frequency) + * xindiv_clock =3D crystal_clock / clock_div + * (x/y) =3D XYD, 32 bit register with 16 bits of x and then 16 bits of y + * clock_div =3D XINCLK_DIVCNT (default set to 10 (0x4)), + * - 3 bit register [ 1, 2, 4, 8, 10, 12, 16, 20 ] + * + * baud_rate =3D ((xindiv_clock) * (x/y)) / ([BRDH,BRDL] * 16) + * + * Selecting divider needs to fulfill + * 1.8432 MHz <=3D xindiv_clk <=3D APB clock / 2 + * The clocks are unknown but a divider of value 1 did not result in a val= id + * waveform. + * + * XYD_y seems to need to be larger then XYD_x for proper waveform generat= ion. + * Setting [BRDH,BRDL] to [0,1] and XYD_y to 65000 gives even values + * for usual baud rates. + */ +static void airoha_set_divisor(struct uart_port *port, unsigned int baud, + unsigned int quot, unsigned int quot_frac) +{ + struct uart_8250_port *up =3D up_to_u8250p(port); + u32 xindiv_clk; + u64 xyd_x, nom; + int div_bit; + + /* Set baud rate calculation defaults (BRDIV [BRDH,BRDL] to 1) */ + serial8250_do_set_divisor(port, baud, UART_BRD_20M); + + /* + * Calculate XYD_x and XINCLKDR register by searching + * through a table of crystal_clock divisors. + */ + nom =3D (u64)baud * XYD_Y; + for (div_bit =3D ARRAY_SIZE(airoha_clk_divs) - 1; div_bit >=3D 0; div_bit= --) { + unsigned int div =3D airoha_clk_divs[div_bit]; + + xindiv_clk =3D XINDIV_CLOCK / div; + xyd_x =3D div_u64(nom * 16, xindiv_clk); + + /* For the HSUART xyd_x needs to be scaled by a factor of 2 */ + if (port->type =3D=3D UART_PORT_AIROHA_HS) + xyd_x /=3D 2; + + if (xyd_x < XYD_Y) + break; + } + + /* Couldn't find a valid xyd_x */ + if (div_bit < 0) { + dev_err(port->dev, "failed to find suitable clock divisor for baud %u\n", + baud); + return; + } + + serial_port_out(port, UART_AIROHA_XINCLKDR, BIT(div_bit)); + serial_port_out(port, UART_AIROHA_XYD, + FIELD_PREP(UART_AIROHA_XYD_X, xyd_x) | + FIELD_PREP(UART_AIROHA_XYD_Y, XYD_Y)); + + /* Restore normal register access. */ + serial_port_out(port, UART_LCR, up->lcr); +} + +static int airoha_8250_probe(struct platform_device *pdev) +{ + struct uart_8250_port uart =3D { }; + struct device *dev =3D &pdev->dev; + struct airoha_8250_priv *priv; + struct resource *res; + int ret; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return dev_err_probe(dev, -EINVAL, "invalid address\n"); + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + uart.port.dev =3D dev; + if (device_is_compatible(dev, "airoha,an7581-hsuart")) + uart.port.type =3D UART_PORT_AIROHA_HS; + else + uart.port.type =3D UART_PORT_AIROHA; + uart.port.flags =3D UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | + UPF_FIXED_TYPE | UPF_IOREMAP; + uart.port.set_divisor =3D airoha_set_divisor; + uart.port.get_divisor =3D airoha_get_divisor; + uart.port.mapbase =3D res->start; + uart.port.mapsize =3D resource_size(res); + + ret =3D uart_read_and_validate_port_properties(&uart.port); + if (ret) + return ret; + + ret =3D serial8250_register_8250_port(&uart); + if (ret < 0) + return ret; + + priv->line =3D ret; + platform_set_drvdata(pdev, priv); + + return 0; +} + +static void airoha_8250_remove(struct platform_device *ofdev) +{ + struct airoha_8250_priv *priv =3D platform_get_drvdata(ofdev); + + serial8250_unregister_port(priv->line); +} + +static const struct of_device_id airoha_8250_dt_ids[] =3D { + { .compatible =3D "airoha,en7523-uart" }, + { .compatible =3D "airoha,an7581-hsuart" }, + { } +}; +MODULE_DEVICE_TABLE(of, airoha_8250_dt_ids); + +static struct platform_driver airoha_8250_driver =3D { + .driver =3D { + .name =3D "8250_airoha", + .of_match_table =3D airoha_8250_dt_ids, + }, + .probe =3D airoha_8250_probe, + .remove =3D airoha_8250_remove, +}; +module_platform_driver(airoha_8250_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Airoha UART driver"); +MODULE_AUTHOR("Benjamin Larsson "); +MODULE_AUTHOR("Christian Marangi "); diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/= 8250_port.c index 630deb7dd344..c888cae7d98b 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -311,6 +311,22 @@ static const struct serial8250_config uart_config[] = =3D { .rxtrig_bytes =3D {1, 8, 16, 30}, .flags =3D UART_CAP_FIFO | UART_CAP_AFE, }, + [UART_PORT_AIROHA] =3D { + .name =3D "Airoha UART", + .fifo_size =3D 8, + .tx_loadsz =3D 1, + .fcr =3D UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | UART_FCR_CLEAR_RCV= R, + .rxtrig_bytes =3D {1, 4, 4, 4}, + .flags =3D UART_CAP_FIFO, + }, + [UART_PORT_AIROHA_HS] =3D { + .name =3D "Airoha HSUART", + .fifo_size =3D 128, + .tx_loadsz =3D 128, + .fcr =3D UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | UART_FCR_CLEAR_RCV= R, + .rxtrig_bytes =3D {1, 4}, + .flags =3D UART_CAP_FIFO, + }, }; =20 /* Uart divisor latch read */ diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kcon= fig index fc3e58d62233..310da7af7a49 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -337,6 +337,17 @@ config SERIAL_8250_ACORN system, say Y to this option. The driver can handle 1, 2, or 3 port cards. If unsure, say N. =20 +config SERIAL_8250_AIROHA + tristate "Airoha UART support" + depends on ARCH_AIROHA || COMPILE_TEST + depends on SERIAL_8250 + help + Selecting this option enables an Airoha SoC specific baud rate + calculation routine on an otherwise 16550 compatible UART hardware. + + If you have an Airoha based board and want to use the serial port, + say Y to this option. If unsure, say N. + config SERIAL_8250_BCM2835AUX tristate "BCM2835 auxiliar mini UART support" depends on ARCH_BCM2835 || COMPILE_TEST diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Mak= efile index 6d21402b4435..83257696ea8a 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SERIAL_8250_CONSOLE) +=3D 8250_early.o =20 obj-$(CONFIG_SERIAL_8250_ACCENT) +=3D 8250_accent.o obj-$(CONFIG_SERIAL_8250_ACORN) +=3D 8250_acorn.o +obj-$(CONFIG_SERIAL_8250_AIROHA) +=3D 8250_airoha.o obj-$(CONFIG_SERIAL_8250_ASPEED_VUART) +=3D 8250_aspeed_vuart.o obj-$(CONFIG_SERIAL_8250_BCM2835AUX) +=3D 8250_bcm2835aux.o obj-$(CONFIG_SERIAL_8250_BCM7271) +=3D 8250_bcm7271.o --=20 2.53.0