From nobody Tue Sep 29 09:46:28 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 690FB37AA95; Sun, 9 Aug 2026 12:16:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786277772; cv=none; b=e1WK0mq2ICPsBByypCJjXgXfKSmNvB6KLjU0gMQAdzOSFqNmn1LvIHfzM/Ig3wGeHothj+NBNI/UB/PI9ClkKcjJIVEoV/+sIdnvHiz9rbTSyYbXUp2VoFsBsV26MP5qh8YCy8Je3/cUfoKHJDtSQSg+5aZArncCcGMfGS7CiGI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786277772; c=relaxed/simple; bh=GS0706aWd/X1ewhqfLjE66a5N9etk1CxR3PFk3+EnSU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n48cd5am7stWiQtQjDjhmHbtQ5aj0KlPHn+h+2btrTciDwZUYViQn59qRTJyVpbSv+tTrdUdPJEHLQMWzE4FMhibW2VFOshCKSX7IyJ7kn0trzFr1BKWG92PGu1SXuYWzutlCz6uUhsc8MrxDGXhaOXqR1+am5OTwvrZWLo1IlU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AvY8pJqh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AvY8pJqh" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0BC77C2BCF5; Sun, 9 Aug 2026 12:16:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786277772; bh=GS0706aWd/X1ewhqfLjE66a5N9etk1CxR3PFk3+EnSU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AvY8pJqh3v3kNHJdkubYRALiohycjtLJcod5jiU9oqnA/tIn5ebcBjh2aPjEK6jrb XDm7IaNRSJnWH1i6YpteEZ1GvDEs2ZG3zEpqyl+lX9tvEQRMXoLILGM/I3HARSIiIV 39aPBIyxwtmNufh3xHV75gWBeUiOAL7vN5h5/E3/mLqmYEceWiW4620bmSZDMDQZiG zfqJ/PHocq4+CyE0QMsd8s2w7pbSdRzxL/6n7eOeTpnlqCflgy7Gn6v3O12P9454sl crYtw3BsozSluxL5/KB+SUHFlCSzTdQ0j0J8ozhoqAQh93diKKMS/eJcjyfCx+g/OJ v2qqRJygyi3TA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDF27C5AD4E; Sun, 9 Aug 2026 12:16:11 +0000 (UTC) From: Sven Peter Date: Sun, 09 Aug 2026 14:16:02 +0200 Subject: [PATCH 1/3] dt-bindings: reset: Add Apple SoC CIO reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260809-b4-cio-reset-v1-1-4f33777d9b4b@kernel.org> References: <20260809-b4-cio-reset-v1-0-4f33777d9b4b@kernel.org> In-Reply-To: <20260809-b4-cio-reset-v1-0-4f33777d9b4b@kernel.org> To: Sven Peter , Janne Grunau , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4500; i=sven@kernel.org; h=from:subject:message-id; bh=GS0706aWd/X1ewhqfLjE66a5N9etk1CxR3PFk3+EnSU=; b=owGbwMvMwCXmIlirolUq95LxtFoSQ1ZFfnvIvV2XKu9/dQityzjywVMjbFLbU1t2sTz2zcu/C vu3PDvbUcrCIMbFICumyLJ9v73pk4dvBJduuvQeZg4rE8gQBi5OAZhI+zKGf2bbsph/HAnbsvRP dYCOQNzN/F2x9Wx91cbr5L6pGP5/rMDwV2Ry7KQTYomhSU9zG2PiGVsCi99bMp98+DZf0PzbZpU nnAA= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 The CIO (USB4/Thunderbolt) blocks on Apple Silicon SoCs have a reset inside the power manager that has to be deasserted before their co-processor can be booted. On t8103 each port comes with a dedicated register page, represented as a standalone node. On t600x a single register shared by all ports of a die is located in the middle of the PMGR MMIO region instead, represented as a sub-node of the PMGR syscon. Signed-off-by: Sven Peter Reviewed-by: Conor Dooley --- .../devicetree/bindings/arm/apple/apple,pmgr.yaml | 6 ++ .../bindings/reset/apple,t8103-cio-reset.yaml | 74 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 3 files changed, 81 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/= Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index c67b67ba065a..2cdecc2c2cea 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -59,6 +59,12 @@ patternProperties: type: object $ref: /schemas/power/apple,pmgr-pwrstate.yaml# =20 + "reset-controller@[0-9a-f]+$": + description: + Reset controller for the CIO (USB4/Thunderbolt) blocks + type: object + $ref: /schemas/reset/apple,t8103-cio-reset.yaml# + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/reset/apple,t8103-cio-reset.= yaml b/Documentation/devicetree/bindings/reset/apple,t8103-cio-reset.yaml new file mode 100644 index 000000000000..5f5be0636b36 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/apple,t8103-cio-reset.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/apple,t8103-cio-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC CIO (USB4/Thunderbolt) block reset controller + +maintainers: + - Sven Peter + +description: | + The CIO (Converged I/O) blocks on Apple Silicon SoCs have a reset + inside the power manager (PMGR) that has to be deasserted before + their co-processor can be booted. On t8103 each port comes with a + dedicated register page, represented as a standalone node. On t600x a + single register shared by all ports of a die with one request bit per + port is used instead. Since this register is located in the middle of + the PMGR MMIO region it is represented as a sub-node of the PMGR + syscon with reg used as an offset into it. + + In both cases the reset id is the CIO port index on the die. + +properties: + compatible: + oneOf: + - enum: + - apple,t8103-cio-reset + - apple,t6000-cio-reset + - items: + - const: apple,t8112-cio-reset + - const: apple,t8103-cio-reset + - items: + - const: apple,t6020-cio-reset + - const: apple,t6000-cio-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + reset-controller@23b784000 { + compatible =3D "apple,t8103-cio-reset"; + reg =3D <0x2 0x3b784000 0x0 0x8000>; + #reset-cells =3D <1>; + }; + }; + - | + power-management@28e080000 { + compatible =3D "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple= -mfd"; + reg =3D <0x8e080000 0x1c000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reset-controller@1a034 { + compatible =3D "apple,t6000-cio-reset"; + reg =3D <0x1a034 0x4>; + #reset-cells =3D <1>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 15011f5752a9..4b78528324c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2606,6 +2606,7 @@ F: Documentation/devicetree/bindings/pinctrl/apple,pi= nctrl.yaml F: Documentation/devicetree/bindings/power/apple* F: Documentation/devicetree/bindings/power/reset/apple,smc-reboot.yaml F: Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml +F: Documentation/devicetree/bindings/reset/apple,t8103-cio-reset.yaml F: Documentation/devicetree/bindings/rtc/apple,smc-rtc.yaml F: Documentation/devicetree/bindings/spi/apple,spi.yaml F: Documentation/devicetree/bindings/spmi/apple,spmi.yaml --=20 2.55.0 From nobody Tue Sep 29 09:46:28 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69033379C5F; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260809-b4-cio-reset-v1-2-4f33777d9b4b@kernel.org> References: <20260809-b4-cio-reset-v1-0-4f33777d9b4b@kernel.org> In-Reply-To: <20260809-b4-cio-reset-v1-0-4f33777d9b4b@kernel.org> To: Sven Peter , Janne Grunau , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7782; i=sven@kernel.org; h=from:subject:message-id; bh=s0VuUVB5ruw7/XiIUSNF4+H9ehJ1hObbx+QlQJOTfhs=; b=owGbwMvMwCXmIlirolUq95LxtFoSQ1ZFfkdY/AmVNMlde1wLd34yLY7ks269ftA06uKJU2eTt S9sknDsKGVhEONikBVTZNm+3970ycM3gks3XXoPM4eVCWQIAxenAEzkQx/DP9vufRkLil96XWfY 2yY6zUwhMLzLQKZQc4HGiXVrOzcu0WP4w6m+v9a6y6Ff/7FiKCPH7x/3j4d+EpAJja8rPT49uTW OFQA= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Add a driver for the reset of the CIO (USB4/Thunderbolt) blocks on Apple Silicon SoCs which has to be deasserted before their co-processor can be booted. On t8103 each port comes with a dedicated register page while t600x uses a single register with one request bit per port shared by all ports of a die inside the PMGR MMIO region. Signed-off-by: Sven Peter --- MAINTAINERS | 1 + drivers/reset/Kconfig | 10 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-apple-cio.c | 182 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 194 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4b78528324c8..5425051c0f99 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2636,6 +2636,7 @@ F: drivers/pinctrl/pinctrl-apple-gpio.c F: drivers/power/reset/macsmc-reboot.c F: drivers/power/supply/macsmc-power.c F: drivers/pwm/pwm-apple.c +F: drivers/reset/reset-apple-cio.c F: drivers/rtc/rtc-macsmc.c F: drivers/soc/apple/* F: drivers/spi/spi-apple.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d009eb0849a3..1e83cb5c68ce 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -22,6 +22,16 @@ config RESET_A10SR This option enables support for the external reset functions for peripheral PHYs on the Altera Arria10 System Resource Chip. =20 +config RESET_APPLE_CIO + tristate "Apple SoC CIO block reset driver" + depends on ARCH_APPLE || COMPILE_TEST + select MFD_SYSCON + help + This enables the reset driver for the CIO (USB4/Thunderbolt) blocks + found on Apple Silicon SoCs. It is required to start the blocks + before the USB4/Thunderbolt host routers inside them can be brought + up by the thunderbolt driver. + config RESET_ASPEED tristate "ASPEED Reset Driver" depends on ARCH_ASPEED || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e52569bd276..6554649bc139 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -7,6 +7,7 @@ obj-y +=3D starfive/ obj-y +=3D sti/ obj-y +=3D tegra/ obj-$(CONFIG_RESET_A10SR) +=3D reset-a10sr.o +obj-$(CONFIG_RESET_APPLE_CIO) +=3D reset-apple-cio.o obj-$(CONFIG_RESET_ASPEED) +=3D reset-aspeed.o obj-$(CONFIG_RESET_ATH79) +=3D reset-ath79.o obj-$(CONFIG_RESET_AXS10X) +=3D reset-axs10x.o diff --git a/drivers/reset/reset-apple-cio.c b/drivers/reset/reset-apple-ci= o.c new file mode 100644 index 000000000000..951340455468 --- /dev/null +++ b/drivers/reset/reset-apple-cio.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Apple SoC CIO (USB4/Thunderbolt) block reset driver + * + * Copyright The Asahi Linux Contributors + * + * The CIO blocks have a reset inside the power manager (PMGR) that + * has to be deasserted before their co-processor can be booted. On + * t8103 each port comes with a dedicated register page while t600x + * uses a single register shared by all ports of a die inside the PMGR + * MMIO region. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define APPLE_CIO_RESET_POLL_US 100 +#define APPLE_CIO_RESET_TIMEOUT_US 100000 + +#define T8103_CIO_CTRL_STRIDE 0x4000 +#define T8103_CIO_CTRL_INIT_REQ BIT(0) +#define T8103_CIO_CTRL_INIT_DONE BIT(2) + +#define T6000_CIO_CTRL_INIT_REQ(port) BIT(port) +#define T6000_CIO_CTRL_INIT_BUSY(port) BIT(16 + (port)) + +struct apple_cio_reset; + +struct apple_cio_reset_variant { + unsigned int nr_resets; + bool pmgr_child; + int (*deassert)(struct apple_cio_reset *priv, unsigned long id); +}; + +struct apple_cio_reset { + struct reset_controller_dev rcdev; + const struct apple_cio_reset_variant *variant; + struct regmap *regmap; + u32 offset; + struct mutex lock; /* serializes access to the shared t600x register */ +}; + +static int t8103_cio_deassert(struct apple_cio_reset *priv, unsigned long = id) +{ + u32 offset =3D priv->offset + id * T8103_CIO_CTRL_STRIDE; + u32 val; + int ret; + + ret =3D regmap_write(priv->regmap, offset, T8103_CIO_CTRL_INIT_REQ); + if (ret) + return ret; + + return regmap_read_poll_timeout(priv->regmap, offset, val, + val =3D=3D T8103_CIO_CTRL_INIT_DONE, + APPLE_CIO_RESET_POLL_US, + APPLE_CIO_RESET_TIMEOUT_US); +} + +static int t6000_cio_deassert(struct apple_cio_reset *priv, unsigned long = id) +{ + u32 val; + int ret; + + guard(mutex)(&priv->lock); + + ret =3D regmap_write(priv->regmap, priv->offset, T6000_CIO_CTRL_INIT_REQ(= id)); + if (ret) + return ret; + + return regmap_read_poll_timeout(priv->regmap, priv->offset, val, + !(val & T6000_CIO_CTRL_INIT_BUSY(id)), + APPLE_CIO_RESET_POLL_US, + APPLE_CIO_RESET_TIMEOUT_US); +} + +static const struct apple_cio_reset_variant apple_t8103_cio_reset =3D { + .nr_resets =3D 2, + .deassert =3D t8103_cio_deassert, +}; + +static const struct apple_cio_reset_variant apple_t6000_cio_reset =3D { + .nr_resets =3D 4, + .pmgr_child =3D true, + .deassert =3D t6000_cio_deassert, +}; + +static int apple_cio_reset_deassert(struct reset_controller_dev *rcdev, un= signed long id) +{ + struct apple_cio_reset *priv =3D + container_of(rcdev, struct apple_cio_reset, rcdev); + + return priv->variant->deassert(priv, id); +} + +static const struct reset_control_ops apple_cio_reset_ops =3D { + .deassert =3D apple_cio_reset_deassert, +}; + +static const struct regmap_config apple_cio_reset_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, +}; + +static int apple_cio_reset_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct apple_cio_reset *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->variant =3D of_device_get_match_data(dev); + + ret =3D devm_mutex_init(dev, &priv->lock); + if (ret) + return ret; + + if (priv->variant->pmgr_child) { + priv->regmap =3D syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(priv->regmap)) + return dev_err_probe(dev, PTR_ERR(priv->regmap), + "Failed to get parent regmap"); + + ret =3D of_property_read_u32(dev->of_node, "reg", &priv->offset); + if (ret) + return dev_err_probe(dev, ret, "Failed to read reg offset"); + } else { + void __iomem *base; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->regmap =3D devm_regmap_init_mmio(dev, base, + &apple_cio_reset_regmap_config); + if (IS_ERR(priv->regmap)) + return dev_err_probe(dev, PTR_ERR(priv->regmap), + "Failed to init MMIO regmap"); + } + + priv->rcdev.owner =3D THIS_MODULE; + priv->rcdev.ops =3D &apple_cio_reset_ops; + priv->rcdev.of_node =3D dev->of_node; + priv->rcdev.nr_resets =3D priv->variant->nr_resets; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + +static const struct of_device_id apple_cio_reset_match[] =3D { + { + .compatible =3D "apple,t8103-cio-reset", + .data =3D &apple_t8103_cio_reset, + }, + { + .compatible =3D "apple,t6000-cio-reset", + .data =3D &apple_t6000_cio_reset, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, apple_cio_reset_match); + +static struct platform_driver apple_cio_reset_driver =3D { + .driver =3D { + .name =3D "apple-cio-reset", + .of_match_table =3D apple_cio_reset_match, + }, + .probe =3D apple_cio_reset_probe, +}; +module_platform_driver(apple_cio_reset_driver); + +MODULE_AUTHOR("Sven Peter "); +MODULE_DESCRIPTION("Apple SoC CIO block reset driver"); +MODULE_LICENSE("Dual MIT/GPL"); --=20 2.55.0 From nobody Tue Sep 29 09:46:28 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68EE535CB8C; Sun, 9 Aug 2026 12:16:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786277772; cv=none; b=QqwiyuHDkCXyW4GsL6/m8gPNIoXM/XTc90q208NVJmPYOnXj9oZYNO/Ul4DR5MLnRYyBAOJMzqau158A6iJtlMyq4CE8jtiTMyJlSxFKArDi6JT00+MbzTAx3vjr2zmGWfhvGUcDLMqiVN65bJNWU8HIW+JTnSaIwCzlSG1lMDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786277772; c=relaxed/simple; bh=NH6TxVvsxwG75iXqtfI7vYJQq5MjARznwzgt/dgex4E=; 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Sun, 9 Aug 2026 12:16:12 +0000 (UTC) From: Sven Peter Date: Sun, 09 Aug 2026 14:16:04 +0200 Subject: [PATCH 3/3] arm64: dts: apple: Add CIO reset controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260809-b4-cio-reset-v1-3-4f33777d9b4b@kernel.org> References: <20260809-b4-cio-reset-v1-0-4f33777d9b4b@kernel.org> In-Reply-To: <20260809-b4-cio-reset-v1-0-4f33777d9b4b@kernel.org> To: Sven Peter , Janne Grunau , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3435; i=sven@kernel.org; h=from:subject:message-id; bh=NH6TxVvsxwG75iXqtfI7vYJQq5MjARznwzgt/dgex4E=; b=owGbwMvMwCXmIlirolUq95LxtFoSQ1ZFfuf8M/GOXStUPf7xTJV6Xv1L2Gz2hkttvBvPHQnUl kr2Pnmqo5SFQYyLQVZMkWX7fnvTJw/fCC7ddOk9zBxWJpAhDFycAjARzpkM/93P+8R8St/2oIRF dMK7N96qfXsv6NWf1Hc1b1GUj7vI9pWR4eeFe8zFPYmqt5ecE42PkP12sHxFTVXIKe6enNl3VSe osgMA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Add the reset controllers used to start the CIO (USB4/Thunderbolt) blocks on t8103 and t600x. On t8103 each port comes with a dedicated register page represented as a standalone node. On t600x a single register shared by all ports of a die is located in the middle of the PMGR MMIO region and represented as a sub-node of its syscon. Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-dieX.dtsi | 8 +++++++- arch/arm64/boot/dts/apple/t602x-dieX.dtsi | 8 +++++++- arch/arm64/boot/dts/apple/t8103.dtsi | 6 ++++++ arch/arm64/boot/dts/apple/t8112.dtsi | 6 ++++++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi b/arch/arm64/boot/dt= s/apple/t600x-dieX.dtsi index 9676d5127039..5e163d756a7f 100644 --- a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi @@ -28,7 +28,13 @@ DIE_NODE(pmgr): power-management@28e080000 { compatible =3D "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells =3D <1>; #size-cells =3D <1>; - reg =3D <0x2 0x8e080000 0 0x4000>; + reg =3D <0x2 0x8e080000 0 0x1c000>; + + DIE_NODE(cio_reset): reset-controller@1a034 { + compatible =3D "apple,t6000-cio-reset"; + reg =3D <0x1a034 0x4>; + #reset-cells =3D <1>; + }; }; =20 DIE_NODE(pmgr_east): power-management@28e580000 { diff --git a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi b/arch/arm64/boot/dt= s/apple/t602x-dieX.dtsi index ae3d535c5acb..fd4d572a04e7 100644 --- a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi +++ b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi @@ -27,7 +27,13 @@ DIE_NODE(pmgr): power-management@28e080000 { compatible =3D "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple= -mfd"; #address-cells =3D <1>; #size-cells =3D <1>; - reg =3D <0x2 0x8e080000 0 0x8000>; + reg =3D <0x2 0x8e080000 0 0xc000>; + + DIE_NODE(cio_reset): reset-controller@a02c { + compatible =3D "apple,t6020-cio-reset", "apple,t6000-cio-reset"; + reg =3D <0xa02c 0x4>; + #reset-cells =3D <1>; + }; }; =20 DIE_NODE(pmgr_south): power-management@28e680000 { diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index da774096b667..83f6f1003424 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -730,6 +730,12 @@ pmgr: power-management@23b700000 { reg =3D <0x2 0x3b700000 0 0x14000>; }; =20 + cio_reset: reset-controller@23b784000 { + compatible =3D "apple,t8103-cio-reset"; + reg =3D <0x2 0x3b784000 0x0 0x8000>; + #reset-cells =3D <1>; + }; + pinctrl_ap: pinctrl@23c100000 { compatible =3D "apple,t8103-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x3c100000 0x0 0x100000>; diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/app= le/t8112.dtsi index 85c47422d4e8..d0637c0384b2 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -737,6 +737,12 @@ pmgr: power-management@23b700000 { /* child nodes are added in t8103-pmgr.dtsi */ }; =20 + cio_reset: reset-controller@23b784000 { + compatible =3D "apple,t8112-cio-reset", "apple,t8103-cio-reset"; + reg =3D <0x2 0x3b784000 0x0 0x8000>; + #reset-cells =3D <1>; + }; + pinctrl_ap: pinctrl@23c100000 { compatible =3D "apple,t8112-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x3c100000 0x0 0x100000>; --=20 2.55.0