From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A1B2415F1E; Sat, 8 Aug 2026 12:44:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786193076; cv=none; b=OO9EcJjqXa65Bc37ZGyyxExu68hL/fSW8LYWIUT9/StnmbGasnKT4ajkGTrHC2+j4Qn+fQ0xHVj8LamXX59W3UFgMGiCopL+T9kZdqy8oY2tf9oSJsnMAnHbRWSkRqVW7svoccrQ61G7M1lbIwrCubJMBQacCEv8szZkd3Uw7jo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786193076; c=relaxed/simple; bh=LAyGolb0cHspUqjIQr3siyEE9NWXtxPLUKsXa7w4Als=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WBsmJ9dllt+HWDzzfQyg6r07t7x0/fUy3S888BZjZg/OVqrYn9pHjqg/zrHqnGuCistdlqAf0LsCk3sryrCgnvhJu44AC3DtS/Xajl0ixs/1lIx6PSqLNJ3Hozw0X/dW+rdX7pCry59mam4KrNYY325lGryz3eAS7YRbiwtVni4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hHKvB2GHpzKHNC1; Sat, 8 Aug 2026 20:24:06 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 6A73F4070E; Sat, 8 Aug 2026 20:24:17 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S3; Sat, 08 Aug 2026 20:24:17 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 01/23] perf capstone: Fix arm64 jump/adrp disassembly mismatch with objdump Date: Sat, 8 Aug 2026 12:23:38 +0000 Message-Id: <20260808122400.2961238-2-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S3 X-Coremail-Antispam: 1UD129KBjvJXoWxtF4rKFyrWF17Kw4kJF4xWFg_yoWxur1rpa 1DC345Jan5XF1fWw1fJa1kXw1ak3yfJr1Yk3y7K39akFnIkrn3XFWxKFya9Fn8GrykWw42 qFs0kr15Wrs3JrJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQlb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUGw A2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV W8JVWxJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx 0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWU JVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxV A2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wrylc7CjxVAKzI0EY4vE52x082I5MxAIw28I cxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2 IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI 42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42 IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280 aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7sRNNVy3UUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The jump and adrp instructions parsed by libcapstone currently lack symbolic representation and use a '#' prefix for addresses. This format is inconsistent with objdump's output, which causes subsequent parsing in jump__parse() and arm64_mov__parse() to fail. Example mismatch: Current: b #0xffff8000800114c8 Fix: b ffff8000800114c8 Current: adrp x18, #0xffff800081f5f000 Fix: adrp x18, ffff800081f5f000 Fix this by implementing extended formatting for these arm64 instructions during symbol__disassemble_capstone(). This ensures the output matches objdump's expected style, including the raw address and the associated suffix. Signed-off-by: Tengda Wu --- tools/perf/util/capstone.c | 136 +++++++++++++++++++++++++++++++++---- tools/perf/util/disasm.c | 5 ++ tools/perf/util/disasm.h | 1 + 3 files changed, 130 insertions(+), 12 deletions(-) diff --git a/tools/perf/util/capstone.c b/tools/perf/util/capstone.c index 74213daf8786..fb8a2bc5558f 100644 --- a/tools/perf/util/capstone.c +++ b/tools/perf/util/capstone.c @@ -3,6 +3,7 @@ =20 #include #include +#include #include =20 #include @@ -31,6 +32,10 @@ #define CS_MODE_RISCVC 4 #endif =20 +#if CS_VERSION_MAJOR < 4 +#define ARM64_GRP_BRANCH_RELATIVE 7 +#endif + #ifdef LIBCAPSTONE_DLOPEN static void *perf_cs_dll_handle(void) { @@ -225,6 +230,12 @@ static int capstone_init(uint16_t e_machine, csh *cs_h= andle, bool is64, bool is_ * on x86 by investigating instruction details. */ perf_cs_option(*cs_handle, CS_OPT_DETAIL, CS_OPT_ON); + } else if (arch =3D=3D CS_ARCH_ARM64) { + /* + * Same as x86: arm64 needs instruction details to resolve + * symbolic addresses. + */ + perf_cs_option(*cs_handle, CS_OPT_DETAIL, CS_OPT_ON); } =20 return 0; @@ -299,10 +310,6 @@ static void print_capstone_detail(struct cs_insn *insn= , char *buf, size_t len, struct map *map =3D args->ms->map; struct symbol *sym; =20 - /* TODO: support more architectures */ - if (!arch__is_x86(args->arch)) - return; - if (insn->detail =3D=3D NULL) return; =20 @@ -354,6 +361,116 @@ static void print_capstone_detail(struct cs_insn *ins= n, char *buf, size_t len, } } =20 +static int print_default_format(struct cs_insn *insn, char *buf, size_t le= n) +{ + return scnprintf(buf, len, " %-7s %s", + insn->mnemonic, insn->op_str); +} + +static void format_capstone_insn_x86(struct cs_insn *insn, char *buf, + size_t len, struct annotate_args *args, + u64 addr) +{ + int printed; + + printed =3D print_default_format(insn, buf, len); + buf +=3D printed; + len -=3D printed; + + print_capstone_detail(insn, buf, len, args, addr); +} + +static bool is_pc_relative_insn(struct cs_insn *insn) +{ + int i; + + if (insn->id =3D=3D ARM64_INS_ADR || insn->id =3D=3D ARM64_INS_ADRP) + return true; + + if (insn->detail =3D=3D NULL) + return false; + + for (i =3D 0; i < insn->detail->groups_count; i++) { + if (insn->detail->groups[i] =3D=3D ARM64_GRP_JUMP || + insn->detail->groups[i] =3D=3D ARM64_GRP_CALL || + insn->detail->groups[i] =3D=3D ARM64_GRP_BRANCH_RELATIVE) + return true; + } + + return false; +} + +static void format_capstone_insn_arm64(struct cs_insn *insn, char *buf, + size_t len, struct annotate_args *args) +{ + struct map *map =3D args->ms->map; + struct symbol *sym; + char *last_imm, *endptr; + u64 orig_addr, addr; + struct map *found_map =3D NULL; + + print_default_format(insn, buf, len); + /* + * Adjust instructions to keep the existing behavior with objdump. + * + * Example conversion: + * From: b #0xffff8000800114c8 + * To: b ffff8000800114c8 + */ + if (is_pc_relative_insn(insn)) { + /* Extract last immediate value as address */ + last_imm =3D strrchr(buf, '#'); + if (!last_imm) + return; + + orig_addr =3D strtoull(last_imm + 1, &endptr, 16); + if (endptr =3D=3D last_imm + 1) + return; + + addr =3D map__objdump_2mem(map, orig_addr); + + /* Relocate map that contains the address */ + if (dso__kernel(map__dso(map))) { + found_map =3D maps__find(map__kmaps(map), addr); + if (found_map =3D=3D NULL) + return; + map =3D found_map; + } + + /* Convert it to map-relative address for search */ + addr =3D map__map_ip(map, addr); + + sym =3D map__find_symbol(map, addr); + if (sym =3D=3D NULL) { + map__put(found_map); + return; + } + + /* Symbolize the resolved address */ + len =3D len - (last_imm - buf); + if (addr =3D=3D sym->start) { + scnprintf(last_imm, len, "%"PRIx64" <%s>", + orig_addr, sym->name); + } else { + scnprintf(last_imm, len, "%"PRIx64" <%s+%#"PRIx64">", + orig_addr, sym->name, addr - sym->start); + } + map__put(found_map); + } +} + +static void format_capstone_insn(struct cs_insn *insn, char *buf, size_t l= en, + struct annotate_args *args, u64 addr) +{ + /* TODO: support more architectures */ + if (arch__is_x86(args->arch)) + format_capstone_insn_x86(insn, buf, len, args, addr); + else if (arch__is_arm64(args->arch)) + format_capstone_insn_arm64(insn, buf, len, args); + else + print_default_format(insn, buf, len); +} + struct find_file_offset_data { u64 ip; u64 offset; @@ -446,14 +563,9 @@ int symbol__disassemble_capstone(const char *filename,= struct symbol *sym, =20 free_count =3D count =3D perf_cs_disasm(handle, buf, buf_len, start, buf_= len, &insn); for (i =3D 0, offset =3D 0; i < count; i++) { - int printed; - - printed =3D scnprintf(disasm_buf, sizeof(disasm_buf), - " %-7s %s", - insn[i].mnemonic, insn[i].op_str); - print_capstone_detail(&insn[i], disasm_buf + printed, - sizeof(disasm_buf) - printed, args, - start + offset); + format_capstone_insn(&insn[i], disasm_buf, + sizeof(disasm_buf), args, + start + offset); =20 args->offset =3D offset; args->line =3D disasm_buf; diff --git a/tools/perf/util/disasm.c b/tools/perf/util/disasm.c index 6cfdbabbb8c7..0ba38f70fe1a 100644 --- a/tools/perf/util/disasm.c +++ b/tools/perf/util/disasm.c @@ -203,6 +203,11 @@ bool arch__is_powerpc(const struct arch *arch) return arch->id.e_machine =3D=3D EM_PPC || arch->id.e_machine =3D=3D EM_P= PC64; } =20 +bool arch__is_arm64(const struct arch *arch) +{ + return arch->id.e_machine =3D=3D EM_AARCH64; +} + static void ins_ops__delete(struct ins_operands *ops) { if (ops =3D=3D NULL) diff --git a/tools/perf/util/disasm.h b/tools/perf/util/disasm.h index 25756e3f47e4..06c664fd4fc2 100644 --- a/tools/perf/util/disasm.h +++ b/tools/perf/util/disasm.h @@ -111,6 +111,7 @@ struct annotate_args { const struct arch *arch__find(uint16_t e_machine, uint32_t e_flags, const = char *cpuid); bool arch__is_x86(const struct arch *arch); bool arch__is_powerpc(const struct arch *arch); +bool arch__is_arm64(const struct arch *arch); =20 extern const struct ins_ops call_ops; extern const struct ins_ops dec_ops; --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77830414A21; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hHKvB2l5czKHMnt; Sat, 8 Aug 2026 20:24:06 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 7E4E240571; Sat, 8 Aug 2026 20:24:17 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S4; Sat, 08 Aug 2026 20:24:17 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 02/23] perf llvm: Fix arm64 adrp instruction disassembly mismatch with objdump Date: Sat, 8 Aug 2026 12:23:39 +0000 Message-Id: <20260808122400.2961238-3-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S4 X-Coremail-Antispam: 1UD129KBjvJXoWxWryxGr4xuw48Zr4xCFykKrg_yoW5ZF4fpr ZFka95Jry5Ar1fZ39IkF47WFn0yrZ2gF45K3y3ArWvkr4ftFyxC34xGry29F1DXryqq3y5 ArZIvFyUGF4kArJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUXw A2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV WxJVW8Jr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v2 6rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMc Ij6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_ Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I 0E8cxan2IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8Ij28IcwCF04k2 0xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI 8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41l IxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMI IF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E 87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRQL00DUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The operands of 'adrp' instructions parsed by libllvm are currently represented as raw immediates rather than the "address " format used by objdump. This inconsistency causes arm64_mov__parse() to fail when parsing these instructions during post-processing. Example of the mismatch: Current: adrp x18, 8014 Fix: adrp x18, ffff800081f5f000 Fix this by manually extracting the target address from the raw adrp instruction via symbol_lookup_callback(). The address is then converted to a specific symbol during symbol__disassemble_llvm() and formatted to match objdump's output, ensuring compatibility with existing parsers. Signed-off-by: Tengda Wu --- tools/perf/util/llvm.c | 50 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 4 deletions(-) diff --git a/tools/perf/util/llvm.c b/tools/perf/util/llvm.c index a0deb742a733..6b53b283205a 100644 --- a/tools/perf/util/llvm.c +++ b/tools/perf/util/llvm.c @@ -9,8 +9,10 @@ #include "symbol.h" #include #include +#include #include #include +#include =20 #ifdef HAVE_LIBLLVM_SUPPORT #include "llvm-c-helpers.h" @@ -108,6 +110,16 @@ symbol_lookup_callback(void *disinfo, uint64_t value, storage->branch_addr =3D value; else if (*ref_type =3D=3D LLVMDisassembler_ReferenceType_In_PCrel_Load) storage->pcrel_load_addr =3D value; + else if (*ref_type =3D=3D LLVMDisassembler_ReferenceType_In_ARM64_ADRP) { + uint64_t adrp_imm; + + /* immhi (bits 23:5) and immlo (bits 30:29) */ + adrp_imm =3D ((value & 0x00ffffe0) >> 3) | ((value >> 29) & 0x3); + adrp_imm =3D sign_extend64(adrp_imm, 20); + + /* Calculate the target page address */ + storage->pcrel_load_addr =3D (address & ~0xfffULL) + (adrp_imm << 12); + } *ref_type =3D LLVMDisassembler_ReferenceType_InOut_None; return NULL; } @@ -230,10 +242,40 @@ int symbol__disassemble_llvm(const char *filename, st= ruct symbol *sym, if (storage.pcrel_load_addr !=3D 0) { char *name =3D llvm_name_for_data(dso, filename, storage.pcrel_load_addr); - disasm_len +=3D scnprintf(disasm_buf + disasm_len, - sizeof(disasm_buf) - disasm_len, - " # %#"PRIx64, - storage.pcrel_load_addr); + + if (arch__is_arm64(args->arch)) { + /* + * For arm64, replace the immediate operand with + * the resolved address to match objdump's output. + * + * Example conversion: + * From: adrp x18, 8014 + * To: adrp x18, ffff800081f5f000 + */ + char *s =3D strchr(disasm_buf, ','); + + if (s =3D=3D NULL) + goto err; + + s++; + *s =3D '\0'; + disasm_len =3D strlen(disasm_buf); + disasm_len +=3D scnprintf(disasm_buf + disasm_len, + sizeof(disasm_buf) - disasm_len, + " %"PRIx64, + storage.pcrel_load_addr); + } else { + /* + * For other archs, append the resolved address + * as an inline comment. + */ + disasm_len +=3D scnprintf(disasm_buf + disasm_len, + sizeof(disasm_buf) - disasm_len, + " # %#"PRIx64, + storage.pcrel_load_addr); + } + + /* Append the resolved symbol name if available */ if (name) { disasm_len +=3D scnprintf(disasm_buf + disasm_len, sizeof(disasm_buf) - --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27E10415F10; Sat, 8 Aug 2026 12:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786193075; cv=none; b=Af62l7mN6eekkqUcePpqffv07OMNlt0EY1o0qWkpiEH18KyyRzuwipJW6mq3e9XlGjWbPsAzFeviAcgW5z3+04pbR7BJiso2JRzj0rsMXbSln54JF0fuVstKnF8qrLnG/k+JgiaT0E3UzKINfWmE40yTDEK3xqp6l6xG/YYQssM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786193075; c=relaxed/simple; bh=2t/lgFs7dstmsFZe9SrXwhZcVoED4djv8SoL4fOhc8o=; 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Sat, 08 Aug 2026 20:24:17 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 03/23] perf annotate-arm64: Generalize arm64_mov__parse to support more instructions Date: Sat, 8 Aug 2026 12:23:40 +0000 Message-Id: <20260808122400.2961238-4-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S5 X-Coremail-Antispam: 1UD129KBjvJXoWxtr1xurWxCw4DZF18Xw45trb_yoW7Crykpa n2k34rtr4rGryFgws3Jr1vvrn3Ww4Ig343Ca40qas3AwsakryrKanakF1akF4rGFyxuFWU tFnYyr1rGrWDJaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQCb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUWw A2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV WxJVW8Jr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v2 6rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMc Ij6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_ Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I 0E8cxan2IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8Ij28IcwCF04k2 0xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI 8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41l IxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMI IF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E 87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRHpBaDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" As the default parser for arm64 instructions, arm64_mov__parse() currently only supports parsing instructions with the 'addr ' suffix. Other instructions are not supported, causing a lack of source and target information for most regular instructions. Generalize arm64_mov__parse to extend its parsing capabilities: 1. Parse 'ops->target.raw' and 'ops->source.raw' by default. 2. Utilize arm64__check_multi_regs() to identify if source and target contain multiple registers. 3. Maintain backward compatibility for instructions containing the 'addr ' suffix. Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 158 ++++++++++++++---- 1 file changed, 126 insertions(+), 32 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 33080fdca125..5e824fd617ee 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -3,6 +3,8 @@ #include #include #include +#include +#include #include #include #include "../annotate.h" @@ -14,59 +16,151 @@ struct arch_arm64 { regex_t jump_insn; }; =20 -static int arm64_mov__parse(const struct arch *arch __maybe_unused, +static bool arm64__is_reg(const char *op) +{ + if (!op || !*op) + return false; + + /* + * General-purpose registers: x0-x30, w0-w30. + * Check for 'x' or 'w' prefix followed by a numeric index. + */ + if ((op[0] =3D=3D 'x' || op[0] =3D=3D 'w') && isdigit(op[1])) + return true; + + /* Special-purpose registers: sp. */ + if (!strncmp(op, "sp", 2)) + return true; + + /* TODO: Support more registers. */ + return false; +} + +static bool arm64__check_multi_regs(const struct arch *arch, const char *o= p) +{ + const char *p =3D op; + int reg_count =3D 0; + + while (p && *p) { + p =3D skip_spaces(p); + if (*p =3D=3D arch->objdump.memory_ref_char) + p++; + + if (arm64__is_reg(p)) + reg_count++; + + if (reg_count >=3D 2) + return true; + + /* Move to next operand after comma */ + p =3D strchr(p, ','); + if (p) + p++; + } + + return false; +} + +/* + * Duplicate @insn, stripping the comment and trailing whitespace. + * Returns a newly allocated string which the caller must free(), + * or NULL on allocation failure or if @insn is NULL. + */ +static char *rstrip_space_and_comment(const char *insn, char comment_char) +{ + const char *end, *comment; + size_t len; + char *result; + + if (insn =3D=3D NULL) + return NULL; + + comment =3D strchr(insn, comment_char); + if (comment !=3D NULL) + end =3D comment; + else + end =3D insn + strlen(insn); + + while (end > insn && isspace(end[-1])) + --end; + + len =3D end - insn; + result =3D malloc(len + 1); + if (result =3D=3D NULL) + return NULL; + + memcpy(result, insn, len); + result[len] =3D '\0'; + + return result; +} + +static int arm64_mov__parse(const struct arch *arch, struct ins_operands *ops, struct map_symbol *ms __maybe_unused, struct disasm_line *dl __maybe_unused) { - char *s =3D strchr(ops->raw, ','), *target, *endptr; + char *s =3D strchr(ops->raw, ','), *source, *endptr; =20 if (s =3D=3D NULL) return -1; =20 + /* Parse target */ *s =3D '\0'; - ops->source.raw =3D strdup(ops->raw); + ops->target.raw =3D strdup(ops->raw); *s =3D ','; =20 - if (ops->source.raw =3D=3D NULL) - return -1; - - target =3D ++s; - ops->target.raw =3D strdup(target); if (ops->target.raw =3D=3D NULL) - goto out_free_source; + return -1; =20 - ops->target.addr =3D strtoull(target, &endptr, 16); - if (endptr =3D=3D target) - goto out_free_target; + ops->target.multi_regs =3D arm64__check_multi_regs(arch, ops->target.raw); =20 - s =3D strchr(endptr, '<'); - if (s =3D=3D NULL) - goto out_free_target; - endptr =3D strchr(s + 1, '>'); - if (endptr =3D=3D NULL) - goto out_free_target; - - *endptr =3D '\0'; - *s =3D ' '; - ops->target.name =3D strdup(s); - *s =3D '<'; - *endptr =3D '>'; - if (ops->target.name =3D=3D NULL) - goto out_free_target; + /* Parse source, stripping comment if present */ + source =3D skip_spaces(++s); + ops->source.raw =3D rstrip_space_and_comment(source, arch->objdump.commen= t_char); + if (ops->source.raw =3D=3D NULL) { + zfree(&ops->target.raw); + return -1; + } + + ops->source.multi_regs =3D arm64__check_multi_regs(arch, ops->source.raw); + + /* Parse 'addr ' from source (if any) */ + ops->source.addr =3D strtoull(ops->source.raw, &endptr, 16); + if (endptr !=3D ops->source.raw) { + s =3D strchr(endptr, '<'); + if (s =3D=3D NULL) { + ops->source.addr =3D 0; + return 0; + } + endptr =3D strrchr(s + 1, '>'); + if (endptr =3D=3D NULL) { + ops->source.addr =3D 0; + return 0; + } + + *endptr =3D '\0'; + ops->source.name =3D strdup(s + 1); + *endptr =3D '>'; + if (ops->source.name =3D=3D NULL) { + ops->source.addr =3D 0; + return 0; + } + } =20 return 0; +} =20 -out_free_target: - zfree(&ops->target.raw); -out_free_source: - zfree(&ops->source.raw); - return -1; +static int arm64_mov__scnprintf(const struct ins *ins, char *bf, size_t si= ze, + struct ins_operands *ops, int max_ins_name) +{ + return scnprintf(bf, size, "%-*s %s, %s", max_ins_name, ins->name, + ops->target.raw, ops->source.name ?: ops->source.raw); } =20 static const struct ins_ops arm64_mov_ops =3D { .parse =3D arm64_mov__parse, - .scnprintf =3D mov__scnprintf, + .scnprintf =3D arm64_mov__scnprintf, }; =20 static const struct ins_ops *arm64__associate_instruction_ops(struct arch = *arch, const char *name) --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 325AA3CCA15; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hHKtH3rr7zYQvbt; Sat, 8 Aug 2026 20:23:19 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id B2EE6408D6; Sat, 8 Aug 2026 20:24:17 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S6; Sat, 08 Aug 2026 20:24:17 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 04/23] perf annotate-arm64: Handle load and store instructions Date: Sat, 8 Aug 2026 12:23:41 +0000 Message-Id: <20260808122400.2961238-5-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S6 X-Coremail-Antispam: 1UD129KBjvJXoW3XF4rXr1xXFyxGF4DKr17Wrg_yoW7uF18pa s2k345tr42qr4rW3Z3JF4kXw1fGa18Jw43KryxJwn3C3yY9ry8tFn5Kw12kF45Gr95uw4a qFn0yry0vF98A3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Add ldst_ops to handle load and store instructions in order to parse the data types and offsets associated with PMU events for memory access instructions. There are many variants of load and store instructions in arm64, making it difficult to match all of these instruction names completely. Therefore, only the instruction prefixes are matched. The prefix 'ld|st' covers most of the memory access instructions, 'cas|swp' matches atomic instructions, and 'prf' matches memory prefetch instructions. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 5e824fd617ee..32752a3bc756 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -14,6 +14,7 @@ struct arch_arm64 { struct arch arch; regex_t call_insn; regex_t jump_insn; + regex_t ldst_insn; /* load and store instruction */ }; =20 static bool arm64__is_reg(const char *op) @@ -163,6 +164,108 @@ static const struct ins_ops arm64_mov_ops =3D { .scnprintf =3D arm64_mov__scnprintf, }; =20 +static bool arm64__insn_is_source_on_left(struct disasm_line *dl) +{ + /* + * Store instructions invert the standard syntax by placing the source + * register before the destination memory address. + */ + return !strncmp(dl->ins.name, "st", 2); +} + +/* + * This function is used to parse arm64 load/store instructions into + * instruction operands. + * + * Typical instructions and their parsing logic: + * + * 1. Immediate offset: + * ldr x2, [x0] -> target=3D"x2", source=3D"[x0]" + * ldr x2, [x0, #24] -> target=3D"x2", source=3D"[x0, #24]" + * ldp x19, x20, [sp, #16] -> target=3D"x19, x20", source=3D"[sp,= #16]" + * + * 2. Pre-index addressing: + * stp x29, x30, [sp, #-64]! -> target=3D"[sp, #-64]!", source=3D"x= 29, x30" + * + * 3. Post-index addressing: + * str x1, [x0], #8 -> target=3D"[x0], #8", source=3D"x1" + * ldr w1, [x21], #4 -> target=3D"w1", source=3D"[x21], #4" + * ldp x29, x30, [sp], #32 -> target=3D"x29, x30", source=3D"[sp]= , #32" + * + * 4. Register offset / extension: + * ldr x0, [x1, w0, sxtw #3] -> target=3D"x0", source=3D"[x1, w0, s= xtw #3]" + * ldr x0, [x1, x0, lsl #3] -> target=3D"x0", source=3D"[x1, x0, l= sl #3]" + * + * 5. Atomic operations: + * cas w3, w1, [x0] -> target=3D"w3, w1", source=3D"[x0]" + * swp x3, x0, [x2] -> target=3D"x3, x0", source=3D"[x2]" + * + * 6. Prefetch memory: + * prfm pstl1strm, [x4] -> target=3D"pstl1strm", source=3D"[x4= ]" + * + * 7. PC-relative loads (No bracket found): + * ldr x0, ffff800080f40c68 <__kvm_nvhe_$d> -> Fallback to default p= arser + * + * Parsing strategy: + * Use the '[' bracket as the boundary to split the operands into left + * and right sides. For non-store instructions, the left side is the + * target and the right side is the source. For store instructions, the + * roles are reversed. + */ +static int arm64_ldst__parse(const struct arch *arch, + struct ins_operands *ops, + struct map_symbol *ms, + struct disasm_line *dl) +{ + char *s, *left, *right; + + right =3D s =3D strchr(ops->raw, arch->objdump.memory_ref_char); + if (!s) { + /* Fallback to default parser for PC-relative loads. */ + return arm64_mov__parse(arch, ops, ms, dl); + } + + while (s > ops->raw && *s !=3D ',') + --s; + + if (s =3D=3D ops->raw) + return -1; + + *s =3D '\0'; + left =3D strdup(ops->raw); + + *s =3D ','; + if (!left) + return -1; + + right =3D rstrip_space_and_comment(right, arch->objdump.comment_char); + if (!right) { + zfree(&left); + return -1; + } + + if (arm64__insn_is_source_on_left(dl)) { + ops->source.raw =3D left; + ops->source.mem_ref =3D false; + ops->target.raw =3D right; + ops->target.mem_ref =3D true; + } else { + ops->source.raw =3D right; + ops->source.mem_ref =3D true; + ops->target.raw =3D left; + ops->target.mem_ref =3D false; + } + + ops->source.multi_regs =3D arm64__check_multi_regs(arch, ops->source.raw); + ops->target.multi_regs =3D arm64__check_multi_regs(arch, ops->target.raw); + + return 0; +} + +static struct ins_ops arm64_ldst_ops =3D { + .parse =3D arm64_ldst__parse, +}; + static const struct ins_ops *arm64__associate_instruction_ops(struct arch = *arch, const char *name) { struct arch_arm64 *arm =3D container_of(arch, struct arch_arm64, arch); @@ -173,6 +276,8 @@ static const struct ins_ops *arm64__associate_instructi= on_ops(struct arch *arch, ops =3D &jump_ops; else if (!regexec(&arm->call_insn, name, 2, match, 0)) ops =3D &call_ops; + else if (!regexec(&arm->ldst_insn, name, 2, match, 0)) + ops =3D &arm64_ldst_ops; else if (!strcmp(name, "ret")) ops =3D &ret_ops; else @@ -197,6 +302,8 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->id =3D *id; arch->objdump.comment_char =3D '/'; arch->objdump.skip_functions_char =3D '+'; + arch->objdump.memory_ref_char =3D '['; + arch->objdump.imm_char =3D '#'; arch->associate_instruction_ops =3D arm64__associate_instruction_ops; =20 /* bl, blr */ @@ -210,8 +317,20 @@ const struct arch *arch__new_arm64(const struct e_mach= ine_and_e_flags *id, if (err) goto out_free_call; =20 + /* + * The ARM64 architecture has many variants of load/store instructions. + * It is quite challenging to match all of them completely. Here, we + * only match the prefixes of these instructions. + */ + err =3D regcomp(&arm->ldst_insn, "^(ld|st|cas|prf|swp)", + REG_EXTENDED); + if (err) + goto out_free_jump; + return arch; =20 +out_free_jump: + regfree(&arm->jump_insn); out_free_call: regfree(&arm->call_insn); out_free_arm: --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 324593C4167; Sat, 8 Aug 2026 12:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786191869; cv=none; b=iHLSdaP4D5Wo0yL4Maln+It8Eg4mjbZ6w6qn02jhyY9nX4jVOLSFm8whBKQ7NEpiWH99yjPOAn5VrM/v7mgYjq0tq+thmlMaQdYrHuxfe0r8IDeqL1e3SqOc0OLemyapQHrACySKFmaon5C5rk+IGg4bV6PaffrH0/w0AzfUpKU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786191869; c=relaxed/simple; bh=V1/lLQAcdtn+hDCtPPbyRi2VQXlV/Q7PaQaL7rKvNq8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TWkVZn4WfulXk6b/GsflmBJCHDQ/K3tf6nflHV4a7FCG4w+2ivPvZvJxygbD6RcCv4TJ3FbQWSN8G6WwA/qzcBZ1SH8KfqnBYs27K24SbC17YEP/PLLJvmOmO6yYMvCOKyAuH5jAETCku8x4KEKhzdfcZaR5O7iSEonl/6Mj/Bk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hHKtH4hcMzYQvgS; Sat, 8 Aug 2026 20:23:19 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id CDE65408E1; Sat, 8 Aug 2026 20:24:17 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S7; Sat, 08 Aug 2026 20:24:17 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 05/23] perf dwarf-regs: Adapt get_dwarf_regnum() for arm64 Date: Sat, 8 Aug 2026 12:23:42 +0000 Message-Id: <20260808122400.2961238-6-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S7 X-Coremail-Antispam: 1UD129KBjvJXoWxAFyxGrW7tFy3Xw1UCry7trb_yoW5Cw48pF srC347Jw4UW3WakwnxAF1fWF1rJw48Zr1FyrW0yw47CrsruF1UZw1fKr1j9F45X3yDJw10 kayDKr18Gr4rJF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The current arm64 DWARF register lookup relies on 'aarch64_regstr_tbl', a static string table. While this works for kprobe-tracer where register names start with '%', it is insufficient for parsing register numbers directly from raw instructions (e.g., extracting '6' from 'x6' or 'w6') during annotation. Since get_dwarf_regnum() is currently used only by 'perf annotate' and does not affect kprobe-tracer, replace the limited table-based lookup with a programmatic implementation in __get_dwarf_regnum_arm64(). This allows resolving arm64 register names (x0-x30, w0-w30, sp, etc.) directly into their corresponding DWARF register numbers. Signed-off-by: Tengda Wu --- .../util/dwarf-regs-arch/dwarf-regs-arm64.c | 22 +++++++++++++++++++ tools/perf/util/dwarf-regs.c | 2 +- tools/perf/util/include/dwarf-regs.h | 1 + 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/dwarf-regs-arch/dwarf-regs-arm64.c b/tools/per= f/util/dwarf-regs-arch/dwarf-regs-arm64.c index 593ca7d4fccc..720c863d1869 100644 --- a/tools/perf/util/dwarf-regs-arch/dwarf-regs-arm64.c +++ b/tools/perf/util/dwarf-regs-arch/dwarf-regs-arm64.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include +#include +#include #include #include "../../../arch/arm64/include/uapi/asm/perf_regs.h" =20 @@ -10,3 +13,22 @@ int __get_dwarf_regnum_for_perf_regnum_arm64(int perf_re= gnum) =20 return perf_regnum; } + +int __get_dwarf_regnum_arm64(const char *name) +{ + int reg; + + if (!strcmp(name, "sp")) + return 31; + + if (*name !=3D 'x' && *name !=3D 'w') + return -ENOENT; + + name++; + if (!isdigit(*name)) + return -ENOENT; + + reg =3D strtol(name, NULL, 10); + + return reg >=3D 0 && reg <=3D 30 ? reg : -ENOENT; +} diff --git a/tools/perf/util/dwarf-regs.c b/tools/perf/util/dwarf-regs.c index 797f455eba0d..bacf5c13c3bc 100644 --- a/tools/perf/util/dwarf-regs.c +++ b/tools/perf/util/dwarf-regs.c @@ -114,7 +114,7 @@ int get_dwarf_regnum(const char *name, unsigned int mac= hine, unsigned int flags) reg =3D _get_dwarf_regnum(arm_regstr_tbl, name); break; case EM_AARCH64: - reg =3D _get_dwarf_regnum(aarch64_regstr_tbl, name); + reg =3D __get_dwarf_regnum_arm64(name); break; case EM_CSKY: reg =3D __get_csky_regnum(name, flags); diff --git a/tools/perf/util/include/dwarf-regs.h b/tools/perf/util/include= /dwarf-regs.h index 46a764cf322f..a25f038bbff2 100644 --- a/tools/perf/util/include/dwarf-regs.h +++ b/tools/perf/util/include/dwarf-regs.h @@ -105,6 +105,7 @@ int __get_dwarf_regnum_x86_64(const char *name); int __get_dwarf_regnum_for_perf_regnum_i386(int perf_regnum); int __get_dwarf_regnum_for_perf_regnum_x86_64(int perf_regnum); =20 +int __get_dwarf_regnum_arm64(const char *name); int __get_dwarf_regnum_for_perf_regnum_arm(int perf_regnum); int __get_dwarf_regnum_for_perf_regnum_arm64(int perf_regnum); =20 --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3236C3C3425; Sat, 8 Aug 2026 12:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786191869; cv=none; b=J+ofmqhI5d2MTM3m4BzuDg/UAxvAvpzOc3DrPTcsTZdnUCeoH5SI7ydoROPMzerYJ6nKYaVxqkDAfd6nw1MQVM6L/DZhF/QxrabwPFkrPlwzLzyd4WnX91gHYj+SdXr0nZw1V0GzKZbfE9u+7C25yc/bEO973TD/94CxH7WE8lM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786191869; c=relaxed/simple; bh=gqunXJZJNSQd7/jBHTsC8Dd4mUBRbsmMmUIBrBXki7s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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Sat, 08 Aug 2026 20:24:17 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 06/23] perf annotate: Adapt arch__dwarf_regnum() for arm64 Date: Sat, 8 Aug 2026 12:23:43 +0000 Message-Id: <20260808122400.2961238-7-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S8 X-Coremail-Antispam: 1UD129KBjvJXoWxArWxCFWrWFW3KryUGrWxZwb_yoW5GFW5pw srCw13Jr18Gr4Fqw43JF4fWFW3Gr1fZF15urs5twn7AFs7uryrJan3tF1Y9ay3Jrs7Jr1j vr4qgr1kXF1fCaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Currently, arch__dwarf_regnum() assumes that all architectures use a register prefix character (e.g., '%' for x86) defined by arch->objdump.register_char, and uses it to match register names in objdump output. However, this assumption does not hold for arm64, where assembly syntax uses bare register names like 'x0', 'w1' without any prefix. As a result, arm64 builds may fail to correctly recognize register names from objdump disassembly, leading to incomplete or incorrect annotation output. To address this: - Make the register prefix check optional, allowing architectures without a prefix character to be parsed correctly. - Extend the delimiter set in strpbrk() to include the closing square bracket ']'. In arm64 assembly, memory operands often use bracketed syntax such as '[x1, #16]' or '[x2]'. Adding ']' ensures clean extraction of register names like 'x2' without trailing characters. - Remove the 'static' qualifier from arch__dwarf_regnum() so that it can be reused by other architecture-specific profiling components in future changes. Signed-off-by: Tengda Wu --- tools/perf/util/annotate.c | 14 ++++++++------ tools/perf/util/annotate.h | 2 ++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index df70e95a8470..9d8b4d6b859b 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -2472,21 +2472,23 @@ int annotate_check_args(void) return 0; } =20 -static int arch__dwarf_regnum(const struct arch *arch, const char *str) +int arch__dwarf_regnum(const struct arch *arch, const char *str) { - const char *p; + const char *p =3D str; char *regname, *q; int reg; =20 - p =3D strchr(str, arch->objdump.register_char); - if (p =3D=3D NULL) - return -1; + if (arch->objdump.register_char) { + p =3D strchr(str, arch->objdump.register_char); + if (p =3D=3D NULL) + return -1; + } =20 regname =3D strdup(p); if (regname =3D=3D NULL) return -1; =20 - q =3D strpbrk(regname, ",) "); + q =3D strpbrk(regname, ",)] "); if (q) *q =3D '\0'; =20 diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index fa08d09b80f7..11b6e4780c02 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -492,6 +492,8 @@ int annotate_parse_percent_type(const struct option *op= t, const char *_str, =20 int annotate_check_args(void); =20 +int arch__dwarf_regnum(const struct arch *arch, const char *str); + /** * struct annotated_op_loc - Location info of instruction operand * @reg1: First register in the operand --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 520DB3CE0A2; Sat, 8 Aug 2026 12:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786191870; cv=none; b=kx2Uc5w3cdHu07Dep5IvC19fGW6nY7es2EGj/eowQEO/49BBQsCbpN2ajZ86C3lOpYVt4F205eBIHkVR8izq59OEh+IuZsIU7WwDUHojqRtpUhJfgQ6htWhhGUUK02+NBVXx95jejQ/mmZhvOCgP01PB9ZInAAtzaSpY7KAjTE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786191870; c=relaxed/simple; bh=j46Non/kCvCuHskhj13We/pZwmVRvow++GkgVqV/xO0=; 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Sat, 08 Aug 2026 20:24:17 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 07/23] perf annotate: Introduce extract_op_location callback for arch-specific parsing Date: Sat, 8 Aug 2026 12:23:44 +0000 Message-Id: <20260808122400.2961238-8-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S9 X-Coremail-Antispam: 1UD129KBjvJXoWxtr1DCrWrGrW8JF18XrWrKrg_yoWfZF4kpw 4ku34rtF1rKr4YqwsrXFs5W3Wakw48WF1Y9r17K39rAFsFyrn5Jan7KF1ayF1rJrZ8ur1j vF4qvr4UXryFkaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Assembly syntax for operands varies significantly across different architectures, which prevents the operand location (op_loc) parsing logic in annotate_get_insn_location() from being directly reused. To simplify the core logic and improve maintainability, move the operand parsing inside the for_each_insn_op_loc loop into arch-specific extract_op_location callbacks. This refactoring is primarily a cleanup, but includes a minor x86-specific change: errors from extract_reg_offset() are now propagated, so unrecognized operands are correctly rejected instead of being silently ignored, , and testing confirms no functional regression from this change. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../util/annotate-arch/annotate-powerpc.c | 10 ++ tools/perf/util/annotate-arch/annotate-x86.c | 82 ++++++++++++++++ tools/perf/util/annotate.c | 94 ++----------------- tools/perf/util/disasm.h | 4 + 4 files changed, 103 insertions(+), 87 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-powerpc.c b/tools/perf/= util/annotate-arch/annotate-powerpc.c index 218207b52581..8d0b8def5955 100644 --- a/tools/perf/util/annotate-arch/annotate-powerpc.c +++ b/tools/perf/util/annotate-arch/annotate-powerpc.c @@ -390,6 +390,15 @@ static void update_insn_state_powerpc(struct type_stat= e *state, } #endif /* HAVE_LIBDW_SUPPORT */ =20 +static int extract_op_location_powerpc(const struct arch *arch __maybe_unu= sed, + struct disasm_line *dl, + const char *op_str __maybe_unused, int op_idx, + struct annotated_op_loc *op_loc) +{ + get_powerpc_regs(dl->raw.raw_insn, !op_idx, op_loc); + return 0; +} + const struct arch *arch__new_powerpc(const struct e_machine_and_e_flags *i= d, const char *cpuid __maybe_unused) { @@ -406,5 +415,6 @@ const struct arch *arch__new_powerpc(const struct e_mac= hine_and_e_flags *id, #ifdef HAVE_LIBDW_SUPPORT arch->update_insn_state =3D update_insn_state_powerpc; #endif + arch->extract_op_location =3D extract_op_location_powerpc; return arch; } diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index 7e6136536393..6044a68966f1 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include +#include #include #include #include @@ -809,6 +811,85 @@ static void update_insn_state_x86(struct type_state *s= tate, } #endif =20 +/* + * Get register number and access offset from the given instruction. + * It assumes AT&T x86 asm format like OFFSET(REG). + * Fills @reg and @offset when return 0. + */ +static int extract_reg_offset(const struct arch *arch, const char *str, + struct annotated_op_loc *op_loc) +{ + char *p; + + if (arch->objdump.register_char =3D=3D 0) + return -1; + + /* + * It should start from offset, but it's possible to skip 0 + * in the asm. So 0(%rax) should be same as (%rax). + * + * However, it also start with a segment select register like + * %gs:0x18(%rbx). In that case it should skip the part. + */ + if (*str =3D=3D arch->objdump.register_char) { + /* FIXME: Handle other segment registers */ + if (!strncmp(str, "%gs:", 4)) + op_loc->segment =3D INSN_SEG_X86_GS; + + while (*str && !isdigit(*str) && + *str !=3D arch->objdump.memory_ref_char) + str++; + } + + op_loc->offset =3D strtol(str, &p, 0); + op_loc->reg1 =3D arch__dwarf_regnum(arch, p); + if (op_loc->reg1 =3D=3D -1) + return -1; + + /* Get the second register */ + if (op_loc->multi_regs) + op_loc->reg2 =3D arch__dwarf_regnum(arch, p + 1); + + return 0; +} + +static int extract_op_location_x86(const struct arch *arch, + struct disasm_line *dl __maybe_unused, + const char *op_str, int op_idx __maybe_unused, + struct annotated_op_loc *op_loc) +{ + const char *s =3D op_str; + char *p =3D NULL; + + if (op_str =3D=3D NULL) + return 0; + + if (strchr(op_str, arch->objdump.memory_ref_char)) { + op_loc->mem_ref =3D true; + return extract_reg_offset(arch, op_str, op_loc); + } + + /* FIXME: Handle other segment registers */ + if (!strncmp(op_str, "%gs:", 4)) { + op_loc->segment =3D INSN_SEG_X86_GS; + op_loc->offset =3D strtol(op_str + 4, + &p, 0); + if (p && p !=3D op_str + 4) + op_loc->imm =3D true; + return 0; + } + + if (*s =3D=3D arch->objdump.register_char) { + op_loc->reg1 =3D arch__dwarf_regnum(arch, s); + } else if (*s =3D=3D arch->objdump.imm_char) { + op_loc->offset =3D strtol(s + 1, &p, 0); + if (p && p !=3D s + 1) + op_loc->imm =3D true; + } + + return 0; +} + const struct arch *arch__new_x86(const struct e_machine_and_e_flags *id, c= onst char *cpuid) { struct arch *arch =3D zalloc(sizeof(*arch)); @@ -848,5 +929,6 @@ const struct arch *arch__new_x86(const struct e_machine= _and_e_flags *id, const c #ifdef HAVE_LIBDW_SUPPORT arch->update_insn_state =3D update_insn_state_x86; #endif + arch->extract_op_location =3D extract_op_location_x86; return arch; } diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 9d8b4d6b859b..20be609ebed2 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -2497,51 +2497,6 @@ int arch__dwarf_regnum(const struct arch *arch, cons= t char *str) return reg; } =20 -/* - * Get register number and access offset from the given instruction. - * It assumes AT&T x86 asm format like OFFSET(REG). Maybe it needs - * to revisit the format when it handles different architecture. - * Fills @reg and @offset when return 0. - */ -static int extract_reg_offset(const struct arch *arch, const char *str, - struct annotated_op_loc *op_loc) -{ - char *p; - - if (arch->objdump.register_char =3D=3D 0) - return -1; - - /* - * It should start from offset, but it's possible to skip 0 - * in the asm. So 0(%rax) should be same as (%rax). - * - * However, it also start with a segment select register like - * %gs:0x18(%rbx). In that case it should skip the part. - */ - if (*str =3D=3D arch->objdump.register_char) { - if (arch__is_x86(arch)) { - /* FIXME: Handle other segment registers */ - if (!strncmp(str, "%gs:", 4)) - op_loc->segment =3D INSN_SEG_X86_GS; - } - - while (*str && !isdigit(*str) && - *str !=3D arch->objdump.memory_ref_char) - str++; - } - - op_loc->offset =3D strtol(str, &p, 0); - op_loc->reg1 =3D arch__dwarf_regnum(arch, p); - if (op_loc->reg1 =3D=3D -1) - return -1; - - /* Get the second register */ - if (op_loc->multi_regs) - op_loc->reg2 =3D arch__dwarf_regnum(arch, p + 1); - - return 0; -} - /** * annotate_get_insn_location - Get location of instruction * @arch: the architecture info @@ -2572,6 +2527,7 @@ int annotate_get_insn_location(const struct arch *arc= h, struct disasm_line *dl, struct ins_operands *ops; struct annotated_op_loc *op_loc; int i; + int ret; =20 if (ins__is_lock(&dl->ins)) ops =3D dl->ops.locked.ops; @@ -2597,49 +2553,13 @@ int annotate_get_insn_location(const struct arch *a= rch, struct disasm_line *dl, /* Invalidate the register by default */ op_loc->reg1 =3D -1; op_loc->reg2 =3D -1; + op_loc->mem_ref =3D mem_ref; + op_loc->multi_regs =3D multi_regs; =20 - if (insn_str =3D=3D NULL) { - if (!arch__is_powerpc(arch)) - continue; - } - - /* - * For powerpc, call get_powerpc_regs function which extracts the - * required fields for op_loc, ie reg1, reg2, offset from the - * raw instruction. - */ - if (arch__is_powerpc(arch)) { - op_loc->mem_ref =3D mem_ref; - op_loc->multi_regs =3D multi_regs; - get_powerpc_regs(dl->raw.raw_insn, !i, op_loc); - } else if (strchr(insn_str, arch->objdump.memory_ref_char)) { - op_loc->mem_ref =3D true; - op_loc->multi_regs =3D multi_regs; - extract_reg_offset(arch, insn_str, op_loc); - } else { - const char *s =3D insn_str; - char *p =3D NULL; - - if (arch__is_x86(arch)) { - /* FIXME: Handle other segment registers */ - if (!strncmp(insn_str, "%gs:", 4)) { - op_loc->segment =3D INSN_SEG_X86_GS; - op_loc->offset =3D strtol(insn_str + 4, - &p, 0); - if (p && p !=3D insn_str + 4) - op_loc->imm =3D true; - continue; - } - } - - if (*s =3D=3D arch->objdump.register_char) { - op_loc->reg1 =3D arch__dwarf_regnum(arch, s); - } - else if (*s =3D=3D arch->objdump.imm_char) { - op_loc->offset =3D strtol(s + 1, &p, 0); - if (p && p !=3D s + 1) - op_loc->imm =3D true; - } + if (arch->extract_op_location) { + ret =3D arch->extract_op_location(arch, dl, insn_str, i, op_loc); + if (ret) + return ret; } } =20 diff --git a/tools/perf/util/disasm.h b/tools/perf/util/disasm.h index 06c664fd4fc2..8796f92769f9 100644 --- a/tools/perf/util/disasm.h +++ b/tools/perf/util/disasm.h @@ -16,6 +16,7 @@ struct symbol; struct data_loc_info; struct type_state; struct disasm_line; +struct annotated_op_loc; =20 struct e_machine_and_e_flags { uint32_t e_flags; @@ -49,6 +50,9 @@ struct arch { struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl); #endif + int (*extract_op_location)(const struct arch *arch, struct disasm_line *= dl, + const char *op_str, int op_idx, + struct annotated_op_loc *op_loc); }; =20 struct ins { --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5703B3D1CA7; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hHKtJ01RbzYQvjg; Sat, 8 Aug 2026 20:23:19 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 2DABF4058F; Sat, 8 Aug 2026 20:24:18 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S10; Sat, 08 Aug 2026 20:24:17 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 08/23] perf annotate-arm64: Implement extract_op_location() callback Date: Sat, 8 Aug 2026 12:23:45 +0000 Message-Id: <20260808122400.2961238-9-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S10 X-Coremail-Antispam: 1UD129KBjvJXoWxAr4rXw1rur4fAry5XF43ZFb_yoWruFWDpw 4jk345tr17tr4aq3WfZrs7WFy3Cw4fGF1Y9rWxC39xArs7ZFn2qa1IkF1a9Fy5JrZxC34j vF4DtFW8XryUGaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Implement the extract_op_location() callback for the arm64 architecture to handle its specific assembly syntax and addressing modes. The extractor handles: 1. Standalone immediate operands (e.g., #0x10). 2. Memory references with diverse addressing modes: - Signed offset: [base{, #imm|reg}] - Pre-index: [base, #imm]! - Post-index: [base], #imm|reg 3. Multi-register operands and primary/secondary register extraction. With this callback in place, 'perf annotate' can now resolve memory locations and register types on arm64, marking the initial enablement of data type profiling for this architecture. Signed-off-by: Tengda Wu Reviewed-by: Shuai Xue --- .../perf/util/annotate-arch/annotate-arm64.c | 67 +++++++++++++++++++ tools/perf/util/annotate.h | 10 +++ 2 files changed, 77 insertions(+) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 32752a3bc756..6b4f1228afa9 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -287,6 +287,72 @@ static const struct ins_ops *arm64__associate_instruct= ion_ops(struct arch *arch, return ops; } =20 +static int extract_op_location_arm64(const struct arch *arch, + struct disasm_line *dl __maybe_unused, + const char *op_str, int op_idx __maybe_unused, + struct annotated_op_loc *op_loc) +{ + const char *s =3D op_str; + char *p =3D NULL; + + if (op_str =3D=3D NULL) + return 0; + + /* Handle standalone immediate operands (e.g., #0x10) */ + if (*s =3D=3D arch->objdump.imm_char) { + op_loc->offset =3D strtol(s + 1, &p, 0); + if (p && p !=3D s + 1) + op_loc->imm =3D true; + return 0; + } + + /* + * Handle memory references, identify arm64 specific addressing modes. + * Reference: Arm Architecture Reference Manual + * (DDI 0487), Chapter C1.3.3: Load/store addressing modes. + */ + if (*s =3D=3D arch->objdump.memory_ref_char) { + op_loc->mem_ref =3D true; + + p =3D strchr(s, ']'); + if (p =3D=3D NULL) + return -1; + + /* Pre-index: [base, #imm]! */ + if (p[1] =3D=3D '!') + op_loc->addr_mode =3D PERF_ADDR_MODE_PRE_INDEX; + /* Post-index: [base], #imm|reg */ + else if (p[1] =3D=3D ',' && + (strchr(p + 1, arch->objdump.imm_char) || + arm64__is_reg(skip_spaces(p + 2)))) + op_loc->addr_mode =3D PERF_ADDR_MODE_POST_INDEX; + /* Signed offset: [base{, #imm|reg}] */ + else + op_loc->addr_mode =3D PERF_ADDR_MODE_SIGNED_OFFSET; + + s++; + } + + /* Extract the primary register */ + op_loc->reg1 =3D arch__dwarf_regnum(arch, s); + if (op_loc->reg1 =3D=3D -1) + return -1; + + /* Move to the next symbol of the operand, if any */ + s =3D strchr(s, ','); + if (s =3D=3D NULL) + return 0; + s =3D skip_spaces(s + 1); + + /* Extract secondary register or immediate offset */ + if (op_loc->multi_regs) + op_loc->reg2 =3D arch__dwarf_regnum(arch, s); + else if (*s =3D=3D arch->objdump.imm_char) + op_loc->offset =3D strtol(s + 1, &p, 0); + + return 0; +} + const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id, const char *cpuid __maybe_unused) { @@ -305,6 +371,7 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->objdump.memory_ref_char =3D '['; arch->objdump.imm_char =3D '#'; arch->associate_instruction_ops =3D arm64__associate_instruction_ops; + arch->extract_op_location =3D extract_op_location_arm64; =20 /* bl, blr */ err =3D regcomp(&arm->call_insn, "^blr?$", REG_EXTENDED); diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index 11b6e4780c02..a44c933f55f5 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -494,12 +494,21 @@ int annotate_check_args(void); =20 int arch__dwarf_regnum(const struct arch *arch, const char *str); =20 +enum annotated_addr_mode { + PERF_ADDR_MODE_NONE =3D 0, + + PERF_ADDR_MODE_SIGNED_OFFSET, + PERF_ADDR_MODE_PRE_INDEX, + PERF_ADDR_MODE_POST_INDEX, +}; + /** * struct annotated_op_loc - Location info of instruction operand * @reg1: First register in the operand * @reg2: Second register in the operand * @offset: Memory access offset in the operand * @segment: Segment selector register + * @addr_mode: Addressing mode, only valid if @mem_ref is true * @mem_ref: Whether the operand accesses memory * @multi_regs: Whether the second register is used * @imm: Whether the operand is an immediate value (in offset) @@ -509,6 +518,7 @@ struct annotated_op_loc { int reg2; int offset; u8 segment; + u8 addr_mode; bool mem_ref; bool multi_regs; bool imm; --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46031412C11; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hHKvC1LrJzKHND9; Sat, 8 Aug 2026 20:24:07 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 474EE4057D; Sat, 8 Aug 2026 20:24:18 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S11; Sat, 08 Aug 2026 20:24:17 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 09/23] perf annotate: Deduplicate overlapping ARM SPE events for data type profiling Date: Sat, 8 Aug 2026 12:23:46 +0000 Message-Id: <20260808122400.2961238-10-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S11 X-Coremail-Antispam: 1UD129KBjvJXoWxGr4fWrWxGr4xtFW5Aw47Jwb_yoWrtrW3pr sI9w15KwnYqr4rKrn3ZF4UXryS93yfXFZ8GwnFya15A3y3ur95tFyxtr15tFZxXwn8Z34a vws0ga98G34rZaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" When data type profiling is enabled on ARM SPE, multiple overlapping events (e.g., l1d-miss, tlb-access) are synthesized for a single sampled instruction, as shown below: Available samples 0 arm_spe_0/ts_enable=3D1,pa_enable=3D1,load_filter=3D1,store_filter=3D1,= min_latency=3D30/ 0 dummy:u 84K l1d-miss 95K l1d-access 77K llc-miss 58K llc-access 9K tlb-miss 108K tlb-access 0 branch 13K remote-access 108K memory 108K instructions While 'perf report' provides an interactive menu for users to select a specific event to prevent duplicate counting, 'perf annotate' lacks such a mechanism. Consequently, it counts all instructions across these overlapping events, which inflates the profile and distorts the data type statistics. Although using the '--itrace' option can work around this issue (e.g.: perf annotate --data-type --stdio --itrace=3Di1i), it is inconvenient for users to specify this explicitly every time. To address this, introduce itrace_synth_opts.dont_overlap. Set this to true when data type profiling is enabled and the user has not explicitly specified an itrace option. Then, during arm_spe_process_auxtrace_info(), adjust the synthesized event options based on the dont_overlap value to only enable instruction event synthesis, thereby achieving automatic deduplication. Signed-off-by: Tengda Wu --- tools/perf/builtin-annotate.c | 8 ++++++++ tools/perf/util/arm-spe.c | 17 +++++++++++++++++ tools/perf/util/auxtrace.h | 2 ++ 3 files changed, 27 insertions(+) diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 69cb72b2082a..616f54bf4868 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -873,6 +873,14 @@ int cmd_annotate(int argc, const char **argv) annotate.session =3D perf_session__new(&data, &annotate.tool); if (IS_ERR(annotate.session)) return PTR_ERR(annotate.session); + /* + * Hardware tracing (e.g.: ARM SPE) may generate overlapping events + * per instruction. When data type profiling is enabled, enable + * dont_overlap to deduplicate them to avoid skewed stats, but only + * if user hasn't specified itrace options (respect user override). + */ + if (annotate.data_type && !itrace_synth_opts.set) + itrace_synth_opts.dont_overlap =3D true; =20 annotate.session->itrace_synth_opts =3D &itrace_synth_opts; =20 diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 401aab529309..1721882423f6 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -2033,6 +2033,9 @@ int arm_spe_process_auxtrace_info(union perf_event *e= vent, /* Default nanoseconds period not supported */ spe->synth_opts.period_type =3D PERF_ITRACE_PERIOD_INSTRUCTIONS; spe->synth_opts.period =3D 1; + + if (session->itrace_synth_opts) + spe->synth_opts.dont_overlap =3D session->itrace_synth_opts->dont_overl= ap; } =20 if (spe->synth_opts.period_type !=3D PERF_ITRACE_PERIOD_INSTRUCTIONS) { @@ -2044,6 +2047,20 @@ int arm_spe_process_auxtrace_info(union perf_event *= event, ui__warning("Arm SPE has a hardware-based sampling period.\n\n" "--itrace periods > 1i downsample by an interval of n SPE samples r= ather than n instructions.\n"); =20 + if (spe->synth_opts.dont_overlap) { + /* + * The 'instructions' event is the most comprehensive, + * synthesize it exclusively. + */ + spe->synth_opts.flc =3D false; + spe->synth_opts.llc =3D false; + spe->synth_opts.tlb =3D false; + spe->synth_opts.branches =3D false; + spe->synth_opts.remote_access =3D false; + spe->synth_opts.mem =3D false; + spe->synth_opts.instructions =3D true; + } + err =3D arm_spe_synth_events(spe, session); if (err) goto err_free_queues; diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h index 6947f3f284c0..ebb4e9e8e574 100644 --- a/tools/perf/util/auxtrace.h +++ b/tools/perf/util/auxtrace.h @@ -80,6 +80,7 @@ enum itrace_period_type { * @intr_events: whether to synthesize interrupt events * @errors: whether to synthesize decoder error events * @dont_decode: whether to skip decoding entirely + * @dont_overlap: whether to deduplicate overlapping events * @log: write a decoding log * @calls: limit branch samples to calls (can be combined with @returns) * @returns: limit branch samples to returns (can be combined with @calls) @@ -128,6 +129,7 @@ struct itrace_synth_opts { bool intr_events; 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Sat, 08 Aug 2026 20:24:18 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 10/23] perf arm-spe: Set default synthesized event period to 1 Date: Sat, 8 Aug 2026 12:23:47 +0000 Message-Id: <20260808122400.2961238-11-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S12 X-Coremail-Antispam: 1UD129KBjvJXoWxXFy7CFyxXFWkWw1kJryftFb_yoW5uw43pr nFgFyfJr4kJry8KwnrAr4UuFy3twsYvF1fGryxGrWUAw1UKry8tr17try5Cr4UWr1Fyr17 XFyqgr1UGr1Utr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" When using --itrace=3DM for data type profiling on arm64, the 'Percent' values in perf annotate output are all zero: Annotate type: 'struct mmu_gather_batch' in [kernel.kallsyms] (15 samples): =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D Percent offset size field 0.00 0 0x10 struct mmu_gather_batch { 0.00 0 0x8 struct mmu_gather_batch* next; 0.00 0x8 0x4 unsigned int nr; 0.00 0xc 0x4 unsigned int max; 0.00 0x10 0 struct encoded_page*[] encoded_pag= es; }; However, adding the -n option (show-nr-samples) reveals non-zero sample cou= nts: Annotate type: 'struct mmu_gather_batch' in [kernel.kallsyms] (15 samples): =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D Samples offset size field 15 0 0x10 struct mmu_gather_batch { 13 0 0x8 struct mmu_gather_batch* next; 2 0x8 0x4 unsigned int nr; 0 0xc 0x4 unsigned int max; 0 0x10 0 struct encoded_page*[] encoded_pag= es; }; The root cause is that when --itrace is used with non-i/y options (e.g., --itrace=3DM), the period remains zero after parsing. During subsequent propagation, the final percentage calculation results in zero: arm_spe_prep_sample() sample->period =3D spe->synth_opts.period; __hists__add_entry() he.stat.period =3D sample->period; annotated_data_type__update_samples() h->period +=3D period; h->addr[offset].period +=3D period; print_annotated_data_value() double percent =3D h->period ? (100.0 * period / h->period) : 0; Fix this by defaulting the period to 1 in the ARM SPE auxtrace info processing path if it is not explicitly specified. This ensures that downstream tool components can correctly accumulate periods and compute event percentages for all synthesized SPE events. With this fix applied, the result is as follows: Annotate type: 'struct mmu_gather_batch' in [kernel.kallsyms] (15 samples): =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D Percent offset size field 100.00 0 0x10 struct mmu_gather_batch { 86.67 0 0x8 struct mmu_gather_batch* next; 13.33 0x8 0x4 unsigned int nr; 0.00 0xc 0x4 unsigned int max; 0.00 0x10 0 struct encoded_page*[] encoded_pag= es; }; Signed-off-by: Tengda Wu --- tools/perf/util/arm-spe.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 1721882423f6..0f656398f2a8 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -2043,6 +2043,17 @@ int arm_spe_process_auxtrace_info(union perf_event *= event, err =3D -EINVAL; goto err_free_queues; } + + /* + * When --itrace is used with non-i/y options (e.g., --itrace=3DM), + * the period remains 0 because the parser does not apply a default + * for those paths. However, synthesized SPE events such as memory + * accesses, TLB walks, and cache misses still require a valid + * sample->period to correctly accumulate periods and compute event + * percentages. Set it to 1 to ensure proper accounting. + */ + spe->synth_opts.period =3D spe->synth_opts.period ?: 1; + if (spe->synth_opts.period > 1) ui__warning("Arm SPE has a hardware-based sampling period.\n\n" "--itrace periods > 1i downsample by an interval of n SPE samples r= ather than n instructions.\n"); --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 575B53D4135; Sat, 8 Aug 2026 12:24:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786191876; cv=none; b=nMR1rKduUeNQS5QKe+NunnmycJeCZ4qBhrbAXhxDPChqjiJRrTDfPMpDkhvHeQAKw+Ue5OW1ZCLbTD/dQl5azu1rgU47QpgeqBZtOwU9I52oGlxiYrb9+jNdDnYt1WphL3K5FBW0kmkbuTxubMG90d6lsm9e/erh9byCfGi+ef0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786191876; c=relaxed/simple; bh=YTDFVZLR0D3uojyu93nDplOkwkwLG56jTNIDoYJPz9c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hNVRmQrTd5FfLbzr4B2URZ8Kv1ixWkWo3HjW034ccR6mDrORBd6iRLJF25yLzJ4lcMwmaB4jUqdw41gfchl+vwOGTMYvHogmGHWYzdnFjDqVV7xZpyX/1y/6cNbmAqyPDxSAV0Q6ogBxN2t2TwdoMP6k07blYd9K6vx95LKnNAw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hHKtJ28WlzYQvh9; Sat, 8 Aug 2026 20:23:20 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 7764E4058F; Sat, 8 Aug 2026 20:24:18 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S13; Sat, 08 Aug 2026 20:24:18 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 11/23] perf annotate-data: Extract invalidate_reg_state() as a common helper Date: Sat, 8 Aug 2026 12:23:48 +0000 Message-Id: <20260808122400.2961238-12-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S13 X-Coremail-Antispam: 1UD129KBjvJXoWxGr1rJry8CF1ktr17Kr4UJwb_yoW5Gw17p3 yDC347Gw43Gr4FgwnxJFW3XFWF9r1fXa4Fk3sYywn7ZF4Iyrn3JF92qFy5tFW7Xr93Gw12 yw1qgr4DJ3yxGaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The invalidate_reg_state() function is currently static and only used within the x86 data type profiling implementation. To prepare for adding arm64 instruction tracking support, extract it as a common helper that can be shared across architectures. No functional change intended. Signed-off-by: Tengda Wu Reviewed-by: Shuai Xue --- tools/perf/util/annotate-arch/annotate-x86.c | 9 --------- tools/perf/util/annotate-data.c | 9 +++++++++ tools/perf/util/annotate-data.h | 1 + 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index 6044a68966f1..ee4e3e7f3209 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -207,15 +207,6 @@ static int x86__cpuid_parse(struct arch *arch, const c= har *cpuid) } =20 #ifdef HAVE_LIBDW_SUPPORT -static void invalidate_reg_state(struct type_state_reg *reg) -{ - reg->kind =3D TSR_KIND_INVALID; - reg->ok =3D false; - reg->lifetime_active =3D false; - reg->lifetime_end =3D 0; - reg->copied_from =3D -1; -} - static void update_insn_state_x86(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 4e4c58764082..104b80d471f1 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -638,6 +638,15 @@ struct type_state_stack *findnew_stack_state(struct ty= pe_state *state, return stack; } =20 +void invalidate_reg_state(struct type_state_reg *reg) +{ + reg->kind =3D TSR_KIND_INVALID; + reg->ok =3D false; + reg->lifetime_active =3D false; + reg->lifetime_end =3D 0; + reg->copied_from =3D -1; +} + /* Maintain a cache for quick global variable lookup */ struct global_var_entry { struct rb_node node; diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index c26130744260..453e13bbe3e2 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -258,6 +258,7 @@ void set_stack_state(struct type_state_stack *stack, in= t offset, u8 kind, Dwarf_Die *type_die, int ptr_offset); struct type_state_stack *find_stack_state(struct type_state *state, int offset); +void invalidate_reg_state(struct type_state_reg *reg); bool get_global_var_type(Dwarf_Die *cu_die, struct data_loc_info *dloc, u64 ip, u64 var_addr, int *var_offset, Dwarf_Die *type_die); --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5E513D1CD7; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hHKtJ2p3HzYQvm0; Sat, 8 Aug 2026 20:23:20 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 8F8DA4097C; Sat, 8 Aug 2026 20:24:18 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S14; Sat, 08 Aug 2026 20:24:18 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 12/23] perf annotate-arm64: Enable instruction tracking support Date: Sat, 8 Aug 2026 12:23:49 +0000 Message-Id: <20260808122400.2961238-13-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S14 X-Coremail-Antispam: 1UD129KBjvJXoW3WFy7Wr48tF1UCrWDuFy5XFb_yoW7Cw4Upa yDCw15GF45Jr4IgwnxAF4xXry3Kw4fW34Ykr9Ygw4SyFsFyr95tan5KFWaya1rJrZ3Cr47 J3WqyF4UX3yUCaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Enable basic instruction tracking for arm64 by implementing three essential functions in the find_data_type_block() call path: find_data_type_block -> arch_supports_insn_tracking (1) -> find_data_type_insn -> init_type_state (2) -> update_var_state -> update_insn_state (3) Changes: * arch_supports_insn_tracking(): add arm64 to the list of supported architectures, allowing find_data_type_block() to proceed with data type analysis. * init_type_state(): correctly identify ret_reg, stack_reg, and caller-saved registers for arm64 during type state initialization. * update_insn_state(): add the update_insn_state_arm64() callback with conservative register invalidation for call instructions and those with destination register(s), preventing stale type propagation. Full instruction-level analysis support will be added incrementally in later patches. With these changes, arm64 gains support for basic variable type inference during instruction tracking. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 66 +++++++++++++++++++ tools/perf/util/annotate-data.c | 11 +++- 2 files changed, 76 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 6b4f1228afa9..44daa0176e51 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -9,6 +9,10 @@ #include #include "../annotate.h" #include "../disasm.h" +#include "../annotate-data.h" +#include "../debug.h" +#include "../map.h" +#include "../symbol.h" =20 struct arch_arm64 { struct arch arch; @@ -353,6 +357,65 @@ static int extract_op_location_arm64(const struct arch= *arch, return 0; } =20 +#ifdef HAVE_LIBDW_SUPPORT +static void update_insn_state_arm64(struct type_state *state, + struct data_loc_info *dloc, Dwarf_Die *cu_die __maybe_unused, + struct disasm_line *dl) +{ + struct annotated_insn_loc loc; + struct annotated_op_loc *dst =3D &loc.ops[INSN_OP_TARGET]; + u32 insn_offset =3D dl->al.offset; + + if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0) + return; + + /* + * Invalidate caller-saved registers on function calls per ARM64 AAPCS64 + * ABI, unless DWARF location info indicates the register remains valid + * beyond the call address. + */ + if (ins__is_call(&dl->ins)) { + struct symbol *func =3D dl->ops.target.sym; + const char *call_name; + u64 call_addr; + + call_name =3D func ? func->name : dl->ops.target.name; + pr_debug_dtp("call [%x] %s\n", insn_offset, call_name ?: ""); + + /* Invalidate caller-saved registers after call */ + call_addr =3D map__rip_2objdump(dloc->ms->map, + dloc->ms->sym->start + dl->al.offset); + for (unsigned int i =3D 0; i < ARRAY_SIZE(state->regs); i++) { + struct type_state_reg *reg =3D &state->regs[i]; + + if (!reg->caller_saved) + continue; + /* Keep register valid within DWARF location lifetime */ + if (reg->lifetime_active && call_addr < reg->lifetime_end) + continue; + invalidate_reg_state(reg); + } + return; + } + + /* + * Invalidate destination register(s) for unsupported instructions to + * prevent stale type info from propagating to subsequent instructions. + */ + if (has_reg_type(state, dst->reg1)) { + pr_debug_dtp("%s [%x] invalidate reg%d", + dl->ins.name, insn_offset, dst->reg1); + invalidate_reg_state(&state->regs[dst->reg1]); + if (dst->multi_regs) { + pr_debug_dtp(" and reg%d", dst->reg2); + invalidate_reg_state(&state->regs[dst->reg2]); + } + pr_debug_dtp("\n"); + return; + } +} +#endif + const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id, const char *cpuid __maybe_unused) { @@ -372,6 +435,9 @@ const struct arch *arch__new_arm64(const struct e_machi= ne_and_e_flags *id, arch->objdump.imm_char =3D '#'; arch->associate_instruction_ops =3D arm64__associate_instruction_ops; arch->extract_op_location =3D extract_op_location_arm64; +#ifdef HAVE_LIBDW_SUPPORT + arch->update_insn_state =3D update_insn_state_arm64; +#endif =20 /* bl, blr */ err =3D regcomp(&arm->call_insn, "^blr?$", REG_EXTENDED); diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 104b80d471f1..c51b20a7af9b 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -28,6 +28,7 @@ =20 /* register number of the stack pointer */ #define X86_REG_SP 7 +#define ARM64_REG_SP 31 =20 static void delete_var_types(struct die_var_type *var_types); =20 @@ -178,6 +179,13 @@ static void init_type_state(struct type_state *state, = const struct arch *arch) state->regs[11].caller_saved =3D true; state->ret_reg =3D 0; state->stack_reg =3D X86_REG_SP; + } else if (arch__is_arm64(arch)) { + int i; + + for (i =3D 0; i < 18; i++) + state->regs[i].caller_saved =3D true; + state->ret_reg =3D 0; + state->stack_reg =3D ARM64_REG_SP; } } =20 @@ -1437,7 +1445,8 @@ static enum type_match_result find_data_type_insn(str= uct data_loc_info *dloc, =20 static int arch_supports_insn_tracking(struct data_loc_info *dloc) { - if ((arch__is_x86(dloc->arch)) || (arch__is_powerpc(dloc->arch))) + if (arch__is_x86(dloc->arch) || arch__is_powerpc(dloc->arch) || + arch__is_arm64(dloc->arch)) return 1; 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charset="utf-8" Enable data type profiling to track function return values in arm64 annotations by looking up the DWARF return type of called functions. Signed-off-by: Tengda Wu --- tools/perf/util/annotate-arch/annotate-arm64.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 44daa0176e51..acff14ca01e0 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -359,7 +359,7 @@ static int extract_op_location_arm64(const struct arch = *arch, =20 #ifdef HAVE_LIBDW_SUPPORT static void update_insn_state_arm64(struct type_state *state, - struct data_loc_info *dloc, Dwarf_Die *cu_die __maybe_unused, + struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) { struct annotated_insn_loc loc; @@ -378,6 +378,8 @@ static void update_insn_state_arm64(struct type_state *= state, struct symbol *func =3D dl->ops.target.sym; const char *call_name; u64 call_addr; + struct type_state_reg *tsr; + Dwarf_Die type_die; =20 call_name =3D func ? func->name : dl->ops.target.name; pr_debug_dtp("call [%x] %s\n", insn_offset, call_name ?: ""); @@ -395,6 +397,20 @@ static void update_insn_state_arm64(struct type_state = *state, continue; invalidate_reg_state(reg); } + + /* Update register with the return type (if any) */ + if (call_name && die_find_func_rettype(cu_die, call_name, &type_die)) { + tsr =3D &state->regs[state->ret_reg]; + tsr->copied_from =3D -1; + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("call [%x] return -> reg%d", + insn_offset, state->ret_reg); + pr_debug_type_name(&type_die, tsr->kind); + } return; } =20 --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60BDE3D170B; Sat, 8 Aug 2026 12:24:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hHKvC4fL1zKHNG5; Sat, 8 Aug 2026 20:24:07 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id BCB4B4057D; Sat, 8 Aug 2026 20:24:18 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S16; Sat, 08 Aug 2026 20:24:18 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 14/23] perf annotate-arm64: Support load instruction tracking Date: Sat, 8 Aug 2026 12:23:51 +0000 Message-Id: <20260808122400.2961238-15-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S16 X-Coremail-Antispam: 1UD129KBjvJXoW3Xr1xCF4DXrWxGrWrGFW8Xrb_yoW3GrWxpF WDG34rKrZrtr4agFsaqFWDJr9xuwn7Gw15Cr98Za1ayF9Fyr1rKa9YkFy3uF45GrZruw43 Ja1DtrWDXw47CaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state_arm64() to handle LDR instructions, tracking register state changes when data is loaded from memory to registers. The implementation handles the three primary arm64 addressing modes: 1. Signed offset: [base, #imm|reg] 2. Pre-index: [base, #imm]! 3. Post-index: [base], #imm Before updating, check the addressing mode via get_reg_index_offset() to obtain the actual source's reg_offset, and then propagate the type. Since a load instruction may have two destination registers (in ldp cases), introduce propagate_load_reg_state() to propagate the type for a specified destination register using a given reg_offset. The respective reg_offset values for the two registers are as follows: dst->reg1: reg_offset =3D get_reg_index_offset() dst->reg2: reg_offset =3D get_reg_index_offset() + reg_size(dst->reg1) Finally, handle the side effects of pre-index and post-index addressing via adjust_reg_index_state(). A real-world example is shown below: ffff80008011f5b0 : ffff80008011f5b8: ldr x0, [x0, #2712] // x0: struct rq* -> task_struct* * ffff80008011f5c0: ldr w1, [x0, #104] Before this commit, the type of x0 was incorrectly inferred as 'struct rq': find data type for 0x68(reg0) at pick_task_stop+0x10 var [8] reg0 offset 0 type=3D'struct rq*' chk [10] reg0 offset=3D0x68 ok=3D1 kind=3D1 (struct rq*) : Good! final result: type=3D'struct rq' After this commit, the type of x0 is correctly inferred as 'struct task_str= uct': find data type for 0x68(reg0) at pick_task_stop+0x10 var [8] reg0 offset 0 type=3D'struct rq*' ldr [8] 0xa98(reg0) -> reg0 type=3D'struct task_struct*' chk [10] reg0 offset=3D0x68 ok=3D1 kind=3D1 (struct task_struct*) : Good! final result: type=3D'struct task_struct' Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 148 +++++++++++++++++- 1 file changed, 147 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index acff14ca01e0..6557c0ad11b2 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -358,11 +358,152 @@ static int extract_op_location_arm64(const struct ar= ch *arch, } =20 #ifdef HAVE_LIBDW_SUPPORT +static int arm64__reg_size(const char *reg) +{ + if (!reg || !*reg || !arm64__is_reg(reg)) + return -1; + + if (reg[0] =3D=3D 'w') + return 4; + + if (reg[0] =3D=3D 'x' || !strncmp(reg, "sp", 2)) + return 8; + + return -1; +} + +static int get_reg_index_offset(struct annotated_op_loc *op_loc) +{ + return op_loc->addr_mode =3D=3D PERF_ADDR_MODE_POST_INDEX ? 0 : op_loc->o= ffset; +} + +/* Apply addressing mode (pre-index, post-index) to register state */ +static void adjust_reg_index_state(struct type_state *state, + struct annotated_op_loc *op_loc, + const char *insn_name, u32 insn_offset) +{ + struct type_state_reg *tsr; + int reg =3D op_loc->reg1; + + if (op_loc->addr_mode !=3D PERF_ADDR_MODE_PRE_INDEX && + op_loc->addr_mode !=3D PERF_ADDR_MODE_POST_INDEX) + return; + + if (!has_reg_type(state, reg) || !state->regs[reg].ok) + return; + + tsr =3D &state->regs[reg]; + tsr->copied_from =3D -1; + tsr->offset =3D op_loc->offset + tsr->offset; + + pr_debug_dtp("%s [%x] %s-index %#x(reg%d) -> reg%d", insn_name, + insn_offset, op_loc->addr_mode =3D=3D PERF_ADDR_MODE_PRE_INDEX ? + "pre" : "post", op_loc->offset, reg, reg); + pr_debug_type_name(&tsr->type, tsr->kind); +} + +/* + * For load insns: propagate type from @src to @dreg, applying @reg_offset + * to the source struct's field offset. + */ +static int propagate_load_reg_state(struct type_state *state, + struct disasm_line *dl, int dreg, + struct annotated_op_loc *src, + int reg_offset, const char *insn_name) +{ + struct type_state_reg *tsr; + struct type_state_reg src_tsr; + Dwarf_Die type_die; + u32 insn_offset =3D dl->al.offset; + int sreg =3D src->reg1; + + if (!has_reg_type(state, dreg)) + return -1; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + +retry: + if (!has_reg_type(state, sreg) || !state->regs[sreg].ok) + return -1; + + src_tsr =3D state->regs[sreg]; + + /* Dereference the pointer if it has one */ + if (src_tsr.kind =3D=3D TSR_KIND_TYPE && + die_deref_ptr_type(&src_tsr.type, + src_tsr.offset + reg_offset, &type_die)) { + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->ok =3D true; + + if (src->multi_regs) { + pr_debug_dtp("%s [%x] %#x(reg%d, reg%d) -> reg%d", + insn_name, insn_offset, reg_offset, + src->reg1, src->reg2, dreg); + } else { + pr_debug_dtp("%s [%x] %#x(reg%d) -> reg%d", + insn_name, insn_offset, reg_offset, + sreg, dreg); + } + pr_debug_type_name(&tsr->type, tsr->kind); + return 0; + } + /* Or try another register if any */ + else if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->re= g2) { + sreg =3D src->reg2; + goto retry; + } + + return -1; +} + +static void update_load_insn_state(struct type_state *state, + struct disasm_line *dl, + struct annotated_op_loc *src, + struct annotated_op_loc *dst) +{ + int reg_offset =3D get_reg_index_offset(src); + const char *insn_name =3D dst->multi_regs ? "ldp" : "ldr"; + + if (!has_reg_type(state, dst->reg1) || + (dst->multi_regs && !has_reg_type(state, dst->reg2))) + goto out_err_adjust; + + /* Handle the first destination register */ + if (propagate_load_reg_state(state, dl, dst->reg1, src, + reg_offset, insn_name)) + goto out_err_adjust; + + /* Handle the second destination register (ldp only) */ + if (dst->multi_regs) { + int reg_size =3D arm64__reg_size(dl->ops.target.raw); + + if (reg_size < 0 || + propagate_load_reg_state(state, dl, dst->reg2, src, + reg_offset + reg_size, insn_name)) + goto out_err_adjust; + } + +out_adjust: + adjust_reg_index_state(state, src, insn_name, dl->al.offset); + return; + +out_err_adjust: + if (has_reg_type(state, dst->reg1)) + invalidate_reg_state(&state->regs[dst->reg1]); + if (dst->multi_regs && has_reg_type(state, dst->reg2)) + invalidate_reg_state(&state->regs[dst->reg2]); + goto out_adjust; +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) { struct annotated_insn_loc loc; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hHKtJ51fHzYQvlt; Sat, 8 Aug 2026 20:23:20 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id DAE044056B; Sat, 8 Aug 2026 20:24:18 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S17; Sat, 08 Aug 2026 20:24:18 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 15/23] perf annotate-arm64: Support store instruction tracking Date: Sat, 8 Aug 2026 12:23:52 +0000 Message-Id: <20260808122400.2961238-16-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S17 X-Coremail-Antispam: 1UD129KBjvJXoW7CFy7JFWkurWktFy7CF1xXwb_yoW8ZF4DpF Z0k34rtr47trs09Fn3JF4Igrya9a1fJr15Kry7tw4vyFWayrn3tFZ3KF43tFWrJrZxCw1U Aw4DKrs8J3y0kw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to handle store (STR) instructions. Unlike load instructions, a store instruction sets a value in the struct within the memory where the destination register resides, and does not alter its type. Therefore, no processing is required for the transfer. The only point to note is that store instructions support pre-index and post-index addressing modes, so calling adjust_reg_index_state() is still necessary to handle their addressing. Signed-off-by: Tengda Wu --- tools/perf/util/annotate-arch/annotate-arm64.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 6557c0ad11b2..ed0f0ef2877d 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -560,7 +560,7 @@ static void update_insn_state_arm64(struct type_state *= state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && - strncmp(dl->ins.name, "ld", 2)) { + strncmp(dl->ins.name, "ld", 2) && strncmp(dl->ins.name, "st", 2)) { pr_debug_dtp("%s [%x] invalidate reg%d", dl->ins.name, insn_offset, dst->reg1); invalidate_reg_state(&state->regs[dst->reg1]); @@ -575,6 +575,17 @@ static void update_insn_state_arm64(struct type_state = *state, /* Memory to register transfers */ if (!strncmp(dl->ins.name, "ld", 2)) update_load_insn_state(state, dl, src, dst); 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Sat, 8 Aug 2026 20:24:18 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S18; Sat, 08 Aug 2026 20:24:18 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 16/23] perf annotate-data: Expand type_state_reg imm_value to u64 Date: Sat, 8 Aug 2026 12:23:53 +0000 Message-Id: <20260808122400.2961238-17-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S18 X-Coremail-Antispam: 1UD129KBjvJXoW7Kry7KFW8ur4xuw1xZF1DZFb_yoW8XrW5p3 90kry7Jwn8Wrs0gwn3tFW5XrWfury3Z3WfGw15twn3AF4fJr93Jryxtr45tFW8W3srAw1U A3Z5Kr4Dta97GaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" The imm_value in struct type_state_reg is defined as u32, which limits the size of values it can pass. Promote imm_value from u32 to u64 and adjust the print format specifier in pr_debug_dtp() accordingly. Signed-off-by: Tengda Wu --- tools/perf/util/annotate-arch/annotate-x86.c | 2 +- tools/perf/util/annotate-data.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index ee4e3e7f3209..eec3d8ce00b8 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -540,7 +540,7 @@ static void update_insn_state_x86(struct type_state *st= ate, tsr->offset =3D 0; tsr->ok =3D true; =20 - pr_debug_dtp("mov [%x] imm=3D%#x -> reg%d\n", + pr_debug_dtp("mov [%x] imm=3D%#"PRIx64" -> reg%d\n", insn_offset, tsr->imm_value, dst->reg1); return; } diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index 453e13bbe3e2..91b83e94c51b 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -173,7 +173,7 @@ extern struct annotated_data_stat ann_data_stat; */ struct type_state_reg { Dwarf_Die type; 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Sat, 08 Aug 2026 20:24:18 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 17/23] perf annotate-data: Track imm_value for stack variables Date: Sat, 8 Aug 2026 12:23:54 +0000 Message-Id: <20260808122400.2961238-18-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S19 X-Coremail-Antispam: 1UD129KBjvJXoWxGF18uw17Jw1DGFyUGFW8Crg_yoW7Jr1Dpr yDWFy7W3W7Wr4IqrsxJF4UXr93Gws2gr1Fk3s0qFnayFyxtr1fG3srtFW5ta17Cryvyw17 Jwn0kr1DXw47KaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Currently, imm_value are tracked in registers but dropped when values are saved to or loaded from stack variables during type profiling. If a register of type TSR_KIND_CONST is stored to the stack, its value will be lost. Add an imm_value field to struct type_state_stack and update set_stack_state() and findnew_stack_state() to accept and preserve the immediate value when updating stack state. Signed-off-by: Tengda Wu Reviewed-by: Shuai Xue --- tools/perf/util/annotate-arch/annotate-x86.c | 8 ++++++-- tools/perf/util/annotate-data.c | 13 +++++++------ tools/perf/util/annotate-data.h | 5 +++-- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-x86.c b/tools/perf/util= /annotate-arch/annotate-x86.c index eec3d8ce00b8..995117525e7d 100644 --- a/tools/perf/util/annotate-arch/annotate-x86.c +++ b/tools/perf/util/annotate-arch/annotate-x86.c @@ -591,6 +591,7 @@ static void update_insn_state_x86(struct type_state *st= ate, tsr->type =3D stack->type; tsr->kind =3D stack->kind; tsr->offset =3D stack->ptr_offset; + tsr->imm_value =3D stack->imm_value; tsr->ok =3D true; } else if (die_get_member_type(&stack->type, offset - stack->offset, @@ -598,6 +599,7 @@ static void update_insn_state_x86(struct type_state *st= ate, tsr->type =3D type_die; tsr->kind =3D TSR_KIND_TYPE; tsr->offset =3D 0; + tsr->imm_value =3D 0; tsr->ok =3D true; } else { invalidate_reg_state(tsr); @@ -773,10 +775,12 @@ static void update_insn_state_x86(struct type_state *= state, */ if (!stack->compound) set_stack_state(stack, offset, tsr->kind, - &tsr->type, tsr->offset); + &tsr->type, tsr->offset, + tsr->imm_value); } else { findnew_stack_state(state, offset, tsr->kind, - &tsr->type, tsr->offset); + &tsr->type, tsr->offset, + tsr->imm_value); } =20 if (dst->reg1 =3D=3D fbreg) { diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index c51b20a7af9b..9dcdc3c7e688 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -590,7 +590,7 @@ struct type_state_stack *find_stack_state(struct type_s= tate *state, } =20 void set_stack_state(struct type_state_stack *stack, int offset, u8 kind, - Dwarf_Die *type_die, int ptr_offset) + Dwarf_Die *type_die, int ptr_offset, u64 imm_value) { int tag; Dwarf_Word size; @@ -607,8 +607,9 @@ void set_stack_state(struct type_state_stack *stack, in= t offset, u8 kind, stack->offset =3D offset; stack->ptr_offset =3D ptr_offset; stack->kind =3D kind; + stack->imm_value =3D imm_value; =20 - if (kind =3D=3D TSR_KIND_POINTER) { + if (kind =3D=3D TSR_KIND_POINTER || kind =3D=3D TSR_KIND_CONST) { stack->compound =3D false; return; } @@ -629,18 +630,18 @@ void set_stack_state(struct type_state_stack *stack, = int offset, u8 kind, struct type_state_stack *findnew_stack_state(struct type_state *state, int offset, u8 kind, Dwarf_Die *type_die, - int ptr_offset) + int ptr_offset, u64 imm_value) { struct type_state_stack *stack =3D find_stack_state(state, offset); =20 if (stack) { - set_stack_state(stack, offset, kind, type_die, ptr_offset); + set_stack_state(stack, offset, kind, type_die, ptr_offset, imm_value); return stack; } =20 stack =3D malloc(sizeof(*stack)); if (stack) { - set_stack_state(stack, offset, kind, type_die, ptr_offset); + set_stack_state(stack, offset, kind, type_die, ptr_offset, imm_value); list_add(&stack->list, &state->stack_vars); } return stack; @@ -935,7 +936,7 @@ static void update_var_state(struct type_state *state, = struct data_loc_info *dlo continue; =20 findnew_stack_state(state, offset, TSR_KIND_TYPE, - &mem_die, /*ptr_offset=3D*/0); + &mem_die, /*ptr_offset=3D*/0, /*imm_value=3D*/0); =20 if (var->reg =3D=3D state->stack_reg) { pr_debug_dtp("var [%"PRIx64"] %#x(reg%d)", diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index 91b83e94c51b..06fc4dbfb35c 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -199,6 +199,7 @@ struct type_state_stack { int size; bool compound; u8 kind; + u64 imm_value; }; =20 /* @@ -253,9 +254,9 @@ bool has_reg_type(struct type_state *state, int reg); struct type_state_stack *findnew_stack_state(struct type_state *state, int offset, u8 kind, Dwarf_Die *type_die, - int ptr_offset); + int ptr_offset, u64 imm_value); void set_stack_state(struct type_state_stack *stack, int offset, u8 kind, - Dwarf_Die *type_die, int ptr_offset); + Dwarf_Die *type_die, int ptr_offset, u64 imm_value); struct type_state_stack *find_stack_state(struct type_state *state, int offset); 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smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hHKvD0fbgzKHNH6; Sat, 8 Aug 2026 20:24:08 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 361EC4056D; Sat, 8 Aug 2026 20:24:19 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S20; Sat, 08 Aug 2026 20:24:18 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 18/23] perf annotate-arm64: Support stack variable tracking Date: Sat, 8 Aug 2026 12:23:55 +0000 Message-Id: <20260808122400.2961238-19-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S20 X-Coremail-Antispam: 1UD129KBjvJXoW3Xry3ArWfKFWrWFWDWr17Jrb_yoW3uw4xpF WDGa4rWrs7Jr4SgFsxJr4UJr93Ww4kKw1jkryDuws2yFy7tF1rKayvyayavFW5Gr97Zw15 Jw1DCr4DXw47taDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to track data types stored on the stack. This allows 'perf annotate' to maintain type information for local variables that are spilled to or loaded from stack slots. The implementation handles: 1. Stack Loads (LDR): Identify when a register is loaded from a stack slot and update the register's type state based on the tracked stack content or compound member types. 2. Stack Stores (STR): Update or create new stack state entries when a tracked register type is stored to the stack. Similar to loads, stores also support saving one or two registers (in the case of 'stp'). Therefore, propagate_store_reg_state() is introduced. The overall offset calculation follows the same logic as the load implementation: src->reg1: reg_offset =3D get_reg_index_offset() src->reg2: reg_offset =3D get_reg_index_offset() + reg_size(src->reg1) With these changes, the instruction tracker can now follow data types as they move between registers and memory, specifically for function local variables and compiler-spilled values on arm64. Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 161 ++++++++++++++++-- 1 file changed, 148 insertions(+), 13 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index ed0f0ef2877d..6e09e9707256 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -407,6 +407,7 @@ static void adjust_reg_index_state(struct type_state *s= tate, * to the source struct's field offset. */ static int propagate_load_reg_state(struct type_state *state, + struct data_loc_info *dloc, struct disasm_line *dl, int dreg, struct annotated_op_loc *src, int reg_offset, const char *insn_name) @@ -416,6 +417,8 @@ static int propagate_load_reg_state(struct type_state *= state, Dwarf_Die type_die; u32 insn_offset =3D dl->al.offset; int sreg =3D src->reg1; + int fbreg =3D dloc->fbreg; + int fboff =3D 0; =20 if (!has_reg_type(state, dreg)) return -1; @@ -423,7 +426,52 @@ static int propagate_load_reg_state(struct type_state = *state, tsr =3D &state->regs[dreg]; tsr->copied_from =3D -1; =20 + if (dloc->fb_cfa) { + u64 ip =3D dloc->ms->sym->start + dl->al.offset; + u64 pc =3D map__rip_2objdump(dloc->ms->map, ip); + + if (die_get_cfa(dloc->di->dbg, pc, &fbreg, &fboff) < 0) + fbreg =3D -1; + } + retry: + /* Check stack variables with offset */ + if (sreg =3D=3D fbreg || sreg =3D=3D state->stack_reg) { + struct type_state_stack *stack; + int offset =3D sreg =3D=3D fbreg ? reg_offset - fboff : reg_offset; + + stack =3D find_stack_state(state, offset); + if (stack =3D=3D NULL) { + return -1; + } else if (!stack->compound) { + tsr->type =3D stack->type; + tsr->kind =3D stack->kind; + tsr->offset =3D stack->ptr_offset; + tsr->imm_value =3D stack->imm_value; + tsr->ok =3D true; + } else if (die_get_member_type(&stack->type, + offset - stack->offset, + &type_die)) { + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->imm_value =3D 0; + tsr->ok =3D true; + } else { + return -1; + } + + if (sreg =3D=3D fbreg) { + pr_debug_dtp("%s [%x] -%#x(stack) -> reg%d", + insn_name, insn_offset, -offset, dreg); + } else { + pr_debug_dtp("%s [%x] %#x(reg%d) -> reg%d", + insn_name, insn_offset, offset, sreg, dreg); + } + pr_debug_type_name(&tsr->type, tsr->kind); + return 0; + } + if (!has_reg_type(state, sreg) || !state->regs[sreg].ok) return -1; =20 @@ -460,6 +508,7 @@ static int propagate_load_reg_state(struct type_state *= state, } =20 static void update_load_insn_state(struct type_state *state, + struct data_loc_info *dloc, struct disasm_line *dl, struct annotated_op_loc *src, struct annotated_op_loc *dst) @@ -472,7 +521,7 @@ static void update_load_insn_state(struct type_state *s= tate, goto out_err_adjust; =20 /* Handle the first destination register */ - if (propagate_load_reg_state(state, dl, dst->reg1, src, + if (propagate_load_reg_state(state, dloc, dl, dst->reg1, src, reg_offset, insn_name)) goto out_err_adjust; =20 @@ -481,7 +530,7 @@ static void update_load_insn_state(struct type_state *s= tate, int reg_size =3D arm64__reg_size(dl->ops.target.raw); =20 if (reg_size < 0 || - propagate_load_reg_state(state, dl, dst->reg2, src, + propagate_load_reg_state(state, dloc, dl, dst->reg2, src, reg_offset + reg_size, insn_name)) goto out_err_adjust; } @@ -498,6 +547,100 @@ static void update_load_insn_state(struct type_state = *state, goto out_adjust; } =20 +/* + * For store insns: propagate type from @sreg to the memory location + * referenced by @dreg, applying @reg_offset to the destination memory off= set. + */ +static int propagate_store_reg_state(struct type_state *state, + struct data_loc_info *dloc, + struct disasm_line *dl, int sreg, int dreg, + int reg_offset, const char *insn_name) +{ + struct type_state_reg *tsr; + u32 insn_offset =3D dl->al.offset; + int fbreg =3D dloc->fbreg; + int fboff =3D 0; + + if (!has_reg_type(state, sreg) || !state->regs[sreg].ok) + return -1; + + if (dloc->fb_cfa) { + u64 ip =3D dloc->ms->sym->start + dl->al.offset; + u64 pc =3D map__rip_2objdump(dloc->ms->map, ip); + + if (die_get_cfa(dloc->di->dbg, pc, &fbreg, &fboff) < 0) + fbreg =3D -1; + } + + /* Check stack variables with offset */ + if (dreg =3D=3D fbreg || dreg =3D=3D state->stack_reg) { + struct type_state_stack *stack; + int offset =3D dreg =3D=3D fbreg ? reg_offset - fboff : reg_offset; + + tsr =3D &state->regs[sreg]; + + stack =3D find_stack_state(state, offset); + if (stack) { + if (!stack->compound) + set_stack_state(stack, offset, tsr->kind, &tsr->type, + tsr->offset, tsr->imm_value); + /* + * If it's a compound type, it means attempting to + * write to a member value of the compound type without + * changing the compound type itself, so do nothing. + */ + } else { + findnew_stack_state(state, offset, tsr->kind, &tsr->type, + tsr->offset, tsr->imm_value); + } + + if (dreg =3D=3D fbreg) { + pr_debug_dtp("%s [%x] reg%d -> -%#x(stack)", + insn_name, insn_offset, sreg, -offset); + } else { + pr_debug_dtp("%s [%x] reg%d -> %#x(reg%d)", + insn_name, insn_offset, sreg, offset, dreg); + } + if (tsr->offset !=3D 0) { + pr_debug_dtp(" reg%d offset %#x ->", + sreg, tsr->offset); + } + pr_debug_type_name(&tsr->type, tsr->kind); + } + /* + * Ignore other transfers since it'd set a value in a struct + * and won't change the type. + */ + + return 0; +} + +static void update_store_insn_state(struct type_state *state, + struct data_loc_info *dloc, + struct disasm_line *dl, + struct annotated_op_loc *src, + struct annotated_op_loc *dst) +{ + int reg_offset =3D get_reg_index_offset(dst); + const char *insn_name =3D src->multi_regs ? "stp" : "str"; + + /* Handle the first source register */ + propagate_store_reg_state(state, dloc, dl, src->reg1, dst->reg1, + reg_offset, insn_name); + + /* Handle the second source register (stp only) */ + if (src->multi_regs) { + int reg_size =3D arm64__reg_size(dl->ops.source.raw); + + if (reg_size >=3D 0) + propagate_store_reg_state(state, dloc, dl, src->reg2, + dst->reg1, reg_offset + reg_size, + insn_name); + } + + adjust_reg_index_state(state, dst, insn_name, dl->al.offset); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -574,18 +717,10 @@ static void update_insn_state_arm64(struct type_state= *state, =20 /* Memory to register transfers */ if (!strncmp(dl->ins.name, "ld", 2)) - update_load_insn_state(state, dl, src, dst); + update_load_insn_state(state, dloc, dl, src, dst); /* Register to memory transfers */ - else if (!strncmp(dl->ins.name, "st", 2)) { - /* - * Ignore transfers since it'd set a value in a struct - * and won't change the type. - * - * Needs to update the pre-index and post-index addressing - * modes for the destination register. - */ - adjust_reg_index_state(state, dst, "str", insn_offset); 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Sat, 08 Aug 2026 20:24:18 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 19/23] perf annotate-arm64: Support 'mov' instruction tracking Date: Sat, 8 Aug 2026 12:23:56 +0000 Message-Id: <20260808122400.2961238-20-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S21 X-Coremail-Antispam: 1UD129KBjvJXoWxXryDZw1DKw48WF47Kw1fCrg_yoWrKrW3pa 4DC345G39Fqr42gFsIqFWUXr9a9w4xKr1jkryqvwnIyFy3tr1rKayktFWavF45Xry8Zw13 Gw4DKrZ8Xw42kF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to support register-to-register and immediate-to-register 'mov' instructions. For register-to-register 'mov' (e.g., mov dreg, sreg), propagate data type information from the source register to the destination register. For immediate-to-register 'mov' (e.g., mov dreg, #imm), store the immediate value in the destination register's imm_value field and set its kind to TSR_KIND_CONST, allowing subsequent instructions to resolve it as a constant. A real-world example is shown below: ffff8000803eebf8 : ffff8000803eec20: mov x21, x0 // x0 (struct vm_area_struct*) -= > x21 ffff8000803eec28: ldr x2, [x0, #112] ffff8000803eec2c: cbz x2, ffff8000803eec94 * ffff8000803eec94: ldr x0, [x21, #152] Before this commit, the type of x21 was unknown, causing the subsequent inference to fail: var [0] reg0 offset 0 type=3D'struct vm_area_struct*' size=3D0x8 chk [9c] reg21 offset=3D0x98 ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the type of x21 is correctly inferred as 'vm_area_struct= ': var [0] reg0 offset 0 type=3D'struct vm_area_struct*' size=3D0x8 mov [28] reg0 -> reg21 type=3D'struct vm_area_struct*' size=3D0x8 chk [9c] reg21 offset=3D0x98 ok=3D1 kind=3D1 (struct vm_area_struct*) : G= ood! found by insn track: 0x98(reg21) type-offset=3D0x98 final result: type=3D'struct vm_area_struct' size=3D0xb0 Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 53 ++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 6e09e9707256..7b780bad8c07 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include #include +#include #include #include #include @@ -484,6 +485,7 @@ static int propagate_load_reg_state(struct type_state *= state, tsr->type =3D type_die; tsr->kind =3D TSR_KIND_TYPE; tsr->offset =3D 0; + tsr->imm_value =3D 0; tsr->ok =3D true; =20 if (src->multi_regs) { @@ -641,6 +643,51 @@ static void update_store_insn_state(struct type_state = *state, adjust_reg_index_state(state, dst, insn_name, dl->al.offset); } =20 +static void update_mov_insn_state(struct type_state *state, + struct disasm_line *dl, + struct annotated_op_loc *src, + struct annotated_op_loc *dst) +{ + struct type_state_reg *tsr; + u32 insn_offset =3D dl->al.offset; + int sreg =3D src->reg1; + int dreg =3D dst->reg1; + + if (!has_reg_type(state, dreg)) + return; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + + if (src->imm) { + tsr->kind =3D TSR_KIND_CONST; + tsr->imm_value =3D src->offset; + tsr->offset =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("mov [%x] imm=3D%#"PRIx64" -> reg%d\n", + insn_offset, tsr->imm_value, dreg); + return; + } + + if (!has_reg_type(state, sreg) || !state->regs[sreg].ok) { + invalidate_reg_state(tsr); + return; + } + + tsr->type =3D state->regs[sreg].type; + tsr->kind =3D state->regs[sreg].kind; + tsr->imm_value =3D state->regs[sreg].imm_value; + tsr->offset =3D state->regs[sreg].offset; + tsr->ok =3D state->regs[sreg].ok; + + if (tsr->kind =3D=3D TSR_KIND_TYPE || tsr->kind =3D=3D TSR_KIND_POINTER) + tsr->copied_from =3D sreg; + + pr_debug_dtp("mov [%x] reg%d -> reg%d", insn_offset, sreg, dreg); + pr_debug_type_name(&tsr->type, tsr->kind); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -703,6 +750,7 @@ static void update_insn_state_arm64(struct type_state *= state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && + strcmp(dl->ins.name, "mov") && strncmp(dl->ins.name, "ld", 2) && strncmp(dl->ins.name, "st", 2)) { pr_debug_dtp("%s [%x] invalidate reg%d", dl->ins.name, insn_offset, dst->reg1); @@ -715,8 +763,11 @@ static void update_insn_state_arm64(struct type_state = *state, return; } =20 + /* Register to register or imm value to register transfers */ + if (!strcmp(dl->ins.name, "mov")) + update_mov_insn_state(state, dl, src, dst); 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Sat, 8 Aug 2026 20:24:19 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S22; Sat, 08 Aug 2026 20:24:19 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 20/23] perf annotate-arm64: Support 'add' instruction tracking Date: Sat, 8 Aug 2026 12:23:57 +0000 Message-Id: <20260808122400.2961238-21-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S22 X-Coremail-Antispam: 1UD129KBjvJXoW3XF1rAr4ftr43JFWxGF48WFg_yoW7Xryfpa 9I934UGrsrtrsFgFs3trWfXr9akrsrJF1jkr90qwnIyFyayr1rKa9xKrW2yFW5Gryfur17 Jw4DKrZ8Xw429aUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to track 'add' instructions for structure member address calculation, which commonly appear as: add dreg, base, #offset add dreg, base, reg2 (reg2 holds a constant) Unlike x86, the arm64 'add' instruction has an extra base register among its source operands. Therefore, in terms of propagating the data type, it is essentially performing a 'mov', except that before the 'mov', it first needs to be updated by adding the offset or reg2. A real-world example is shown below: ffff80008001c9a8 : ffff80008001c9c4: add x19, x0, #0xeb8 // x0 (task_struct*) + 0xeb8 ->= x19 * ffff80008001c9d0: ldr x0, [x19] Before this commit, the type flow broke at the 'add' instruction, leaving the subsequent load with no type information: chk [28] reg19 offset=3D0 ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the tracker correctly follows the member address calculation: var [0] reg0 offset 0 type=3D'struct task_struct*' add [1c] address of 0xeb8(reg0) -> reg19 type=3D'struct task_struct*' chk [28] reg19 offset=3D0 ok=3D1 kind=3D1 (struct task_struct*) : Good! found by insn track: 0(reg19) type-offset=3D0xeb8 final result: type=3D'struct task_struct' Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 87 ++++++++++++++++++- 1 file changed, 85 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 7b780bad8c07..eaeb4433fc3a 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -688,6 +688,87 @@ static void update_mov_insn_state(struct type_state *s= tate, pr_debug_type_name(&tsr->type, tsr->kind); } =20 +static void update_add_insn_state(struct type_state *state, + struct disasm_line *dl, + struct annotated_op_loc *src, + struct annotated_op_loc *dst) +{ + struct type_state_reg *tsr; + struct type_state_reg src_tsr; + u32 insn_offset =3D dl->al.offset; + int sreg =3D src->reg1; + int dreg =3D dst->reg1; + u64 imm_value; + + if (!has_reg_type(state, dreg)) + return; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + +retry: + if (!has_reg_type(state, sreg) || !state->regs[sreg].ok) { + invalidate_reg_state(tsr); + return; + } + + src_tsr =3D state->regs[sreg]; + + /* + * Handle 'add' instructions of the form: + * add dreg, base, #offset (immediate offset) + * add dreg, base, reg2 (reg2 holds a constant) + * + * For case 2, retrieve the constant value from reg2 + * and use it as the offset. + */ + imm_value =3D src->offset; + if (src->multi_regs) { + int reg2 =3D (sreg =3D=3D src->reg1) ? src->reg2 : src->reg1; + + if (!has_reg_type(state, reg2) || !state->regs[reg2].ok) { + /* Unable to resolve type for dst, bail out */ + invalidate_reg_state(tsr); + return; + } + if (state->regs[reg2].kind =3D=3D TSR_KIND_CONST) + imm_value =3D state->regs[reg2].imm_value; + } + + if (src_tsr.kind =3D=3D TSR_KIND_CONST) { + tsr->kind =3D src_tsr.kind; + tsr->imm_value =3D src_tsr.imm_value + imm_value; + tsr->offset =3D 0; + tsr->ok =3D src_tsr.ok; + + pr_debug_dtp("add [%x] imm %#"PRIx64"(reg%d) -> reg%d\n", + insn_offset, imm_value, sreg, dreg); + return; + } + + if (src_tsr.kind =3D=3D TSR_KIND_POINTER || + (src_tsr.kind =3D=3D TSR_KIND_TYPE && + dwarf_tag(&src_tsr.type) =3D=3D DW_TAG_pointer_type)) { + tsr->type =3D src_tsr.type; + tsr->kind =3D src_tsr.kind; + tsr->imm_value =3D src_tsr.imm_value; + tsr->offset =3D src_tsr.offset + imm_value; + tsr->ok =3D src_tsr.ok; + + pr_debug_dtp("add [%x] address of %#"PRIx64"(reg%d) -> reg%d", + insn_offset, imm_value, sreg, dreg); + pr_debug_type_name(&tsr->type, tsr->kind); + return; + } + + /* Try another register if any */ + if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->reg2) { + sreg =3D src->reg2; + goto retry; + } + invalidate_reg_state(tsr); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -750,7 +831,7 @@ static void update_insn_state_arm64(struct type_state *= state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && - strcmp(dl->ins.name, "mov") && + strcmp(dl->ins.name, "add") && strcmp(dl->ins.name, "mov") && strncmp(dl->ins.name, "ld", 2) && strncmp(dl->ins.name, "st", 2)) { pr_debug_dtp("%s [%x] invalidate reg%d", dl->ins.name, insn_offset, dst->reg1); @@ -763,8 +844,10 @@ static void update_insn_state_arm64(struct type_state = *state, return; } =20 + if (!strcmp(dl->ins.name, "add")) + update_add_insn_state(state, dl, src, dst); /* Register to register or imm value to register transfers */ - if (!strcmp(dl->ins.name, "mov")) + else if (!strcmp(dl->ins.name, "mov")) update_mov_insn_state(state, dl, src, dst); /* Memory to register transfers */ else if (!strncmp(dl->ins.name, "ld", 2)) --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DFCE379C24; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hHKvD3BrfzKHNJR; Sat, 8 Aug 2026 20:24:08 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 8F1BD409C8; Sat, 8 Aug 2026 20:24:19 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S23; Sat, 08 Aug 2026 20:24:19 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 21/23] perf annotate-arm64: Support 'adrp' instruction to track global variables Date: Sat, 8 Aug 2026 12:23:58 +0000 Message-Id: <20260808122400.2961238-22-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S23 X-Coremail-Antispam: 1UD129KBjvJXoW3AF4UZr1xXrWfGr13CF17ZFb_yoWfKw1DpF WDC34UWw47tr4SgFs3JFWUXr9a9ws7Ga4jkryqvwsayFW7trn3GayktFWavFW5GF95Zw13 Jw4DKr4DXw42kaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHFb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x02 67AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YV CY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY1x0264kExVAvwVAq07x20xyl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to track global variable types calculated via page-relative addressing. On arm64, global variables are typically accessed by first calculating the page address using 'adrp', followed by an 'add' or 'ldr' to get the specific symbol address. Without tracking 'adrp', the instruction tracker loses the base address, making it impossible to resolve global symbols and their associated DWARF types. Introduce TSR_KIND_GLOBAL_ADDR to represent a partial global address state. When encountering 'adrp', store the page-aligned target address in the register's type state. Upon a subsequent 'add' or 'ldr' instruction that references a TSR_KIND_GLOBAL_ADDR register, combine the page address with the immediate offset. A real-world example is shown below: ffff80008032e008 : ffff80008032e048: adrp x24, ffff80008202f000 ffff80008032e050: add x24, x24, #0xd40 * ffff80008032e078: ldr x0, [x24] Before this commit, x24 was unknown, leading to no type information: chk [70] reg24 offset=3D0 ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the tracker correctly follows the adrp/add flow: adrp [40] global addr=3D0xffff80008202f000 -> reg24 add [48] global 0xd40(reg24) -> reg24 chk [70] reg24 offset=3D0 ok=3D1 kind=3D7 global addr : Good! final result: type=3D'struct folio*' Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 82 +++++++++++++++++-- tools/perf/util/annotate-data.c | 25 +++++- tools/perf/util/annotate-data.h | 1 + 3 files changed, 98 insertions(+), 10 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index eaeb4433fc3a..7eb3bef26a64 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -408,7 +408,7 @@ static void adjust_reg_index_state(struct type_state *s= tate, * to the source struct's field offset. */ static int propagate_load_reg_state(struct type_state *state, - struct data_loc_info *dloc, + struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl, int dreg, struct annotated_op_loc *src, int reg_offset, const char *insn_name) @@ -500,6 +500,32 @@ static int propagate_load_reg_state(struct type_state = *state, pr_debug_type_name(&tsr->type, tsr->kind); return 0; } + /* Or check if it's a global variable */ + else if (src_tsr.kind =3D=3D TSR_KIND_GLOBAL_ADDR) { + u64 ip =3D dloc->ms->sym->start + dl->al.offset; + u64 addr =3D src_tsr.imm_value + reg_offset; + int offset; + + if (!get_global_var_type(cu_die, dloc, ip, addr, &offset, &type_die) || + !die_get_member_type(&type_die, offset, &type_die)) + return -1; + + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->imm_value =3D 0; + tsr->ok =3D true; + + if (src->multi_regs) { + pr_debug_dtp("%s [%x] global (reg%d, reg%d) -> reg%d", + insn_name, insn_offset, src->reg1, src->reg2, dreg); + } else { + pr_debug_dtp("%s [%x] global (reg%d) -> reg%d", + insn_name, insn_offset, sreg, dreg); + } + pr_debug_type_name(&tsr->type, tsr->kind); + return 0; + } /* Or try another register if any */ else if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->re= g2) { sreg =3D src->reg2; @@ -510,7 +536,7 @@ static int propagate_load_reg_state(struct type_state *= state, } =20 static void update_load_insn_state(struct type_state *state, - struct data_loc_info *dloc, + struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl, struct annotated_op_loc *src, struct annotated_op_loc *dst) @@ -523,7 +549,7 @@ static void update_load_insn_state(struct type_state *s= tate, goto out_err_adjust; =20 /* Handle the first destination register */ - if (propagate_load_reg_state(state, dloc, dl, dst->reg1, src, + if (propagate_load_reg_state(state, dloc, cu_die, dl, dst->reg1, src, reg_offset, insn_name)) goto out_err_adjust; =20 @@ -532,7 +558,7 @@ static void update_load_insn_state(struct type_state *s= tate, int reg_size =3D arm64__reg_size(dl->ops.target.raw); =20 if (reg_size < 0 || - propagate_load_reg_state(state, dloc, dl, dst->reg2, src, + propagate_load_reg_state(state, dloc, cu_die, dl, dst->reg2, src, reg_offset + reg_size, insn_name)) goto out_err_adjust; } @@ -735,14 +761,16 @@ static void update_add_insn_state(struct type_state *= state, imm_value =3D state->regs[reg2].imm_value; } =20 - if (src_tsr.kind =3D=3D TSR_KIND_CONST) { + if (src_tsr.kind =3D=3D TSR_KIND_CONST || src_tsr.kind =3D=3D TSR_KIND_GL= OBAL_ADDR) { tsr->kind =3D src_tsr.kind; + /* For 'adrp + add' pair: resolve the full global variable address. */ tsr->imm_value =3D src_tsr.imm_value + imm_value; tsr->offset =3D 0; tsr->ok =3D src_tsr.ok; =20 - pr_debug_dtp("add [%x] imm %#"PRIx64"(reg%d) -> reg%d\n", - insn_offset, imm_value, sreg, dreg); + pr_debug_dtp("add [%x] %s %#"PRIx64"(reg%d) -> reg%d\n", + insn_offset, src_tsr.kind =3D=3D TSR_KIND_CONST ? + "imm" : "global", imm_value, sreg, dreg); return; } =20 @@ -769,6 +797,39 @@ static void update_add_insn_state(struct type_state *s= tate, invalidate_reg_state(tsr); } =20 +static void update_adrp_insn_state(struct type_state *state, + struct disasm_line *dl, + struct annotated_op_loc *dst) +{ + struct type_state_reg *tsr; + u32 insn_offset =3D dl->al.offset; + int dreg =3D dst->reg1; + + if (!has_reg_type(state, dreg)) + return; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + + if (!dl->ops.source.addr) { + invalidate_reg_state(tsr); + return; + } + + tsr->kind =3D TSR_KIND_GLOBAL_ADDR; + /* + * Stores a partial page-relative address. The full absolute address + * of the global variable will be resolved when a subsequent 'add' or + * 'ldr' instruction consumes this register. + */ + tsr->imm_value =3D dl->ops.source.addr; + tsr->offset =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("adrp [%x] global addr=3D%#"PRIx64" -> reg%d\n", + insn_offset, tsr->imm_value, dreg); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -831,6 +892,7 @@ static void update_insn_state_arm64(struct type_state *= state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && + strcmp(dl->ins.name, "adrp") && strcmp(dl->ins.name, "add") && strcmp(dl->ins.name, "mov") && strncmp(dl->ins.name, "ld", 2) && strncmp(dl->ins.name, "st", 2)) { pr_debug_dtp("%s [%x] invalidate reg%d", @@ -844,14 +906,16 @@ static void update_insn_state_arm64(struct type_state= *state, return; } =20 - if (!strcmp(dl->ins.name, "add")) + if (!strcmp(dl->ins.name, "adrp")) + update_adrp_insn_state(state, dl, dst); + else if (!strcmp(dl->ins.name, "add")) update_add_insn_state(state, dl, src, dst); /* Register to register or imm value to register transfers */ else if (!strcmp(dl->ins.name, "mov")) update_mov_insn_state(state, dl, src, dst); /* Memory to register transfers */ else if (!strncmp(dl->ins.name, "ld", 2)) - update_load_insn_state(state, dloc, dl, src, dst); + update_load_insn_state(state, dloc, cu_die, dl, src, dst); /* Register to memory transfers */ else if (!strncmp(dl->ins.name, "st", 2)) update_store_insn_state(state, dloc, dl, src, dst); diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 9dcdc3c7e688..7fe5b979563f 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -70,6 +70,9 @@ void pr_debug_type_name(Dwarf_Die *die, enum type_state_k= ind kind) case TSR_KIND_CANARY: pr_info(" stack canary\n"); return; + case TSR_KIND_GLOBAL_ADDR: + pr_info(" global address\n"); + return; case TSR_KIND_TYPE: default: break; @@ -609,7 +612,8 @@ void set_stack_state(struct type_state_stack *stack, in= t offset, u8 kind, stack->kind =3D kind; stack->imm_value =3D imm_value; =20 - if (kind =3D=3D TSR_KIND_POINTER || kind =3D=3D TSR_KIND_CONST) { + if (kind =3D=3D TSR_KIND_POINTER || kind =3D=3D TSR_KIND_CONST || + kind =3D=3D TSR_KIND_GLOBAL_ADDR) { stack->compound =3D false; return; } @@ -1279,6 +1283,25 @@ static enum type_match_result check_matching_type(st= ruct type_state *state, if (dloc->op->offset < 0 && reg !=3D state->stack_reg && reg !=3D dloc->= fbreg) goto check_kernel; } + + if (state->regs[reg].kind =3D=3D TSR_KIND_GLOBAL_ADDR) { + u64 var_addr =3D state->regs[reg].imm_value + dloc->op->offset; + int var_offset; + + pr_debug_dtp("global addr"); + + /* + * The register holds the address of a global variable. Try to + * find the variable by the address and get its type. + */ + if (get_global_var_type(cu_die, dloc, dloc->ip, var_addr, + &var_offset, type_die)) { + dloc->type_offset =3D var_offset; + return PERF_TMR_OK; + } + /* No need to retry global variables */ + return PERF_TMR_BAIL_OUT; + } check_non_register: if (reg =3D=3D dloc->fbreg || reg =3D=3D state->stack_reg) { struct type_state_stack *stack; diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-dat= a.h index 06fc4dbfb35c..8158e43b30df 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -37,6 +37,7 @@ enum type_state_kind { TSR_KIND_PERCPU_POINTER, TSR_KIND_POINTER, TSR_KIND_CANARY, + TSR_KIND_GLOBAL_ADDR, }; =20 /** --=20 2.34.1 From nobody Tue Sep 29 11:19:33 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59DB83D3332; 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dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4hHKvD3tL3zKHNJv; Sat, 8 Aug 2026 20:24:08 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id A56ED4056E; Sat, 8 Aug 2026 20:24:19 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S24; Sat, 08 Aug 2026 20:24:19 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 22/23] perf annotate-arm64: Support per-cpu variable access tracking Date: Sat, 8 Aug 2026 12:23:59 +0000 Message-Id: <20260808122400.2961238-23-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S24 X-Coremail-Antispam: 1UD129KBjvJXoW3Xr15KrWDAF4kuw1kJFW8WFg_yoWxuw13p3 95KFyUG34Dtr47uws3try5XryF9397Jas2k34Yvw1avryIkr1UG397Kr15tFWUGF93A3W7 trZxtr47XrsFkaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHjb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E 14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7 xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Y z7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6x kF7I0E8cxan2IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8Ij28IcwCF 04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r 18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vI r41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr1j6r xdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY 6I8E87Iv6xkF7I0E14v26F4UJVW0obIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to handle per-cpu variable addressing. On arm64, per-cpu variables are accessed by adding a per-cpu offset (typically from the '__per_cpu_offset' array) to the address of a global variable or a local variable with '__percpu' modifier (e.g., 's32 __percpu *counters' in struct percpu_counter). This results in instruction patterns like: ldr x0, [x6, x5] // Pattern A: direct load per-cpu instance add x0, x6, x5 // Pattern B: compute per-cpu address where x6 holds the per-cpu offset retrieved from: adrp x4, add x4, x4, #offset // x4 =3D &__per_cpu_offset ldr x6, [x4, w0, sxtw #3] // x6 =3D __per_cpu_offset[cpu] and x5 is one of the following: case 1: global variable adrp x5, add x5, x5, #offset // x5 =3D &global_var case 2: local variable with '__percpu' modifier ldr x1, [x25, #32] // x1 =3D local_percpu_ptr To handle such cases: 1. Identify per-cpu base initialization: Detect 'adrp + ldr' pairs that resolve to the '__per_cpu_offset' symbol and mark the destination register as TSR_KIND_PERCPU_BASE. 2. Propagate type information: During subsequent 'ldr' or 'add' instructions, if one register is TSR_KIND_PERCPU_BASE, attempt to resolve the type from the other register. A real-world example is shown below: ffff8000808f2d28 : ffff8000808f2d38: adrp x2, ffff800082033000 ffff8000808f2d3c: add x5, x2, #0x3f8 // x5 =3D &__per_cpu_offs= et ffff8000808f2d44: adrp x2, ffff800081f73000 ffff8000808f2d48: add x2, x2, #0x6b8 // x2 =3D &cpu_pcc_subspa= ce_idx ffff8000808f2d6c: ldr x5, [x5, w0, sxtw #3] // x5 =3D __per_cpu_offse= t[cpu] * ffff8000808f2d80: ldr w23, [x5, x2] // per_cpu(cpu_pcc_subspa= ce_idx, cpu) Before this commit, the tracker could not link x5 back to a per-cpu context, resulting in an incorrect data type resolution: adrp [10] global addr=3D0xffff800082033000 -> reg2 add [14] global 0x3f8(reg2) -> reg5 adrp [1c] global addr=3D0xffff800081f73000 -> reg2 add [20] global 0x6b8(reg2) -> reg2 ldr [44] global (reg5, reg0) -> reg5 type=3D'long unsigned int[]' size=3D= 0x1000 chk [58] reg5 offset=3D0 ok=3D1 kind=3D1 (long unsigned int[]) : Good! found by insn track: 0(reg5, reg2) type-offset=3D0 final result: type=3D'long unsigned int' size=3D0x8 After this commit, the tracker correctly identifies the per-cpu flow and resolves the actual variable type: ldr [44] global (reg5, reg0) -> reg5 percpu base chk [58] reg5 offset=3D0 ok=3D1 kind=3D2 percpu var : retry chk [58] reg2 offset=3D0 ok=3D1 kind=3D7 global addr : Good! found by insn track: 0(reg5, reg2) type-offset=3D0 final result: type=3D'int' size=3D0x4 Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 61 ++++++++++++++++++- tools/perf/util/annotate-data.c | 24 +++++++- 2 files changed, 83 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index 7eb3bef26a64..b01fa6cf865f 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -12,6 +12,7 @@ #include "../disasm.h" #include "../annotate-data.h" #include "../debug.h" +#include "../dso.h" #include "../map.h" #include "../symbol.h" =20 @@ -505,13 +506,23 @@ static int propagate_load_reg_state(struct type_state= *state, u64 ip =3D dloc->ms->sym->start + dl->al.offset; u64 addr =3D src_tsr.imm_value + reg_offset; int offset; + u8 kind; + const char *var_name =3D NULL; + + /* it might be per-cpu offset */ + if (dso__kernel(map__dso(dloc->ms->map)) && + get_global_var_info(dloc, addr, &var_name, &offset) && + !strcmp(var_name, "__per_cpu_offset")) + kind =3D TSR_KIND_PERCPU_BASE; + else + kind =3D TSR_KIND_TYPE; =20 if (!get_global_var_type(cu_die, dloc, ip, addr, &offset, &type_die) || !die_get_member_type(&type_die, offset, &type_die)) return -1; =20 tsr->type =3D type_die; - tsr->kind =3D TSR_KIND_TYPE; + tsr->kind =3D kind; tsr->offset =3D 0; tsr->imm_value =3D 0; tsr->ok =3D true; @@ -526,6 +537,24 @@ static int propagate_load_reg_state(struct type_state = *state, pr_debug_type_name(&tsr->type, tsr->kind); return 0; } + /* Or check if it's a per-cpu access */ + else if (src_tsr.kind =3D=3D TSR_KIND_PERCPU_BASE) { + int reg2; + + if (!src->multi_regs || src->reg1 =3D=3D src->reg2 || + sreg =3D=3D src->reg2 /* retried */) + return -1; + + reg2 =3D src->reg2; + if (!has_reg_type(state, reg2) || !state->regs[reg2].ok || + (state->regs[reg2].kind !=3D TSR_KIND_GLOBAL_ADDR && + state->regs[reg2].kind !=3D TSR_KIND_TYPE)) + return -1; + + /* Treat percpu as array: resolve type from reg2 */ + sreg =3D src->reg2; + goto retry; + } /* Or try another register if any */ else if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->re= g2) { sreg =3D src->reg2; @@ -789,6 +818,36 @@ static void update_add_insn_state(struct type_state *s= tate, return; } =20 + if (src_tsr.kind =3D=3D TSR_KIND_PERCPU_BASE) { + int reg2; + + if (!src->multi_regs) { + invalidate_reg_state(tsr); + return; + } + + reg2 =3D (sreg =3D=3D src->reg1) ? src->reg2 : src->reg1; + + if (!has_reg_type(state, reg2) || !state->regs[reg2].ok || + (state->regs[reg2].kind !=3D TSR_KIND_GLOBAL_ADDR && + state->regs[reg2].kind !=3D TSR_KIND_TYPE)) { + invalidate_reg_state(tsr); + return; + } + + /* Treat percpu as array: inherit type from reg2 */ + tsr->type =3D state->regs[reg2].type; + tsr->kind =3D state->regs[reg2].kind; + tsr->offset =3D state->regs[reg2].offset; + tsr->imm_value =3D state->regs[reg2].imm_value; + tsr->ok =3D state->regs[reg2].ok; + + pr_debug_dtp("add [%x] percpu (reg%d, reg%d) -> reg%d", + insn_offset, src->reg1, src->reg2, dreg); + pr_debug_type_name(&tsr->type, tsr->kind); + return; + } + /* Try another register if any */ if (src->multi_regs && src->reg1 !=3D src->reg2 && sreg !=3D src->reg2) { sreg =3D src->reg2; diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index 7fe5b979563f..8b0584486cce 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -1253,11 +1253,33 @@ static enum type_match_result check_matching_type(s= truct type_state *state, } =20 if (state->regs[reg].kind =3D=3D TSR_KIND_PERCPU_BASE) { - u64 var_addr =3D dloc->op->offset; + u64 var_addr; int var_offset; =20 pr_debug_dtp("percpu var"); =20 + if (arch__is_arm64(dloc->arch)) { + int reg2; + + if (!dloc->op->multi_regs || + dloc->op->reg1 =3D=3D dloc->op->reg2 || !retry) + return PERF_TMR_BAIL_OUT; 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Sat, 8 Aug 2026 20:24:19 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgB34YjkH3dqbrhMBg--.41805S25; Sat, 08 Aug 2026 20:24:19 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v4 23/23] perf annotate-arm64: Support 'mrs' instruction to track 'current' pointer Date: Sat, 8 Aug 2026 12:24:00 +0000 Message-Id: <20260808122400.2961238-24-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260808122400.2961238-1-wutengda@huaweicloud.com> References: <20260808122400.2961238-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgB34YjkH3dqbrhMBg--.41805S25 X-Coremail-Antispam: 1UD129KBjvJXoW3JrW3KFykCr4xKw1DKryxAFb_yoWxJw4fpa yDC34DGrs7Jw4aganxJFWUZryfK393Ww15Kr90ywsayF47Kr1xK3WktFW2kay5Jr95uw17 Jr4DKrs8Ww42vF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHjb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVWxJr0_GcWl84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E 14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7 xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Y z7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6x kF7I0E8cxan2IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8Ij28IcwCF 04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r 18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vI r41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr1j6r xdMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY 6I8E87Iv6xkF7I0E14v26F4UJVW0obIYCTnIWIevJa73UjIFyTuYvjTRQYFCDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" Extend update_insn_state() for arm64 to handle the 'mrs' instruction, enabling the tracking of the 'current' task pointer in the kernel. On arm64, the kernel uses the 'sp_el0' system register to store the address of the currently executing 'struct task_struct'. This is typically accessed via the 'get_current()' inline function, resulting in the instruction 'mrs xN, sp_el0'. To resolve the data type of the target register, first verify the access is to 'sp_el0' within a kernel DSO. Then, locate the 'get_current()' inline function's DWARF Die at the current PC and extract its return type (which is 'struct task_struct *'). Introduce 'task_struct_cache' to cache the DWARF offset of task_struct alongside its corresponding dbg handle. This is particularly important because the compiler-generated stack canary check code (which loads from 'current->stack_canary') often exists in code sections or leaf functions where the local Compilation Unit (CU) lacks a full 'struct task_struct' definition. Caching the offset allows 'perf annotate' to consistently resolve task-related fields across the entire kernel binary. A real-world example is shown below: ffff8000800deee8 : ffff8000800deef0: mrs x0, sp_el0 // x0 =3D current * ffff8000800deef4: ldr w1, [x0, #44] Before this commit, the type flow starts with no information: chk [c] reg0 offset=3D0x2c ok=3D0 kind=3D0 cfa : no type information final result: no type information After this commit, the tracker identifies the 'current' pointer from the system register: mrs [8] sp_el0 -> reg0 type=3D'struct task_struct*' chk [c] reg0 offset=3D0x2c ok=3D1 kind=3D1 (struct task_struct*) : Good! found by insn track: 0x2c(reg0) type-offset=3D0x2c final result: type=3D'struct task_struct' Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 97 ++++++++++++++++++- 1 file changed, 95 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/ut= il/annotate-arch/annotate-arm64.c index b01fa6cf865f..9d1f315dcb28 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -15,6 +15,7 @@ #include "../dso.h" #include "../map.h" #include "../symbol.h" +#include "../strbuf.h" =20 struct arch_arm64 { struct arch arch; @@ -889,6 +890,96 @@ static void update_adrp_insn_state(struct type_state *= state, insn_offset, tsr->imm_value, dreg); } =20 +static struct { + Dwarf_Off dieoff; + Dwarf *dbg; +} task_struct_cache; + +static void update_mrs_insn_state(struct type_state *state, + struct data_loc_info *dloc, Dwarf_Die *cu_die, + struct disasm_line *dl, + struct annotated_op_loc *dst) +{ + struct type_state_reg *tsr; + Dwarf_Die type_die; + u32 insn_offset =3D dl->al.offset; + int dreg =3D dst->reg1; + Dwarf_Die func_die; + Dwarf_Attribute attr; + u64 ip, pc; + + if (!has_reg_type(state, dreg)) + return; + + tsr =3D &state->regs[dreg]; + tsr->copied_from =3D -1; + + /* Handle case difference: LLVM (SP_EL0) vs objdump (sp_el0) */ + if (!dso__kernel(map__dso(dloc->ms->map)) || + strcasecmp(dl->ops.source.raw, "sp_el0")) { + invalidate_reg_state(tsr); + return; + } + + ip =3D dloc->ms->sym->start + dl->al.offset; + pc =3D map__rip_2objdump(dloc->ms->map, ip); + + /* + * Invalidate cached DIE offset if the debug info handle changed + * (e.g. switching between vmlinux and a kernel module). + */ + if (task_struct_cache.dbg !=3D dloc->di->dbg) { + task_struct_cache.dieoff =3D 0; + task_struct_cache.dbg =3D dloc->di->dbg; + } + + if (!task_struct_cache.dieoff || + !dwarf_offdie(dloc->di->dbg, task_struct_cache.dieoff, &type_die)) { + struct strbuf sb; + char *type_name; + /* + * Find the inline function 'get_current()' Dwarf_Die + * and obtain its return value data type, which should + * be 'struct task_struct*'. + */ + if (!die_find_inlinefunc(cu_die, pc, &func_die) || + !die_compare_name(&func_die, "get_current") || + !dwarf_attr_integrate(&func_die, DW_AT_type, &attr) || + !dwarf_formref_die(&attr, &type_die)) { + invalidate_reg_state(tsr); + return; + } + + strbuf_init(&sb, 32); + die_get_typename_from_type(&type_die, &sb); + type_name =3D strbuf_detach(&sb, NULL); + + if (!type_name || strcmp(type_name, "struct task_struct*")) { + invalidate_reg_state(tsr); + free(type_name); + return; + } + + /* + * Cache the 'struct task_struct*' die offset globally. + * This allows us to resolve stack canary accesses even + * in CUs that lack a full task_struct definition (e.g., + * compiler-generated entry/exit code). + */ + task_struct_cache.dieoff =3D dwarf_dieoffset(&type_die); + free(type_name); + } + + tsr->type =3D type_die; + tsr->kind =3D TSR_KIND_TYPE; + tsr->offset =3D 0; + tsr->imm_value =3D 0; + tsr->ok =3D true; + + pr_debug_dtp("mrs [%x] sp_el0 -> reg%d", insn_offset, dreg); + pr_debug_type_name(&type_die, tsr->kind); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -951,7 +1042,7 @@ static void update_insn_state_arm64(struct type_state = *state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && - strcmp(dl->ins.name, "adrp") && + strcmp(dl->ins.name, "mrs") && strcmp(dl->ins.name, "adrp") && strcmp(dl->ins.name, "add") && strcmp(dl->ins.name, "mov") && strncmp(dl->ins.name, "ld", 2) && strncmp(dl->ins.name, "st", 2)) { pr_debug_dtp("%s [%x] invalidate reg%d", @@ -965,7 +1056,9 @@ static void update_insn_state_arm64(struct type_state = *state, return; } =20 - if (!strcmp(dl->ins.name, "adrp")) + if (!strcmp(dl->ins.name, "mrs")) + update_mrs_insn_state(state, dloc, cu_die, dl, dst); + else if (!strcmp(dl->ins.name, "adrp")) update_adrp_insn_state(state, dl, dst); else if (!strcmp(dl->ins.name, "add")) update_add_insn_state(state, dl, src, dst); --=20 2.34.1