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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a1e7cae4d1sm857274a12.11.2026.08.07.11.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:17 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 01/19] iommufd: Convert struct iommufd_sw_msi_maps to a growable bitmap Date: Fri, 7 Aug 2026 20:16:55 +0200 Message-ID: <20260807181713.228535-2-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: vtyOH2CqJUZPAHbpul5yHzkB35MRjcyH X-Proofpoint-GUID: vtyOH2CqJUZPAHbpul5yHzkB35MRjcyH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX6PVmbC3tMlfR 5Jzn3KROdfufk1AuM1vsl8EBQ9qhZkoSkl2zpTgv6XD+Jmkd3NBflQe8w5rfQyNSZYCm1SEVMH5 ZlCJ1ZOrp0/ZPKliq7bDpFTK827+YkNRU3O/uGQN9TS3izH7+6qTDWj7OuQDhd0OfShkvp6SsrI ZQQgxgcHQushylF2kkssSZtFhSdZrh0/xQMrsTu2fKvp+UPzhZ/XF7MZH2Rxzz1WM+ij6+E6HO5 vzSgWIOteMsK8J335el/7z1y2eFEnn7Ql2xk4ibQ9SDhaYNn3rdNGnRx5YxXj77X2CQsS+xi40m JXU3BPJ+7q8z0ZdedmGWbJbBHxxlSC4THz+m5BKhl2keoesYlgA7CAjpes7q3m7DGzuw62yw2gt Y21C/AOIPLzh7ZOBls4BroMv2lvDW+qgoluLeuqmFpgmhi1w08gcx2PA6ivYqm5pBs++1ZkDM91 eM2CgVh19cqwf5Xxo6w== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXxiMHIgxPJQZ2 egPbQhruT1fii3RbSSJnN1n4qn6D1z9lWbEyDZQJ91B1+3ayo7lyHmZg0dHvLrmcE0549d1vfs4 n6H2XNhyZ6fNvQkdpcW+/YwLUgwnSt8= X-Authority-Analysis: v=2.4 cv=YJevDxGx c=1 sm=1 tr=0 ts=6a76212f cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=sJeJdZliiPf9M_nNF58A:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" struct iommufd_sw_msi_maps currently uses a fixed 64-bit bitmap, capping the number of distinct SW MSI mappings a context or hwpt can track. An upcoming caller needs one mapping per possible CPU. Convert the fixed bitmap to a pointer plus size that grows on demand via iommufd_sw_msi_maps_ensure(). Add iommufd_sw_msi_maps_test_bit() alongside it: unlike the __set_bit() call sites, which always follow their own successful iommufd_sw_msi_maps_ensure() call on the same id, iommufd_group_setup_msi() tests an id from the fd-global sw_msi_list against a specific group's required_sw_msi map, which may not have been grown to cover that id yet. The bitmap is arbitrarily capped at 16K entries in order to simplify arithmetic validation (i.e. simple bounds checks vs. integer wrap control). Signed-off-by: Andrew Jones --- drivers/iommu/iommufd/device.c | 3 +- drivers/iommu/iommufd/driver.c | 38 +++++++++++++++-------- drivers/iommu/iommufd/hw_pagetable.c | 1 + drivers/iommu/iommufd/iommufd_private.h | 41 +++++++++++++++++++++++-- 4 files changed, 67 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index 170a7005f0bc..402251c7b887 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -34,6 +34,7 @@ static void iommufd_group_release(struct kref *kref) NULL, GFP_KERNEL); iommu_group_put(igroup->group); mutex_destroy(&igroup->lock); + kfree(igroup->required_sw_msi.bitmap); kfree(igroup); } =20 @@ -384,7 +385,7 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, int rc; =20 if (cur->sw_msi_start !=3D igroup->sw_msi_start || - !test_bit(cur->id, igroup->required_sw_msi.bitmap)) + !iommufd_sw_msi_maps_test_bit(&igroup->required_sw_msi, cur->id)) continue; =20 rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, cur); diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 3b8067976eac..9b9316ae4266 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -196,13 +196,15 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys= _addr_t msi_addr, list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { if (cur->sw_msi_start !=3D sw_msi_start) continue; + if (cur->pgoff =3D=3D UINT_MAX) + return ERR_PTR(-EOVERFLOW); max_pgoff =3D max(max_pgoff, cur->pgoff + 1); if (cur->msi_addr =3D=3D msi_addr) return cur; } =20 - if (ictx->sw_msi_id >=3D - BITS_PER_BYTE * sizeof_field(struct iommufd_sw_msi_maps, bitmap)) + if (ictx->sw_msi_id > IOMMUFD_SW_MSI_MAX_ID || + max_pgoff > (ULONG_MAX - sw_msi_start) / PAGE_SIZE) return ERR_PTR(-EOVERFLOW); =20 cur =3D kzalloc_obj(*cur); @@ -222,21 +224,26 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, struct iommufd_sw_msi_map *msi_map) { unsigned long iova; + int rc; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 + if (iommufd_sw_msi_maps_test_bit(&hwpt_paging->present_sw_msi, + msi_map->id)) + return 0; + iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; - if (!test_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap)) { - int rc; - - rc =3D iommu_map(hwpt_paging->common.domain, iova, - msi_map->msi_addr, PAGE_SIZE, - IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, - GFP_KERNEL_ACCOUNT); - if (rc) - return rc; - __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); - } + rc =3D iommufd_sw_msi_maps_ensure(&hwpt_paging->present_sw_msi, msi_map->= id); + if (rc) + return rc; + + rc =3D iommu_map(hwpt_paging->common.domain, iova, + msi_map->msi_addr, PAGE_SIZE, + IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, + GFP_KERNEL_ACCOUNT); + if (rc) + return rc; + __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); return 0; } EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); @@ -290,6 +297,11 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, if (IS_ERR(msi_map)) return PTR_ERR(msi_map); =20 + rc =3D iommufd_sw_msi_maps_ensure(&handle->idev->igroup->required_sw_msi, + msi_map->id); + if (rc) + return rc; + rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, msi_map); if (rc) return rc; diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/h= w_pagetable.c index 623cc608ca0c..54873de43eb0 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -32,6 +32,7 @@ void iommufd_hwpt_paging_destroy(struct iommufd_object *o= bj) } =20 __iommufd_hwpt_destroy(&hwpt_paging->common); + kfree(hwpt_paging->present_sw_msi.bitmap); refcount_dec(&hwpt_paging->ioas->obj.users); } =20 diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommuf= d/iommufd_private.h index 43fbc5bed8de..9ca5f9f92cdf 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -29,11 +30,47 @@ struct iommufd_sw_msi_map { unsigned int id; }; =20 -/* Bitmap of struct iommufd_sw_msi_map::id */ +/* Bitmap of struct iommufd_sw_msi_map::id; starts empty, grows on demand.= */ struct iommufd_sw_msi_maps { - DECLARE_BITMAP(bitmap, 64); + unsigned long *bitmap; + unsigned int nbits; }; =20 +/* Large enough for foreseeable SW MSI users while bounding bitmap growth.= */ +#define IOMMUFD_SW_MSI_MAX_ID (16U * 1024 - 1) + +/* Grow bitmap to accommodate id. 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a1e7d7648dsm828368a12.30.2026.08.07.11.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:19 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 02/19] iommufd: Add iommufd_sw_map_msi() Date: Fri, 7 Aug 2026 20:16:56 +0200 Message-ID: <20260807181713.228535-3-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX9KVNnSCxqIVs eBEUcGEQ2+Y9+flOFSZeee3zLT8y7q9dIUWhEQsGnviXMVCYxn0Z0gRTBlFMgnga9ZMrb+JPLEI 6nSNEo5zqAU+TybrdDd91XWVCEVkaXHhaILOKiYfltgHAWZNj20GmEdZ7G2Zso3SPls4QILLiN9 KJnqUhT/y3m9XuaBboTy+LgFydC5X79e2PKo0pPYSeUW2PLjZc8PzF5+K5FzvP0nRKIUW3ID/9C 566IkPMRLi5YYaKsrXu4B+oXduSZwv3qCbTvCRw0sj72GmWfhQGFbLbsZTT3X4BZRgIcQNQTEBp sQqkjp/KRLs+n2Uu/pYXpT9bCechLiTzxkZNttEmPJIBUgKFpLXUPU36moE7/1d5wFXd2f2dpSK bUqACOdEq8J5IGeHslpFbKMQH+fulJ7Wna9aPzEb5v7oilzIEa9sKiI0iYOZVRk//IjbWLFnqsA l0NmWeT+0aCAH9ZdVwg== X-Authority-Analysis: v=2.4 cv=QsBuG1yd c=1 sm=1 tr=0 ts=6a762132 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=5IMjXt7tboKol454yg4A:9 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXzkPihi+5yQfp I0Ayjb18ygAJvd96+GKZ86SbXvvBwuVR62YfA2mcP1616Uk5aCm7CBm7CLnjSFL9DVB2JpULMrb ABYwO+bZKFIkamhykMH+NuSZI+mEfAQ= X-Proofpoint-ORIG-GUID: NvrUS4W2erxYu2Q9QOEwRSUp5tsNg3qD X-Proofpoint-GUID: NvrUS4W2erxYu2Q9QOEwRSUp5tsNg3qD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" Add a descriptor-free counterpart to iommufd_sw_msi(). The existing function is tied to a struct msi_desc and stores the result in the descriptor. This variant returns the IOVA directly so callers can pre-map MSI targets before any descriptor has been allocated. Signed-off-by: Andrew Jones --- drivers/iommu/iommu-priv.h | 11 +++++++ drivers/iommu/iommufd/driver.c | 60 +++++++++++++++++++++++++--------- 2 files changed, 56 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index aaffad5854fc..f60373cd2f70 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -55,12 +55,23 @@ int iommu_replace_group_handle(struct iommu_group *grou= p, #if IS_ENABLED(CONFIG_IOMMUFD_DRIVER_CORE) && IS_ENABLED(CONFIG_IRQ_MSI_IO= MMU) int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, phys_addr_t msi_addr); +int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, + phys_addr_t msi_addr, size_t required_size, + dma_addr_t *msi_iova, unsigned int *msi_shift); #else /* !CONFIG_IOMMUFD_DRIVER_CORE || !CONFIG_IRQ_MSI_IOMMU */ static inline int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, phys_addr_t msi_addr) { return -EOPNOTSUPP; } + +static inline int iommufd_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + return -EOPNOTSUPP; +} #endif /* CONFIG_IOMMUFD_DRIVER_CORE && CONFIG_IRQ_MSI_IOMMU */ =20 int iommu_replace_device_pasid(struct iommu_domain *domain, diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 9b9316ae4266..69b3dbcbee3b 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -249,15 +249,23 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); =20 /* - * Called by the irq code if the platform translates the MSI address throu= gh the - * IOMMU. msi_addr is the physical address of the MSI page. iommufd will - * allocate a fd global iova for the physical page that is the same on all - * domains and devices. + * Descriptor-free counterpart to iommufd_sw_msi(). Maps an MSI physical p= age + * into the domain and returns the IOVA. Used for pre-mapping MSI targets = before + * any MSI descriptor has been set (e.g. IMSIC doorbell pages). The IOVA is + * global to the iommufd file descriptor: every domain and device using the + * same MSI parameters gets the same IOVA. + * + * msi_addr is the exact byte offset of the MSI doorbell; the caller must = have + * verified it is contained within an MMIO region safe to map at PAGE_SIZE= . If + * required_size is non-zero it must equal PAGE_SIZE. @msi_iova and @msi_s= hift + * must be non-NULL. + * + * The caller must hold @dev's iommu group mutex. */ -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) +int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, + phys_addr_t msi_addr, size_t required_size, + dma_addr_t *msi_iova, unsigned int *msi_shift) { - struct device *dev =3D msi_desc_to_dev(desc); struct iommufd_hwpt_paging *hwpt_paging; struct iommu_attach_handle *raw_handle; struct iommufd_attach_handle *handle; @@ -266,6 +274,12 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, unsigned long iova; int rc; =20 + *msi_iova =3D 0; + *msi_shift =3D 0; + + if (required_size && required_size !=3D PAGE_SIZE) + return -EOPNOTSUPP; + /* * It is safe to call iommu_attach_handle_get() here because the iommu * core code invokes this under the group mutex which also prevents any @@ -286,13 +300,7 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, =20 ictx =3D handle->idev->ictx; guard(mutex)(&ictx->sw_msi_lock); - /* - * The input msi_addr is the exact byte offset of the MSI doorbell, we - * assume the caller has checked that it is contained with a MMIO region - * that is secure to map at PAGE_SIZE. - */ - msi_map =3D iommufd_sw_msi_get_map(handle->idev->ictx, - msi_addr & PAGE_MASK, + msi_map =3D iommufd_sw_msi_get_map(ictx, msi_addr & PAGE_MASK, handle->idev->igroup->sw_msi_start); if (IS_ERR(msi_map)) return PTR_ERR(msi_map); @@ -308,7 +316,29 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, __set_bit(msi_map->id, handle->idev->igroup->required_sw_msi.bitmap); =20 iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; - msi_desc_set_iommu_msi_iova(desc, iova, PAGE_SHIFT); + *msi_iova =3D iova; + *msi_shift =3D PAGE_SHIFT; + return 0; +} +EXPORT_SYMBOL_NS_GPL(iommufd_sw_map_msi, "IOMMUFD"); + +/* + * Called by the irq layer when the platform translates MSI addresses thro= ugh + * the IOMMU. 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080ab446bsm79425666b.27.2026.08.07.11.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:21 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 03/19] iommu/dma: Add iommu_dma_sw_map_msi() Date: Fri, 7 Aug 2026 20:16:57 +0200 Message-ID: <20260807181713.228535-4-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXxrmyh3WLqECM mKR3x+hpw+nw0l9dwPExHEcy6OyrbudbOzpHshnjKWupg3imaENq2jwHGSPFCLY6zrvloCc9kcu 1v00dwTbu5JYnYsJTTCBkESXjAdx+6Ga37JdewCwXWq9g4RsciEKeEnHK7Jypd4C4Vv7oDIK0Ty FEsmg0VngBPntzj0mKu8MQB39js3eCFwHFSxSVLUer6YYpaa/2L2UzLpKWe92Tq6dzaEu3akciZ J3Z+mKyuWZesB6khpK0x66dSmwNYxgpitzSM+9lR9BKt26OfFOOKCL3Zl2huaqSt6KOC73mAK6I SK/bk2pNu4zfhhR27kEus1LWD6elrL6gsr3tc8RDDlc3FSAR5xuFQXeveot9NV7/oXlMGPI5Gew 7AhN45ImMKTjP8gCvgFRlxyFpx/TbbnWSpBCWFhBIboalPyv2xQs9O7zolOvNM3rjKFzbePowIA k+upvR19d8tjvIgZG8Q== X-Authority-Analysis: v=2.4 cv=QsBuG1yd c=1 sm=1 tr=0 ts=6a762133 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=B9hF7e9JpKM1iJhnVVUA:9 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX9vEGjNZVfFoG /gPrFhUixYZj/Jgv53siXCbmqnkdjK5JcRzfhWfrhkXbgwhSlf1PhIPHXGzdJtCwvZkxm6h8ypJ XX5b8Rag6fI/D7qop78BvdI0QrRL300= X-Proofpoint-ORIG-GUID: jlfESNxk3S8bgq412mnwsfYXBejXO6qx X-Proofpoint-GUID: jlfESNxk3S8bgq412mnwsfYXBejXO6qx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" Add a descriptor-free counterpart to iommu_dma_sw_msi(). The existing function is tied to a struct msi_desc and stores the result in the descriptor. This variant returns the IOVA directly so callers can pre-map MSI targets before any descriptor has been allocated. Callers may pass a required mapping size so MSI doorbells that must not share a larger IOMMU leaf, such as RISC-V IMSIC files, can fail before a mapping is installed. Signed-off-by: Andrew Jones --- drivers/iommu/dma-iommu.c | 48 ++++++++++++++++++++++++++++++++------- drivers/iommu/dma-iommu.h | 12 ++++++++++ 2 files changed, 52 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9abaec0703ef..56a5072b4dde 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2234,24 +2234,56 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi= _page(struct device *dev, return NULL; } =20 -int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) +/* + * Descriptor-free counterpart to iommu_dma_sw_msi(). Maps an MSI physical + * page into the domain and returns the IOVA and mapping granule. Used for + * pre-mapping MSI targets before any MSI descriptor has been set. + * + * The caller must pass a device attached to @domain and hold @dev's IOMMU + * group mutex. If @required_size is non-zero then it must exactly match t= he + * domain's MSI mapping granule. @msi_iova and @msi_shift must be non-NULL. + */ +int iommu_dma_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) { - struct device *dev =3D msi_desc_to_dev(desc); const struct iommu_dma_msi_page *msi_page; + size_t size; =20 - if (!has_msi_cookie(domain)) { - msi_desc_set_iommu_msi_iova(desc, 0, 0); + *msi_iova =3D 0; + *msi_shift =3D 0; + + if (!has_msi_cookie(domain)) return 0; - } + + size =3D cookie_msi_granule(domain); + if (required_size && size !=3D required_size) + return -EOPNOTSUPP; =20 iommu_group_mutex_assert(dev); msi_page =3D iommu_dma_get_msi_page(dev, msi_addr, domain); if (!msi_page) return -ENOMEM; =20 - msi_desc_set_iommu_msi_iova(desc, msi_page->iova, - ilog2(cookie_msi_granule(domain))); + *msi_iova =3D msi_page->iova; + *msi_shift =3D ilog2(size); + return 0; +} + +int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, + phys_addr_t msi_addr) +{ + struct device *dev =3D msi_desc_to_dev(desc); + dma_addr_t msi_iova; + unsigned int msi_shift; + int ret; + + ret =3D iommu_dma_sw_map_msi(domain, dev, msi_addr, 0, &msi_iova, &msi_sh= ift); + if (ret) + return ret; + + msi_desc_set_iommu_msi_iova(desc, msi_iova, msi_shift); return 0; } =20 diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 040d00252563..3e1adeafdcac 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -19,6 +19,10 @@ int iommu_dma_init_fq(struct iommu_domain *domain); =20 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list= ); =20 +int iommu_dma_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift); int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, phys_addr_t msi_addr); =20 @@ -53,6 +57,14 @@ static inline void iommu_dma_get_resv_regions(struct dev= ice *dev, struct list_he { } =20 +static inline int iommu_dma_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + return -ENODEV; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080a2b1f1sm82039066b.12.2026.08.07.11.17.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:23 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 04/19] iommu/dma: Add iommu_dma_map_msi() Date: Fri, 7 Aug 2026 20:16:58 +0200 Message-ID: <20260807181713.228535-5-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=RKaD2Yi+ c=1 sm=1 tr=0 ts=6a762136 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=nir-2xX3lSHJcyBuNR8A:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXwLpOllUdON76 WVn2S9B1OxITIMeZK6avwJOxVk8OJ0bx2ehoOQJrEwaZZML1YcZWyoa2obVPo+UVQrAAlm/bUoy yFe3sHN75inc9CkVNsczGG5SGcy6Sq8= X-Proofpoint-ORIG-GUID: 90kAGqSpGAZBlgqhtwU9fbUcjvgsDJdL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX78LFKO47toxI sWgze+EkSDfadbQ/VIee106uSRQ1KdjiZsmRt/INv4lEExJIfRrEnJDB7/AMIUztJxTsTbmXHuy LMjd0ZYxPXwTEirJk50mxGzc4TO+Pors/JZmh2G2d+dOC0DHfGrvJNls+QU6VzG1NQBuCaBAJP9 T7sv5EDJTAjjPz4vD/EsondCodCpPrj79xe/rwnrEartNjqNZSR4m3dLSkMg+Np4bNMlYHwhl8q +0YMWYhl8U/sZR9xJ/2d6+dOupTdhTPfwoHwk7xvrGDpxw3OCrWrlxP1fDAzCDXGHeYcEaOoUJK mcq+PiK+1EvnlE5Wyewzs9iR3ORHAjG9Kf7X0dfva8B/txfMJRfg4T6v6eTLxQJjcGGxSmfXRkm CzHtMXIwnvo3UF5rQRvaUbJSD7OGYBXpN/QjHwmq+hb7VtT4v5bIj7je/TLoXoRZBdy1ZZ8dXbK aZFlYtAdjTH8TkTRo3A== X-Proofpoint-GUID: 90kAGqSpGAZBlgqhtwU9fbUcjvgsDJdL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" Add iommu_dma_map_msi() to map an MSI doorbell and return the IOVA and granule shift to callers that need their own PA->IOVA lookup, dispatching to the DMA-IOMMU or iommufd cookie implementation as appropriate. Callers may pass a required mapping size so MSI doorbells that must not share a larger IOMMU leaf, such as RISC-V IMSIC files, can fail before a mapping is installed. iommu_dma_map_msi() requires the caller to hold @dev's iommu group mutex, but struct iommu_group is private to drivers/iommu/iommu.c, so a caller outside the core (e.g. an interrupt-remapping driver building a table of mappings ahead of any MSI descriptor existing) has no way to take it. Add iommu_group_mutex_lock()/iommu_group_mutex_unlock() to bridge that gap, next to the existing iommu_group_mutex_assert(). Signed-off-by: Andrew Jones --- drivers/iommu/dma-iommu.c | 22 +------ drivers/iommu/dma-iommu.h | 8 --- drivers/iommu/iommu-priv.h | 8 --- drivers/iommu/iommu.c | 104 ++++++++++++++++++++++++++++----- drivers/iommu/iommufd/driver.c | 31 ++-------- include/linux/iommu.h | 31 ++++++++++ 6 files changed, 127 insertions(+), 77 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 56a5072b4dde..bcd3eb94bee5 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2235,9 +2235,9 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_p= age(struct device *dev, } =20 /* - * Descriptor-free counterpart to iommu_dma_sw_msi(). Maps an MSI physical - * page into the domain and returns the IOVA and mapping granule. Used for - * pre-mapping MSI targets before any MSI descriptor has been set. + * Maps an MSI physical page into the domain and returns the IOVA and + * mapping granule. Used for pre-mapping MSI targets before any MSI + * descriptor has been set. * * The caller must pass a device attached to @domain and hold @dev's IOMMU * group mutex. If @required_size is non-zero then it must exactly match t= he @@ -2271,22 +2271,6 @@ int iommu_dma_sw_map_msi(struct iommu_domain *domain, return 0; } =20 -int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) -{ - struct device *dev =3D msi_desc_to_dev(desc); - dma_addr_t msi_iova; - unsigned int msi_shift; - int ret; - - ret =3D iommu_dma_sw_map_msi(domain, dev, msi_addr, 0, &msi_iova, &msi_sh= ift); - if (ret) - return ret; - - msi_desc_set_iommu_msi_iova(desc, msi_iova, msi_shift); - return 0; -} - static int iommu_dma_init(void) { if (is_kdump_kernel()) diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 3e1adeafdcac..7d707157aebb 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -23,8 +23,6 @@ int iommu_dma_sw_map_msi(struct iommu_domain *domain, struct device *dev, phys_addr_t msi_addr, size_t required_size, dma_addr_t *msi_iova, unsigned int *msi_shift); -int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr); =20 extern bool iommu_dma_forcedac; =20 @@ -65,11 +63,5 @@ static inline int iommu_dma_sw_map_msi(struct iommu_doma= in *domain, return -ENODEV; } =20 -static inline int iommu_dma_sw_msi(struct iommu_domain *domain, - struct msi_desc *desc, phys_addr_t msi_addr) -{ - return -ENODEV; -} - #endif /* CONFIG_IOMMU_DMA */ #endif /* __DMA_IOMMU_H */ diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index f60373cd2f70..109aca07470b 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -53,18 +53,10 @@ int iommu_replace_group_handle(struct iommu_group *grou= p, struct iommu_attach_handle *handle); =20 #if IS_ENABLED(CONFIG_IOMMUFD_DRIVER_CORE) && IS_ENABLED(CONFIG_IRQ_MSI_IO= MMU) -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr); int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, phys_addr_t msi_addr, size_t required_size, dma_addr_t *msi_iova, unsigned int *msi_shift); #else /* !CONFIG_IOMMUFD_DRIVER_CORE || !CONFIG_IRQ_MSI_IOMMU */ -static inline int iommufd_sw_msi(struct iommu_domain *domain, - struct msi_desc *desc, phys_addr_t msi_addr) -{ - return -EOPNOTSUPP; -} - static inline int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, phys_addr_t msi_addr, size_t required_size, dma_addr_t *msi_iova, diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index e8f13dcebbde..15adaf55666f 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1364,15 +1364,46 @@ void iommu_group_remove_device(struct device *dev) } EXPORT_SYMBOL_GPL(iommu_group_remove_device); =20 -#if IS_ENABLED(CONFIG_LOCKDEP) && IS_ENABLED(CONFIG_IOMMU_API) +#if IS_ENABLED(CONFIG_IOMMU_API) +/* + * iommu_group_mutex_lock(), iommu_group_mutex_unlock(), and + * iommu_group_mutex_assert() must be called after device group param is + * set. + */ + +/** + * iommu_group_mutex_lock - Lock the iommu group mutex for a device + * @dev: the device whose group mutex should be locked + * + * Callers that need to invoke a function documented as requiring the + * device's iommu group mutex (e.g. iommu_dma_map_msi()) from outside + * drivers/iommu/ use this instead of reaching into struct iommu_group, + * which is private to the core. Must be paired with + * iommu_group_mutex_unlock(). + */ +void iommu_group_mutex_lock(struct device *dev) +{ + mutex_lock(&dev->iommu_group->mutex); +} +EXPORT_SYMBOL_GPL(iommu_group_mutex_lock); + +/** + * iommu_group_mutex_unlock - Unlock the iommu group mutex for a device + * @dev: the device whose group mutex should be unlocked + */ +void iommu_group_mutex_unlock(struct device *dev) +{ + mutex_unlock(&dev->iommu_group->mutex); +} +EXPORT_SYMBOL_GPL(iommu_group_mutex_unlock); + +#if IS_ENABLED(CONFIG_LOCKDEP) /** * iommu_group_mutex_assert - Check device group mutex lock * @dev: the device that has group param set * * This function is called by an iommu driver to check whether it holds * group mutex lock for the given device or not. - * - * Note that this function must be called after device group param is set. */ void iommu_group_mutex_assert(struct device *dev) { @@ -1381,7 +1412,8 @@ void iommu_group_mutex_assert(struct device *dev) lockdep_assert_held(&group->mutex); } EXPORT_SYMBOL_GPL(iommu_group_mutex_assert); -#endif +#endif /* CONFIG_LOCKDEP */ +#endif /* CONFIG_IOMMU_API */ =20 static struct device *iommu_group_first_dev(struct iommu_group *group) { @@ -4223,6 +4255,52 @@ void pci_dev_reset_iommu_done(struct pci_dev *pdev) EXPORT_SYMBOL_GPL(pci_dev_reset_iommu_done); =20 #if IS_ENABLED(CONFIG_IRQ_MSI_IOMMU) +/** + * iommu_dma_map_msi() - Map an MSI page in an IOMMU domain + * @domain: IOMMU domain to map into + * @dev: Device used to allocate the IOVA + * @msi_addr: MSI target address to be mapped + * @required_size: Required mapping size, or 0 to accept any size + * @msi_iova: IOVA for @msi_addr, or 0 for passthrough + * @msi_shift: Mapping granule shift, or 0 for passthrough + * + * The caller must hold @dev's iommu group mutex, e.g. via + * iommu_group_mutex_lock()/iommu_group_mutex_unlock(). This function does + * not take the mutex itself because callers building a table of mappings + * (e.g. one IOVA per possible CPU's IMSIC page) call it in a loop; locking + * inside would mean re-acquiring the mutex on every iteration and would n= ot + * stop the domain from changing between iterations, leaving the table + * inconsistent. The caller locks once around the whole loop instead. + * + * Return: 0 on success or negative error code if the mapping failed. + */ +int iommu_dma_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + *msi_iova =3D 0; + *msi_shift =3D 0; + + if (!domain) + return -EINVAL; + + if (domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) + return 0; + + switch (domain->cookie_type) { + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_DMA_IOVA: + return iommu_dma_sw_map_msi(domain, dev, msi_addr, + required_size, msi_iova, msi_shift); + case IOMMU_COOKIE_IOMMUFD: + return iommufd_sw_map_msi(domain, dev, msi_addr, + required_size, msi_iova, msi_shift); + default: + return -EOPNOTSUPP; + } +} + /** * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU domain * @desc: MSI descriptor, will store the MSI page @@ -4238,6 +4316,8 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys= _addr_t msi_addr) { struct device *dev =3D msi_desc_to_dev(desc); struct iommu_group *group =3D dev->iommu_group; + dma_addr_t msi_iova; + unsigned int msi_shift; int ret =3D 0; =20 if (!group) @@ -4246,18 +4326,10 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, ph= ys_addr_t msi_addr) mutex_lock(&group->mutex); /* An IDENTITY domain must pass through */ if (group->domain && group->domain->type !=3D IOMMU_DOMAIN_IDENTITY) { - switch (group->domain->cookie_type) { - case IOMMU_COOKIE_DMA_MSI: - case IOMMU_COOKIE_DMA_IOVA: - ret =3D iommu_dma_sw_msi(group->domain, desc, msi_addr); - break; - case IOMMU_COOKIE_IOMMUFD: - ret =3D iommufd_sw_msi(group->domain, desc, msi_addr); - break; - default: - ret =3D -EOPNOTSUPP; - break; - } + ret =3D iommu_dma_map_msi(group->domain, dev, msi_addr, 0, + &msi_iova, &msi_shift); + if (!ret) + msi_desc_set_iommu_msi_iova(desc, msi_iova, msi_shift); } mutex_unlock(&group->mutex); return ret; diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 69b3dbcbee3b..b39796bc7251 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -249,11 +249,11 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); =20 /* - * Descriptor-free counterpart to iommufd_sw_msi(). Maps an MSI physical p= age - * into the domain and returns the IOVA. Used for pre-mapping MSI targets = before - * any MSI descriptor has been set (e.g. IMSIC doorbell pages). The IOVA is - * global to the iommufd file descriptor: every domain and device using the - * same MSI parameters gets the same IOVA. + * Maps an MSI physical page into the domain and returns the IOVA. Used for + * pre-mapping MSI targets before any MSI descriptor has been set (e.g. + * IMSIC doorbell pages). The IOVA is global to the iommufd file + * descriptor: every domain and device using the same MSI parameters gets + * the same IOVA. * * msi_addr is the exact byte offset of the MSI doorbell; the caller must = have * verified it is contained within an MMIO region safe to map at PAGE_SIZE= . If @@ -321,27 +321,6 @@ int iommufd_sw_map_msi(struct iommu_domain *domain, st= ruct device *dev, return 0; } EXPORT_SYMBOL_NS_GPL(iommufd_sw_map_msi, "IOMMUFD"); - -/* - * Called by the irq layer when the platform translates MSI addresses thro= ugh - * the IOMMU. Wraps iommufd_sw_map_msi() and stores the result in the desc= riptor. - */ -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) -{ - dma_addr_t msi_iova; - unsigned int msi_shift; - int rc; - - rc =3D iommufd_sw_map_msi(domain, msi_desc_to_dev(desc), msi_addr, - 0, &msi_iova, &msi_shift); - if (rc) - return rc; - - msi_desc_set_iommu_msi_iova(desc, msi_iova, msi_shift); - return 0; -} -EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi, "IOMMUFD"); #endif =20 MODULE_DESCRIPTION("iommufd code shared with builtin modules"); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index d20aa6f6863a..1745ef1525da 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -8,6 +8,7 @@ #define __LINUX_IOMMU_H =20 #include +#include #include #include #include @@ -1561,8 +1562,22 @@ static inline void pci_dev_reset_iommu_done(struct p= ci_dev *pdev) =20 #ifdef CONFIG_IRQ_MSI_IOMMU #ifdef CONFIG_IOMMU_API +int iommu_dma_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift); int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr); #else +static inline int iommu_dma_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + *msi_iova =3D 0; + *msi_shift =3D 0; + return 0; +} + static inline int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) { @@ -1571,6 +1586,22 @@ static inline int iommu_dma_prepare_msi(struct msi_d= esc *desc, #endif /* CONFIG_IOMMU_API */ #endif /* CONFIG_IRQ_MSI_IOMMU */ =20 +#if IS_ENABLED(CONFIG_IOMMU_API) +void iommu_group_mutex_lock(struct device *dev); +void iommu_group_mutex_unlock(struct device *dev); +#else +static inline void iommu_group_mutex_lock(struct device *dev) { } +static inline void iommu_group_mutex_unlock(struct device *dev) { } +#endif + +/* + * scoped_guard(iommu_group, dev) { ... } locks dev's iommu group mutex for + * the scope of the block. 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a1e7cab285sm938856a12.9.2026.08.07.11.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:26 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v3 05/19] genirq/msi: Provide DOMAIN_BUS_MSI_REMAP Date: Fri, 7 Aug 2026 20:16:59 +0200 Message-ID: <20260807181713.228535-6-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Fp01OWrq c=1 sm=1 tr=0 ts=6a762138 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=cHhBG6FuOey2j-0mYlgA:9 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-GUID: kwQo2ojCRfX2OPN1jpwilHhQb7VCdIJ2 X-Proofpoint-ORIG-GUID: kwQo2ojCRfX2OPN1jpwilHhQb7VCdIJ2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXzmiSceMvctav ZgEaw421qv+XXokokRkTi2VBhZpKzmuZfEfR64Qr4MCs4qffaKd5BhKqPnntBO7eakBrXPgcFyA QRkNTR42gJI4JpGRVY0ZjmZksYvcth6Qd3qEEteUeYMqZduOVqr0b9IrMRvnEJGYi78ACUElPb9 2JikAKz5iKwpsKYlgy5nIqKv+xinEWgZNCi0viDZ1cBgNVkuKC4gCeg7A440IxDz71+fN1w57ez 5rDF9vybEj12REU/bBLmCalTMqaKUOfUYZAEReY33eb/fwkCyZcLgpWYbAaCWeQhstzGpDpQXxh oNvLfFICK9os9j6rd/ab8zMrw2oOGi5KWL6YFZSfkvQoWXVcxGQoCPZxh5CYe6jt8OW1edjqDGv dLYIDMfw5Z6OEjXwm9DXB+zDRSGywByCl5D6bPbCPdLOSQ/IIsA/IRGFxk9iIFY0GqWW2qU3uVa iyStrQYF7h77DVWA8zw== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX/4xffn/AmKLF 6mTVs1ti5ECPalL5QpR6grmtET5f+cLTT601G8vfrqst2L5R1XmnZy+UXXd8kOKY/uRt1SeDxST +qyVZyKr4kk+E4giyBtowpcyLDu6S3A= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 spamscore=0 clxscore=1015 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" Add a bus token for MSI domains that remap interrupts, needed by the upcoming RISC-V IOMMU interrupt-remapping domain to distinguish itself from NEXUS domains. The token is generic because remapping itself is the only property that needs to be conveyed -- there is nothing RISC-V-specific about it. Such a domain implements init_dev_msi_info() via msi_parent_init_dev_msi_info(), which leaves 'domain' pointing at the NEXUS domain while 'real_parent' points at the remap domain itself. Accept that combination in msi_lib_init_dev_msi_info(); no other msi-lib changes are needed. Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu --- drivers/irqchip/irq-msi-lib.c | 8 ++++---- include/linux/irqdomain_defs.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-msi-lib.c b/drivers/irqchip/irq-msi-lib.c index 45e0ed3134ce..9027dfbab15e 100644 --- a/drivers/irqchip/irq-msi-lib.c +++ b/drivers/irqchip/irq-msi-lib.c @@ -36,14 +36,14 @@ bool msi_lib_init_dev_msi_info(struct device *dev, stru= ct irq_domain *domain, return false; =20 /* - * MSI parent domain specific settings. For now there is only the - * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is - * possible to stack MSI parents. See x86 vector -> irq remapping + * MSI parent domain specific settings. There may be only the root + * parent domain, e.g. NEXUS, acting as a MSI parent, or there may + * be stacked MSI parents, typically used for remapping. */ if (domain->bus_token =3D=3D pops->bus_select_token) { if (WARN_ON_ONCE(domain !=3D real_parent)) return false; - } else { + } else if (real_parent->bus_token !=3D DOMAIN_BUS_MSI_REMAP) { WARN_ON_ONCE(1); return false; } diff --git a/include/linux/irqdomain_defs.h b/include/linux/irqdomain_defs.h index 3a03bdfeeee9..954cf585b3c4 100644 --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -26,6 +26,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_AMDVI, DOMAIN_BUS_DEVICE_MSI, DOMAIN_BUS_WIRED_TO_MSI, + DOMAIN_BUS_MSI_REMAP, }; =20 #endif /* _LINUX_IRQDOMAIN_DEFS_H */ --=20 2.43.0 From nobody Tue Sep 29 13:19:51 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F0CA36EA84 for ; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080cc386esm80002966b.45.2026.08.07.11.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:28 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 06/19] irqchip/riscv-imsic: Compose MSI updates through the hierarchy Date: Fri, 7 Aug 2026 20:17:00 +0200 Message-ID: <20260807181713.228535-7-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: D231vNtcCrahMj4CZMztS_yZO8a42njf X-Authority-Analysis: v=2.4 cv=SYbHsPRu c=1 sm=1 tr=0 ts=6a76213a cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=3qtCRIp3mPeaHrg9mH0A:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX76wZwZHKbEMF YzvqkS6LNfw2I3n7aIsN9JP5Fu7Ff6UO1rQPbZSdDmbj6qSl9yBfpTsR8XRCVAFcMyacRQEUgoE LaVyIo8wgk/ylf94qzWZIeWlzV9JGK8= X-Proofpoint-GUID: D231vNtcCrahMj4CZMztS_yZO8a42njf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXzZ18p0pfh9ev FcMNo1nTBHNJO3JwGE/nOYpduF7BW7QlgesfYZOPA7XpgGU7UGHJ0N8FkqhtoWBu+9sp/5HUppa 2koaLkeF+ZT6pQlAIdnF9CGqitkE04JQ5Y49hLvDw9y19SuqfiPgiBUs0A6fDnxy63z9o4UMqux Q4TGkmyz63nYYoiwripgTPlJtV0oixdlCCgARciCXBoZYXbnSRGu9oftc3qvBsmYpL2KfjDezsK +gzUjQFJ3SMY4hhdIH+N6A2WPxoFfQYalC+PzZo1sO3Gi3e3//uL3a7FH09YnMKBWV4xA9dPeqL X/COPHPv/5JwlREB3KN3dYs/tJ1SWEuI1oPo32YrVOSIbvbsmQxFHSDqiW7pDctocwkqBpikVK/ xcs+xTT9hUsspvRoiqkH7KIZGdTWZTKwJP0JjrybRhoZK87x36vutOygbu+0BIsxqYVz6pd9/vC YCfGHhQ1pc7ruucFATw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" imsic_irq_set_affinity() wrote the new IMSIC target straight to the device via imsic_msi_update_msg(), bypassing the irqdomain hierarchy. That skips any intermediate IOMMU irqdomain sitting between IMSIC and the device, so a remapped device would keep the pre-remap physical address after every affinity change. Compose MSI updates via irq_chip_compose_msi_msg() starting from the top of the hierarchy instead, so an intermediate remap domain gets to translate the target before the device is written. For the temporary vector used by non-atomic affinity updates, compose the current vector through the hierarchy before d->chip_data is switched to the new vector, then replace only msg.data with the new local ID. This preserves the required old-address/new-data temporary target while also allowing an intermediate remap domain to refresh or clear any MSI IOVA state cached on the device's MSI descriptor. Moving the final write to after d->chip_data =3D new_vec is required because irq_chip_compose_msi_msg() reads d->chip_data. Keep it before updating effective affinity and migrating vector state so the device is retargeted before the old vector is disabled. Signed-off-by: Andrew Jones --- drivers/irqchip/irq-riscv-imsic-platform.c | 27 ++++++++-------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 643c8e459611..5634641dc223 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -90,19 +90,12 @@ static void imsic_irq_compose_msg(struct irq_data *d, s= truct msi_msg *msg) } =20 #ifdef CONFIG_SMP -static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *= vec) -{ - struct msi_msg msg =3D { }; - - imsic_irq_compose_vector_msg(vec, &msg); - irq_data_get_irq_chip(d)->irq_write_msi_msg(d, &msg); -} - static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask= *mask_val, bool force) { + struct irq_data *top =3D irq_get_irq_data(d->irq); struct imsic_vector *old_vec, *new_vec; - struct imsic_vector tmp_vec; + struct msi_msg msg =3D { }; =20 /* * Requirements for the downstream irqdomains (or devices): @@ -153,20 +146,20 @@ static int imsic_irq_set_affinity(struct irq_data *d,= const struct cpumask *mask */ if (!irq_can_move_in_process_context(d) && new_vec->local_id !=3D old_vec->local_id) { - /* Setup temporary vector */ - tmp_vec.cpu =3D old_vec->cpu; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080cf749fsm82183166b.58.2026.08.07.11.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:30 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 07/19] iommu/riscv: Add IRQ domain for interrupt remapping Date: Fri, 7 Aug 2026 20:17:01 +0200 Message-ID: <20260807181713.228535-8-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Cb44Irrl c=1 sm=1 tr=0 ts=6a76213c cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=qlKvAlJJmACmlsHknIYA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: Ncp_fEcqY1NbDzKnOHmy4rh9Cl2z03pg X-Proofpoint-ORIG-GUID: Ncp_fEcqY1NbDzKnOHmy4rh9Cl2z03pg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX6tTwILu9ToYd oGvvE/LtgVcmxsuCdSAnHxjVbmEH9S2nAFzh4sSUgv7lkzETh8+nCWurnpl45ciP+8Pl/AulqMq S3TWgxf1h68rbdSJWRTfMwOP07XyanS36Me36pshpmw5mUGVzgsBaGMdwBQahJCmQOMEZsagvbh UKf+lAu4PGRw1ksRrniLMOynAz92noGrw+EdhYmiwK/kU587uJrzOTHtP69+oSpAyAZ698HzBZI Ev8U3YHE9lNwNtw3/tX/N+xfWgckK1ImAv7xVFGvUWQ0D99poKeNG3ROTGaiEcZYSqofgMPZwWz cjeJVzgG8QtIatQMYdDdASJ/cnl7rM5/GBoJZxDEzGEm3fG5vP863MnvgVX/UDTQmqElmUJyZex 114NBGlScjXEPTzRNhcpaE2DjgAT01xAkGHXgx9GIccAU8ZT0DCEUfCjzxniTsuOg8/pwOwkJDj RvnHe8wVEPuabgMY31w== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX+seHSkmBsAj6 zMLc1p3VBskl3NV5VO70yXC9Umhb0OomBsAtKq8fE2Pc1NdFwVYkrEYoVOWb/t/3dgOaun2WP6Z MDqjg5S6qZeZALgZy8Z23izhDRtnYgQ= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" Create a per-device MSI parent irqdomain as the hierarchy hook for future interrupt remapping. The remapping tables will be owned by the attached paging domain since the MSI IOVA mappings live in its page tables. The domain is installed from probe_device() and removed from release_device(). This is only the initial skeleton: it does not remap interrupts yet, and non-paging IOMMU domains will fall back to the raw IMSIC physical address when remapping is added. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/Makefile | 2 +- drivers/iommu/riscv/iommu-ir.c | 119 ++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 46 ++++++----- drivers/iommu/riscv/iommu.h | 27 +++++++ include/linux/irqchip/riscv-imsic.h | 7 ++ 5 files changed, 182 insertions(+), 19 deletions(-) create mode 100644 drivers/iommu/riscv/iommu-ir.c diff --git a/drivers/iommu/riscv/Makefile b/drivers/iommu/riscv/Makefile index b5929f9f23e6..9c83f877d50f 100644 --- a/drivers/iommu/riscv/Makefile +++ b/drivers/iommu/riscv/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D iommu.o iommu-platform.o +obj-y +=3D iommu.o iommu-ir.o iommu-platform.o obj-$(CONFIG_RISCV_IOMMU_PCI) +=3D iommu-pci.o diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c new file mode 100644 index 000000000000..5873addf2a1b --- /dev/null +++ b/drivers/iommu/riscv/iommu-ir.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * IOMMU Interrupt Remapping + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + */ +#include +#include +#include + +#include "iommu.h" + +static struct irq_chip riscv_iommu_ir_irq_chip =3D { + .name =3D "IOMMU-IR", + .irq_ack =3D irq_chip_ack_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, +}; + +static int riscv_iommu_ir_irq_domain_alloc_irqs(struct irq_domain *irqdoma= in, + unsigned int irq_base, unsigned int nr_irqs, + void *arg) +{ + struct irq_data *data; + int i, ret; + + ret =3D irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + data =3D irq_domain_get_irq_data(irqdomain, irq_base + i); + data->chip =3D &riscv_iommu_ir_irq_chip; + } + + return 0; +} + +static const struct irq_domain_ops riscv_iommu_ir_irq_domain_ops =3D { + .alloc =3D riscv_iommu_ir_irq_domain_alloc_irqs, + .free =3D irq_domain_free_irqs_parent, +}; + +static const struct msi_parent_ops riscv_iommu_ir_msi_parent_ops =3D { + .prefix =3D "IR-", + .supported_flags =3D MSI_GENERIC_FLAGS_MASK | + MSI_FLAG_PCI_MSIX, + .required_flags =3D MSI_FLAG_USE_DEF_DOM_OPS | + MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSI_MASK_PARENT, + .chip_flags =3D MSI_CHIP_FLAG_SET_ACK, + .init_dev_msi_info =3D msi_parent_init_dev_msi_info, +}; + +struct irq_domain *riscv_iommu_ir_irq_domain_create(struct device *dev, + struct riscv_iommu_info *info) +{ + struct irq_domain *irqparent =3D dev_get_msi_domain(dev); + struct irq_domain *irqdomain; + struct fwnode_handle *fn; + char *fwname __free(kfree) =3D NULL; + + if (!irqparent) + return NULL; + + fwname =3D kasprintf(GFP_KERNEL, "IOMMU-IR-%s", dev_name(dev)); + if (!fwname) + return ERR_PTR(-ENOMEM); + + fn =3D irq_domain_alloc_named_fwnode(fwname); + if (!fn) + return ERR_PTR(-ENOMEM); + + irqdomain =3D irq_domain_create_hierarchy(irqparent, 0, 0, fn, + &riscv_iommu_ir_irq_domain_ops, + info); + if (!irqdomain) { + irq_domain_free_fwnode(fn); + return ERR_PTR(-ENOMEM); + } + + /* + * The RISC-V IOMMU doesn't validate MSI data, so we can't set + * IRQ_DOMAIN_FLAG_ISOLATED_MSI. This means VFIO requires + * allow_unsafe_interrupts. + */ + irqdomain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; + irqdomain->msi_parent_ops =3D &riscv_iommu_ir_msi_parent_ops; + irq_domain_update_bus_token(irqdomain, DOMAIN_BUS_MSI_REMAP); + + dev_set_msi_domain(dev, irqdomain); + + return irqdomain; +} + +void riscv_iommu_ir_irq_domain_remove(struct device *dev, struct riscv_iom= mu_info *info) +{ + struct fwnode_handle *fn; + + if (!info->irqdomain) + return; + + dev_set_msi_domain(dev, info->irqdomain->parent); + fn =3D info->irqdomain->fwnode; + irq_domain_remove(info->irqdomain); + info->irqdomain =3D NULL; + irq_domain_free_fwnode(fn); +} + +int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, + struct iommu_domain *old) +{ + return 0; +} + +void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain) +{ +} diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index cec3ddd7ab10..bfe606a0cb9a 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -19,9 +19,9 @@ #include #include #include +#include #include #include -#include =20 #include "../iommu-pages.h" #include "iommu-bits.h" @@ -810,26 +810,9 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iom= mu_device *iommu, return 0; } =20 -/* This struct contains protection domain specific IOMMU driver data. */ -struct riscv_iommu_domain { - union { - struct iommu_domain domain; - struct pt_iommu_riscv_64 riscvpt; - }; - struct list_head bonds; - spinlock_t lock; /* protect bonds list updates. */ - int pscid; -}; -PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); - #define iommu_domain_to_riscv(iommu_domain) \ container_of(iommu_domain, struct riscv_iommu_domain, domain) =20 -/* Private IOMMU data for managed devices, dev_iommu_priv_* */ -struct riscv_iommu_info { - struct riscv_iommu_domain *domain; -}; - /* * Linkage between an iommu_domain and attached devices. * @@ -1258,6 +1241,8 @@ static void riscv_iommu_free_paging_domain(struct iom= mu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 + riscv_iommu_ir_free_paging_domain(iommu_domain); + if ((int)domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); =20 @@ -1289,6 +1274,7 @@ static int riscv_iommu_attach_paging_domain(struct io= mmu_domain *iommu_domain, struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); struct pt_iommu_riscv_64_hw_info pt_info; u64 fsc, ta; + int ret; =20 pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); =20 @@ -1303,6 +1289,12 @@ static int riscv_iommu_attach_paging_domain(struct i= ommu_domain *iommu_domain, if (riscv_iommu_bond_link(domain, dev)) return -ENOMEM; =20 + ret =3D riscv_iommu_ir_attach_paging_domain(iommu_domain, dev, old); + if (ret) { + riscv_iommu_bond_unlink(domain, dev); + return ret; + } + riscv_iommu_iodir_update(iommu, dev, fsc, ta); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D domain; @@ -1430,6 +1422,7 @@ static int riscv_iommu_of_xlate(struct device *dev, c= onst struct of_phandle_args static struct iommu_device *riscv_iommu_probe_device(struct device *dev) { struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); + struct irq_domain *irqdomain =3D NULL; struct riscv_iommu_device *iommu; struct riscv_iommu_info *info; struct riscv_iommu_dc *dc; @@ -1453,6 +1446,21 @@ static struct iommu_device *riscv_iommu_probe_device= (struct device *dev) info =3D kzalloc_obj(*info); if (!info) return ERR_PTR(-ENOMEM); + + if (imsic_enabled()) { + irqdomain =3D riscv_iommu_ir_irq_domain_create(dev, info); + if (IS_ERR(irqdomain)) { + kfree(info); + return ERR_CAST(irqdomain); + } + } + + /* + * irqdomain is NULL when it's not necessary; either there aren't + * any IMSICs or no MSI domain has been set up for the device. + */ + info->irqdomain =3D irqdomain; + /* * Allocate and pre-configure device context entries in * the device directory. Do not mark the context valid yet. @@ -1461,6 +1469,7 @@ static struct iommu_device *riscv_iommu_probe_device(= struct device *dev) for (i =3D 0; i < fwspec->num_ids; i++) { dc =3D riscv_iommu_get_dc(iommu, fwspec->ids[i]); if (!dc) { + riscv_iommu_ir_irq_domain_remove(dev, info); kfree(info); return ERR_PTR(-ENODEV); } @@ -1478,6 +1487,7 @@ static void riscv_iommu_release_device(struct device = *dev) { struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); =20 + riscv_iommu_ir_irq_domain_remove(dev, info); kfree_rcu_mightsleep(info); } =20 diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 46df79dd5495..5d83537911b6 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -14,9 +14,29 @@ #include #include #include +#include +#include =20 #include "iommu-bits.h" =20 +/* This struct contains protection domain specific IOMMU driver data. */ +struct riscv_iommu_domain { + union { + struct iommu_domain domain; + struct pt_iommu_riscv_64 riscvpt; + }; + struct list_head bonds; + spinlock_t lock; /* protect bonds list updates. */ + int pscid; +}; +PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); + +/* Private IOMMU data for managed devices, dev_iommu_priv_* */ +struct riscv_iommu_info { + struct riscv_iommu_domain *domain; + struct irq_domain *irqdomain; +}; + struct riscv_iommu_device; =20 struct riscv_iommu_queue { @@ -66,6 +86,13 @@ int riscv_iommu_init(struct riscv_iommu_device *iommu); void riscv_iommu_remove(struct riscv_iommu_device *iommu); void riscv_iommu_disable(struct riscv_iommu_device *iommu); =20 +struct irq_domain *riscv_iommu_ir_irq_domain_create(struct device *dev, + struct riscv_iommu_info *info); +void riscv_iommu_ir_irq_domain_remove(struct device *dev, struct riscv_iom= mu_info *info); +int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, + struct iommu_domain *old); +void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain); 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080cc3835sm85483366b.44.2026.08.07.11.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:31 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 08/19] iommu/riscv: Prepare info->domain for concurrent RCU read access Date: Fri, 7 Aug 2026 20:17:02 +0200 Message-ID: <20260807181713.228535-9-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Cb44Irrl c=1 sm=1 tr=0 ts=6a76213e cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=j3M2sUOd0rYxyD8OH6gA:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: DkNcKVPUe_Hejx25_xYyUxnJElqyJnbP X-Proofpoint-ORIG-GUID: DkNcKVPUe_Hejx25_xYyUxnJElqyJnbP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX1BYH42TV5MXL fT1aZoIRkSey3+Ruc5t3TFg8s+6F8GV0ZaA0ZFMkw5XBspumH7/7ozvLL9yz02VdPm+Vso18/YJ oq7gMwwzgYLf4zhZfUugL7z4bVBQFdmWIWbs8L7hoKg9goJx7p1Ua7tYHLB1q9wTQRC8cDXbCMf wYYI0xZjs/5LN13rflsqa4sq9cU2AVubia6fGwc0fp7HE/74eK3sm14aXz4BIlM8q3mWooDnC+f DfLATVdpEdXydH5azdHNYmKaMaTIY3tkkeTbSLGdUuGo/OUqiJdeL2+XSFnZV26tJOVL2rj2VfZ +Nou/ZKQEfCpInz0ENRvLzEUgiI2bd7bj/M6rPUUrNG823nGvVczecmoZJb42szndooilgVBTLb HIosctNztXY3ynO/QyK/y7mwMCsuJYUNixM6fmyx7HLIu/eJuKRAF6ylRMsIUBaZHbFfSQ7Wtex 6UkZJJ7BtKrsLXNjp+Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXwCu3THIYSqfH BytPTqIxhONQBXTfjHZ59mGW0Tez6rXCuyJLL1rTOPsm8ZpyWRpRRiPMdNtK2F+WwvsHb7W6KLN nJiDAuwtwlRaq79w4TE4Veo9BxnTHnY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" An upcoming compose_msi_msg() implementation reads info->domain from potentially atomic context, concurrent with domain switches. Apply RCU in preparation. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 14 ++++++++------ drivers/iommu/riscv/iommu.h | 3 ++- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index bfe606a0cb9a..27dfd60834ac 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1241,6 +1241,8 @@ static void riscv_iommu_free_paging_domain(struct iom= mu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 + synchronize_rcu(); + riscv_iommu_ir_free_paging_domain(iommu_domain); =20 if ((int)domain->pscid > 0) @@ -1296,8 +1298,8 @@ static int riscv_iommu_attach_paging_domain(struct io= mmu_domain *iommu_domain, } =20 riscv_iommu_iodir_update(iommu, dev, fsc, ta); - riscv_iommu_bond_unlink(info->domain, dev); - info->domain =3D domain; + riscv_iommu_bond_unlink(rcu_access_pointer(info->domain), dev); + rcu_assign_pointer(info->domain, domain); =20 return 0; } @@ -1373,8 +1375,8 @@ static int riscv_iommu_attach_blocking_domain(struct = iommu_domain *iommu_domain, =20 /* Make device context invalid, translation requests will fault w/ #258 */ riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); - riscv_iommu_bond_unlink(info->domain, dev); - info->domain =3D NULL; + riscv_iommu_bond_unlink(rcu_access_pointer(info->domain), dev); + rcu_assign_pointer(info->domain, NULL); =20 return 0; } @@ -1394,8 +1396,8 @@ static int riscv_iommu_attach_identity_domain(struct = iommu_domain *iommu_domain, struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); =20 riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, RISCV_IOMMU_PC= _TA_V); - riscv_iommu_bond_unlink(info->domain, dev); - info->domain =3D NULL; + riscv_iommu_bond_unlink(rcu_access_pointer(info->domain), dev); + rcu_assign_pointer(info->domain, NULL); =20 return 0; } diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 5d83537911b6..ded18aec8010 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #include "iommu-bits.h" @@ -33,7 +34,7 @@ PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.= iommu, domain); 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080a29a41sm83503666b.5.2026.08.07.11.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:33 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 09/19] iommu/riscv: Publish IOMMU_RESV_SW_MSI region for iommufd MSI remapping Date: Fri, 7 Aug 2026 20:17:03 +0200 Message-ID: <20260807181713.228535-10-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXxFoyE+p8DlVb mVXauX4+QVumFQRCEl8ZkR/YwZ/FASPOZ4NzDyjqWc3u1hj0Nh4q7ufHugmVfcK14K3uyLEz3zi V2x+o66s0ibfqt8cBQyRAnLi7c1OUDM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX44AH/iUuCqzt BUX3+WXP7xyan4AylMOUlQCSKVk5ynAyxJZIJfnLlkTj/NRoxJUPdmRySptYdcKk0uiEtBabTt5 cGj9aMnpH0ZFnFVFc86fhUiDmN9y2DrVN0+pT8ruEBAOotJXnULjO616OYjKeuTWwbAE56UZsYa UmAWCfEYM9ZcFgpe74MG3O4qs4C6U9/L7KARblEkEkLrram/zbnPQRThsH2FpnEQE40VDMA6jLE KUFPt9hABbk442wIGFyvKR+cD87qwhnDV0mtpAWtp10kPjnF8jNLtNauTlqzoZ2HrMPHtTXuilB qS0W3SUrNyQM1F3544uGJls0jKS6DNBf3EO4FpVTqoyS4SZ8bjdST0wKJc/utmAIR6F2TOQRqCj ptnrsdKGESSV7ERNXcBy1zqPilsFwGvnccWOvQAardeihb+cBQ3XHdkPb5/PY6zdfLgPmmqJ4YK vQmEnYO34DcMQuW9EIw== X-Proofpoint-ORIG-GUID: LBNEuh9-KdxIWQNyJ_Ul_gqAjyV2B7hG X-Proofpoint-GUID: LBNEuh9-KdxIWQNyJ_Ul_gqAjyV2B7hG X-Authority-Analysis: v=2.4 cv=Wssb99fv c=1 sm=1 tr=0 ts=6a76213f cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=yKliekd0n2ghiC2AktsA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" iommufd's SW MSI path (iommufd_sw_map_msi) requires an IOMMU_RESV_SW_MSI reservation region to know the IOVA base (sw_msi_start) for MSI page mappings. Without it, sw_msi_start stays at PHYS_ADDR_MAX and iommufd_sw_map_msi silently returns passthrough. Add a get_resv_regions callback that, when IMSIC-based MSI is in use, reserves an IOVA range of num_possible_cpus() pages starting at RISCV_IOMMU_MSI_IOVA_BASE. This is large enough to hold one 4 KiB IMSIC supervisor page per hart. RISCV_IOMMU_MSI_IOVA_BASE is set to 128 MiB, matching the ARM SMMU convention. That value is arbitrary for ARM too; its introducing commit (f3ebee80b313) calls it an "arbitrary MSI IOVA window", so there is nothing riscv-specific lost by reusing it here. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 16 ++++++++++++++++ drivers/iommu/riscv/iommu.c | 8 ++++++++ drivers/iommu/riscv/iommu.h | 5 +++++ 3 files changed, 29 insertions(+) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 5873addf2a1b..1e157faf7bbe 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -117,3 +117,19 @@ int riscv_iommu_ir_attach_paging_domain(struct iommu_d= omain *iommu_domain, struc void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain) { } + +void riscv_iommu_ir_get_resv_regions(struct device *dev, struct list_head = *head) +{ + struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct iommu_resv_region *region; + + if (!info || !info->irqdomain) + return; + + region =3D iommu_alloc_resv_region(RISCV_IOMMU_MSI_IOVA_BASE, + (size_t)num_possible_cpus() * PAGE_SIZE, + IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO, + IOMMU_RESV_SW_MSI, GFP_KERNEL); + if (region) + list_add_tail(®ion->list, head); +} diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 27dfd60834ac..106cc8216942 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -23,6 +23,7 @@ #include #include =20 +#include "../dma-iommu.h" #include "../iommu-pages.h" #include "iommu-bits.h" #include "iommu.h" @@ -1493,6 +1494,12 @@ static void riscv_iommu_release_device(struct device= *dev) kfree_rcu_mightsleep(info); } =20 +static void riscv_iommu_get_resv_regions(struct device *dev, struct list_h= ead *head) +{ + riscv_iommu_ir_get_resv_regions(dev, head); + iommu_dma_get_resv_regions(dev, head); +} + static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, .identity_domain =3D &riscv_iommu_identity_domain, @@ -1502,6 +1509,7 @@ static const struct iommu_ops riscv_iommu_ops =3D { .device_group =3D riscv_iommu_device_group, .probe_device =3D riscv_iommu_probe_device, .release_device =3D riscv_iommu_release_device, + .get_resv_regions =3D riscv_iommu_get_resv_regions, }; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080cf5da5sm80900866b.53.2026.08.07.11.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:35 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 10/19] iommu/riscv: Pre-map IMSIC MSI targets Date: Fri, 7 Aug 2026 20:17:04 +0200 Message-ID: <20260807181713.228535-11-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX6nAMUd7yOAL9 mghUUsLUhaIoTtpJSxv+kkTC28d0NFJbUGl5WqAhAGx6wr5z1NjptB2Mweca1ukGxbWnOnwaqAk U9+n3m6FbpxLcnGlzoyGLJRC5Llftuk= X-Authority-Analysis: v=2.4 cv=N5cZ0W9B c=1 sm=1 tr=0 ts=6a762141 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=JmVyJN48mWrVe0T4eXUA:9 a=O8hF6Hzn-FEA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: 6G17vaTY8yYHdyJ5pLsSJXbv73Me1r1C X-Proofpoint-ORIG-GUID: 6G17vaTY8yYHdyJ5pLsSJXbv73Me1r1C X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX6GGfKhQ3y1pe eYTSM+L8gMxolRAwTqJR8TMqkHWqTWUOz52D48fOsaRX4EWL27Db9HazFy47oc6nhFGd0gIxUTl pPvDAjhIsdZBOaZWI/tLKbrkW4oWqioSjqfI6A551tfzby7tfhkLh4OByojLL0tYF7CgrosIc4s MUoXN3jWKNpcAmBgn6w+YBFwLFwcuaf1iTtDkdbIIYcKdeFG52GIoRlKPNaHQIYXpNJwTMfeLbv 90PkjdleV983CGF92gRbWx6eB2cwQAlECKSN9cAEajviDjz9ELB+YahcYnaAttb8xYmOZYvIZW1 xcGnzk8VtgfUguwBZvX9YoUNJsKYl2x9BF/VnRh4RJkMYV1FxT3jlmM/lHhgFQeVxEYPjR4gI4v z+lJqJBQPqUmyUtumwd7ocBbScUQVBlKpONZuvMqJ7pijykikxTKEff/QW/dCK+x4+yEkwToroY 9dTRn9zpWUYdH9B3ebw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 bulkscore=0 suspectscore=0 spamscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" Prepare for irq_compose_msi_msg() to redirect IMSIC-targeted MSIs through the IOMMU with an O(1) lookup. Unlike fixed-target MSI controllers, IMSIC target PAs change on irq_set_affinity(), which may run in atomic context, so compose cannot map the selected target on demand. Pre-map each populated IMSIC MSI target page into a domain-local IOVA table when the device's paging domain first allocates IMSIC-remapped IRQs, so every possible target IOVA is available at lookup time. The table is indexed by a transformed IMSIC physical address using the same transformation defined in the IOMMU specification for the MSI table (and the function will be used for the MSI table when that support is added later). The table is sized by riscv_iommu_ir_msi_iova_count(), i.e. BIT(group_index_bits + hart_index_bits), rather than num_possible_cpus(). This is because riscv_iommu_ir_msi_iova_idx() derives its index from hart_index_bits and group_index_bits, which are sized for the group with the most harts, i.e. there may be a sparse mapping. Select IRQ_MSI_IOMMU so iommu_dma_map_msi() and iommufd_sw_map_msi() are available to the driver. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/Kconfig | 1 + drivers/iommu/riscv/iommu-ir.c | 105 +++++++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 12 +++- drivers/iommu/riscv/iommu.h | 6 ++ 4 files changed, 121 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/riscv/Kconfig b/drivers/iommu/riscv/Kconfig index b86e5ab94183..f557b55c2c14 100644 --- a/drivers/iommu/riscv/Kconfig +++ b/drivers/iommu/riscv/Kconfig @@ -10,6 +10,7 @@ config RISCV_IOMMU select GENERIC_PT select IOMMU_PT select IOMMU_PT_RISCV64 + select IRQ_MSI_IOMMU help Support for implementations of the RISC-V IOMMU architecture that complements the RISC-V MMU capabilities, providing similar address diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 1e157faf7bbe..0dff74aa9b18 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -5,11 +5,97 @@ * Copyright (c) 2026 Qualcomm Technologies, Inc. */ #include +#include #include #include =20 #include "iommu.h" =20 +/* + * Compute the MSI index for an MSI physical address using the + * IOMMU "extract" function (RISC-V IOMMU spec section 2.3.3). + */ +static size_t riscv_iommu_ir_extract_msi_idx(phys_addr_t pa) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + phys_addr_t mask, addr =3D pa >> 12; + size_t idx; + + mask =3D BIT(global->hart_index_bits + global->guest_index_bits) - 1; + idx =3D addr & mask; + + if (global->group_index_bits) { + phys_addr_t group_mask =3D BIT(global->group_index_bits) - 1; + phys_addr_t group_shift =3D global->group_index_shift - 12; + phys_addr_t group =3D (addr >> group_shift) & group_mask; + + idx |=3D group << fls64(mask); + } + + return idx; +} + +static size_t riscv_iommu_ir_msi_iova_idx(phys_addr_t pa) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + + /* msi_iova[] is only used for the host imsics */ + return riscv_iommu_ir_extract_msi_idx(pa) >> global->guest_index_bits; +} + +static size_t riscv_iommu_ir_msi_iova_count(void) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + + return BIT(global->group_index_bits + global->hart_index_bits); +} + +static int riscv_iommu_ir_build_msi_iova(struct riscv_iommu_domain *domain= , struct device *dev) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + struct iommu_domain *d =3D &domain->domain; + dma_addr_t *msi_iova __free(kfree) =3D NULL; + unsigned int cpu; + int ret; + + guard(mutex)(&domain->mutex); + + if (domain->msi_iova) + return 0; + + switch (d->cookie_type) { + case IOMMU_COOKIE_DMA_IOVA: + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_IOMMUFD: + break; + default: + return 0; + } + + msi_iova =3D kcalloc(riscv_iommu_ir_msi_iova_count(), sizeof(*msi_iova), = GFP_KERNEL); + if (!msi_iova) + return -ENOMEM; + + for_each_possible_cpu(cpu) { + const struct imsic_local_config *local =3D per_cpu_ptr(global->local, cp= u); + phys_addr_t pa =3D local->msi_pa; + unsigned int shift; + size_t idx; + + if (!pa) + continue; + + idx =3D riscv_iommu_ir_msi_iova_idx(pa); + ret =3D iommu_dma_map_msi(d, dev, pa, IMSIC_MMIO_PAGE_SZ, &msi_iova[idx]= , &shift); + if (ret) + return ret; + } + + domain->msi_iova =3D no_free_ptr(msi_iova); + + return 0; +} + static struct irq_chip riscv_iommu_ir_irq_chip =3D { .name =3D "IOMMU-IR", .irq_ack =3D irq_chip_ack_parent, @@ -22,9 +108,25 @@ static int riscv_iommu_ir_irq_domain_alloc_irqs(struct = irq_domain *irqdomain, unsigned int irq_base, unsigned int nr_irqs, void *arg) { + struct riscv_iommu_info *info =3D irqdomain->host_data; + struct riscv_iommu_domain *domain; struct irq_data *data; int i, ret; =20 + /* + * MSI IOVAs are domain-local, just like DMA IOVAs. The device must be + * quiesced, including MSI teardown, before switching away from or freeing + * the domain. iommu_dma_map_msi() requires the group mutex to be held; + * take it around the domain lookup too so info->domain can't change + * out from under the build. + */ + scoped_guard(iommu_group, info->dev) { + domain =3D rcu_dereference_protected(info->domain, true); + ret =3D domain ? riscv_iommu_ir_build_msi_iova(domain, info->dev) : 0; + } + if (ret) + return ret; + ret =3D irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); if (ret) return ret; @@ -116,6 +218,9 @@ int riscv_iommu_ir_attach_paging_domain(struct iommu_do= main *iommu_domain, struc =20 void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain) { + struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); + + kfree(domain->msi_iova); } =20 void riscv_iommu_ir_get_resv_regions(struct device *dev, struct list_head = *head) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 106cc8216942..07287c0e72e7 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -811,9 +811,6 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iomm= u_device *iommu, return 0; } =20 -#define iommu_domain_to_riscv(iommu_domain) \ - container_of(iommu_domain, struct riscv_iommu_domain, domain) - /* * Linkage between an iommu_domain and attached devices. * @@ -1337,6 +1334,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_= domain(struct device *dev) if (!domain) return ERR_PTR(-ENOMEM); =20 + mutex_init(&domain->mutex); + INIT_LIST_HEAD_RCU(&domain->bonds); spin_lock_init(&domain->lock); /* @@ -1450,6 +1449,13 @@ static struct iommu_device *riscv_iommu_probe_device= (struct device *dev) if (!info) return ERR_PTR(-ENOMEM); =20 + /* + * Set info->dev before creating the irqdomain: riscv_iommu_ir_irq_domain= _create() + * publishes the irqdomain via dev_set_msi_domain(), making the .alloc ca= llback + * (which dereferences info->dev) reachable. + */ + info->dev =3D dev; + if (imsic_enabled()) { irqdomain =3D riscv_iommu_ir_irq_domain_create(dev, info); if (IS_ERR(irqdomain)) { diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 16b3c9c4cf8c..8bd41dd63f0e 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -32,14 +32,20 @@ struct riscv_iommu_domain { }; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c90494sm80217466b.36.2026.08.07.11.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:36 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 11/19] iommu/riscv: Copy MSI IOVA table when replacing an iommufd domain Date: Fri, 7 Aug 2026 20:17:05 +0200 Message-ID: <20260807181713.228535-12-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=RKaD2Yi+ c=1 sm=1 tr=0 ts=6a762143 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=advkBHUnGrKv1w340x8A:9 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX2fOS8EhKBUzg 3masvY6ZvyweAQOBgfwKomTBIQLv1erRXPjKmQkAJBdHGSRcWxq2L5ZL6srn26fz/XEfElZA0YG gvoVR3woUoexGn+9TLsniMgNQ2dBUpQ= X-Proofpoint-ORIG-GUID: Le0K7QUohjtNwzK2A02l99la4dUb-97y X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX/wnLH05hDjWV Yhvr7nvJYmaVyNYYXL6xEgHnCZgWll3Xqx4/X7C/LoJJ6J6ALg2MBN/J2aIkaoBVK5xPDaFgd1o 1s+30LRobps+N0ru/Xma1uh2+iX/xuvnunY/kQxrwHK+0cAuUV3k/bY2wYub/S2ltkBTpFs5tOq dFEunWcWGYz3Uz+UJuZExct0q+A7SDYuQq/yK0F04wpe+qkAWwv9FmRbj5g5cEnx7D8BJYMHt7N zzwIiITNP2M1zNdL3l1ZdjU8mQZnFtWw7YwTp+sduzkAo1zmx0lahuH+NpjXOT/2AphcVXAvAu5 koR1kCCySEQLEV6F16sd2Eog4i7BoWMaMV4kN+a2yztydray3H62sd7uiDj6PEJP9jp0Ci74fio W+5UtkBXrYH3YAZVF787lG15KcnsbEO7nHDo9LPHRbmu1MxbSN/cRz98bKj1m7APkp81L+HCFA2 NfdyWVAqgM67nJsCrRw== X-Proofpoint-GUID: Le0K7QUohjtNwzK2A02l99la4dUb-97y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" iommufd may replace one paging domain with another on a device while leaving the device otherwise operational, e.g. when converting a device's HWPT. If the old domain already had a populated MSI IOVA table then the new domain must inherit that table rather than wait to build its own, since the MSI IOVAs are only built on the next irq_domain_alloc_irqs(), which does not happen on a domain replacement. Only copy from an old domain that is a genuine RISC-V paging domain; iommu.c already has riscv_iommu_paging_domain_ops in scope to check this, so do the check there and pass NULL down on a mismatch. This keeps riscv_iommu_ir_attach_paging_domain() simple: a non-NULL old is always safe to cast with iommu_domain_to_riscv(). Only iommufd cookie domains are copied from and to, since VFIO type1 and DMA API domains build their own tables from irq_domain_alloc_irqs() before any device is attached, and are never replaced while a device is live. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 78 ++++++++++++++++++++++++++++++++-- drivers/iommu/riscv/iommu.h | 2 + 2 files changed, 77 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 0dff74aa9b18..7d9a1eaca92e 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -118,18 +118,26 @@ static int riscv_iommu_ir_irq_domain_alloc_irqs(struc= t irq_domain *irqdomain, * quiesced, including MSI teardown, before switching away from or freeing * the domain. iommu_dma_map_msi() requires the group mutex to be held; * take it around the domain lookup too so info->domain can't change - * out from under the build. + * out from under the build. Bump info->nr_msis here too, before + * irq_domain_alloc_irqs_parent() runs unlocked below, so a concurrent + * riscv_iommu_ir_attach_paging_domain() can never observe a count that + * is lower than the number of MSIs actually in flight for this device. */ scoped_guard(iommu_group, info->dev) { domain =3D rcu_dereference_protected(info->domain, true); ret =3D domain ? riscv_iommu_ir_build_msi_iova(domain, info->dev) : 0; + if (!ret) + info->nr_msis +=3D nr_irqs; } if (ret) return ret; =20 ret =3D irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); - if (ret) + if (ret) { + guard(iommu_group)(info->dev); + info->nr_msis -=3D nr_irqs; return ret; + } =20 for (i =3D 0; i < nr_irqs; i++) { data =3D irq_domain_get_irq_data(irqdomain, irq_base + i); @@ -139,9 +147,25 @@ static int riscv_iommu_ir_irq_domain_alloc_irqs(struct= irq_domain *irqdomain, return 0; } =20 +static void riscv_iommu_ir_irq_domain_free_irqs(struct irq_domain *irqdoma= in, + unsigned int irq_base, unsigned int nr_irqs) +{ + struct riscv_iommu_info *info =3D irqdomain->host_data; + + irq_domain_free_irqs_parent(irqdomain, irq_base, nr_irqs); + + /* + * Decrement only after the parent free completes, so a concurrent + * riscv_iommu_ir_attach_paging_domain() never observes a count lower + * than the number of MSIs that are actually still live. + */ + scoped_guard(iommu_group, info->dev) + info->nr_msis -=3D nr_irqs; +} + static const struct irq_domain_ops riscv_iommu_ir_irq_domain_ops =3D { .alloc =3D riscv_iommu_ir_irq_domain_alloc_irqs, - .free =3D irq_domain_free_irqs_parent, + .free =3D riscv_iommu_ir_irq_domain_free_irqs, }; =20 static const struct msi_parent_ops riscv_iommu_ir_msi_parent_ops =3D { @@ -213,6 +237,54 @@ void riscv_iommu_ir_irq_domain_remove(struct device *d= ev, struct riscv_iommu_inf int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, struct iommu_domain *old) { + struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); + struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct riscv_iommu_domain *old_domain =3D NULL; + dma_addr_t *msi_iova =3D NULL; + + if (old && (old->type & __IOMMU_DOMAIN_PAGING)) + old_domain =3D iommu_domain_to_riscv(old); + + /* + * Copying is only correct between two IOMMUFD domains: their MSI IOVAs + * come from the fd-wide SW_MSI reservation, so they match across + * domain instances. Every other cookie type derives its MSI IOVAs from + * domain-local allocator state. + */ + if (old_domain && old_domain->domain.cookie_type =3D=3D IOMMU_COOKIE_IOMM= UFD && + iommu_domain->cookie_type =3D=3D IOMMU_COOKIE_IOMMUFD) { + scoped_guard(mutex, &old_domain->mutex) { + if (old_domain->msi_iova) { + msi_iova =3D kmemdup(old_domain->msi_iova, + riscv_iommu_ir_msi_iova_count() * + sizeof(*msi_iova), + GFP_KERNEL); + if (!msi_iova) + return -ENOMEM; + } + } + + if (msi_iova) { + guard(mutex)(&domain->mutex); + + if (domain->msi_iova) + kfree(msi_iova); + else + domain->msi_iova =3D msi_iova; + + return 0; + } + } + + /* + * No table to copy: build one from scratch if this device has ever + * allocated MSIs, since those MSIs may already be live and expecting + * riscv_iommu_ir_compose_msi_msg() to find a populated table for + * whatever domain is now attached. + */ + if (info->nr_msis) + return riscv_iommu_ir_build_msi_iova(domain, dev); + return 0; } =20 diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 8bd41dd63f0e..77328282a236 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -46,6 +46,8 @@ struct riscv_iommu_info { struct riscv_iommu_domain __rcu *domain; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a1e7d48dcasm833503a12.15.2026.08.07.11.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:39 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 12/19] iommu/riscv: Gate identity boundary switches with live MSIs Date: Fri, 7 Aug 2026 20:17:06 +0200 Message-ID: <20260807181713.228535-13-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: O4jklWMHPqehre1n32ts1tJaw1eLilJh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX4syBCAG9tv79 hAdQDl9xYpF0S7DVa+yB6JyJ8wee3EtZo23aQyUJP6bb+J/bBOPd+9QTl3J4zpGRBoVSb8Fcd6A hVGfMynuXmS5c1ujSw06PUEF94IwBYBlgLupe8gokfbc1Tpqv91W0e+6mO/+5T7/+9MHDJ6m10L NLoSNmn6wV14podjz8KdYhROO4dBKjd52nusRtWgNJHEITR3NBNjALlXOJPbBzk9006EIYczI/p 9aAFf2Ayz6CJp0BXwWbq3S4C90LC/x0mzmiWjuBPXaaZ5pjRS9JHTMCtNNoQpQ4NO968Kv0nygO JABEkPwQ8c4Tv//2ECd9ggqdaZPGWB+pQIXgQ4aHWrjh7K9PVvueQfVlJSLzHpGHOczbBm42xRF HGOMbrZL2YZi4+1qxh0wXgSzvJZxIjDcTewHCU+e/RMDZNbc9Wju73VOTSzO7yhICzemEa72tEr kfaKSK5HoGKUL0AzN4A== X-Authority-Analysis: v=2.4 cv=bcBbluPB c=1 sm=1 tr=0 ts=6a762145 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=RNHjlBfCUNiOovmqR6wA:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: O4jklWMHPqehre1n32ts1tJaw1eLilJh X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXwD81oIbHf2W8 oBZp2GNvSS5sJ8sT8aCcL6Fc0V6DBdhqWVVAITOwMOWYE8HHxUGgScJr7lYMLORuYtzSMIRy4q5 hu+bjV8ZScvnk6C0eWAs2xFg6spuGJg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" Reject identity-boundary domain transitions while a device still has allocated MSIs. The RISC-V IOMMU MSI compose path can run concurrently with domain attach and derives the MSI address rewrite policy from info->domain. Across an identity boundary, a stale decision can turn into a wrong addressing mode (IOVA vs PA), so require nr_msis =3D=3D 0 when crossing between paging and identity domains. This is just a defensive guard since MSI state should be quiesced before crossing the identity boundary anyway. Do not gate paging <-> blocking: blocking is the fail-stop mode and must become available immediately, even with live MSIs. Do not gate paging -> paging: that path already uses nr_msis to ensure new-domain MSI table readiness before install. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 07287c0e72e7..f40db2cda417 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1272,10 +1272,14 @@ static int riscv_iommu_attach_paging_domain(struct = iommu_domain *iommu_domain, struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + bool old_identity =3D old && old->type =3D=3D IOMMU_DOMAIN_IDENTITY; struct pt_iommu_riscv_64_hw_info pt_info; u64 fsc, ta; int ret; =20 + if (old_identity && info->nr_msis) + return -EBUSY; + pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); =20 if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode)) @@ -1394,6 +1398,10 @@ static int riscv_iommu_attach_identity_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a1e7d7648dsm828651a12.30.2026.08.07.11.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:42 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 13/19] iommu/riscv: Implement irq_compose_msi_msg for IMSIC remapping Date: Fri, 7 Aug 2026 20:17:07 +0200 Message-ID: <20260807181713.228535-14-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Cb44Irrl c=1 sm=1 tr=0 ts=6a762149 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=wDfzXBFmrApTGnkBQMcA:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: 91knT7v5GCTtTrC67_F4QdaRZXrCIQy4 X-Proofpoint-ORIG-GUID: 91knT7v5GCTtTrC67_F4QdaRZXrCIQy4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX43/boWz66Cfy 34czKMwQzMxRCTx5GxWzjxZB3uEgvFOkmD1hM6Wr58/IqzcIy6rQvoxhfNMStqYezhXCN2R9PmF nnqh8hQaWhM50NGzdbracD/Q4Uaii747w/kDcbljNqDPaTqq+EWk5J52e8yV71MgX4Okrjd2/Xp fJEmWkO7pzI/D+86WSoet4H8LvUU8bo8zjcSWvgrbL73oF+jnV/JOrmgtN2PksWLEuARGu0vki5 mfVubTm1XB3+ZUM7zNxx9EtVdvU9h7kaoJpPXpzMi1A40tKiFU5LhrXZP5a+CbPbk6SQgtEA5y4 431AwD8388hOjzPHcErxnSOF5XuIrCX+D8AwKsjhmbf2VQpQ1ckDWaD6v6PGPpGK8OLXQBB2cd0 tNwHG+wqiQBE5lVckmyHNu0SnsLvpdctmW9dJHzm1ClnupNQYvfdZCmsp9B7Y/lY/mjWGS03PVu MDvpiU4ZYZV8AClItmA== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX4eB4i68is7qZ +qxdNqM7M6n2myCXINVhxC9GXlLEjaM4w61s2cP9/Wee2XhAH/Qdf8NkZfEga+cmLjiJvpE4Bht vShUSYrgA+QwFTtqVHMQwkAfW0IA2uo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" Wire up irq_compose_msi_msg() on the IOMMU-IR irq chip to look up the pre-mapped IOVA for the target IMSIC page and rewrite the composed message to use it, redirecting MSI writes through the IOMMU instead of landing at the raw IMSIC physical address. The lookup is O(1), since the "extract" function used to build the table's index is also used here, which is necessary since the number of IMSICs may eventually be in the hundreds and irq_compose_msi_msg() may run in atomic context. domain->msi_iova is read here without domain->mutex, since compose can run in atomic context, and RCU only protects info->domain itself. Pair smp_store_release()/smp_load_acquire() on domain->msi_iova to ensure it's observably filled before publishing its pointer. That guarantees a non-NULL domain->msi_iova observed here is safe to use. A NULL domain->msi_iova falls back to the raw IMSIC physical address, same as when info->domain itself is NULL, since a live paging domain should not normally reach compose without a populated table. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 49 +++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 7d9a1eaca92e..98be3e3fddad 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -91,17 +91,56 @@ static int riscv_iommu_ir_build_msi_iova(struct riscv_i= ommu_domain *domain, stru return ret; } =20 - domain->msi_iova =3D no_free_ptr(msi_iova); + /* Pair with smp_load_acquire() in riscv_iommu_ir_compose_msi_msg() */ + smp_store_release(&domain->msi_iova, no_free_ptr(msi_iova)); =20 return 0; } =20 +static void riscv_iommu_ir_compose_msi_msg(struct irq_data *data, struct m= si_msg *msg) +{ + struct riscv_iommu_info *info =3D data->domain->host_data; + struct riscv_iommu_domain *domain; + dma_addr_t *msi_iova; + struct msi_desc *desc; + phys_addr_t pa; + size_t idx; + + BUG_ON(irq_chip_compose_msi_msg(data->parent_data, msg)); + + desc =3D irq_data_get_msi_desc(data); + if (WARN_ON_ONCE(!desc)) + return; + + guard(rcu)(); + + domain =3D rcu_dereference(info->domain); + if (!domain) { + msi_desc_set_iommu_msi_iova(desc, 0, 0); + return; + } + + /* Pair with smp_store_release() in riscv_iommu_ir_build_msi_iova() */ + msi_iova =3D smp_load_acquire(&domain->msi_iova); + if (!msi_iova) { + msi_desc_set_iommu_msi_iova(desc, 0, 0); + return; + } + + pa =3D ((u64)msg->address_hi << 32) | msg->address_lo; + idx =3D riscv_iommu_ir_msi_iova_idx(pa); + + msi_desc_set_iommu_msi_iova(desc, msi_iova[idx], IMSIC_MMIO_PAGE_SHIFT); + msi_msg_set_addr(desc, msg, pa); +} + static struct irq_chip riscv_iommu_ir_irq_chip =3D { .name =3D "IOMMU-IR", .irq_ack =3D irq_chip_ack_parent, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_compose_msi_msg =3D riscv_iommu_ir_compose_msi_msg, }; =20 static int riscv_iommu_ir_irq_domain_alloc_irqs(struct irq_domain *irqdoma= in, @@ -267,10 +306,12 @@ int riscv_iommu_ir_attach_paging_domain(struct iommu_= domain *iommu_domain, struc if (msi_iova) { guard(mutex)(&domain->mutex); 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Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones --- drivers/iommu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 6e07bd69467a..1c9f2ad10f36 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -151,7 +151,7 @@ config OF_IOMMU =20 # IOMMU-agnostic DMA-mapping layer config IOMMU_DMA - def_bool ARM64 || X86 || S390 + def_bool ARM64 || X86 || S390 || (RISCV && 64BIT) select DMA_OPS_HELPERS select IOMMU_API select IOMMU_IOVA --=20 2.43.0 From nobody Tue Sep 29 13:19:51 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 167D631AAA8 for ; Fri, 7 Aug 2026 18:17:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c90d21sm83079366b.39.2026.08.07.11.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:47 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v3 15/19] iommu/riscv: report iommu capabilities Date: Fri, 7 Aug 2026 20:17:09 +0200 Message-ID: <20260807181713.228535-16-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: aLmykn__9eFlDLC5M3TDXTjYCztmhc_w X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX2p55FfNJAtTc MMyxepj9BwfYIdE0zyezEgbTCwHCsuo4N6waiSyFaUORvxCMv0s+KdAjrlL8G2vrcGAZQand0sc xV/V4iczUnujPHdsRuWipNxm2+p3868= X-Proofpoint-GUID: aLmykn__9eFlDLC5M3TDXTjYCztmhc_w X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX9qE5pWJju5E/ UMynmmz873nTpCVeesa5KA4eJn3Gdjnko9JFyGmbzMLc8tWWJt7Rbhm9H9E+XY3BuKWCU/YF5Sb uSF6v/SSaOZuVQPK9LON6D4y1hQv+nG7oP0E6FS6Po+xFUpbhEIbCpSObR2UI3W4HORZTLF8KJ3 K3tk1zjXRR8gF9+a22HGttig4Wn4nQofa8ZYh6und7cZD40vofqu9ww/FXeC1+m+eWKuQ4yKxJF AE08G0yI5MqoXvvBPPg6U6CbvWGJctAJl9Dwt90DwnQVvNSHft3ydxBN8yRjmLA2GyDOa1JAcfk 52OsUwxFtO6Pg0Yrwk28b6hrsonjmC5PYHVmecUzWESE8e2/SrbaoQnzJgGNoBCzNMAMsUdtwjJ ZFDOBxlsVAB1JPE6eWc7m14Pnw8RsICkMlBDG6wjb/zcZXlRQdSTKCJyl6gjb2YRlQvBk2iCf9B VPDPjUa7X5cmjOcHIbw== X-Authority-Analysis: v=2.4 cv=X71i7mTe c=1 sm=1 tr=0 ts=6a76214d cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=h0uksLzaAAAA:8 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=eWAdAM1PFmNr0JmOMJYA:9 a=dawVfQjAaf238kedN5IG:22 a=MSi_79tMYmZZG2gvAgS0:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Report RISC-V IOMMU capability required by the VFIO subsystem to enable PCIe device assignment. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu --- drivers/iommu/riscv/iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index f40db2cda417..a286f5a24c16 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1424,6 +1424,17 @@ static struct iommu_group *riscv_iommu_device_group(= struct device *dev) return generic_device_group(dev); } =20 +static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + /* The RISC-V IOMMU is always DMA cache coherent. */ + return true; + default: + return false; + } +} + static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandl= e_args *args) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -1516,6 +1527,7 @@ static void riscv_iommu_get_resv_regions(struct devic= e *dev, struct list_head *h =20 static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, + .capable =3D riscv_iommu_capable, .identity_domain =3D &riscv_iommu_identity_domain, .blocked_domain =3D &riscv_iommu_blocking_domain, .release_domain =3D &riscv_iommu_blocking_domain, --=20 2.43.0 From nobody Tue Sep 29 13:19:51 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A53937A4B8 for ; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c90eb4sm80115466b.35.2026.08.07.11.17.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:48 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v3 16/19] vfio: enable IOMMU_TYPE1 for RISC-V Date: Fri, 7 Aug 2026 20:17:10 +0200 Message-ID: <20260807181713.228535-17-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: o0ER4plw9uGstCuA0JZ6jT2Mmd5YqYEX X-Authority-Analysis: v=2.4 cv=SYbHsPRu c=1 sm=1 tr=0 ts=6a76214e cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=h0uksLzaAAAA:8 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=e-vb6wPzIjHU0Swrx_MA:9 a=kacYvNCVWA4VmyqE58fU:22 a=MSi_79tMYmZZG2gvAgS0:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX39K324biRCdj pGc/rrBR+QrB6tFI6zwfC2UvqW59lkgvH6nzNMYI9+RCt2GG2FNw0zBTOGZL0wSgSLosZMGBIyB xMgeiVWGEQ2W+iOuUKsuh9OjV4OKY5w= X-Proofpoint-GUID: o0ER4plw9uGstCuA0JZ6jT2Mmd5YqYEX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXxrbvC/l+H6Gy rQpvesr0MJKM1yBDGUV6AhaoqK6/FbDgyeZLNMPD8tITb6Y2+6I+TuyvYvLVeAQHFfiHI4N6i9A 33uf9hIqC+ICmucaGQKwSdDH0ADytl8akBC/kYAWVCJ/B6xbSXF1ovkDE462nHQOKyfz98cJaqq 2ZntgyFWIRp2IX3UFyJfd4QTQ4w1Hfm0lS39SOFSWVGQRoQcWKpJ0252k2+TpsQm6AgThnBSYr3 hJIKWo1JxPjU9tlBO5RDc6Vk+PBBOnU/kK5h9PEODrAQStSvPrdpxs2/xvWzTNUnGowt2AMfqE3 h1Z8UE9O8lkfwJkUi4RtYKe9KspNCUh7RB7cmwwaP/md935JCN5tOV6253f8D2zDY5OwX/ZLvic BqxdkYqfcrZF+xIDswdf/L2E4APHIwbI+R+03BnGWU0squdxmGx9cpIEs0Imup5yrpGmva7FRxu QTS8g2uP0EeTgAHNUBQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Enable VFIO support on RISC-V architecture, now that the RISC-V IOMMU driver reports the IOMMU_CAP_CACHE_COHERENCY capability VFIO_TYPE1 and iommufd both require before allowing a device to be bound. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu --- drivers/vfio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index ceae52fd7586..ad62205b4e45 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -39,7 +39,7 @@ config VFIO_GROUP =20 config VFIO_CONTAINER bool "Support for the VFIO container /dev/vfio/vfio" - select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64) + select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || RISCV) depends on VFIO_GROUP default y help --=20 2.43.0 From nobody Tue Sep 29 13:19:51 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40027379C57 for ; Fri, 7 Aug 2026 18:17:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c9155fsm76965466b.37.2026.08.07.11.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:50 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v3 17/19] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch Date: Fri, 7 Aug 2026 20:17:11 +0200 Message-ID: <20260807181713.228535-18-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=RKaD2Yi+ c=1 sm=1 tr=0 ts=6a762150 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=h0uksLzaAAAA:8 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=Hp3hLBw8nfLOXl02dSwA:9 a=uxP6HrT_eTzRwkO_Te1X:22 a=MSi_79tMYmZZG2gvAgS0:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX8QmbGbvAB669 pwAMs/GTjYyYVZ6EzDZVKo6kBDD/kbnpopwoU8KOt3vRzn4w1UAOG0PYu25+Nx2RUviIRzeQR75 bR/P8YmcfxHxEF5cvc+qLDIzgAx50ac= X-Proofpoint-ORIG-GUID: OkUUK3bIOKBL6ivxuvQJV37ooKvoe8Yv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX3ULDsJ9xZQIy +yo55tb55hMjmsOIEB2hGVmCN1BVSjLnUK2r5SZRfhUT7kVp/BTT5ikxAv+adTd7rP8Ty10QTrn 5kySKSHbIrAAyInXt02JZiwI8xEO3LKx+ZGzSZ1VqplUqIaS03SgJI/Q2V4PgQMhapMRDxmr5cG tyqB9STSHNLbUYRp4WWx1yIa6iTV7bKVdtRsJXVWqf1a3FUNGLrP3+p5F3MQP8kMpLhSjlfHTzS I3V3y00Mri9HbbojzvGvjGL76ada+O9O+aVb7ldEDVEgjKTN5BZkBQzD6EVxQGwD/kcCEYQ8tyL n3zQBocRlQfVDe2yZvz0/X8jydtGJAuhyfKBCMLMENEWY5uRC4qwbE4vtDD0ntW1nxB5YCHUQK5 j4w8sByNuaPex4rnbl7ZYs9m3sGPuAY2yfIO4ow0uC3uZ9GpAfwJIQ5PtYwGc3Z251aQwvCaBwW M+kmkECPW6G+eN1+FOQ== X-Proofpoint-GUID: OkUUK3bIOKBL6ivxuvQJV37ooKvoe8Yv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Enable KVM/VFIO support on RISC-V architecture, now that VFIO device assignment is available on RISC-V through VFIO_IOMMU_TYPE1, so a RISC-V KVM guest can be notified about VFIO-assigned devices. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu --- arch/riscv/kvm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index ec2cee0a39e0..49179aae9504 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -29,6 +29,7 @@ config KVM select KVM_GENERIC_DIRTYLOG_READ_PROTECT select KVM_GENERIC_HARDWARE_ENABLING select KVM_MMIO + select KVM_VFIO select VIRT_XFER_TO_GUEST_WORK select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS --=20 2.43.0 From nobody Tue Sep 29 13:19:51 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1140437BE7F for ; Fri, 7 Aug 2026 18:17:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; 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Signed-off-by: Andrew Jones --- arch/riscv/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ed605b5e3162..bae9a0f32f89 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -249,6 +249,10 @@ CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm CONFIG_DW_AXI_DMAC=3Dy CONFIG_MMP_PDMA=3Dm +CONFIG_IOMMUFD=3Dm +CONFIG_VFIO_DEVICE_CDEV=3Dy +CONFIG_VFIO=3Dm +CONFIG_VFIO_PCI=3Dm CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.43.0 From nobody Tue Sep 29 13:19:51 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7569537DEB6 for ; Fri, 7 Aug 2026 18:17:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080cf6fc7sm80926366b.56.2026.08.07.11.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:54 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 19/19] selftests/vfio: Allow building on RISC-V Date: Fri, 7 Aug 2026 20:17:13 +0200 Message-ID: <20260807181713.228535-20-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: cSQORK6DxGIsOcEb8j3VEMs1aAt1GXi4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX0jFZDbZ5hgV+ VnQ/+haHGIf9EJ0B/OPTAJDDUjOeGmYwv4MkJOOiF0L/z7Nj3zQ42HxmQCGneI17nDHRM2qkoZN B+gRGSSE7rn5uxJKd04ow90VgxDfuFH8J5jLKrKt5ceg+aBFYRubBnjqZ8xZk7R9gkDUaiGtHeG PSLryh3j2U4b3MZv0tP0l2Rf3k2F5lm6Op2mCxJFenKjg/M0X8vXisK6HLrqIhOAhTLGSd9pKfK ZbmBAJghxX077YqscodtD/c2Ege0htRW71OQwBXSy6fqZoxA9zpGOe8wacz8yAfQLWL7sCefCBk 4B2RQR2RA5pPYAXgP2n6Tih+z6qZ1c4BBgdQiJovMy5VgAFE1eEkjz+57yRydzuXyBdUPcG70wy 4zVgMrHKmAt0lfS7MD/JepcTcnPXUbqI2Vl2BV69k/p4G3213F++RkOA3hFuUOSrlXIy55DHn8M mDA7v2g7egDPx1QvgTw== X-Authority-Analysis: v=2.4 cv=bcBbluPB c=1 sm=1 tr=0 ts=6a762154 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=iQCmQhr-3cNeY7cWxoMA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: cSQORK6DxGIsOcEb8j3VEMs1aAt1GXi4 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX1lhDqkcgMveF JLZxNuQAFFQBeixrolEv3/FiQ1v5wstnvHx8ObHeT5mt+bZc4P4CytyYP/ulAV7LiSzpVKsRVfg z3wfSbctNMHVvsEgBo5x1fVMeSecuD0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Content-Type: text/plain; charset="utf-8" The generic VFIO and iommufd selftests can now run on RISC-V. Signed-off-by: Andrew Jones --- tools/testing/selftests/vfio/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/vfio/Makefile b/tools/testing/selftest= s/vfio/Makefile index 2c32c48db509..c39f95086a54 100644 --- a/tools/testing/selftests/vfio/Makefile +++ b/tools/testing/selftests/vfio/Makefile @@ -1,6 +1,6 @@ ARCH ?=3D $(shell uname -m) =20 -ifeq (,$(filter $(ARCH),aarch64 arm64 x86 x86_64)) +ifeq (,$(filter $(ARCH),aarch64 arm64 x86 x86_64 riscv)) # Do nothing on unsupported architectures include ../lib.mk else --=20 2.43.0