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Fri, 07 Aug 2026 04:49:58 -0700 (PDT) Received: from lin-0772.qualcomm.com ([212.136.9.4]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c9047esm43046266b.33.2026.08.07.04.49.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 04:49:58 -0700 (PDT) From: Atanas Filipov To: djakov@kernel.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: dmitry.baryshkov@oss.qualcomm.com, krzysztof.kozlowski@oss.qualcomm.com, odelu.kukatla@oss.qualcomm.com, raviteja.laggyshetty@oss.qualcomm.com, vivek.aknurwar@oss.qualcomm.com, quic_afilipov@quicinc.com, loic.poulain@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, atanas.filipov@oss.qualcomm.com Subject: [PATCH v1 1/3] dt-bindings: interconnect: Add Qualcomm CAMNOC ICC binding Date: Fri, 7 Aug 2026 14:49:49 +0300 Message-Id: <20260807114951.4164439-2-atanas.filipov@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260807114951.4164439-1-atanas.filipov@oss.qualcomm.com> References: <20260807114951.4164439-1-atanas.filipov@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=frDsol4f c=1 sm=1 tr=0 ts=6a75c667 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=dNlqnMcrdpbb+gQrTujlOQ==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=4OcPW1pHXCyAC2ZdQ0wA:9 a=uxP6HrT_eTzRwkO_Te1X:22 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: irV9lkoin00wUQLnCw299QGLTRYiycVP X-Proofpoint-ORIG-GUID: irV9lkoin00wUQLnCw299QGLTRYiycVP X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA5MSBTYWx0ZWRfX/LyoXF/muUfp JVPNNjT/vPvl3u4RFqsWuQN7q824WZfiF76RYjryvCpHAti2EcoBJps7fH693E8KbcZ6Hhx2+oP FRJHQWdUwpU9QBTghbTCVLp5Zbdm7/Q= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA5MSBTYWx0ZWRfXyj44KGPuhTx7 YLKrgeVxk47YaJ377pPvC9zwZ5gUyhHDe6+Ml9aaMsYH6VD/+xXvt+M7CqWOrZueohEDrKUbHC5 OkzHpJM7roeKxCeNARzEWPYt84zeTEoHAquqJG3MeUNn/xkRPo/jrJyeC9q+ktFlxvjrZHA/Fki TLifqcDAUkIsfw7p7oUgyoyZ7ZzAkiWozcOEljpRPj4rKSnV3zKMNYj0CHbZ/+CdwNGlEP2SqIv gmGYHVxeAnAbrBezqLsoasGz0W0WkKCZSdPj3WLZwkchGmTVP3eePrqdj3re5/nMlb1GAkIHhwo jiICAnK0bMMO1BOaXztfAmtEqqPt98jPmhfPO/zDaeK3g7qIx5Vx5PfdlYCMOfwx3qzb089oC1q SWHe5Jdu+hgv6RafXjpqUGoE8pjF+qIpYYI8APgYNxceL0Sxk8SguLFUg3g6WQ+SdMsLAnL+TYX 1Uhc+FWIQCXuTvwQyRg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070091 Content-Type: text/plain; charset="utf-8" Add a device tree binding for the Qualcomm Camera Network-on-Chip (CAMNOC) interconnect provider. CAMNOC is the internal AXI interconnect within the camera subsystem that arbitrates bandwidth between camera sub-devices and the external memory interconnect. The CAMNOC ICC provider aggregates bandwidth requests from multiple independent consumers and scales the CAMNOC AXI clock accordingly, avoiding the race conditions that arise when each consumer calls clk_set_rate() directly on the shared clock. Signed-off-by: Atanas Filipov --- .../bindings/interconnect/qcom,camnoc.yaml | 98 +++++++++++++++++++ .../dt-bindings/interconnect/qcom,camnoc.h | 12 +++ 2 files changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,cam= noc.yaml create mode 100644 include/dt-bindings/interconnect/qcom,camnoc.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,camnoc.yam= l b/Documentation/devicetree/bindings/interconnect/qcom,camnoc.yaml new file mode 100644 index 000000000000..b2f5c140ff80 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,camnoc.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,camnoc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera NOC (CAMNOC) Interconnect Provider + +maintainers: + - Aleksandar Filipov + +description: + The Camera Network-on-Chip (CAMNOC) is the internal AXI interconnect + within the Qualcomm camera subsystem. It arbitrates AXI bandwidth + between camera sub-devices (IFE, JPEG, BPS, etc.) and the external + memory interconnect. Multiple consumers may independently request + bandwidth; the CAMNOC ICC provider aggregates these requests and + scales CAM_CC_CAMNOC_AXI_CLK accordingly. + +properties: + compatible: + enum: + - qcom,sm8250-cam-virt + + clocks: + items: + - description: CAMNOC AXI clock + + clock-names: + items: + - const: camnoc_axi + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + camnoc_icc: interconnect { + compatible =3D "qcom,sm8250-cam-virt"; + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-names =3D "camnoc_axi"; + #interconnect-cells =3D <1>; + }; + + /* Example camera sub-device consuming the CAMNOC provider above */ + camera-subsystem@ac53000 { + reg =3D <0x0ac53000 0x1000>; + + interconnects =3D <&camnoc_icc MASTER_CAMNOC_JPEG + &camnoc_icc SLAVE_CAMNOC_AXI>; + interconnect-names =3D "camnoc"; + + /* + * Optional: an operating-points-v2 table lets the consumer + * drive its CAMNOC bandwidth vote from the same OPP that + * selects its core clock rate and RPMh performance state. + */ + operating-points-v2 =3D <&camera_opp_table>; + + camera_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + opp-peak-kBps =3D <22246>; + required-opps =3D <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-peak-kBps =3D <44492>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-peak-kBps =3D <88983>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + opp-peak-kBps =3D <106780>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; diff --git a/include/dt-bindings/interconnect/qcom,camnoc.h b/include/dt-bi= ndings/interconnect/qcom,camnoc.h new file mode 100644 index 000000000000..a03f5e3f6446 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,camnoc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_CAMNOC_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_CAMNOC_H + +#define MASTER_CAMNOC_JPEG 0 +#define SLAVE_CAMNOC_AXI 1 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_CAMNOC_H */ --=20 2.34.1 From nobody Tue Sep 29 13:20:40 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18D1D420478 for ; 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Fri, 07 Aug 2026 04:50:00 -0700 (PDT) Received: from lin-0772.qualcomm.com ([212.136.9.4]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c9047esm43046266b.33.2026.08.07.04.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 04:50:00 -0700 (PDT) From: Atanas Filipov To: djakov@kernel.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: dmitry.baryshkov@oss.qualcomm.com, krzysztof.kozlowski@oss.qualcomm.com, odelu.kukatla@oss.qualcomm.com, raviteja.laggyshetty@oss.qualcomm.com, vivek.aknurwar@oss.qualcomm.com, quic_afilipov@quicinc.com, loic.poulain@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, atanas.filipov@oss.qualcomm.com Subject: [PATCH v1 2/3] interconnect: qcom: Add CAMNOC interconnect provider driver Date: Fri, 7 Aug 2026 14:49:50 +0300 Message-Id: <20260807114951.4164439-3-atanas.filipov@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260807114951.4164439-1-atanas.filipov@oss.qualcomm.com> References: <20260807114951.4164439-1-atanas.filipov@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=EYH4hvmC c=1 sm=1 tr=0 ts=6a75c66a cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=dNlqnMcrdpbb+gQrTujlOQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=muAYhjqZ-AtuC14g7DYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: jeS53ZM5Uc1bFpUkFkFOCQwEtPCqZqQy X-Proofpoint-GUID: jeS53ZM5Uc1bFpUkFkFOCQwEtPCqZqQy X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA5MSBTYWx0ZWRfX94zKc02H981l mMx8A+lGhVxwpTbH+lVZU5L8dye2yjBBMdB21iBAGlBArpcQgJP7g0Kyi/+Nso+pveZ31zcZN6F D0Y07giHS/Bs1GcEfuVTEYSywopPyt8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA5MSBTYWx0ZWRfX20rbjKBaG1or X0mogEMBEl0m/HWo3Mi8LTPUSquNEwVa7cX1aNj6xxlHaTxzECBwfC0lKzwF2okXjRM3/ky0MJr jReGybXuYoxFaF1qL0TFMwYVfva3tZliCIohQyFJ9ile/xe+UkH33tKZd+Gt2i0648RiSxOz6zP JbHGskrsA9wowfyEKIB7FxQaYAeaKDOsmni7Mz2FVZb3c9TwMzN1ff7rySe8/zrjz5SPYrd2wqd pJOj1RGcKvbhD5Cey3u7GKRFm5ssl+ZKFxkT/vRYogtF1BCS9/xEj0AuYP2TWv/fuy9bndu+9r0 AbL+I+uY5pw35HP6SAMcbXFDpxZIficEbX5HhP0saIdgTito7yXP3U2hGL02XlyofGk7VqeALtu uQAtAGoqoxJ5bq73snKrMlk2MUyGc5RncJZL+1MIyRk7jhEoglemkjzItdDTn91QugdiIC1MD7A 8yJxKB1wGXrfQmkt4PA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 suspectscore=0 priorityscore=1501 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070091 The Camera Network-on-Chip (CAMNOC) is the internal AXI interconnect within the camera subsystem. Multiple camera sub-devices share the CAMNOC AXI clock. When each sub-device calls clk_set_rate() directly on this shared clock, a last-writer-wins race condition arises: the final caller sets the rate regardless of what other active consumers require. Introduce a lightweight ICC provider for CAMNOC that solves this by leveraging the ICC aggregation framework. Each consumer obtains an ICC path to SLAVE_CAMNOC_AXI and votes for bandwidth via icc_set_bw(). The ICC core aggregates all votes (max of peak_bw across consumers) and the provider's set() callback translates the result into a single clk_set_rate() call on the CAMNOC AXI clock. Consumers encode the required clock frequency directly as peak_bw in kBps (e.g. 400000 for 400 MHz). The conversion is: rate_hz =3D peak_bw_kBps * 1000 Implement get_bw() returning 0 for both avg and peak to prevent the ICC core from defaulting to INT_MAX before any consumer has voted. Signed-off-by: Atanas Filipov --- drivers/interconnect/qcom/Kconfig | 10 ++ drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/qcom-camnoc.c | 184 ++++++++++++++++++++++++ 3 files changed, 196 insertions(+) create mode 100644 drivers/interconnect/qcom/qcom-camnoc.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 5b8a094ca4ed..9d9d238019a0 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -135,6 +135,16 @@ config INTERCONNECT_QCOM_NORD the RPMh hardware and communicates via Bus Clock Manager (BCM) through the Resource State Coordinator (RSC). =20 +config INTERCONNECT_QCOM_CAMNOC + tristate "Qualcomm CAMNOC interconnect driver" + depends on INTERCONNECT_QCOM || COMPILE_TEST + depends on ARM64 || COMPILE_TEST + help + Say y here to support the Camera Network-on-Chip (CAMNOC) + interconnect driver for Qualcomm SoCs. It aggregates bandwidth + requests from camera sub-devices (IFE, JPEG, BPS, etc.) and + scales CAM_CC_CAMNOC_AXI_CLK accordingly. + config INTERCONNECT_QCOM_OSM_L3 tristate "Qualcomm OSM L3 interconnect driver" depends on INTERCONNECT_QCOM || COMPILE_TEST diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 1c7d410b40cc..52a5998ae6a8 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -18,6 +18,7 @@ qnoc-msm8974-objs :=3D msm8974.o qnoc-msm8976-objs :=3D msm8976.o qnoc-msm8996-objs :=3D msm8996.o qnoc-nord-objs :=3D nord.o +icc-camnoc-objs :=3D qcom-camnoc.o icc-osm-l3-objs :=3D osm-l3.o qnoc-qcm2290-objs :=3D qcm2290.o qnoc-qcs404-objs :=3D qcs404.o @@ -66,6 +67,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) +=3D qnoc-msm8974= .o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8976) +=3D qnoc-msm8976.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) +=3D qnoc-msm8996.o obj-$(CONFIG_INTERCONNECT_QCOM_NORD) +=3D qnoc-nord.o +obj-$(CONFIG_INTERCONNECT_QCOM_CAMNOC) +=3D icc-camnoc.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) +=3D icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) +=3D qnoc-qcm2290.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) +=3D qnoc-qcs404.o diff --git a/drivers/interconnect/qcom/qcom-camnoc.c b/drivers/interconnect= /qcom/qcom-camnoc.c new file mode 100644 index 000000000000..a5a484491515 --- /dev/null +++ b/drivers/interconnect/qcom/qcom-camnoc.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Qualcomm Camera NOC (CAMNOC) interconnect provider. + * + * CAMNOC is the internal AXI interconnect within the Qualcomm camera + * subsystem. Multiple camera sub-devices (IFE, JPEG, BPS, etc.) share + * CAM_CC_CAMNOC_AXI_CLK. This driver acts as an ICC provider so that + * each sub-device can independently vote for bandwidth; the ICC core + * aggregates the votes (max of peak_bw across all consumers) and this + * driver translates the result into a clk_set_rate() call, avoiding + * the last-writer-wins race that occurs with direct clk_set_rate(). + * + * Consumers express their required clock rate directly as peak_bw in + * kBps (e.g. 400000 for 400 MHz). The driver converts kBps =E2=86=92 Hz: + * rate_hz =3D peak_bw_kBps * 1000 + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define to_camnoc_provider(_p) \ + container_of(_p, struct qcom_camnoc_icc_provider, provider) + +struct qcom_camnoc_icc_provider { + struct clk *clk; + struct icc_provider provider; +}; + +struct qcom_camnoc_node { + const char *name; + u16 buswidth; +}; + +static const struct qcom_camnoc_node camnoc_master_jpeg =3D { + .name =3D "master-camnoc-jpeg", + .buswidth =3D 16, +}; + +static const struct qcom_camnoc_node camnoc_slave_axi =3D { + .name =3D "slave-camnoc-axi", + .buswidth =3D 16, +}; + +static const struct qcom_camnoc_node * const camnoc_nodes[] =3D { + [MASTER_CAMNOC_JPEG] =3D &camnoc_master_jpeg, + [SLAVE_CAMNOC_AXI] =3D &camnoc_slave_axi, +}; + +#define CAMNOC_NUM_NODES ARRAY_SIZE(camnoc_nodes) + +static int qcom_camnoc_get_bw(struct icc_node *node, u32 *avg, u32 *peak) +{ + *avg =3D 0; + *peak =3D 0; + + return 0; +} + +static int qcom_camnoc_set(struct icc_node *src, struct icc_node *dst) +{ + struct qcom_camnoc_icc_provider *cp =3D + to_camnoc_provider(src->provider); + unsigned long rate; + + /* + * peak_bw is the aggregated max across all consumers (kBps). + * Consumers encode the required clock frequency directly as kBps, + * so the conversion is simply: rate_hz =3D peak_bw * 1000. + * A vote of 0 means no requirement; leave the clock at its minimum. + */ + rate =3D icc_units_to_bps(dst->peak_bw); + + dev_dbg(src->provider->dev, + "CAMNOC set: aggregated peak_bw=3D%u kBps -> rate=3D%lu Hz\n", + dst->peak_bw, rate); + + return clk_set_rate(cp->clk, rate); +} + +static void qcom_camnoc_remove(struct platform_device *pdev) +{ + struct qcom_camnoc_icc_provider *cp =3D platform_get_drvdata(pdev); + + icc_provider_deregister(&cp->provider); + icc_nodes_remove(&cp->provider); +} + +static int qcom_camnoc_probe(struct platform_device *pdev) +{ + struct qcom_camnoc_icc_provider *cp; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct icc_node *node; + unsigned int i; + int ret; + + cp =3D devm_kzalloc(&pdev->dev, sizeof(*cp), GFP_KERNEL); + if (!cp) + return -ENOMEM; + + cp->clk =3D devm_clk_get(&pdev->dev, "camnoc_axi"); + if (IS_ERR(cp->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(cp->clk), + "failed to get camnoc_axi clock\n"); + + data =3D devm_kzalloc(&pdev->dev, + struct_size(data, nodes, CAMNOC_NUM_NODES), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->num_nodes =3D CAMNOC_NUM_NODES; + + provider =3D &cp->provider; + provider->dev =3D &pdev->dev; + provider->get_bw =3D qcom_camnoc_get_bw; + provider->set =3D qcom_camnoc_set; + provider->aggregate =3D icc_std_aggregate; + provider->xlate =3D of_icc_xlate_onecell; + provider->data =3D data; + + icc_provider_init(provider); + + for (i =3D 0; i < CAMNOC_NUM_NODES; i++) { + node =3D icc_node_create_dyn(); + if (IS_ERR(node)) { + ret =3D PTR_ERR(node); + goto err_remove; + } + + ret =3D icc_node_set_name(node, provider, camnoc_nodes[i]->name); + if (ret) { + icc_node_destroy(node->id); + goto err_remove; + } + + node->data =3D (void *)camnoc_nodes[i]; + icc_node_add(node, provider); + data->nodes[i] =3D node; + } + + icc_link_nodes(data->nodes[MASTER_CAMNOC_JPEG], + &data->nodes[SLAVE_CAMNOC_AXI]); + + ret =3D icc_provider_register(provider); + if (ret) + goto err_remove; + + platform_set_drvdata(pdev, cp); + + return 0; + +err_remove: + icc_nodes_remove(provider); + return ret; +} + +static const struct of_device_id qcom_camnoc_of_match[] =3D { + { .compatible =3D "qcom,sm8250-cam-virt" }, + { } +}; +MODULE_DEVICE_TABLE(of, qcom_camnoc_of_match); + +static struct platform_driver qcom_camnoc_driver =3D { + .probe =3D qcom_camnoc_probe, + .remove =3D qcom_camnoc_remove, + .driver =3D { + .name =3D "qcom-camnoc-icc", + .of_match_table =3D qcom_camnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; +module_platform_driver(qcom_camnoc_driver); + +MODULE_DESCRIPTION("Qualcomm CAMNOC interconnect driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Tue Sep 29 13:20:40 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC13C4756A0 for ; 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charset="utf-8" Add the cam_virt CAMNOC interconnect provider node to the sm8250 SoC DTSI. The node uses the CAMNOC AXI clock to aggregate bandwidth votes from camera sub-devices via the ICC framework. The node is placed alongside the other virtual interconnect nodes, after mmss_noc. Signed-off-by: Atanas Filipov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 7076720413ab..33535c83a4d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -377,6 +378,13 @@ qup_virt: interconnect-qup-virt { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + cam_virt: interconnect-cam-virt { + compatible =3D "qcom,sm8250-cam-virt"; + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-names =3D "camnoc_axi"; + #interconnect-cells =3D <1>; + }; + cpu0_opp_table: opp-table-cpu0 { compatible =3D "operating-points-v2"; opp-shared; --=20 2.34.1