From nobody Tue Sep 29 13:19:51 2026 Received: from mx0a-0002e601.pphosted.com (mx0a-0002e601.pphosted.com [148.163.150.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F22EE42E8C4; Fri, 7 Aug 2026 11:06:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.150.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786100764; cv=fail; b=ruGqfCe+aLJRi+4bQxJBk5/MD2lp2IEvyPa6+YPUkbzGn2wLSqY0FGo6GCP91d7zZLzIKSrcErwX7RCoJS62lQQ4YWaPkP+V1w9qAF1WnLxdQ4VHTBNvWgD9uRe9m0LoTZN6+cJsEqvFp+MDDdSRckqYCrXAx1dS2cwaEpFUoWQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786100764; c=relaxed/simple; bh=Xf5ou+E9xTP7bBlKzDLxKXBX/U7f+3OiJdtpl3SovbQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DEAQXq48R/d3np/CLpPY2joBy6+yI6p92giKCH/2k4R/Ax+DWWhu9yGps253MH8hVA7pJQ73sQPA8DJL77PoqLr279WFjZxga5Isho29uUco3X2pKI/8kQH2XgIpwuXhIlWmzeP0sZUjW1wQU7wnKytvlHCu5UDteUjpnJaHlck= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=SY1Z8MZV; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=W6PBySKZ; arc=fail smtp.client-ip=148.163.150.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="SY1Z8MZV"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="W6PBySKZ" Received: from pps.filterd (m0384305.ppops.net [127.0.0.1]) by m0384305.ppops.net (8.18.1.11/8.18.1.11) with ESMTP id 6777d7u33187543; Fri, 7 Aug 2026 06:05:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=dpxTQ6bO8y2KgrE0IfffDQ9jABOVUL0eQ7Pw0WTgf v8=; b=SY1Z8MZVEwwJXITetMyqVPD0T8znwYlX6q96zhgb6oxGWFa8rJCNygDsI tS4Jp1x2GicZDE7LQlqUF1ATG5zWe3IQstcIsanDQSLhSYDRADgI6f0SIqsPz7Cz ooQ6DpnCu3dBe6lxjgmI6B6lsEuULL9AAXLTcjRCBrLeMoRHG2NylgGP9b1ddWm5 9sN7hJlHWHOeY0QIcdl9QMnoX+iWpip+Xczek2A9jIwyh//GNx/bDGq8JZJpjyM1 Gn/iyjyIIPJiSYWujVYPNwDQZL/+0ohCxqaXOemlfwDUmJKrAhPsAAJxcNJiuYj9 umOfSdQqfVRLiFCDYGV4coND7VNbw== Received: from bn1pr04cu002.outbound.protection.outlook.com (mail-eastus2azon11010027.outbound.protection.outlook.com [52.101.56.27]) by m0384305.ppops.net (PPS) with ESMTPS id 4fwb5p909r-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Fri, 07 Aug 2026 06:05:57 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=sfa5RZ3Q43vb0VXh4g1ItSKBS+WDl3u2Cnr0nDH04WlEpmFTQ/Ye3HOQgl04hZ67aOGRe/vlSbZMujyyYm61RqxGwnSDYQrrOKfwSMcZg6cL2nEjg6EkJtofsW68bPreVMaUO246ekAM+Z1acETe2bqcEjJuMF/MhHe7fBMMMB5MEQ8stHeMiBup+pP0UtX5I8Hu75WOSsxw7kVgEaUWRxlpqsQ0qQrckk4K1i+smJUEi86icwQzLT0XvjxlGPRHoMWv0R6EzxuoXyaw5sDqwZFO5zgK1wB5CvaUZ+AZF91ZrGVMGbFDUtZjDIlFcuOvGbUuGUp+gilckA8dYN8Izw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dpxTQ6bO8y2KgrE0IfffDQ9jABOVUL0eQ7Pw0WTgfv8=; b=c0OWBNGPd7YbdK6GrPF1RQs3HxUyRv/NJ/eBqGQKJ/UL1FF4KKRXxzmsHz9Qr+Owtz5ykiAFsZhR1SjCKjDNGMv6jqRiooFiWp4+4Bn2kKMI5lRBqtMXwzNOwvkj2BPZO9U4ZPS/StReUhZ0j6DW9fqpGzHQ8A0Pgfv4WWSgDPG4vE2EZIBNDa0+W3jCaH8taWqiaitiISoFCVqUeQd4Pk7aaTb6pxAv/p9Kg6ckWx3kGp/enjfAUk9b7KpMck93InWvVwFZal1VOJsKNMU6iTBKBmpc0RArAL/uEXh0svyC5mEws7JRKfPsjqbKbkNmQRPdpBMxFWXtYFFncZZbDw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.194) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dpxTQ6bO8y2KgrE0IfffDQ9jABOVUL0eQ7Pw0WTgfv8=; b=W6PBySKZPfcP/cpZmqNCs/gWKuvSeDaLvwmXgD0rU5ztumCU0dxhWutk3z4muzvzRhgvI2peTq33zL51dzj4Xfs8oDz7D0ukIRr025UiLgD8oMfq8ABkbRobfmIN+grOUbrl1Oiwxxocl+xl09S3Wb/f9mN1fHLG8J3O8ABzliA= Received: from CY5PR18CA0053.namprd18.prod.outlook.com (2603:10b6:930:13::29) by SA2PR10MB4683.namprd10.prod.outlook.com (2603:10b6:806:112::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.19; Fri, 7 Aug 2026 11:05:50 +0000 Received: from CY4PEPF0000EE33.namprd05.prod.outlook.com (2603:10b6:930:13:cafe::2) by CY5PR18CA0053.outlook.office365.com (2603:10b6:930:13::29) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.24 via Frontend Transport; Fri, 7 Aug 2026 11:05:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 198.47.21.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.194; helo=flwvzet200.ext.ti.com; pr=C Received: from flwvzet200.ext.ti.com (198.47.21.194) by CY4PEPF0000EE33.mail.protection.outlook.com (10.167.242.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Fri, 7 Aug 2026 11:05:48 +0000 Received: from DFLE215.ent.ti.com (10.64.6.73) by flwvzet200.ext.ti.com (10.248.192.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Fri, 7 Aug 2026 06:05:45 -0500 Received: from DFLE207.ent.ti.com (10.64.6.65) by DFLE215.ent.ti.com (10.64.6.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Fri, 7 Aug 2026 06:05:45 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE207.ent.ti.com (10.64.6.65) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37 via Frontend Transport; Fri, 7 Aug 2026 06:05:45 -0500 Received: from pratham-Workstation-PC (pratham-workstation-pc.dhcp.ti.com [10.24.53.205]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 677B5htf944625; Fri, 7 Aug 2026 06:05:44 -0500 From: T Pratham To: T Pratham , Herbert Xu , "David S. Miller" CC: Manorit Chawdhry , Shiva Tripathi , Sebin Francis , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v5 1/3] crypto: ti - Add support for SHA224/256/384/512 in DTHEv2 driver Date: Fri, 7 Aug 2026 16:34:57 +0530 Message-ID: <20260807110501.975130-2-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260807110501.975130-1-t-pratham@ti.com> References: <20260807110501.975130-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE33:EE_|SA2PR10MB4683:EE_ X-MS-Office365-Filtering-Correlation-Id: f7bc1f1e-c986-4812-850e-08def473d67c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|23010399003|22082099003|18002099003|3023799007|10067099003|56012099006; X-Microsoft-Antispam-Message-Info: wTnAHKdjuzXaa3ihVaygtNY1E7jJbP5OY5n0i92/DcknN6hx0CGqIBcrUu2UqLsMRcMb44tTuGr6okncYF0E2CWK+YPAAVGWpBufIAIg/sPNH+KtPooFktAS1GL6DrghS9r7l5zCfNx0Q8NrAMLszEKSGmOSDBIjsHxPns1H6Xtk7KdVTiOi1tnG85XdiEfoqqVEHs6ijQ9YOE/u+PJ1qFtKncwF2I/WVo708JimCsTPdjzmdMiZYdg9W2cQo9iu8GTWSee8zzj0ruRFT563lk+wvYKnVKYKir/4/l7oOgsCNRb73JWPL+OsHl6n8kxCWCwzn3qCfQMLIpmBEkRWC14Uy6WBs5IMDI9itx4AyZZAvfpDEp7HorwOARvk5K966S/DXwgtMWmMwlTakIz4RDtK7KH8RqgctgLyN3yqxyidcpfxICgeSJKbh8vmcp4KMcnIm9ppCCIKjv2YfCQvUhSCwY3wr9aCC5RdOpNojETXg/rA+WKUQKLwaYy6YF1AA2nIxafYNNGpX8XTGG8htQzwKd37orLiT7lWcZQ3gO4Dcr2nyIFcQrSW89sH0g7vFgHOgjvApuaeOPTgtXZRgFdQkKb2LtO7U2neXZ1R5EDWfaw0QhEJxJh2Bc1/rlz1UMIB819w2Oe50UcewgvkFw== X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(23010399003)(22082099003)(18002099003)(3023799007)(10067099003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OFyoatpPe0wXmOTF8ziiGyQ0hssR3mVqidOuwaGMmvEifzaLE6pBmtsKH+EKl0kF9HZwkbiE2CQcOPTH4UcjVbigSJFsNo0HLz1DgIgbJzD0bDDGKJddqPyGE9GC3UxKlEvBkJFQBzOKwvwl8LzRDxqkKBzL77jXvOZl+7bRpo/4mBNzE/AdRLgahheq0Kw7vT2cRQnrTUgKkguJbHj/yi2MxzlZAmTLiAslAqw9bMvmiQUmjZMP2S9cSAm85lHkXsU7bH33BIfEhHrMRFEaTPxIK5zDjglVHAdY4BI5pv4f7hDcCijXt5jTJpFlFJFInO/YJdlnEohfs+042Bs+d7SJ1NB9yFI6nhw1S/gQhHyvUrSkUNfbdwCKcdsxPbPlu931mkiIMjFtN36QXmfUeEKsgPyXalJVOtJr2Ffb0k+joK1SkpJk9v4mMT8h+xYJ X-Exchange-RoutingPolicyChecked: gV1MORmUKWbyZw0A/Ej2C9LAXzCntleyY3BY/vIHQ93UtooyNOVvFvZ9Ko4E6jLyE55MXIkMGVTnLSWDSxdqB0DyEPXVj7kS2wzRO1mmDtikG8MePNUt7K8adiM11YwnIMSskrZjCa/OHw0W+8I5ZlWUiLk9t9cYaHpppR7U9Pnb9bA4JCzfu//WHHZrZ9VDI20vgS4tEI+VxQ9F2MPTqnddgbTS0jmUr2jdsGmSUrIqaNkbJhUGttBYP7U0NxVUUGl0odrdGqlOvc+vga6BJ0LDAhJcs2i18Ti9uvCZCiYDjpOcqHXhsrJGS5w80eKyXzVzHJ8EkTufGrVyspWnYw== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2026 11:05:48.9268 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7bc1f1e-c986-4812-850e-08def473d67c X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE33.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR10MB4683 X-Proofpoint-ORIG-GUID: MTe9pK1ef0IGnjm06rcBqmb-D0DGBC6a X-Proofpoint-GUID: MTe9pK1ef0IGnjm06rcBqmb-D0DGBC6a X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA4NSBTYWx0ZWRfX0ncW+ElQnskz sy88HYn58lhQw/f6NXbIjLFKFxpIXZsrxbkGJpDkgbhJcK4HtCh8zqaW21ORbhXW+VcAyfP2xM7 JXd4fs2WnG0L3r+jVE3iWKQ3JGjDuhGAD4N9h2Se/IvGZK+d//6PNxQb+N7S6/kks6rdG4E8t6G D9YJ/vPX7BGJfsXBhJXwzjzaE7d8QdUaCuudF8PHGT8SLqwXXbJhzFFUmG96Llo21l8dCVq7SqO 6IGc/YggPxBygmunh1Ue1SCNdq7TuHmKWZ0soDK7eRLp63yeVKbNPktCjcc74pDmXVyvmA3JJJF EKI6ILq8/AsE+kgaIgQJk19xrQvU9f5VVeh4ebSXM+/uTLi5aGjkyW5t87fhz7ch/ilpVbYTm42 AqvdOx6jqtf047FesJ46MldjVfPAPBii4Vbq3B0sTsO61TwFURt492kovddUCGGwhjO5h5H9Op8 njCwbvB2W8VX/SkDUyA== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA4NSBTYWx0ZWRfX6MxpWzDFVOAd NV1NYqxiHEK4pUu1rpvm+PxJug2BCo4w7+qUYb5q7D4zOUDsKmaMPck7bqiCKfKoGGJdnOha86w jovEMq2qJx1ipzexWdEXuN+9DMRrK2o= X-Authority-Analysis: v=2.4 cv=XOgAjwhE c=1 sm=1 tr=0 ts=6a75bc15 cx=c_pps a=zeiJWWlNkXVQCS8hXHnWBw==:117 a=iwqwCZQqcuTv3JOpYdM7/Q==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=Sv0fKeRqtYgA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=taLDd7a_hP9WKsMzeGRc:22 a=sozttTNsAAAA:8 a=6uMOsyVnTnPNBkKtTW8A:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070085 Content-Type: text/plain; charset="utf-8" Add support for SHA224, SHA256, SHA384, SHA512 algorithms in the Hashing Engine of the DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 2 + drivers/crypto/ti/Makefile | 2 +- drivers/crypto/ti/dthev2-aes.c | 6 +- drivers/crypto/ti/dthev2-common.c | 43 +- drivers/crypto/ti/dthev2-common.h | 50 ++- drivers/crypto/ti/dthev2-hash.c | 695 ++++++++++++++++++++++++++++++ 6 files changed, 784 insertions(+), 14 deletions(-) create mode 100644 drivers/crypto/ti/dthev2-hash.c diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 1a3a571ac8cef..90af2c7cb1c55 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -10,6 +10,8 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_XTS select CRYPTO_GCM select CRYPTO_CCM + select CRYPTO_SHA256 + select CRYPTO_SHA512 select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/Makefile b/drivers/crypto/ti/Makefile index b883078f203d7..a90bc97a52321 100644 --- a/drivers/crypto/ti/Makefile +++ b/drivers/crypto/ti/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_CRYPTO_DEV_TI_DTHEV2) +=3D dthev2.o -dthev2-objs :=3D dthev2-common.o dthev2-aes.o +dthev2-objs :=3D dthev2-common.o dthev2-aes.o dthev2-hash.o diff --git a/drivers/crypto/ti/dthev2-aes.c b/drivers/crypto/ti/dthev2-aes.c index eb5cd902dfb59..164e72c07ee3f 100644 --- a/drivers/crypto/ti/dthev2-aes.c +++ b/drivers/crypto/ti/dthev2-aes.c @@ -512,7 +512,7 @@ static int dthe_aes_run(struct crypto_engine *engine, v= oid *areq) } =20 local_bh_disable(); - crypto_finalize_skcipher_request(dev_data->engine, req, ret); + crypto_finalize_skcipher_request(engine, req, ret); local_bh_enable(); return 0; } @@ -547,7 +547,7 @@ static int dthe_aes_crypt(struct skcipher_request *req) return 0; } =20 - engine =3D dev_data->engine; + engine =3D dev_data->aes_engine; return crypto_transfer_skcipher_request_to_engine(engine, req); } =20 @@ -1183,7 +1183,7 @@ static int dthe_aead_crypt(struct aead_request *req) (ctx->aes_mode =3D=3D DTHE_AES_CCM && !is_zero_ctr)) return dthe_aead_do_fallback(req); =20 - engine =3D dev_data->engine; + engine =3D dev_data->aes_engine; return crypto_transfer_aead_request_to_engine(engine, req); } =20 diff --git a/drivers/crypto/ti/dthev2-common.c b/drivers/crypto/ti/dthev2-c= ommon.c index a2ad79bec105a..88d0ccd5d0227 100644 --- a/drivers/crypto/ti/dthev2-common.c +++ b/drivers/crypto/ti/dthev2-common.c @@ -96,6 +96,11 @@ static int dthe_dma_init(struct dthe_data *dev_data) goto err_dma_sha_tx; } =20 + /* + * Do AES Rx and Tx channel config here because it is invariant of AES mo= de + * SHA Tx channel config is done before DMA transfer depending on hashing= algorithm + */ + memzero_explicit(&cfg, sizeof(cfg)); =20 cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; @@ -130,11 +135,21 @@ static int dthe_dma_init(struct dthe_data *dev_data) =20 static int dthe_register_algs(void) { - return dthe_register_aes_algs(); + int ret =3D 0; + + ret =3D dthe_register_hash_algs(); + if (ret) + return ret; + ret =3D dthe_register_aes_algs(); + if (ret) + dthe_unregister_hash_algs(); + + return ret; } =20 static void dthe_unregister_algs(void) { + dthe_unregister_hash_algs(); dthe_unregister_aes_algs(); } =20 @@ -163,15 +178,26 @@ static int dthe_probe(struct platform_device *pdev) if (ret) goto probe_dma_err; =20 - dev_data->engine =3D crypto_engine_alloc_init(dev, 1); - if (!dev_data->engine) { + dev_data->aes_engine =3D crypto_engine_alloc_init(dev, 1); + if (!dev_data->aes_engine) { ret =3D -ENOMEM; goto probe_engine_err; } + dev_data->hash_engine =3D crypto_engine_alloc_init(dev, 1); + if (!dev_data->hash_engine) { + ret =3D -ENOMEM; + goto probe_hash_engine_err; + } + + ret =3D crypto_engine_start(dev_data->aes_engine); + if (ret) { + dev_err(dev, "Failed to start crypto engine for AES\n"); + goto probe_engine_start_err; + } =20 - ret =3D crypto_engine_start(dev_data->engine); + ret =3D crypto_engine_start(dev_data->hash_engine); if (ret) { - dev_err(dev, "Failed to start crypto engine\n"); + dev_err(dev, "Failed to start crypto engine for hash\n"); goto probe_engine_start_err; } =20 @@ -184,7 +210,9 @@ static int dthe_probe(struct platform_device *pdev) return 0; =20 probe_engine_start_err: - crypto_engine_exit(dev_data->engine); + crypto_engine_exit(dev_data->hash_engine); +probe_hash_engine_err: + crypto_engine_exit(dev_data->aes_engine); probe_engine_err: dma_release_channel(dev_data->dma_aes_rx); dma_release_channel(dev_data->dma_aes_tx); @@ -207,7 +235,8 @@ static void dthe_remove(struct platform_device *pdev) =20 dthe_unregister_algs(); =20 - crypto_engine_exit(dev_data->engine); + crypto_engine_exit(dev_data->aes_engine); + crypto_engine_exit(dev_data->hash_engine); =20 dma_release_channel(dev_data->dma_aes_rx); dma_release_channel(dev_data->dma_aes_tx); diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index d4a3b9c18bbc1..d3fb7c5ff3052 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include #include @@ -33,6 +34,16 @@ */ #define DTHE_MAX_KEYSIZE (AES_MAX_KEY_SIZE * 2) =20 +enum dthe_hash_alg_sel { + DTHE_HASH_MD5 =3D 0, + DTHE_HASH_SHA1 =3D BIT(1), + DTHE_HASH_SHA224 =3D BIT(2), + DTHE_HASH_SHA256 =3D BIT(1) | BIT(2), + DTHE_HASH_SHA384 =3D BIT(0), + DTHE_HASH_SHA512 =3D BIT(0) | BIT(1), + DTHE_HASH_ERR =3D BIT(0) | BIT(1) | BIT(2), +}; + enum dthe_aes_mode { DTHE_AES_ECB =3D 0, DTHE_AES_CBC, @@ -49,7 +60,8 @@ enum dthe_aes_mode { * @dev: Device pointer * @regs: Base address of the register space * @list: list node for dev - * @engine: Crypto engine instance + * @aes_engine: Crypto engine instance for AES Engine + * @hash_engine: Crypto engine instance for Hashing Engine * @dma_aes_rx: AES Rx DMA Channel * @dma_aes_tx: AES Tx DMA Channel * @dma_sha_tx: SHA Tx DMA Channel @@ -58,7 +70,8 @@ struct dthe_data { struct device *dev; void __iomem *regs; struct list_head list; - struct crypto_engine *engine; + struct crypto_engine *aes_engine; + struct crypto_engine *hash_engine; =20 struct dma_chan *dma_aes_rx; struct dma_chan *dma_aes_tx; @@ -83,6 +96,8 @@ struct dthe_list { * @authsize: Authentication size for modes with authentication * @key: AES key * @aes_mode: AES mode + * @hash_mode: Hashing Engine mode + * @phash_size: partial hash size of the hash algorithm selected * @aead_fb: Fallback crypto aead handle * @skcipher_fb: Fallback crypto skcipher handle for AES-XTS mode */ @@ -91,7 +106,11 @@ struct dthe_tfm_ctx { unsigned int keylen; unsigned int authsize; u32 key[DTHE_MAX_KEYSIZE / sizeof(u32)]; - enum dthe_aes_mode aes_mode; + union { + enum dthe_aes_mode aes_mode; + enum dthe_hash_alg_sel hash_mode; + }; + unsigned int phash_size; union { struct crypto_sync_aead *aead_fb; struct crypto_sync_skcipher *skcipher_fb; @@ -110,6 +129,28 @@ struct dthe_aes_req_ctx { struct completion aes_compl; }; =20 +/** + * struct dthe_hash_req_ctx - Hashing engine ctx struct + * @phash: buffer to store a partial hash from a previous operation + * @digestcnt: stores the digest count from a previous operation; currentl= y hardware only provides + * a single 32-bit value even for SHA384/512 + * @padding: padding buffer for handling unaligned data + * @data: buffer to store one block of data to defer operations for non-ze= ro final. + * @flags: bitfield of flags for internal use. + * bit 0: Current operation (update/finup) + * bit 1: If phash is available from a previous operation + * bit 2: If data is buffered from a previous operation + * @hash_compl: Completion variable for use in manual completion in case o= f DMA callback failure + */ +struct dthe_hash_req_ctx { + u32 phash[SHA512_DIGEST_SIZE / sizeof(u32)]; + u64 digestcnt[2]; + u8 padding[SHA512_BLOCK_SIZE]; + u8 data[SHA512_BLOCK_SIZE]; + u8 flags; + struct completion hash_compl; +}; + /* Struct definitions end */ =20 struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx); @@ -131,4 +172,7 @@ struct scatterlist *dthe_copy_sg(struct scatterlist *ds= t, int dthe_register_aes_algs(void); void dthe_unregister_aes_algs(void); =20 +int dthe_register_hash_algs(void); +void dthe_unregister_hash_algs(void); + #endif diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-has= h.c new file mode 100644 index 0000000000000..dc7a397a9e58c --- /dev/null +++ b/drivers/crypto/ti/dthev2-hash.c @@ -0,0 +1,695 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * K3 DTHE V2 crypto accelerator driver + * + * Copyright (C) Texas Instruments 2025 - https://www.ti.com + * Author: T Pratham + */ + +#include +#include +#include +#include +#include + +#include "dthev2-common.h" + +#include +#include +#include +#include +#include +#include + +/* Registers */ + +#define DTHE_P_HASH_BASE 0x5000 +#define DTHE_P_HASH512_IDIGEST_A 0x0240 +#define DTHE_P_HASH512_DIGEST_COUNT 0x0280 +#define DTHE_P_HASH512_MODE 0x0284 +#define DTHE_P_HASH512_LENGTH 0x0288 +#define DTHE_P_HASH512_DATA_IN_START 0x0080 +#define DTHE_P_HASH512_DATA_IN_END 0x00FC + +#define DTHE_P_HASH_SYSCONFIG 0x0110 +#define DTHE_P_HASH_IRQSTATUS 0x0118 +#define DTHE_P_HASH_IRQENABLE 0x011C + +/* Register write values and macros */ +#define DTHE_HASH_SYSCONFIG_INT_EN BIT(2) +#define DTHE_HASH_SYSCONFIG_DMA_EN BIT(3) +#define DTHE_HASH_IRQENABLE_EN_ALL GENMASK(3, 0) +#define DTHE_HASH_IRQSTATUS_OP_READY BIT(0) +#define DTHE_HASH_IRQSTATUS_IP_READY BIT(1) +#define DTHE_HASH_IRQSTATUS_PH_READY BIT(2) +#define DTHE_HASH_IRQSTATUS_CTX_READY BIT(3) + +#define DTHE_HASH_MODE_USE_ALG_CONST BIT(3) +#define DTHE_HASH_MODE_CLOSE_HASH BIT(4) + +/* rctx flag bitfields */ +#define DTHE_HASH_FLAG_OP BIT(0) +#define DTHE_HASH_FLAG_PHASH_AVAIL BIT(1) +#define DTHE_HASH_FLAG_IS_DATA_HELD BIT(2) + +enum dthe_hash_op { + DTHE_HASH_OP_UPDATE =3D 0, + DTHE_HASH_OP_FINUP =3D 1, +}; + +static inline bool dthe_hash_has_flag(struct dthe_hash_req_ctx *rctx, u8 f= lag) +{ + return rctx->flags & flag; +} + +static inline void dthe_hash_flag_set(struct dthe_hash_req_ctx *rctx, u8 f= lag) +{ + rctx->flags |=3D flag; +} + +static inline void dthe_hash_flag_clear(struct dthe_hash_req_ctx *rctx, u8= flag) +{ + rctx->flags &=3D ~flag; +} + +static inline bool dthe_hash_flag_is_op(struct dthe_hash_req_ctx *rctx, en= um dthe_hash_op op) +{ + return FIELD_GET(DTHE_HASH_FLAG_OP, rctx->flags) =3D=3D op; +} + +static inline void dthe_hash_flag_set_op(struct dthe_hash_req_ctx *rctx, e= num dthe_hash_op op) +{ + FIELD_MODIFY(DTHE_HASH_FLAG_OP, &rctx->flags, op); +} + +static void dthe_hash_write_zero_message(enum dthe_hash_alg_sel mode, void= *dst) +{ + switch (mode) { + case DTHE_HASH_SHA512: + memcpy(dst, sha512_zero_message_hash, SHA512_DIGEST_SIZE); + break; + case DTHE_HASH_SHA384: + memcpy(dst, sha384_zero_message_hash, SHA384_DIGEST_SIZE); + break; + case DTHE_HASH_SHA256: + memcpy(dst, sha256_zero_message_hash, SHA256_DIGEST_SIZE); + break; + case DTHE_HASH_SHA224: + memcpy(dst, sha224_zero_message_hash, SHA224_DIGEST_SIZE); + break; + default: + break; + } +} + +static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(struct crypto_ahash = *tfm) +{ + unsigned int ds =3D crypto_ahash_digestsize(tfm); + enum dthe_hash_alg_sel hash_mode; + + /* + * Currently, all hash algorithms supported by DTHEv2 have unique digest = sizes. + * So we can do this. Otherwise, we would have to get the algorithm from = the + * alg_name and do a strcmp. + */ + switch (ds) { + case SHA512_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA512; + break; + case SHA384_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA384; + break; + case SHA256_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA256; + break; + case SHA224_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA224; + break; + default: + hash_mode =3D DTHE_HASH_ERR; + break; + } + + return hash_mode; +} + +static unsigned int dthe_hash_get_phash_size(struct dthe_tfm_ctx *ctx) +{ + unsigned int phash_size =3D 0; + + switch (ctx->hash_mode) { + case DTHE_HASH_SHA512: + case DTHE_HASH_SHA384: + phash_size =3D SHA512_DIGEST_SIZE; + break; + case DTHE_HASH_SHA256: + case DTHE_HASH_SHA224: + phash_size =3D SHA256_DIGEST_SIZE; + break; + default: + break; + } + + return phash_size; +} + +static int dthe_hash_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + + if (!dev_data) + return -ENODEV; + + ctx->dev_data =3D dev_data; + + ctx->hash_mode =3D dthe_hash_get_hash_mode(tfm); + if (ctx->hash_mode =3D=3D DTHE_HASH_ERR) + return -EINVAL; + + ctx->phash_size =3D dthe_hash_get_phash_size(ctx); + + return 0; +} + +static int dthe_hash_config_dma_chan(struct dma_chan *chan, struct crypto_= ahash *tfm) +{ + struct dma_slave_config cfg; + int bs =3D crypto_ahash_blocksize(tfm); + + memzero_explicit(&cfg, sizeof(cfg)); + + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_maxburst =3D bs / 4; + + return dmaengine_slave_config(chan, &cfg); +} + +static void dthe_hash_dma_in_callback(void *data) +{ + struct ahash_request *req =3D (struct ahash_request *)data; + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + + complete(&rctx->hash_compl); +} + +static int dthe_hash_dma_start(struct ahash_request *req, struct scatterli= st *src, + int src_nents, size_t len) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + struct device *tx_dev; + struct dma_async_tx_descriptor *desc_out; + int mapped_nents; + enum dma_data_direction src_dir =3D DMA_TO_DEVICE; + u32 hash_mode; + int ds =3D crypto_ahash_digestsize(tfm); + int ret =3D 0; + u32 *dst; + u32 dst_len; + void __iomem *sha_base_reg =3D dev_data->regs + DTHE_P_HASH_BASE; + + u32 hash_sysconfig_val =3D DTHE_HASH_SYSCONFIG_INT_EN | DTHE_HASH_SYSCONF= IG_DMA_EN; + u32 hash_irqenable_val =3D DTHE_HASH_IRQENABLE_EN_ALL; + + writel_relaxed(hash_sysconfig_val, sha_base_reg + DTHE_P_HASH_SYSCONFIG); + writel_relaxed(hash_irqenable_val, sha_base_reg + DTHE_P_HASH_IRQENABLE); + + /* Config SHA DMA channel as per SHA mode */ + ret =3D dthe_hash_config_dma_chan(dev_data->dma_sha_tx, tfm); + if (ret) { + dev_err(dev_data->dev, "Can't configure sha_tx dmaengine slave: %d\n", r= et); + goto hash_err; + } + + tx_dev =3D dmaengine_get_dma_device(dev_data->dma_sha_tx); + if (!tx_dev) { + ret =3D -ENODEV; + goto hash_err; + } + + mapped_nents =3D dma_map_sg(tx_dev, src, src_nents, src_dir); + if (mapped_nents =3D=3D 0) { + ret =3D -EINVAL; + goto hash_err; + } + + desc_out =3D dmaengine_prep_slave_sg(dev_data->dma_sha_tx, src, mapped_ne= nts, + DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc_out) { + dev_err(dev_data->dev, "OUT prep_slave_sg() failed\n"); + ret =3D -EINVAL; + goto hash_prep_err; + } + + desc_out->callback =3D dthe_hash_dma_in_callback; + desc_out->callback_param =3D req; + + init_completion(&rctx->hash_compl); + + hash_mode =3D ctx->hash_mode; + + if (dthe_hash_flag_is_op(rctx, DTHE_HASH_OP_FINUP)) { + hash_mode |=3D DTHE_HASH_MODE_CLOSE_HASH; + + if (dthe_hash_has_flag(rctx, DTHE_HASH_FLAG_PHASH_AVAIL)) { + for (int i =3D 0; i < ctx->phash_size / sizeof(u32); ++i) + writel_relaxed(rctx->phash[i], + sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); + + writel_relaxed(rctx->digestcnt[0], + sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); + } else { + hash_mode |=3D DTHE_HASH_MODE_USE_ALG_CONST; + } + + writel_relaxed(hash_mode, sha_base_reg + DTHE_P_HASH512_MODE); + writel_relaxed(len, sha_base_reg + DTHE_P_HASH512_LENGTH); + + dmaengine_submit(desc_out); + + dma_async_issue_pending(dev_data->dma_sha_tx); + + ret =3D wait_for_completion_timeout(&rctx->hash_compl, + msecs_to_jiffies(DTHE_DMA_TIMEOUT_MS)); + if (!ret) { + dmaengine_terminate_sync(dev_data->dma_sha_tx); + ret =3D -ETIMEDOUT; + } else { + ret =3D 0; + } + + if (dthe_hash_flag_is_op(rctx, DTHE_HASH_OP_UPDATE)) { + /* If coming from update, we need to read the phash and store it for fut= ure */ + dst =3D rctx->phash; + dst_len =3D ctx->phash_size / sizeof(u32); + } else { + /* If coming from finup or final, we need to read the final digest */ + dst =3D (u32 *)req->result; + dst_len =3D ds / sizeof(u32); + } + + for (int i =3D 0; i < dst_len; ++i) + dst[i] =3D readl_relaxed(sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); + + rctx->digestcnt[0] =3D readl_relaxed(sha_base_reg + DTHE_P_HASH512_DIGEST= _COUNT); + dthe_hash_flag_set(rctx, DTHE_HASH_FLAG_PHASH_AVAIL); + +hash_prep_err: + dma_unmap_sg(tx_dev, src, src_nents, src_dir); +hash_err: + return ret; +} + +static int dthe_hash_run(struct crypto_engine *engine, void *areq) +{ + struct ahash_request *req =3D container_of(areq, struct ahash_request, ba= se); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + + struct scatterlist *src, *sg; + int src_nents =3D 0; + unsigned int bs =3D crypto_ahash_blocksize(tfm); + unsigned int tot_len =3D req->nbytes; + unsigned int len_to_process; + unsigned int len_to_buffer; + unsigned int len_to_send; + unsigned int pad_len =3D 0; + bool is_data_held =3D dthe_hash_has_flag(rctx, DTHE_HASH_FLAG_IS_DATA_HEL= D); + u8 *pad_buf =3D rctx->padding; + int ret =3D 0; + + if (dthe_hash_flag_is_op(rctx, DTHE_HASH_OP_UPDATE)) { + len_to_process =3D tot_len - (tot_len % bs); + len_to_buffer =3D tot_len % bs; + + if (len_to_process =3D=3D 0) { + ret =3D len_to_buffer; + goto hash_buf_all; + } + + /* + * Additionally hold back a trailing block in req ctx, so + * that hardware has data to do CLOSE_HASH in finup. + * Consume any block held from a previous round first. + */ + len_to_process -=3D bs; + len_to_send =3D len_to_process + (is_data_held ? bs : 0); + + if (len_to_send =3D=3D 0) { + memcpy_from_sglist(rctx->data, req->src, 0, bs); + dthe_hash_flag_set(rctx, DTHE_HASH_FLAG_IS_DATA_HELD); + ret =3D len_to_buffer; + goto hash_buf_all; + } + } else { + len_to_process =3D tot_len; + len_to_send =3D len_to_process + (is_data_held ? bs : 0); + len_to_buffer =3D 0; + } + + src_nents =3D sg_nents_for_len(req->src, len_to_process); + if (is_data_held) + src_nents++; + + /* + * Certain DMA restrictions forced us to send data in multiples of BLOCK_= SIZE + * bytes. So, add a padding 0s at the end of src scatterlist if data is n= ot a + * multiple of block_size bytes (Can only happen in final or finup). The = extra + * data is ignored by the DTHE hardware. + */ + if (len_to_send % bs) { + pad_len =3D bs - (len_to_send % bs); + src_nents++; + } + + src =3D kcalloc(src_nents, sizeof(*src), GFP_KERNEL); + if (!src) { + ret =3D -ENOMEM; + goto hash_buf_all; + } + + sg_init_table(src, src_nents); + sg =3D src; + if (is_data_held) { + sg_set_buf(sg, rctx->data, bs); + sg =3D sg_next(sg); + } + sg =3D dthe_copy_sg(sg, req->src, len_to_process); + if (pad_len > 0) { + memset(pad_buf, 0, pad_len); + sg_set_buf(sg, pad_buf, pad_len); + } + + ret =3D dthe_hash_dma_start(req, src, src_nents, len_to_send); + if (!ret) { + if (dthe_hash_flag_is_op(rctx, DTHE_HASH_OP_UPDATE)) { + memcpy_from_sglist(rctx->data, req->src, len_to_process, bs); + dthe_hash_flag_set(rctx, DTHE_HASH_FLAG_IS_DATA_HELD); + } + ret =3D len_to_buffer; + } + + kfree(src); + +hash_buf_all: + local_bh_disable(); + crypto_finalize_hash_request(engine, req, ret); + local_bh_enable(); + return 0; +} + +static int dthe_hash_init(struct ahash_request *req) +{ + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + + rctx->flags =3D 0; + rctx->digestcnt[0] =3D 0; + rctx->digestcnt[1] =3D 0; + + return 0; +} + +static int dthe_hash_update(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + struct crypto_engine *engine =3D dev_data->hash_engine; + + if (req->nbytes =3D=3D 0) + return 0; + + dthe_hash_flag_set_op(rctx, DTHE_HASH_OP_UPDATE); + + return crypto_transfer_hash_request_to_engine(engine, req); +} + +static int dthe_hash_final(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + struct crypto_engine *engine =3D dev_data->hash_engine; + + /** + * We are always buffering data in update, except when nbytes =3D 0. + * So, either we get the buffered data here (nbytes > 0), or there is + * a full block held back from a previous update (IS_DATA_HELD), or it + * is the case that we got a zero message to begin with. + */ + if (req->nbytes > 0 || dthe_hash_has_flag(rctx, DTHE_HASH_FLAG_IS_DATA_HE= LD)) { + dthe_hash_flag_set_op(rctx, DTHE_HASH_OP_FINUP); + + return crypto_transfer_hash_request_to_engine(engine, req); + } + + dthe_hash_write_zero_message(ctx->hash_mode, req->result); + + return 0; +} + +static int dthe_hash_finup(struct ahash_request *req) +{ + /* With AHASH_ALG_BLOCK_ONLY, final becomes same as finup. */ + return dthe_hash_final(req); +} + +static int dthe_hash_digest(struct ahash_request *req) +{ + dthe_hash_init(req); + return dthe_hash_finup(req); +} + +static const u32 sha224_init_state[SHA256_DIGEST_SIZE / sizeof(u32)] =3D { + SHA224_H0, SHA224_H1, SHA224_H2, SHA224_H3, + SHA224_H4, SHA224_H5, SHA224_H6, SHA224_H7 +}; + +static const u32 sha256_init_state[SHA256_DIGEST_SIZE / sizeof(u32)] =3D { + SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, + SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7 +}; + +static const u64 sha384_init_state[SHA512_DIGEST_SIZE / sizeof(u64)] =3D { + SHA384_H0, SHA384_H1, SHA384_H2, SHA384_H3, + SHA384_H4, SHA384_H5, SHA384_H6, SHA384_H7 +}; + +static const u64 sha512_init_state[SHA512_DIGEST_SIZE / sizeof(u64)] =3D { + SHA512_H0, SHA512_H1, SHA512_H2, SHA512_H3, + SHA512_H4, SHA512_H5, SHA512_H6, SHA512_H7 +}; + +static const void *dthe_hash_get_init_state(struct dthe_tfm_ctx *ctx) +{ + switch (ctx->hash_mode) { + case DTHE_HASH_SHA224: + return sha224_init_state; + case DTHE_HASH_SHA256: + return sha256_init_state; + case DTHE_HASH_SHA384: + return sha384_init_state; + case DTHE_HASH_SHA512: + return sha512_init_state; + default: + return NULL; + } +} + +static int dthe_hash_export(struct ahash_request *req, void *out) +{ + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + unsigned int bs =3D crypto_ahash_blocksize(tfm); + union { + u8 *u8; + u64 *u64; + } p =3D { .u8 =3D out }; + + if (dthe_hash_has_flag(rctx, DTHE_HASH_FLAG_PHASH_AVAIL)) + memcpy(out, rctx->phash, ctx->phash_size); + else + memcpy(out, dthe_hash_get_init_state(ctx), ctx->phash_size); + + p.u8 +=3D ctx->phash_size; + put_unaligned(rctx->digestcnt[0], p.u64++); + if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) + put_unaligned(rctx->digestcnt[1], p.u64++); + + memcpy(p.u8, rctx->data, bs); + p.u8 +=3D bs; + put_unaligned(rctx->flags, p.u8++); + + return 0; +} + +static int dthe_hash_import(struct ahash_request *req, const void *in) +{ + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + unsigned int bs =3D crypto_ahash_blocksize(tfm); + union { + const u8 *u8; + const u64 *u64; + } p =3D { .u8 =3D in }; + + memcpy(rctx->phash, in, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + rctx->digestcnt[0] =3D get_unaligned(p.u64++); + if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) + rctx->digestcnt[1] =3D get_unaligned(p.u64++); + + memcpy(rctx->data, p.u8, bs); + p.u8 +=3D bs; + rctx->flags =3D get_unaligned(p.u8++); + + return 0; +} + +static struct ahash_engine_alg hash_algs[] =3D { + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA512_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha512", + .cra_driver_name =3D "sha512-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA384_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha384", + .cra_driver_name =3D "sha384-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA256_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha256", + .cra_driver_name =3D "sha256-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA224_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha224", + .cra_driver_name =3D "sha224-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, +}; + +int dthe_register_hash_algs(void) +{ + return crypto_engine_register_ahashes(hash_algs, ARRAY_SIZE(hash_algs)); +} + +void dthe_unregister_hash_algs(void) +{ + crypto_engine_unregister_ahashes(hash_algs, ARRAY_SIZE(hash_algs)); +} --=20 2.34.1 From nobody Tue Sep 29 13:19:51 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 754FB42FCD9; Fri, 7 Aug 2026 11:06:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786100792; cv=fail; b=AxAf3aiRWycQ3ZT56kSwwR0aawN/ykzWQ1Ksdk1hkPTmXcELB+1DfS7yhQ8m/O3lCTGsZOIGRvEnPj9B8UstoMjTXSA+jchK8Qopu99kqCIaFIT3PKDnaVV0abCTzNg2pKVhTrPk03/yDRZzTC1pIpJWlrJj0bHKUHZsNFkl5oE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786100792; c=relaxed/simple; bh=iKu3PR7tNQxltSK+nDXTxYsf+vbkKv6v0DnAYUi4zJs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JPXIUadyS+Z8VMko9BrexnjvdrpjKY1j/Tm7zON0DTJ6lewBTaowKYqDXBXEwotLeltWD5Ok4sGFzUjFANuUPWNRnh9QKlpYkBROa+Vyt81RAM1EKiEC6xOqTldGYqNJEYMT2YPy0hPA9iqG00I+jMnxIEVZyWiPxIHf3/CLz/M= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=SkFvdAu/; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=cpK5lAL3; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="SkFvdAu/"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="cpK5lAL3" Received: from pps.filterd (m0374956.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6777bYDr2210988; Fri, 7 Aug 2026 06:06:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=vbPgoWR35+38CeJq1jbnrtPT62+k80Lt15d6ii8Tu bU=; b=SkFvdAu/fWrc11RUU3BE8o/iep7dJE3ZFmQtXmPy4RzvA5QwdfoNfZI1Y kxXbJPiMaM9rG8B3c5yFuB2LgaVCxy81A86hWxayQgcpWT0ZjqZKhckHsZ2gYgqc hO9AsQqXIx6wE3enpoaWc0rodu/KZCqY45iX+Jpr63nhkxdKICnEyMrTcPVnO0aG xsivkbr7X0D+b7HM9ScXvk9HdPPwfdSpBHbIBxRbzvNXg0ua7XZIfcHRsF0sUDwO gGXmp6Hd0OZPHccwHdjh7AYi9HB0g2vjxgCp448hQ4K1bz7uS/ou0/YI7o0KzyMS RLyE25vq0cE/AqGFwrff7LUd3fimw== Received: from dm5pr21cu001.outbound.protection.outlook.com (mail-centralusazon11011053.outbound.protection.outlook.com [52.101.62.53]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4fwb4wry92-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Fri, 07 Aug 2026 06:06:25 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=E1uY9mgR+mIroj7CokrYf1d/1A24Ix7Y9j6I+VkMMsyaVWE2m16w7Yid6AnzoKZmEYmMCxBULCOK3et6W82j6HZJcOlyYhyTw2TbCu4NVOvgkPCyWhwO2mMNvnPETSLQXzFJxSPfrQKrstJ7fXVTrDZTaTjBxEuc3mgsTuopR6v7VGz5Sj1X1/w4GDKdeDLru76sg/z5g4CS9H7wgbjV+xKnXotW4mZZZReei2Xgiuh0mBh29wZeKdfjHlp5jGS7cYzjIrZE6apf8IPqIBj7/oBoqSDmZezwfS//UnCnDFdSfsju8i4qtokVZKiFBL5+Uqgyu2JpCF4D+kINKYS2HA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vbPgoWR35+38CeJq1jbnrtPT62+k80Lt15d6ii8TubU=; b=dJua/eQwwlAOwSB30MUGUM67OWbZxTSN1u+NC7lHVkbJCZVwZGmU5OtIjUKfVDaNtrEHYWrKpdWDx1L2enax9ThqBbDLvAoxX/Pe/CMB0g2LeVHoOVVOfWgLBS6GHAyi9/p8WXDl2Lpz1GZW/MEsug6efUuOhZYBkRV63bVDauPiOBbMtZkReZOmESO/3xUD2iT8iapLo9N3qgzrZ9bCkJ5MgqOa1/h6W83n2ago2OkNccjMJ247SKGWSxJC4qsiUvZzuLgSpRSmcngoA1VWM8BeEao9pf+VjUr68MfqC+4katzoDaTgR9cKbupjmHabAW2YEMyXb33sKnqp+w6bQw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.194) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vbPgoWR35+38CeJq1jbnrtPT62+k80Lt15d6ii8TubU=; b=cpK5lAL3/jQMHkJJxH4xkZj/kdyWjEy5s9HgUqAKDJn8n4Nq1OlTs6Acb3lnKIGhocAJ4qMjMxQys6mxmbDiAP1trhWD8WcxnJhhWnDdeLRbyYd3x5k2KKWfzIDdKszuFY/mkOroTINSeBbw+HToCP+UgJTfrcTW/pY17Af3YI4= Received: from SJ0PR03CA0187.namprd03.prod.outlook.com (2603:10b6:a03:2ef::12) by CO6PR10MB5603.namprd10.prod.outlook.com (2603:10b6:303:14a::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.23; Fri, 7 Aug 2026 11:06:17 +0000 Received: from CO1PEPF00012E64.namprd05.prod.outlook.com (2603:10b6:a03:2ef:cafe::76) by SJ0PR03CA0187.outlook.office365.com (2603:10b6:a03:2ef::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.21 via Frontend Transport; Fri, 7 Aug 2026 11:06:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 198.47.23.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.194; helo=lewvzet200.ext.ti.com; pr=C Received: from lewvzet200.ext.ti.com (198.47.23.194) by CO1PEPF00012E64.mail.protection.outlook.com (10.167.249.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Fri, 7 Aug 2026 11:06:16 +0000 Received: from DLEE215.ent.ti.com (157.170.170.118) by lewvzet200.ext.ti.com (10.4.14.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Fri, 7 Aug 2026 06:05:51 -0500 Received: from DLEE209.ent.ti.com (157.170.170.98) by DLEE215.ent.ti.com (157.170.170.118) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Fri, 7 Aug 2026 06:05:51 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE209.ent.ti.com (157.170.170.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37 via Frontend Transport; Fri, 7 Aug 2026 06:05:51 -0500 Received: from pratham-Workstation-PC (pratham-workstation-pc.dhcp.ti.com [10.24.53.205]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 677B5nE41705312; Fri, 7 Aug 2026 06:05:50 -0500 From: T Pratham To: T Pratham , Herbert Xu , "David S. Miller" CC: Manorit Chawdhry , Shiva Tripathi , Sebin Francis , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v5 2/3] crypto: ti - Add support for MD5 in DTHEv2 Hashing Engine driver Date: Fri, 7 Aug 2026 16:34:58 +0530 Message-ID: <20260807110501.975130-3-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260807110501.975130-1-t-pratham@ti.com> References: <20260807110501.975130-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E64:EE_|CO6PR10MB5603:EE_ X-MS-Office365-Filtering-Correlation-Id: e153a949-a829-4cb7-6730-08def473e706 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|23010399003|82310400026|10067099003|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: jLdLuVZKgosXusPBiw7c/YFcL229WKb0jSRx0H2GpTnnYPdZoxslF6mIQMUaP/Bdb0NkFive0dO6b55z1JrB7CQz2o2EEYUWu+WBwW3c2gXgI/AVKwYN8SoQC0v5SwdjiVzIrPyhjRog58agZhswr9d5Ub3BSLGHGRHN07I4AX+zqwpdXcu0KmGL0YlvMKZruOcThx9WQy1cuDoQCAvlwKINK/JXY97mHb3aLxyrSrPtO/gfG0Aer8VaqHa8YnpOagML8nETNNxQlG3PI07l464n196udZkzw192iQzuW1/819L9dM2wedWXZH8BOlJUV0ql6VNN57G/iAZJq8eUzvoU3nhLee5sjYQJw8TSisPRp7FlpeboVSdZPqqusPT8+CrU8i8o9XQQAnsGn5uV1LsZ6S1SVKgh9qvvHsGUDDMcszi4bulIr3E/fdKIVXl7VChXB3P/5vYJx8L9V6eG5XtAQf5aC6E7ZpmWDoJbs2xlJjfOaqlTbcUxc5kLvSgGQ50Ss6W0+HeVAC0DcbsZ0SE/soSJY5TPHMk3wc2FtTorM1A1eUnIgI69RfgdGJF2srTII0rMTAeo799jJezHa2wkgsijIRdBrO6kOrfDTKuEso2doe49maKnWrdBIawMAI1ub65cMm6m+UAHlzqfpXaHLvSUf/cfLjf+5ZvlH91y5YyW+Ml5qzxEjiMWCKzUJ9RP3eKTBTwNZF+yvjKl6g== X-Forefront-Antispam-Report: CIP:198.47.23.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet200.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(376014)(23010399003)(82310400026)(10067099003)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: I8T9xX7yKR7L5AIC3gvAKe0LS33NutyP4Ki7TGnsFuL8cLD9pqn01mcHEJ5nWcfRl7GqOZ56k1HoHUTXfKULG/21NlgOcpBSDgcTK0jE6ebXOjYEvCcEMtezVZ1Er/U1gPvT+YJs7EYfLa7CmWw6mAF95i5xS/rQ2SFKvESRd3DdueA6s7uTZcbTKvvteHDE0MOohJazLmqwdMC/386hSep49sySjhJoMo0+tik7HylcUuMbnUKX7FeNMXd3+AWdc5FhuYLxcdLGN+6m79UdDW5eQTZau6yIsHSh6Gv7/sS2STXox+e7co7aKLCmWv/sZEzuwoguVLk6Dt8Pb01kAMxGH2HPp31VOCGHyEZMkE17A5hhOw2dyJhF1WPWR79HMVC+T/+6fGxEg1WjCdjHrxRJ2R+KVKj2RZBQYfpRgOGYZSzDXlqt10ZXEuhCbxwB X-Exchange-RoutingPolicyChecked: ZznFtaL5LAMcIHa21n4SduFAeZkwJw2jLozMp2dXI+WazphWZeDPvV9KCAfAIegOFuiRHn6+zMCqITjh9v6QHnaJHJb5Ki3Ca91oCP1s8Q2CW3i9Csu6vRVPybsLTJeOeGrZ9QGsn/lElnD2ocl8vp0PYlRBPj61s4c02ls/3EagdgnSGyq4cyPcoFb1MSC9A0uEux4dDyAsv2QawmJ3TSZjf4ZVKlTbiEo38QDGah4Iik8x/xczRbCaVM4V/J/J1RzedI5NtOQIuPBrxfqyYRKQewcPjUgTqcnfao653MDApmuh2fqmG9eArCHemamq6ZCnsANCaWGBKno3DhYhig== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2026 11:06:16.6208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e153a949-a829-4cb7-6730-08def473e706 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E64.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5603 X-Authority-Analysis: v=2.4 cv=FaEHAp+6 c=1 sm=1 tr=0 ts=6a75bc32 cx=c_pps a=9V9/KAGQR/RGwytZTnC4xw==:117 a=WotqVVQAdb04rnGuttW3Kw==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=Sv0fKeRqtYgA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=jwouBfj2j3NM8CExmVVE:22 a=sozttTNsAAAA:8 a=_Bk9PBcLl1eLgj3c6_AA:9 X-Proofpoint-ORIG-GUID: JflvBGeaLzA4EomyID2sEP55-l94Into X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA4NSBTYWx0ZWRfX9vtSRsJxq78z ggXnJ7xvou5tfd84EWGmN5P5W2AfArsVk8mfFXRLJxlW77/WbxqzJA/7mHua2qf3VEZ1AMiwV0O kpqUPdU/Ea5aUKTZ/9upfKnjePP9UxU= X-Proofpoint-GUID: JflvBGeaLzA4EomyID2sEP55-l94Into X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA4NSBTYWx0ZWRfX7CbBVsU0aRx1 rHyCuIO10pT8e9CFk8gzVwrO/4WnCCSNdhlh8hAR4jk3tDZMY+JIMGqh2RHhiReeAVIIgUEqPyI pkXj3211CkDEyR9gnjGPDC2pLzJS7KAx1Cx8GA1FVYtVd7wEr6r7W7TiA07nHTjpm8PfGa7Ipc6 GdU4B+tbF6Kwwb5iLv8WItRwlisx0ddTOpsMJosh3KC9pGkdpPCpo44/zKTYV3JOZpTPwVATK/R 5MKDpFgoFSjtAiaiYd446qmtfhjfYm25H6JFWHby4JmaYjIapV/6sr2Gh8ovhKOrsEBUbrsO0m3 N541Vw/IS8sPUH4MgOH948v8HLmVK6FuKcZVQs2tHNcufsbBWouTyiPNPkkhKbPWYl/V2gT1pU9 Y4yD0+TG4Ihc9zcN9WUgMKA0hZT/Oan7SAor+RDE+GGY46DSdJjcNTrJ0BT0d6rYmJ2FfTmLqNc rpgHL4ahSQH3Uvtr4DQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 priorityscore=1501 spamscore=0 phishscore=0 bulkscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070085 Content-Type: text/plain; charset="utf-8" Add support for MD5 algorithm in the hashing engine of DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 1 + drivers/crypto/ti/dthev2-common.h | 1 + drivers/crypto/ti/dthev2-hash.c | 47 +++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 90af2c7cb1c55..9c2aa50cfbfbe 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -12,6 +12,7 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_CCM select CRYPTO_SHA256 select CRYPTO_SHA512 + select CRYPTO_MD5 select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index d3fb7c5ff3052..2c6e06df16d35 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 #include diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-has= h.c index dc7a397a9e58c..1606b982e4581 100644 --- a/drivers/crypto/ti/dthev2-hash.c +++ b/drivers/crypto/ti/dthev2-hash.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include =20 @@ -97,6 +98,9 @@ static void dthe_hash_write_zero_message(enum dthe_hash_a= lg_sel mode, void *dst) case DTHE_HASH_SHA224: memcpy(dst, sha224_zero_message_hash, SHA224_DIGEST_SIZE); break; + case DTHE_HASH_MD5: + memcpy(dst, md5_zero_message_hash, MD5_DIGEST_SIZE); + break; default: break; } @@ -125,6 +129,9 @@ static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(s= truct crypto_ahash *tfm) case SHA224_DIGEST_SIZE: hash_mode =3D DTHE_HASH_SHA224; break; + case MD5_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_MD5; + break; default: hash_mode =3D DTHE_HASH_ERR; break; @@ -146,6 +153,9 @@ static unsigned int dthe_hash_get_phash_size(struct dth= e_tfm_ctx *ctx) case DTHE_HASH_SHA224: phash_size =3D SHA256_DIGEST_SIZE; break; + case DTHE_HASH_MD5: + phash_size =3D MD5_DIGEST_SIZE; + break; default: break; } @@ -489,6 +499,10 @@ static const u64 sha512_init_state[SHA512_DIGEST_SIZE = / sizeof(u64)] =3D { SHA512_H4, SHA512_H5, SHA512_H6, SHA512_H7 }; =20 +static const u32 md5_init_state[MD5_DIGEST_SIZE / sizeof(u32)] =3D { + MD5_H0, MD5_H1, MD5_H2, MD5_H3 +}; + static const void *dthe_hash_get_init_state(struct dthe_tfm_ctx *ctx) { switch (ctx->hash_mode) { @@ -500,6 +514,8 @@ static const void *dthe_hash_get_init_state(struct dthe= _tfm_ctx *ctx) return sha384_init_state; case DTHE_HASH_SHA512: return sha512_init_state; + case DTHE_HASH_MD5: + return md5_init_state; default: return NULL; } @@ -682,6 +698,37 @@ static struct ahash_engine_alg hash_algs[] =3D { }, .op.do_one_request =3D dthe_hash_run, }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D MD5_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "md5", + .cra_driver_name =3D "md5-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D MD5_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, }; =20 int dthe_register_hash_algs(void) --=20 2.34.1 From nobody Tue Sep 29 13:19:51 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA9F042F71F; Fri, 7 Aug 2026 11:06:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=148.163.154.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786100811; cv=fail; b=s2ezXl4EwDJiQODqEo9BNBvIRZVHOQ07tqTnLi4WuzmEJk5Ks96zSMzhtHq6nv+Dov7fHRS9wHslylQX0UlLDQbBKHv/+vfSEgrwjPJH2XKZmxDYFS1qvlZ5uvqtCY3Gody/+9If/mAlclLk2R9afCcEmpcO7gkxlwmjJElw0yU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786100811; c=relaxed/simple; bh=HyUiu7333CFvY+/FdUiAVHLFGhNt89JMVzZTqH0JCec=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Elz7IuY+D6eKeIFbi+fA6V+U1H7M+8RCLnBYHufBNG2I/0IPiUZdf4E2mnwcz3qi9d8fQqbLbW1EkYYGX/Mdsv4F3YkZiM+Tfr1Lws8L6ARt46qgC/cu+SO3MH7FpEWz6ax6lndU+vRMZUpASRlLmhz/xC4fd2hbitoGPDLi0tc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b=HwypuFg7; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ag5+uNCG; arc=fail smtp.client-ip=148.163.154.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ti.com header.i=@ti.com header.b="HwypuFg7"; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ag5+uNCG" Received: from pps.filterd (m0374955.ppops.net [127.0.0.1]) by mx0b-0002e601.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6777j0tP2583830; Fri, 7 Aug 2026 06:06:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= proofpoint-05-2026; bh=drs9Mbi8yLZXeb2+Vkc652DgOgwPEHRF2O/jaeZUT x4=; b=HwypuFg7DNRCp0LOenVf3xeKvcgFZMxt/jAgv+fHQobXXMwUHImgUU3fq WNTu/VqZOREu1qHO4279Hm5XHTihOe46a0GZVY2bJXCUqevH/ssKB2cJGAlLa/l/ 2MImnN5a+Qk1uMg5scnx99E2bT+43wT7ndiQwIebvJaBzDtKHtSW0nzd+0ITHSHf Jrl04cl+SZ89eaQXC4ErwE+3PJn8PM3x9fRSaAFGjbrKkQi0Llb1vwMO1igX1asT xhL8VaNbCCm5hrF7xZpIRIzUa5TG85LCSzzOhAl67o8cKvlUxo0m9rEXdl3a8Uvu w5pHLSwaFFF837rmeUaTSmE5TryVw== Received: from sn4pr0501cu005.outbound.protection.outlook.com (mail-southcentralusazon11011066.outbound.protection.outlook.com [40.93.194.66]) by mx0b-0002e601.pphosted.com (PPS) with ESMTPS id 4fwb8dgwt3-1 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Fri, 07 Aug 2026 06:06:44 -0500 (CDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=m5yk875t2PvsAkZqxu8lIBWVmkn25AJJ4FG70nI0HHO/HPxFNdmmOg5ypOYmA62phLSUwcR27E0eYmnhP0FEwZ+p1KttJQWn+GXhVQ3DZ/JedCPdH7tegXIAwgvVWMDoWMzf/mXY1jlpFBbJG4thplABi9cDTu+P7mqje3MiNG6TGDlVqTYhgj5TfxJwJE1rL/gEatZ6KMrIMaA41mSrr4GEFJ9eIzJ62Zzdvl5j7kyST62kqgzmtIk01w22qz8gVVT8PBjO4sWpsuncOsipbqU2lqzzj6+3E1owTjySsz6fScoLi3dvaag5OUO6W+EX4+mWaYAgMn88G/uBgUHDng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=drs9Mbi8yLZXeb2+Vkc652DgOgwPEHRF2O/jaeZUTx4=; b=b+zUpbmAWMxuJ81gDV0B68/NlGvH5s2MPtqbboeDIFwwW/pkFqRia4roJHH3Gb6qw8/CmoL6glmLK4dNSJY1MaDhVnU5O1nOpEKaJuTQslbPMH4lJ9gisy8AXXGaiqw7WkOMQvt3C9rcyFuE/9Yc4z71XsUCNZq4XJEhXMlDpjbf11sYBi7pdx/mVXbxIeCmSY3gODAnhWoT293ryMVV0h1512VlRKhPnhg6tndSd0LnVlM2tsPrjga6ZueFUU74M94Fknhq6jx94MWYv2qZUwgmLEYRL2mWleDjm2RvtmyIpjyKxYiPO2j/yjNrIHVCwBp7pcoDr+INvIu90pufUQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.194) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=drs9Mbi8yLZXeb2+Vkc652DgOgwPEHRF2O/jaeZUTx4=; b=ag5+uNCGdH8i8Le6eJGjU/KvzhGZtk0/C9IytJXvKWfJj+YtXoXF9ky5QHcW6ffRgiyXhIYrBgqQ4n68WtIkq56nJgoxA8OiEXtqGb6P2Qme5ySP58otGs5l135ENYgLDrG2G1Mh70wP7GcCgs1ZbJJZCjN8fqw3Vpx+sZjpbBY= Received: from CYZPR19CA0023.namprd19.prod.outlook.com (2603:10b6:930:8e::29) by DS4PPF109C7C399.namprd10.prod.outlook.com (2603:10b6:f:fc00::d0a) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.19; Fri, 7 Aug 2026 11:06:40 +0000 Received: from CY4PEPF0000EE30.namprd05.prod.outlook.com (2603:10b6:930:8e:cafe::26) by CYZPR19CA0023.outlook.office365.com (2603:10b6:930:8e::29) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.24 via Frontend Transport; Fri, 7 Aug 2026 11:06:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 198.47.21.194) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.194 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.194; helo=flwvzet200.ext.ti.com; pr=C Received: from flwvzet200.ext.ti.com (198.47.21.194) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Fri, 7 Aug 2026 11:06:38 +0000 Received: from DFLE214.ent.ti.com (10.64.6.72) by flwvzet200.ext.ti.com (10.248.192.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Fri, 7 Aug 2026 06:05:59 -0500 Received: from DFLE214.ent.ti.com (10.64.6.72) by DFLE214.ent.ti.com (10.64.6.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Fri, 7 Aug 2026 06:05:59 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE214.ent.ti.com (10.64.6.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37 via Frontend Transport; Fri, 7 Aug 2026 06:05:59 -0500 Received: from pratham-Workstation-PC (pratham-workstation-pc.dhcp.ti.com [10.24.53.205]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 677B5viW944863; Fri, 7 Aug 2026 06:05:58 -0500 From: T Pratham To: T Pratham , Herbert Xu , "David S. Miller" CC: Manorit Chawdhry , Shiva Tripathi , Sebin Francis , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v5 3/3] crypto: ti - Add support for HMAC in DTHEv2 Hashing Engine driver Date: Fri, 7 Aug 2026 16:34:59 +0530 Message-ID: <20260807110501.975130-4-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260807110501.975130-1-t-pratham@ti.com> References: <20260807110501.975130-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|DS4PPF109C7C399:EE_ X-MS-Office365-Filtering-Correlation-Id: 7b041202-9d9a-44ec-a51e-08def473f427 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|23010399003|82310400026|1800799024|56012099006|10067099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: h3gIcvJhLWmBbn1MDt86uU07g8UTjDqAgQT2qaxLzPuvHz0i7gG0Yx7SHxz2Lb0LryyUHxV4nPuQorYl+Qfw6VpPxYbmZBCtzaHPReN2iYTfXm6B6gwlcuLqg22K295Q6ogf5mPscvvZvM3nSKH110lIIkDOS/jXymRjnDMmBqQ/7AIwIv+jjJbSiew4gMjPX/agVeVwZAW9OqITvTemGinjEg2SZrrPCY4OQsHxLvmZGCzZi7AwDCDgu6R7mkMC2MeTbPWFWGwva3uzWPb3gtK4/hqr2ejZwgSgQgXyMu+X6V/xzxDW/aSB63bL+geDvLEnE+1HPToun/BMuTjQ590yrvWiQFpfi3nxsIMAK4ZVsrTzYW/iuxdsZGB44O/6q30AzbGQIMxuzAk8zVwvxJMSN7bAe2O/gYfM3htUL7dExeMhTlZUU/biYtIJRqq4yf9tG1XHNKKMQHja9b0r6IKfomgh/ZXdAWbIR4mVuwsOykkyVkH938ONgTjlYCLfOlljc/2x9z4zIlFMNl2Yi6eMYDO2gGYTl7mjl0joP9va3CE0V716H5N8cliiSp/yqOLy5gt1mkTK088My5gTOrYgGQkS4n2SDRgHClF5jAlxgw6uTcKy4YNCdIFTKKEvaARtWmqHpn5QmMkQN3Z9lkEIvHuS5/ZlPml7thKErpnXd/bwVY7NeddmfQh2jpbVTQVAv5IXDrs1nHpquWSTIw== X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(376014)(36860700016)(23010399003)(82310400026)(1800799024)(56012099006)(10067099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rFePVio+C9NCMYFSEA7+fhxew//1ZNzqiGeDPtWs+6XvNmuu3VAvTMto5xrnzX7vTDrGJOD2g+kqK27hwBGmgMHlp/1sEUUyiWLOL+9u0KW7WHjf9FIicY5EK3pv0L0irxLmAvJYnd1Y1YZOcIm7hU4wDn02tlaj7NoDN3SSWS2+wDhdLRjvtBcP61M9oD7DX2svmSmE5obXj5vztywrpHi1vCa/wuQaJ7sFs1xfu6c8VJ2ZmQ/EAytG3LGkwMv8Xn2j/yizXAlGB4njaJ2wKHBtAG7pJL3jNaqej+P0pV1e85tFjKqIU84AEaJoovz4gSgDf1X8tQoGE6VzJsksNFkA0dfecC3EBDofDgTZJTZhey/+/447nVvLfMcXZGdFd+uSrLaDSWZ8MreDbJfseSc3Q3UQujIhAtfgL2QCAgMaKEGfdesmDMcdG1SfSUu7 X-Exchange-RoutingPolicyChecked: pD7/W6JlGt6lbStCkRU6M2/jfBxT85pqplE+fQp+JOIZGonGTNg06CqC6gZVBYepOxWrVJo9w4McY/jCHOX283bdh8C8eZ/GUqgrqcidMwhJdf1hujstqtClWrPPzN9TBK66Z03Q43OQGp600vyTHSsJAp3mh4FmDsm8pKuZjCjDgX9cZf6UQHKkQPwmjRm1WWqUXAAkBTQrftxyiqu8Hju0qhbwPQlJu3KDTkQptwzBMz+z6aUNm0zBOVsaZ/S01qCXmZldDWjoPR3lp0pur7Y9V/X9zV7DBeBFzdaryrQsIk8NkEvrrI6G1sJT2RNhvg+zXNk7kXjvZJZOPj0E+Q== X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2026 11:06:38.7050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b041202-9d9a-44ec-a51e-08def473f427 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PPF109C7C399 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA4NCBTYWx0ZWRfXxpfSBCq7/3sp XfnXPgjjEsf57OtxFUBtKHQNgn2Dlc8dEd1hA0/hfUWaKkMwGcz85xzpv7Zhas5mKlpTFjmYIii trYkmMFbtIRZn19GVEEUCOTer8qRSMcayIRHSvCIs0Ksghxh9Pw+vekYY6tsSh81/CATydSxbj/ YniGTtiq+n8KpKHJyyq9WaCeGTOu9Vdnm6kSrrH+revGPDxr2YDJlO8tTNRYI4akZSSaky4m6YW IMHaQgNN8Tk0CTPXrccQW4EW5gmBzBJhsbYrhVPNtnLVs3sBx3RJXtKKH1wH5wXVl+L7MmBcU+T 5hVoaoV34gHQw98Lxi/FpE0uyXRH0gumWZv9GXGTY0mAE6OiFikd1AkjYkDpZMDoi46IK19rSvi urfpPnTuDmVChfo2GOuj/FUsS24RU+3ToI2wti78eBv8LOfOCki3zAKx21xsNcDTeBcsJ9QvSwo gE6nMpdenGvI5wXaF+w== X-Proofpoint-ORIG-GUID: GopJ0ZwglqpdhD4cwXgKz8gnPni-1jRs X-Proofpoint-GUID: GopJ0ZwglqpdhD4cwXgKz8gnPni-1jRs X-Authority-Analysis: v=2.4 cv=Ouh/DS/t c=1 sm=1 tr=0 ts=6a75bc44 cx=c_pps a=1t1hxDBgkqdAqWWjFE2LMw==:117 a=iwqwCZQqcuTv3JOpYdM7/Q==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=Sv0fKeRqtYgA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=fPAWb5peG099m5CrUpKH:22 a=sozttTNsAAAA:8 a=UJvMcVJv5lc1T41YKn0A:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA4NCBTYWx0ZWRfXykJxkwK292tu w6e9aH6Z0PzSqzVl5pLCfan3kpq4/lFzY15GnsL9ay/r6PgQBL61jnsKA2+6xutupk2ohtceBEa UID1wLpIe+/PxC2g9hIDEZon0rZ/TUE= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 priorityscore=1501 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070084 Content-Type: text/plain; charset="utf-8" Add support for HMAC-SHA512/384/256/224 and HMAC-MD5 algorithms in the hashing engine of the DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 1 + drivers/crypto/ti/dthev2-common.h | 10 +- drivers/crypto/ti/dthev2-hash.c | 334 +++++++++++++++++++++++++++++- 3 files changed, 340 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 9c2aa50cfbfbe..68dccf92f5382 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -13,6 +13,7 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_SHA256 select CRYPTO_SHA512 select CRYPTO_MD5 + select CRYPTO_HMAC select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index 2c6e06df16d35..965e4004be77e 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -31,9 +31,9 @@ #define DTHE_DMA_TIMEOUT_MS 2000 /* * Size of largest possible key (of all algorithms) to be stored in dthe_t= fm_ctx - * This is currently the keysize of XTS-AES-256 which is 512 bits (64 byte= s) + * This is currently the keysize of HMAC-SHA512 which is 1024 bits (128 by= tes) */ -#define DTHE_MAX_KEYSIZE (AES_MAX_KEY_SIZE * 2) +#define DTHE_MAX_KEYSIZE (SHA512_BLOCK_SIZE) =20 enum dthe_hash_alg_sel { DTHE_HASH_MD5 =3D 0, @@ -93,9 +93,9 @@ struct dthe_list { /** * struct dthe_tfm_ctx - Transform ctx struct containing ctx for all sub-c= omponents of DTHE V2 * @dev_data: Device data struct pointer - * @keylen: AES key length + * @keylen: Key length for algorithms that use a key * @authsize: Authentication size for modes with authentication - * @key: AES key + * @key: Buffer storing the key * @aes_mode: AES mode * @hash_mode: Hashing Engine mode * @phash_size: partial hash size of the hash algorithm selected @@ -135,6 +135,7 @@ struct dthe_aes_req_ctx { * @phash: buffer to store a partial hash from a previous operation * @digestcnt: stores the digest count from a previous operation; currentl= y hardware only provides * a single 32-bit value even for SHA384/512 + * @odigest: buffer to store the outer digest from a previous operation * @padding: padding buffer for handling unaligned data * @data: buffer to store one block of data to defer operations for non-ze= ro final. * @flags: bitfield of flags for internal use. @@ -146,6 +147,7 @@ struct dthe_aes_req_ctx { struct dthe_hash_req_ctx { u32 phash[SHA512_DIGEST_SIZE / sizeof(u32)]; u64 digestcnt[2]; + u32 odigest[SHA512_DIGEST_SIZE / sizeof(u32)]; u8 padding[SHA512_BLOCK_SIZE]; u8 data[SHA512_BLOCK_SIZE]; u8 flags; diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-has= h.c index 1606b982e4581..7bac7294f0034 100644 --- a/drivers/crypto/ti/dthev2-hash.c +++ b/drivers/crypto/ti/dthev2-hash.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -25,6 +26,7 @@ /* Registers */ =20 #define DTHE_P_HASH_BASE 0x5000 +#define DTHE_P_HASH512_ODIGEST_A 0x0200 #define DTHE_P_HASH512_IDIGEST_A 0x0240 #define DTHE_P_HASH512_DIGEST_COUNT 0x0280 #define DTHE_P_HASH512_MODE 0x0284 @@ -47,6 +49,13 @@ =20 #define DTHE_HASH_MODE_USE_ALG_CONST BIT(3) #define DTHE_HASH_MODE_CLOSE_HASH BIT(4) +#define DTHE_HASH_MODE_HMAC_KEY_PROCESSING BIT(5) +#define DTHE_HASH_MODE_HMAC_OUTER_HASH BIT(7) + +/* Misc */ +#define DTHE_HMAC_SHA512_MAX_KEYSIZE (SHA512_BLOCK_SIZE) +#define DTHE_HMAC_SHA256_MAX_KEYSIZE (SHA256_BLOCK_SIZE) +#define DTHE_HMAC_MD5_MAX_KEYSIZE (MD5_BLOCK_SIZE) =20 /* rctx flag bitfields */ #define DTHE_HASH_FLAG_OP BIT(0) @@ -106,6 +115,19 @@ static void dthe_hash_write_zero_message(enum dthe_has= h_alg_sel mode, void *dst) } } =20 +static int dthe_hmac_write_zero_message(struct ahash_request *req) +{ + HASH_FBREQ_ON_STACK(fbreq, req); + int ret; + + ahash_request_set_crypt(fbreq, req->src, req->result, + req->nbytes); + + ret =3D crypto_ahash_digest(fbreq); + HASH_REQUEST_ZERO(fbreq); + return ret; +} + static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(struct crypto_ahash = *tfm) { unsigned int ds =3D crypto_ahash_digestsize(tfm); @@ -163,6 +185,18 @@ static unsigned int dthe_hash_get_phash_size(struct dt= he_tfm_ctx *ctx) return phash_size; } =20 +static const char *dthe_hash_get_alg_name(struct dthe_tfm_ctx *ctx) +{ + switch (ctx->hash_mode) { + case DTHE_HASH_SHA224: return "sha224"; + case DTHE_HASH_SHA256: return "sha256"; + case DTHE_HASH_SHA384: return "sha384"; + case DTHE_HASH_SHA512: return "sha512"; + case DTHE_HASH_MD5: return "md5"; + default: return NULL; + } +} + static int dthe_hash_init_tfm(struct crypto_ahash *tfm) { struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); @@ -216,6 +250,7 @@ static int dthe_hash_dma_start(struct ahash_request *re= q, struct scatterlist *sr enum dma_data_direction src_dir =3D DMA_TO_DEVICE; u32 hash_mode; int ds =3D crypto_ahash_digestsize(tfm); + bool is_hmac =3D (ctx->keylen > 0); int ret =3D 0; u32 *dst; u32 dst_len; @@ -263,6 +298,9 @@ static int dthe_hash_dma_start(struct ahash_request *re= q, struct scatterlist *sr =20 if (dthe_hash_flag_is_op(rctx, DTHE_HASH_OP_FINUP)) { hash_mode |=3D DTHE_HASH_MODE_CLOSE_HASH; + if (is_hmac) + hash_mode |=3D DTHE_HASH_MODE_HMAC_OUTER_HASH; + } =20 if (dthe_hash_has_flag(rctx, DTHE_HASH_FLAG_PHASH_AVAIL)) { for (int i =3D 0; i < ctx->phash_size / sizeof(u32); ++i) @@ -270,9 +308,28 @@ static int dthe_hash_dma_start(struct ahash_request *r= eq, struct scatterlist *sr sha_base_reg + DTHE_P_HASH512_IDIGEST_A + (DTHE_REG_SIZE * i)); + if (is_hmac) { + for (int i =3D 0; i < ctx->phash_size / sizeof(u32); ++i) + writel_relaxed(rctx->odigest[i], + sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } =20 writel_relaxed(rctx->digestcnt[0], sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); + } else if (is_hmac) { + hash_mode |=3D DTHE_HASH_MODE_HMAC_KEY_PROCESSING; + + for (int i =3D 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i], sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + for (int i =3D 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i + (ctx->keylen / 2) / sizeof(u32)], + sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); } else { hash_mode |=3D DTHE_HASH_MODE_USE_ALG_CONST; } @@ -307,6 +364,12 @@ static int dthe_hash_dma_start(struct ahash_request *r= eq, struct scatterlist *sr dst[i] =3D readl_relaxed(sha_base_reg + DTHE_P_HASH512_IDIGEST_A + (DTHE_REG_SIZE * i)); + if (is_hmac) { + for (int i =3D 0; i < dst_len; ++i) + rctx->odigest[i] =3D readl_relaxed(sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } =20 rctx->digestcnt[0] =3D readl_relaxed(sha_base_reg + DTHE_P_HASH512_DIGEST= _COUNT); dthe_hash_flag_set(rctx, DTHE_HASH_FLAG_PHASH_AVAIL); @@ -462,6 +525,10 @@ static int dthe_hash_final(struct ahash_request *req) return crypto_transfer_hash_request_to_engine(engine, req); } =20 + if (ctx->keylen > 0) + /* HMAC with zero-length message */ + return dthe_hmac_write_zero_message(req); + dthe_hash_write_zero_message(ctx->hash_mode, req->result); =20 return 0; @@ -521,6 +588,53 @@ static const void *dthe_hash_get_init_state(struct dth= e_tfm_ctx *ctx) } } =20 +/* + * Compute the HMAC inner or outer pad state (the intermediate hash state = after + * processing one block of key XOR pad_byte) and write it to @out. Only the + * first ctx->phash_size bytes are written, which is always the raw hash s= tate + * at the start of the shash export struct. + */ +static int dthe_hmac_compute_pad_state(struct dthe_tfm_ctx *ctx, u8 pad_by= te, + void *out) +{ + const char *alg_name =3D dthe_hash_get_alg_name(ctx); + struct crypto_shash *ktfm; + u8 data[SHA512_BLOCK_SIZE]; + unsigned int ss; + u8 *state; + int ret; + + ktfm =3D crypto_alloc_shash(alg_name, 0, 0); + if (IS_ERR(ktfm)) + return PTR_ERR(ktfm); + + ss =3D crypto_shash_statesize(ktfm); + state =3D kmalloc(ss, GFP_KERNEL); + if (!state) { + crypto_free_shash(ktfm); + return -ENOMEM; + } + + SHASH_DESC_ON_STACK(desc, ktfm); + + desc->tfm =3D ktfm; + for (int i =3D 0; i < ctx->keylen; i++) + data[i] =3D ((u8 *)ctx->key)[i] ^ pad_byte; + + ret =3D crypto_shash_init(desc) ?: + crypto_shash_update(desc, data, ctx->keylen) ?: + crypto_shash_export(desc, state); + + if (!ret) + memcpy(out, state, ctx->phash_size); + + memzero_explicit(state, ss); + kfree(state); + crypto_free_shash(ktfm); + memzero_explicit(data, sizeof(data)); + return ret; +} + static int dthe_hash_export(struct ahash_request *req, void *out) { struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); @@ -531,9 +645,12 @@ static int dthe_hash_export(struct ahash_request *req,= void *out) u8 *u8; u64 *u64; } p =3D { .u8 =3D out }; + int ret =3D 0; =20 if (dthe_hash_has_flag(rctx, DTHE_HASH_FLAG_PHASH_AVAIL)) memcpy(out, rctx->phash, ctx->phash_size); + else if (ctx->keylen > 0) + ret =3D dthe_hmac_compute_pad_state(ctx, HMAC_IPAD_VALUE, out); else memcpy(out, dthe_hash_get_init_state(ctx), ctx->phash_size); =20 @@ -542,11 +659,16 @@ static int dthe_hash_export(struct ahash_request *req= , void *out) if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) put_unaligned(rctx->digestcnt[1], p.u64++); =20 + if (ctx->keylen > 0) { + memcpy(p.u8, rctx->odigest, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + } + memcpy(p.u8, rctx->data, bs); p.u8 +=3D bs; put_unaligned(rctx->flags, p.u8++); =20 - return 0; + return ret; } =20 static int dthe_hash_import(struct ahash_request *req, const void *in) @@ -566,6 +688,11 @@ static int dthe_hash_import(struct ahash_request *req,= const void *in) if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) rctx->digestcnt[1] =3D get_unaligned(p.u64++); =20 + if (ctx->keylen > 0) { + memcpy(rctx->odigest, p.u8, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + } + memcpy(rctx->data, p.u8, bs); p.u8 +=3D bs; rctx->flags =3D get_unaligned(p.u8++); @@ -573,6 +700,51 @@ static int dthe_hash_import(struct ahash_request *req,= const void *in) return 0; } =20 +static int dthe_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct crypto_ahash *fb =3D crypto_ahash_fb(tfm); + const char *hash_alg_name =3D dthe_hash_get_alg_name(ctx); + unsigned int max_keysize; + + memzero_explicit(ctx->key, sizeof(ctx->key)); + + switch (ctx->hash_mode) { + case DTHE_HASH_SHA512: + case DTHE_HASH_SHA384: + max_keysize =3D DTHE_HMAC_SHA512_MAX_KEYSIZE; + break; + case DTHE_HASH_SHA256: + case DTHE_HASH_SHA224: + max_keysize =3D DTHE_HMAC_SHA256_MAX_KEYSIZE; + break; + case DTHE_HASH_MD5: + max_keysize =3D DTHE_HMAC_MD5_MAX_KEYSIZE; + break; + default: + return -EINVAL; + } + + if (keylen > max_keysize) { + struct crypto_shash *ktfm =3D crypto_alloc_shash(hash_alg_name, 0, 0); + SHASH_DESC_ON_STACK(desc, ktfm); + int err; + + desc->tfm =3D ktfm; + err =3D crypto_shash_digest(desc, key, keylen, (u8 *)ctx->key); + crypto_free_shash(ktfm); + if (err) + return err; + } else { + memcpy(ctx->key, key, keylen); + } + + ctx->keylen =3D max_keysize; + + return crypto_ahash_setkey(fb, key, keylen); +} + static struct ahash_engine_alg hash_algs[] =3D { { .base.init_tfm =3D dthe_hash_init_tfm, @@ -729,6 +901,166 @@ static struct ahash_engine_alg hash_algs[] =3D { }, .op.do_one_request =3D dthe_hash_run, }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA512_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha512)", + .cra_driver_name =3D "hmac-sha512-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA384_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha384)", + .cra_driver_name =3D "hmac-sha384-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA256_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha256)", + .cra_driver_name =3D "hmac-sha256-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA224_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha224)", + .cra_driver_name =3D "hmac-sha224-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D MD5_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(md5)", + .cra_driver_name =3D "hmac-md5-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D MD5_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, }; =20 int dthe_register_hash_algs(void) --=20 2.34.1