From nobody Tue Sep 29 11:56:08 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D19B035CB60; Fri, 7 Aug 2026 14:46:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786114023; cv=none; b=JYZ0Qyzh70cHAcT1til2RZy1N7M2f7yC3l70dDxp74I/Oy9kz7Sbe8V7TgXq90UXoeM8ifdC5xRhcMzh/upolumaOB0qtoqFA2STvhECNvxINK1vngmkj31MZBKygNVCj+CTziB/h7CyZG8yZPIqfXfO2WsLc0bagRiV3vKOjAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786114023; c=relaxed/simple; bh=6U/Z+bAw+q5xT//V5j5bGdzx7yiFSpk9YA3+F2HTaLU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LYud4Vb/uJVHAdzQk95J4JdcSvzB4EpwPhl/hZGMKh5ouuv866F2V/NKlqq/GKBQsuoZg8vBeDU3yILpbNkQdZnW0K9ux0M5lJGvGgLstcRvMkMwWH5LuqBNv9sbWthrowqOymKQ0X4jPtdGnyUwtb1VqVsKvPkzSzz5/bIX+cI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=dwyPBSkO; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="dwyPBSkO" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 7B0C14E41140; Fri, 7 Aug 2026 14:46:56 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 505BC603F0; Fri, 7 Aug 2026 14:46:56 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F3BC711C37A5C; Fri, 7 Aug 2026 16:46:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1786114015; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=iyEhVWiiJcMafyU2wvE/rdUOzD3sdnM9u1y11KR3HLs=; b=dwyPBSkORIwBhtcXMH3U1Tl8HmDDkGLV6ErCoTW7EAuvYbTM6A59mxFohdz+KBGaCrx+Yv MrqA0FqFHCmjHfI2DU+LNiIHeZsaRgG5tEL46l9ZQ8cFjpk+3Hv8xg8PLSycj9ZwOEnJGk rN8qN7E7VOvfLXKTD8oJH8GjB2lkffn7Llx4FAKiq+lmnZJw9Wuap2AufWPgD1OEfIi1HK 7mhPGayFIdDPORQJBCmzPTfzj4ts3N00PIsVrbkmv9aTCOkidJ0mfuDGM0OohY2nQSyBZA R4dvWvKKoDvJIRHXcxPgSOU0ycOGv16Z+GVrij6ZiisC7k4iP54ckkoGRRS8zQ== From: Miquel Raynal Date: Fri, 07 Aug 2026 16:46:47 +0200 Subject: [PATCH v2 1/3] spi: spi-mem: Flag DQS capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-winbond-nand-next-phy-tuning-v2-1-73595e89d6e3@bootlin.com> References: <20260807-winbond-nand-next-phy-tuning-v2-0-73595e89d6e3@bootlin.com> In-Reply-To: <20260807-winbond-nand-next-phy-tuning-v2-0-73595e89d6e3@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 DQS is a typical SPI memory signal used to help with reading the data on the bus at high speeds (especially in DTR mode) by avoiding clock skews. The chip generates a clock signal synchronized with its data output fronts, also called data strobe. SPI NOR and SPI NAND cores must set this flag in order to indicate to other layers that DQS is available. Create a getter and a setter to reach this capability. Signed-off-by: Miquel Raynal Acked-by: Mark Brown --- drivers/spi/spi-mem.c | 32 ++++++++++++++++++++++++++++++++ include/linux/spi/spi-mem.h | 4 ++++ 2 files changed, 36 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 1816d9d2712a..cb5ec486f494 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -541,6 +541,38 @@ const char *spi_mem_get_name(struct spi_mem *mem) } EXPORT_SYMBOL_GPL(spi_mem_get_name); =20 +/** + * spi_mem_set_dqs() - Mark DQS as being available + * @mem: the SPI memory + * + * When reading at high frequencies (> 100MHz), especially when DTR is ena= bled, + * transfer speed is limited due to clock skews. In particular, the contro= ller + * does not know the board propagation delay nor the memory chip internal = delay + * (clock in to data out) and thus cannot optimize its sampling points. + * Mitigating this limitation is possible with the addition of a data stro= be + * signal, commonly named DQS. + * + * Set the DQS boolean if the feature is available and configured at the c= hip + * level. Controllers may query this value. + */ +void spi_mem_set_dqs(struct spi_mem *mem) +{ + mem->dqs =3D true; +} +EXPORT_SYMBOL_GPL(spi_mem_set_dqs); + +/** + * spi_mem_has_dqs() - Query whether the DQS is available or not + * @mem: the SPI memory + * + * Return: a boolean indicating whether the DQS signal is available or not. + */ +bool spi_mem_has_dqs(struct spi_mem *mem) +{ + return mem->dqs; +} +EXPORT_SYMBOL_GPL(spi_mem_has_dqs); + /** * spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation = to * match controller limitations diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index c4e7ebafdf0e..89d3f0218cc9 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -275,6 +275,7 @@ struct spi_mem_dirmap_desc { * @spi: the underlying SPI device * @drvpriv: spi_mem_driver private data * @name: name of the SPI memory device + * @dqs: extra data trobe pin available for high frequency read operations * * Extra information that describe the SPI memory device and may be needed= by * the controller to properly handle this device should be placed here. @@ -286,6 +287,7 @@ struct spi_mem { struct spi_device *spi; void *drvpriv; const char *name; + bool dqs; }; =20 /** @@ -463,6 +465,8 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, } #endif /* CONFIG_SPI_MEM */ =20 +void spi_mem_set_dqs(struct spi_mem *mem); +bool spi_mem_has_dqs(struct spi_mem *mem); int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op); u64 spi_mem_calc_op_duration(struct spi_mem *mem, struct spi_mem_op *op); --=20 2.54.0 From nobody Tue Sep 29 11:56:08 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0E92385D86; Fri, 7 Aug 2026 14:47:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786114027; cv=none; b=TO9PuP6xrZhCJR6FHu+Hih/ZrR8nLWiPruezo69pD1+ofrsrJRIOgzTkstkyQsbVvORDTAeYpUEnPHEMKCtA5cCdaJacmVkeqcJdyeSpnaroH6s8O1KgIJPJsxKTQ7761tUhI2PKWTTW2XpPa14nIhWMv5wDf1WyMIrAEsD0VCU= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-winbond-nand-next-phy-tuning-v2-2-73595e89d6e3@bootlin.com> References: <20260807-winbond-nand-next-phy-tuning-v2-0-73595e89d6e3@bootlin.com> In-Reply-To: <20260807-winbond-nand-next-phy-tuning-v2-0-73595e89d6e3@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Check whether the NAND is capable of generating a DQS signal and set the flag accordingly. Not wiring the DQS signal on a DQS capable chip that will be used at frequency requiring this signal may be considered a hardware bug, so let's assume this line will be routed "in most cases". If/when we get issues with this assumption, a DT property describing the lacking line in the routing can be created. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 4 ++++ include/linux/mtd/spinand.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 72a630b266f8..6ffd0f1b9c26 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -2057,6 +2057,10 @@ static int spinand_probe(struct spi_mem *mem) read_op =3D *spinand->op_templates->read_cache; write_op =3D *spinand->op_templates->write_cache; =20 + /* Assume manufacturer drivers will enable the DQS pin if it is available= */ + if (spinand->flags & SPINAND_HAS_DQS) + spi_mem_set_dqs(mem); + ret =3D spi_mem_execute_tuning(mem, &read_op, &write_op); if (ret && ret !=3D -EOPNOTSUPP) { dev_warn(&mem->spi->dev, "Failed to execute PHY tuning: %d\n", diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index ec6efcfeef83..fe05b477afef 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -490,6 +490,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3) #define SPINAND_NO_RAW_ACCESS BIT(4) #define SPINAND_ODTR_PACKED_PAGE_READ BIT(5) +#define SPINAND_HAS_DQS BIT(6) =20 /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine stru= cture --=20 2.54.0 From nobody Tue Sep 29 11:56:08 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72931381AE4; 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bh=Zn32rgRm94l4EzfC6PqAkGOthXJmT/0MRbdxmTrZ2XE=; b=qkTjnvftG3/KC9ag4s9GYcRqH+2v/QHeK2dBr3m8xdcOnzAEunpKcc1I6VBIyWbYaTiBB4 vEOHjXcD6WDcZ1A41FKVUpK1w12v8P0+okm8GNYihESdP1Wc6rdhVKSZwdQK4qMmRABBuD Lq7yPUCqN7Rw9H0aiGsCt7MZoYdpGB3UXfr+FxqrYUoc2ydLDeHCSaCFxEkc0aU2mta5XU Qp5toZI6sPzqNSY58bERZqi+GCfaisuDF1r2ei/pNsf6L9BoA9vWHWJbGLhK6C3RDX7qGq 0T9wJP1AX2NC3baIZsg1ghFC2Wz9TKu7zwdPWvol8XXsUFFuaPkPz5AvgHN6OA== From: Miquel Raynal Date: Fri, 07 Aug 2026 16:46:49 +0200 Subject: [PATCH v2 3/3] mtd: spi-nand: winbond: Enable the DQS pin on W35N**JW series Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-winbond-nand-next-phy-tuning-v2-3-73595e89d6e3@bootlin.com> References: <20260807-winbond-nand-next-phy-tuning-v2-0-73595e89d6e3@bootlin.com> In-Reply-To: <20260807-winbond-nand-next-phy-tuning-v2-0-73595e89d6e3@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 These chips have a DQS pin, enable it by default in DTR mode because there is apparently no issue in setting it for lower frequencies, and the extra power consumption seems very low compared to the current drawn by the NAND array itself while operating. This setting will be required for high speed I/O transfers (with PHY tuning). Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 9b78c1e6cbc9..8209b214e594 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -607,7 +607,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and, else if (!single && !dtr) io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_SDR; else if (!single && dtr) - io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR; + io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR_DS; else return -EINVAL; =20 @@ -689,7 +689,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants, &cont_read_cache_octal_variants), - 0, + SPINAND_HAS_DQS, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg), @@ -744,7 +744,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants, &cont_read_cache_octal_variants), - SPINAND_ODTR_PACKED_PAGE_READ, + SPINAND_ODTR_PACKED_PAGE_READ | SPINAND_HAS_DQS, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg), @@ -776,7 +776,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants, &cont_read_cache_octal_variants), - SPINAND_ODTR_PACKED_PAGE_READ, + SPINAND_ODTR_PACKED_PAGE_READ | SPINAND_HAS_DQS, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg), --=20 2.54.0