From nobody Wed Sep 30 13:30:47 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F03139F165 for ; Fri, 7 Aug 2026 13:52:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786110746; cv=none; b=k7dgNY62nhrSPr+Qa+nIcIDdgzfQ+motbgziUXCFsp9+XNemfS/9GQh1jt6WBMKOz0cb1thXklOQbSaSTryADcFJfOMmQpe18mGj3dAHjSkSwFMZ2qDQYluDPOIrractby8o/AWlDLy4BKYuxrNhgGJc2ykB1zFPg6oqAtngqyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786110746; c=relaxed/simple; bh=ObBWfLfE4GPP8LCHnfNTzpcfqHPLFsSPFFNTLOW+PNE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OEqFm3Yia1cXqbA3OaYlJb3FN8/ZAYwXjvuk0vhUOJqdjiyjaJFfe0yOPvA2mSzOe66GczKmDEiL5iiC72HhNjNQGbGcnskT+PApocYeWNQaQM0LJHRiSrp7F4A1bq2z2t3EVC+9liaDVXqjt4woaiZ7KLILcJzEels6TMm41yc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Ek9JFAUh; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ek9JFAUh" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-47fde295992so1776519f8f.0 for ; Fri, 07 Aug 2026 06:52:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786110733; x=1786715533; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=zuBQp/Lf41ln9pCgsCu9cfS2v+qSw/epBAvyAhrlgD4=; b=Ek9JFAUh/Gl6G8ziRPNcUzTlwEOlUuOAEsRe0VkTys2P+61QNtJfnN7qkhirOIGvk6 A89C2YwXA3jCEejPalxt9Wt2NL83JHiwsz5lqCZYZY+UjCmyvOjxj76Gx1LEx2JBJ7lk 5b3yeb0HjiWGgJooH8tf4NzVsTXmhcMaWECQSslAbVNk9TggUSUwDc4RsQ80e/VHCKpO 61kNUFOEDBHFZiUkvYdw9XBpH9draeKo2e/hi0WnZA+odqUXCkgiGGud+BlWayZ29KsA EZf1gfE/Hgj2BtfHeOXip1iQuKE89RHqDrTWGYFbYiYSWWTmKZ8B87jAPRHzm/MSt6D6 GGPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786110733; x=1786715533; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=zuBQp/Lf41ln9pCgsCu9cfS2v+qSw/epBAvyAhrlgD4=; b=eRjBjsU5kS3991QiBCYI32g73HnhJ7/dvNMeBo4PA67J+pWjB1j74M3RRxB2KXU5JD MbpVdKLxhypGmyJbnhtr2hw8KpBtlYDFy367LFEK7r+3rWch1AN/QFm6Vi5NVkMUSrBc U4axMXwsaujqLiHqeCBthhMjyJaonfi6EJXJ6b3a/8V4+5ycOXHEGXWL9tgsNRVGx526 7qSwLmqYmUs7Z0usKx6BGNAtpaX+grdgC+vI+rxfSG4QuEtjeDLGGcvsYzZouEZAX/CB glUxmpbEagcMVe5DriEmIQFmy8NzngouxV+wRvcQE8nsK3rVphD3IU/RRp/fjbsRyfFa RwTw== X-Forwarded-Encrypted: i=1; AHgh+RqpYt7EC+Nbezij2AYklzOoKdNQgBek9CoOejsPeEiRURQus8nuMeC8F8ifyTiZ+gn3ugYsghxVA9YBqW4=@vger.kernel.org X-Gm-Message-State: AOJu0Yyct+a3MwSBpLgcMl6t1a0qrw1ESkWEXU2ndmcEpenOWTYdgLZg manazLVFoqfbW9+hwublGCkpFr0JSiU2gYfGR0hWhaxcQGYKcNDty1ha X-Gm-Gg: AR+sD11ycAjUZVK7T/estEjMRnj8bzQYbI1JO2HZhNO/BZVBnmzBDjuFp8EgfdHy60C /7mYkSavlJtnmXUAZ2a2gx8E3lP8yRByJsQFVmSQZi9EheLGXE0usfSFpUABzrKNN/isw9ry564 Xg+d/vlBwFb+du1BgC5luKDSxmtW4bcmasdIcYCim4ypM1A54vXmkw8SkeEYzY7q0mz2UM+vIIL xUoCusYaVweKPQCxJSg4crYINndBmkkMXaAhVRE/kzd2+oG5rpcsyRJEaSgc8yFQsgCVsZa+Nio qCr+uRQB4B9z1JXOk57BmAJuA8NqIAyb8waQ92F6QkL69wpblKtJNiGK7e0Ev2MVnuaiKUktiQc ffV0DNMLWZPfhtxAly4USsnJ1/uJgVrRg59yvRaaNVZx8SXY5MPH/AYaG/yOWNeebdweA/fSLUA NrmuZPmZC8JjtQsiuD2IbYmtskl4O2H3ulODaM77bcB8qGm8jlIzhIgcbnuchTQuuWV2TEdGHNT nA+VA== X-Received: by 2002:a5d:6604:0:b0:47f:e746:dcab with SMTP id ffacd0b85a97d-48130b2299emr186184f8f.10.1786110732955; Fri, 07 Aug 2026 06:52:12 -0700 (PDT) Received: from [127.0.1.1] ([2001:4bb8:13c:7c2e:7f0a:5759:2e0d:bf8c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-480021e8b09sm6581333f8f.23.2026.08.07.06.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 06:52:12 -0700 (PDT) From: Javier Carrasco Date: Fri, 07 Aug 2026 15:51:52 +0200 Subject: [PATCH v5 1/4] dt-bindings: iio: light: veml6030: add veml6031x00 ALS series Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-veml6031x00-v5-1-e60876fb3640@gmail.com> References: <20260807-veml6031x00-v5-0-e60876fb3640@gmail.com> In-Reply-To: <20260807-veml6031x00-v5-0-e60876fb3640@gmail.com> To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Javier Carrasco , Jonathan Cameron , Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786110728; l=3090; i=javier.carrasco.cruz@gmail.com; s=20260111; h=from:subject:message-id; bh=ObBWfLfE4GPP8LCHnfNTzpcfqHPLFsSPFFNTLOW+PNE=; b=1tAjfOJlzciAG4mERMzK8NKDVCbJ/ifi/y9kQKxvrX0bx4Ly9stwiXSkCcJVV/m1aShkQ1FdF GvrCeOCs1FqDQ3Ncb1F4qshdJ4MMF2K4AiBTo6WD/I9fKH4SW1hbQ6Q X-Developer-Key: i=javier.carrasco.cruz@gmail.com; a=ed25519; pk=Lge8w8xidNSf/INy7JAIbAW+Hezkp3nsBh2OjKL7lLU= These ambient light sensors share their properties with the ones from the same manufacturer that are supported by this bindings. Note that only two datasheets are provided as every one of them covers two devices (veml6031x00/veml60311x00 and veml6031x01/veml60311x01). Reviewed-by: Krzysztof Kozlowski Signed-off-by: Javier Carrasco --- .../devicetree/bindings/iio/light/vishay,veml6030.yaml | 13 +++++++++= +++- MAINTAINERS | 5 +++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/light/vishay,veml6030.ya= ml b/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml index 0041e1db6838..6a387c76df35 100644 --- a/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml +++ b/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml @@ -4,7 +4,8 @@ $id: http://devicetree.org/schemas/iio/light/vishay,veml6030.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: VEML3235, VEML3328, VEML6030, VEML6035 and VEML7700 Ambient Light S= ensors (ALS) +title: VEML3235, VEML3328, VEML6030, VEML6031x00 series, VEML6035 +and VEML7700 Ambient Light Sensors (ALS) =20 maintainers: - Rishi Gupta @@ -23,6 +24,8 @@ description: | https://www.vishay.com/docs/80131/veml3235.pdf https://www.vishay.com/docs/84968/veml3328.pdf https://www.vishay.com/docs/84366/veml6030.pdf + https://www.vishay.com/docs/80007/veml6031x00.pdf + https://www.vishay.com/docs/80008/veml6031x01.pdf https://www.vishay.com/docs/84889/veml6035.pdf https://www.vishay.com/docs/84286/veml7700.pdf =20 @@ -32,6 +35,10 @@ properties: - vishay,veml3235 - vishay,veml3328 - vishay,veml6030 + - vishay,veml6031x00 + - vishay,veml6031x01 + - vishay,veml60311x00 + - vishay,veml60311x01 - vishay,veml6035 - vishay,veml7700 =20 @@ -69,6 +76,8 @@ allOf: properties: compatible: enum: + - vishay,veml6031x00 + - vishay,veml6031x01 - vishay,veml6035 then: properties: @@ -82,6 +91,8 @@ allOf: enum: - vishay,veml3235 - vishay,veml3328 + - vishay,veml60311x00 + - vishay,veml60311x01 - vishay,veml7700 then: properties: diff --git a/MAINTAINERS b/MAINTAINERS index 15011f5752a9..4369cbf8b5ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -28761,6 +28761,11 @@ S: Maintained F: Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml F: drivers/iio/light/veml6030.c =20 +VISHAY VEML6031X00 AMBIENT LIGHT SENSOR DRIVER +M: Javier Carrasco +S: Maintained +F: Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml + VISHAY VEML6046X00 RGBIR COLOR SENSOR DRIVER M: Andreas Klinger S: Maintained --=20 2.43.0 From nobody Wed Sep 30 13:30:47 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D77F3246ED for ; Fri, 7 Aug 2026 13:52:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786110750; cv=none; b=dVT4KUyJZfj5AogAA6WEFnXyKJqeyuP1FK1UaEMw/RWgmjAylTa0ZXu0cCuF+JV6mH1e/Qqv59rxTkxpDCc0atD6UL07r+rNRkzFjnBaRXBJ6G2KcA5MzcEIz1u4GnzrUENOIel5faCoi6JwhhmNiwHdrxb17h1VgpSUl+CO+xk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786110750; c=relaxed/simple; bh=7F35gn4dhST8hi91cpJGLSJhLTPnsBx/ke/HTjvE5Ak=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i7o+kv5+LtH8gPKiALTvJyBNN9DKQXZPo4bzJhcP0U+f6cWNWQtxZdORhIphjJ0SjMVhu3sMngCm4+5OyCzvor6txyyYXxMa7TOc8Q7KPkDDpCJcUCK3JoVFDMn53gwukUJfy4Rhl48aF4kLNKv8jseKiw73gNpkWwA5KKlrd0Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=V+7NMypq; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="V+7NMypq" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-47fecbbafdaso1056278f8f.0 for ; Fri, 07 Aug 2026 06:52:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786110735; x=1786715535; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=N/megHqq5+bV/YhXdUbW2xqXWE7uNZiP726IKM/G6qU=; b=V+7NMypq+X3e3jFho4UmrOwi/gh1bBP7/Lsr4pb9oN03+heV7JgGgBjw0EoxV/56I6 bDkMcAoG7FOTrJ2l54aOrYkcJ+kwrEwxWL0qmEY67xjwlatWIJdlFDBCbdRZNuibF77O NKZ+JqfwZ4egJtcld7Yp8Gjqh/YoGif3gTi5Y70FHHvJZbQTJX7URYK4bw8Ai8eFgqbz jFhSOFxX8760TPAeq86aMGe4QhKqlBSbChSu4PjEL1RyAMW2s8rZcacQYiB/VGuk/Fce AosZCs8er+2uLETKFISE0FLz/uKAeVnAb8quVxgpzwBmO6zgwR+xRzyUJpxUxAYg8maH FOSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786110735; x=1786715535; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=N/megHqq5+bV/YhXdUbW2xqXWE7uNZiP726IKM/G6qU=; b=RFe4dEGysJHcQx8KWroT62kLoyjcs1sTJ3/AhV55s4GEY3ASKMZMqy9ffB4SKGCyu9 TNE4lqV6+Yt5Bqmn0McWc6PsJel09MBVL32pW17P/M+eMsDY6IhZTzAC68yIRTZ585EM 4UpPCGPSF94ivNDs4SKhVOguZeUJysZKLCwPfb9U3VNHSyXKIMMm1oS4QZImAdA1JcZ5 mpwG1A0uJ2BSzUnJOA/kw6zbTtcRoVGHDUOS6BfbFsMkWt15BaVHAyLX6tfW7Ks1nH0B WINoJgqwelwgXfsxBo2PF+/4fSJ4g+navBQ3si9ax71U9Qc46WJYvuBkC7r+DVn5mHBK B53w== X-Forwarded-Encrypted: i=1; AHgh+RpT/LIQxIVp1vmPboLdYi5aldsIdUY4b7yttTE7Ez7UIp/Tu6pYeH/zBwmf7iN7odkMxH+80QsfhXM9OTs=@vger.kernel.org X-Gm-Message-State: AOJu0YzLRc5vpI6yFSAZ27OLdLIzelnfhbpIcnH5d8XBP33EAbKrQiVb +47n8PQhQA0lzQ+no45O1rcAe9NUupnpumioeGsjh1uUkKsyHGEkR2cTtqXKzQ== X-Gm-Gg: AR+sD11ljB5ec7hN6VqYWU3NfUk0IbaISLCFDNlv1mFhhdGTbEXFUioWPQpykODkbxY EidpBQryNtakTKRz5PyvQy3d+fjfsrkrglyPS+eysokEK2gKdGa1kXbMvACScQV/fIMkLVVLzii L6iPrJx4qR0Qzq0N+PWeD0Tz/f8ZYU2kwoNpP6wCMccmPguabXKZMQZpr3LAhQqC82dXHnaTZ2j p/1HWDbctvjW+oZDvJNGFBoYAW8qCp4y8zPK6Jd6F/8YPO+7Kz4VRH3686COowj9zt/nnV+QekN EU0g1yv5+pHi/US971VFzFiPf8x5KGw+RyYejcwi0zmEoaal3z3MFxVnsoP1aubTRs4aXcXqTci sDhMrPB4Cqo600NrfXW3pE6ATU8wpEEcEo8f/pVPha4umsbgGWZMDRGiws5+zu2FZuGIdl7bdc+ SHahvI/OBTE63YIHpPJaESCk4Zx+mTdVX2AMo+Bw1pex9eu0Oz4K4T0MtLbiD7AsArQk0hjdfTo GrWhw== X-Received: by 2002:a05:6000:2585:b0:47f:90cb:630c with SMTP id ffacd0b85a97d-47fec512a47mr33364256f8f.8.1786110735151; Fri, 07 Aug 2026 06:52:15 -0700 (PDT) Received: from [127.0.1.1] ([2001:4bb8:13c:7c2e:7f0a:5759:2e0d:bf8c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-480021e8b09sm6581333f8f.23.2026.08.07.06.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 06:52:14 -0700 (PDT) From: Javier Carrasco Date: Fri, 07 Aug 2026 15:51:53 +0200 Subject: [PATCH v5 2/4] iio: light: add support for veml6031x00 ALS series Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-veml6031x00-v5-2-e60876fb3640@gmail.com> References: <20260807-veml6031x00-v5-0-e60876fb3640@gmail.com> In-Reply-To: <20260807-veml6031x00-v5-0-e60876fb3640@gmail.com> To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Javier Carrasco , Jonathan Cameron X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786110728; l=22012; i=javier.carrasco.cruz@gmail.com; s=20260111; h=from:subject:message-id; bh=7F35gn4dhST8hi91cpJGLSJhLTPnsBx/ke/HTjvE5Ak=; b=+kbYMtJqSBZwS9oBSDKWgeCEbeMGRXoS8BHAQhagK3oHcf0Bt30xpqZYCRKXvY04Uxo+dpqZT UAHYFgnEsLTCDWMJxZvYo6yOhI8BSb8gxEkaxyTw2XTdOSDakA4Xb89 X-Developer-Key: i=javier.carrasco.cruz@gmail.com; a=ed25519; pk=Lge8w8xidNSf/INy7JAIbAW+Hezkp3nsBh2OjKL7lLU= These sensors provide two light channels (ALS and IR), I2C communication and a multiplexed interrupt line to signal data ready and configurable threshold alarms. This first implementation provides basic functionality (measurement configuration, raw reads and ID validation) and defines the different register regions in preparation for extended features in the subsequent patches of the series. Signed-off-by: Javier Carrasco --- MAINTAINERS | 1 + drivers/iio/light/Kconfig | 12 + drivers/iio/light/Makefile | 1 + drivers/iio/light/veml6031x00.c | 695 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 709 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4369cbf8b5ca..85b35948da32 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -28765,6 +28765,7 @@ VISHAY VEML6031X00 AMBIENT LIGHT SENSOR DRIVER M: Javier Carrasco S: Maintained F: Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml +F: drivers/iio/light/veml6031x00.c =20 VISHAY VEML6046X00 RGBIR COLOR SENSOR DRIVER M: Andreas Klinger diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig index ef36824f312f..985b776e71d6 100644 --- a/drivers/iio/light/Kconfig +++ b/drivers/iio/light/Kconfig @@ -738,6 +738,18 @@ config VEML6030 To compile this driver as a module, choose M here: the module will be called veml6030. =20 +config VEML6031X00 + tristate "VEML6031X00 ambient light sensor series" + select REGMAP_I2C + select IIO_GTS_HELPER + depends on I2C + help + Say Y here if you want to build a driver for the Vishay VEML6031X00 + ambient light sensor series. + + To compile this driver as a module, choose M here: the + module will be called veml6031x00. + config VEML6040 tristate "VEML6040 RGBW light sensor" select REGMAP_I2C diff --git a/drivers/iio/light/Makefile b/drivers/iio/light/Makefile index 64e354c49ed8..6672ed01a819 100644 --- a/drivers/iio/light/Makefile +++ b/drivers/iio/light/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_VCNL4035) +=3D vcnl4035.o obj-$(CONFIG_VEML3235) +=3D veml3235.o obj-$(CONFIG_VEML3328) +=3D veml3328.o obj-$(CONFIG_VEML6030) +=3D veml6030.o +obj-$(CONFIG_VEML6031X00) +=3D veml6031x00.o obj-$(CONFIG_VEML6040) +=3D veml6040.o obj-$(CONFIG_VEML6046X00) +=3D veml6046x00.o obj-$(CONFIG_VEML6070) +=3D veml6070.o diff --git a/drivers/iio/light/veml6031x00.c b/drivers/iio/light/veml6031x0= 0.c new file mode 100644 index 000000000000..30cccda51ca0 --- /dev/null +++ b/drivers/iio/light/veml6031x00.c @@ -0,0 +1,695 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * VEML6031X00 Ambient Light Sensor + * + * Copyright (c) 2026, Javier Carrasco + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Device registers */ +#define VEML6031X00_REG_CONF0 0x00 +#define VEML6031X00_REG_CONF1 0x01 +#define VEML6031X00_REG_ALS_L 0x10 +#define VEML6031X00_REG_ALS_H 0x11 +#define VEML6031X00_REG_IR_L 0x12 +#define VEML6031X00_REG_IR_H 0x13 +#define VEML6031X00_REG_ID_L 0x14 +#define VEML6031X00_REG_ID_H 0x15 + +/* Bit masks for specific functionality */ +#define VEML6031X00_CONF0_SD BIT(0) +#define VEML6031X00_CONF1_IR_SD BIT(7) + +struct veml6031x00_rf { + struct regmap_field *gain; + struct regmap_field *it; + struct regmap_field *pd_div4; +}; + +struct veml6031x00_chip { + const char *name; + const int part_id; +}; + +struct veml6031x00_data { + struct iio_gts gts; + struct regmap *regmap; + struct veml6031x00_rf rf; + const struct veml6031x00_chip *chip; + /* + * Serialize access to scale register fields scattered across multiple + * registers (rf.gain, rf.pd_div4, rf.it) to read and write them as a + * consistent set. + */ + struct mutex scale_lock; +}; + +static const struct iio_itime_sel_mul veml6031x00_it_sel[] =3D { + GAIN_SCALE_ITIME_US(3125, 0, 1), + GAIN_SCALE_ITIME_US(6250, 1, 2), + GAIN_SCALE_ITIME_US(12500, 2, 4), + GAIN_SCALE_ITIME_US(25000, 3, 8), + GAIN_SCALE_ITIME_US(50000, 4, 16), + GAIN_SCALE_ITIME_US(100000, 5, 32), + GAIN_SCALE_ITIME_US(200000, 6, 64), + GAIN_SCALE_ITIME_US(400000, 7, 128), +}; + +/* + * The gain selector encodes (PD_D4 << 2) | GAIN to identify each gain set= ting. + * Gains are multiplied by 8 to work with integers. The values in the iio-= gts + * tables don't need corrections because the maximum value of the scale re= fers + * to GAIN =3D x1, and the rest of the values are obtained from the result= ing + * linear function. + * TODO: add support for GAIN_0_165 and GAIN_0_660 + */ +#define VEML6031X00_SEL_GAIN_0_125 0x07 +#define VEML6031X00_SEL_GAIN_0_250 0x04 +#define VEML6031X00_SEL_GAIN_0_500 0x03 +#define VEML6031X00_SEL_GAIN_1_000 0x00 +#define VEML6031X00_SEL_GAIN_2_000 0x01 +static const struct iio_gain_sel_pair veml6031x00_gain_sel[] =3D { + GAIN_SCALE_GAIN(1, VEML6031X00_SEL_GAIN_0_125), + GAIN_SCALE_GAIN(2, VEML6031X00_SEL_GAIN_0_250), + GAIN_SCALE_GAIN(4, VEML6031X00_SEL_GAIN_0_500), + GAIN_SCALE_GAIN(8, VEML6031X00_SEL_GAIN_1_000), + GAIN_SCALE_GAIN(16, VEML6031X00_SEL_GAIN_2_000), +}; + +/* + * The shutdown bits (SD and ALS_IR_SD) are in different registers, which + * must be written together when configuring the device. + */ +static int veml6031x00_set_power_state(struct veml6031x00_data *data, bool= on) +{ + u8 conf[2]; + int ret; + + ret =3D regmap_bulk_read(data->regmap, VEML6031X00_REG_CONF0, + conf, sizeof(conf)); + if (ret) + return ret; + + if (on) { + conf[0] &=3D ~VEML6031X00_CONF0_SD; + conf[1] &=3D ~VEML6031X00_CONF1_IR_SD; + } else { + conf[0] |=3D VEML6031X00_CONF0_SD; + conf[1] |=3D VEML6031X00_CONF1_IR_SD; + } + + return regmap_bulk_write(data->regmap, VEML6031X00_REG_CONF0, + conf, sizeof(conf)); +} + +static void veml6031x00_als_shutdown_action(void *data) +{ + struct veml6031x00_data *veml =3D data; + int ret; + + ret =3D veml6031x00_set_power_state(veml, false); + if (ret) + dev_err(regmap_get_device(veml->regmap), + "Failed to shut down device: %d\n", ret); +} + +static const struct iio_chan_spec veml6031x00_channels[] =3D { + { + .type =3D IIO_LIGHT, + .address =3D VEML6031X00_REG_ALS_L, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_INT_TIME) | + BIT(IIO_CHAN_INFO_SCALE), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_INT_TIME) | + BIT(IIO_CHAN_INFO_SCALE), + }, + { + .type =3D IIO_INTENSITY, + .address =3D VEML6031X00_REG_IR_L, + .modified =3D 1, + .channel2 =3D IIO_MOD_LIGHT_IR, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), + } +}; + +static const struct regmap_range veml6031x00_readable_ranges[] =3D { + regmap_reg_range(VEML6031X00_REG_CONF0, VEML6031X00_REG_CONF1), + regmap_reg_range(VEML6031X00_REG_ALS_L, VEML6031X00_REG_ID_H), +}; + +static const struct regmap_access_table veml6031x00_readable_table =3D { + .yes_ranges =3D veml6031x00_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(veml6031x00_readable_ranges), +}; + +static const struct regmap_range veml6031x00_writable_ranges[] =3D { + regmap_reg_range(VEML6031X00_REG_CONF0, VEML6031X00_REG_CONF1), +}; + +static const struct regmap_access_table veml6031x00_writable_table =3D { + .yes_ranges =3D veml6031x00_writable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(veml6031x00_writable_ranges), +}; + +static const struct regmap_range veml6031x00_volatile_ranges[] =3D { + /* AF_TRIG in CONF0 is volatile */ + regmap_reg_range(VEML6031X00_REG_CONF0, VEML6031X00_REG_CONF0), + regmap_reg_range(VEML6031X00_REG_ALS_L, VEML6031X00_REG_IR_H), +}; + +static const struct regmap_access_table veml6031x00_volatile_table =3D { + .yes_ranges =3D veml6031x00_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(veml6031x00_volatile_ranges), +}; + +static const struct regmap_config veml6031x00_regmap_config =3D { + .name =3D "veml6031x00_regmap", + .reg_bits =3D 8, + .val_bits =3D 8, + .rd_table =3D &veml6031x00_readable_table, + .wr_table =3D &veml6031x00_writable_table, + .volatile_table =3D &veml6031x00_volatile_table, + .max_register =3D VEML6031X00_REG_ID_H, + .cache_type =3D REGCACHE_MAPLE, +}; + +static const struct reg_field veml6031x00_rf_it =3D + REG_FIELD(VEML6031X00_REG_CONF0, 4, 6); + +static const struct reg_field veml6031x00_rf_gain =3D + REG_FIELD(VEML6031X00_REG_CONF1, 3, 4); + +static const struct reg_field veml6031x00_rf_pd_div4 =3D + REG_FIELD(VEML6031X00_REG_CONF1, 6, 6); + +static int veml6031x00_regfield_init(struct veml6031x00_data *data) +{ + struct regmap_field *rm_field; + struct veml6031x00_rf *rf =3D &data->rf; + + rm_field =3D devm_regmap_field_alloc(regmap_get_device(data->regmap), + data->regmap, veml6031x00_rf_gain); + if (IS_ERR(rm_field)) + return PTR_ERR(rm_field); + rf->gain =3D rm_field; + + rm_field =3D devm_regmap_field_alloc(regmap_get_device(data->regmap), + data->regmap, veml6031x00_rf_it); + if (IS_ERR(rm_field)) + return PTR_ERR(rm_field); + rf->it =3D rm_field; + + rm_field =3D devm_regmap_field_alloc(regmap_get_device(data->regmap), + data->regmap, veml6031x00_rf_pd_div4); + if (IS_ERR(rm_field)) + return PTR_ERR(rm_field); + rf->pd_div4 =3D rm_field; + + return 0; +} + +static int __veml6031x00_get_it(struct veml6031x00_data *data, int *val2) +{ + unsigned int it_idx; + int ret; + + ret =3D regmap_field_read(data->rf.it, &it_idx); + if (ret) + return ret; + + ret =3D iio_gts_find_int_time_by_sel(&data->gts, it_idx); + if (ret < 0) + return ret; + + *val2 =3D ret; + + return IIO_VAL_INT_PLUS_MICRO; +} + +static int veml6031x00_get_it(struct veml6031x00_data *data, int *val2) +{ + scoped_guard(mutex, &data->scale_lock) + return __veml6031x00_get_it(data, val2); +} + +static int veml6031x00_write_gain(struct veml6031x00_data *data, unsigned = int gain) +{ + int ret; + + ret =3D regmap_field_write(data->rf.pd_div4, gain >> 2); + if (ret) + return ret; + + return regmap_field_write(data->rf.gain, gain & 0x03); +} + +static int veml6031x00_set_it(struct iio_dev *iio, int val, int val2) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + int ret, gain_sel, new_gain, prev_gain, prev_it; + unsigned int gain_reg, it_idx, pd_div4; + bool in_range; + + if (val || !iio_gts_valid_time(&data->gts, val2)) + return -EINVAL; + + guard(mutex)(&data->scale_lock); + + ret =3D regmap_field_read(data->rf.it, &it_idx); + if (ret) + return ret; + + ret =3D regmap_field_read(data->rf.gain, &gain_reg); + if (ret) + return ret; + + ret =3D regmap_field_read(data->rf.pd_div4, &pd_div4); + if (ret) + return ret; + + prev_it =3D iio_gts_find_int_time_by_sel(&data->gts, it_idx); + if (prev_it < 0) + return prev_it; + + if (prev_it =3D=3D val2) + return 0; + + prev_gain =3D iio_gts_find_gain_by_sel(&data->gts, (pd_div4 << 2) | gain_= reg); + if (prev_gain < 0) + return prev_gain; + + ret =3D iio_gts_find_new_gain_by_gain_time_min(&data->gts, prev_gain, pre= v_it, + val2, &new_gain, &in_range); + if (ret) + return ret; + + if (!in_range) + dev_dbg(regmap_get_device(data->regmap), "Optimal gain out of range\n"); + + ret =3D iio_gts_find_sel_by_int_time(&data->gts, val2); + if (ret < 0) + return ret; + + ret =3D regmap_field_write(data->rf.it, ret); + if (ret) + return ret; + + gain_sel =3D iio_gts_find_sel_by_gain(&data->gts, new_gain); + if (gain_sel < 0) + return gain_sel; + + return veml6031x00_write_gain(data, gain_sel); +} + +static int veml6031x00_set_scale(struct iio_dev *iio, int val, int val2) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + int gain_sel, it_sel, ret; + + ret =3D iio_gts_find_gain_time_sel_for_scale(&data->gts, val, val2, + &gain_sel, &it_sel); + if (ret) + return ret; + + guard(mutex)(&data->scale_lock); + + ret =3D regmap_field_write(data->rf.it, it_sel); + if (ret) + return ret; + + return veml6031x00_write_gain(data, gain_sel); +} + +static int veml6031x00_get_scale(struct veml6031x00_data *data, int *val, + int *val2) +{ + int gain, it, gain_reg, pd_div4, it_reg, ret, sel; + + scoped_guard(mutex, &data->scale_lock) { + ret =3D regmap_field_read(data->rf.gain, &gain_reg); + if (ret) + return ret; + + ret =3D regmap_field_read(data->rf.pd_div4, &pd_div4); + if (ret) + return ret; + + sel =3D (pd_div4 << 2) | gain_reg; + gain =3D iio_gts_find_gain_by_sel(&data->gts, sel); + if (gain < 0) + return gain; + + ret =3D regmap_field_read(data->rf.it, &it_reg); + if (ret) + return ret; + } + + it =3D iio_gts_find_int_time_by_sel(&data->gts, it_reg); + if (it < 0) + return it; + + ret =3D iio_gts_get_scale(&data->gts, gain, it, val, val2); + if (ret) + return ret; + + return IIO_VAL_INT_PLUS_NANO; +} + +static int veml6031x00_single_read(struct iio_dev *iio, enum iio_chan_type= type, + int *val) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + int addr, it_usec, ret; + __le16 regval; + + switch (type) { + case IIO_LIGHT: + addr =3D VEML6031X00_REG_ALS_L; + break; + case IIO_INTENSITY: + addr =3D VEML6031X00_REG_IR_L; + break; + default: + return -EINVAL; + } + + guard(mutex)(&data->scale_lock); + + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(regmap_get_device(data->regmap), pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + ret =3D __veml6031x00_get_it(data, &it_usec); + if (ret < 0) + return ret; + + /* integration time + 10% to ensure completion */ + fsleep(it_usec + (it_usec / 10)); + + ret =3D regmap_bulk_read(data->regmap, addr, ®val, sizeof(regval)); + if (ret) + return ret; + + *val =3D le16_to_cpu(regval); + + return IIO_VAL_INT; +} + +static int veml6031x00_read_raw(struct iio_dev *iio, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + return veml6031x00_single_read(iio, chan->type, val); + case IIO_CHAN_INFO_INT_TIME: + *val =3D 0; + return veml6031x00_get_it(data, val2); + case IIO_CHAN_INFO_SCALE: + return veml6031x00_get_scale(data, val, val2); + default: + return -EINVAL; + } +} + +static int veml6031x00_read_avail(struct iio_dev *iio, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + + switch (mask) { + case IIO_CHAN_INFO_INT_TIME: + return iio_gts_avail_times(&data->gts, vals, type, length); + case IIO_CHAN_INFO_SCALE: + return iio_gts_all_avail_scales(&data->gts, vals, type, length); + default: + return -EINVAL; + } +} + +static int veml6031x00_write_raw(struct iio_dev *iio, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_INT_TIME: + return veml6031x00_set_it(iio, val, val2); + case IIO_CHAN_INFO_SCALE: + return veml6031x00_set_scale(iio, val, val2); + default: + return -EINVAL; + } +} + +static int veml6031x00_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + case IIO_CHAN_INFO_INT_TIME: + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static const struct iio_info veml6031x00_info =3D { + .read_raw =3D veml6031x00_read_raw, + .read_avail =3D veml6031x00_read_avail, + .write_raw =3D veml6031x00_write_raw, + .write_raw_get_fmt =3D veml6031x00_write_raw_get_fmt, +}; + +static int veml6031x00_validate_part_id(struct veml6031x00_data *data) +{ + int part_id, ret; + __le16 regval; + + ret =3D regmap_bulk_read(data->regmap, VEML6031X00_REG_ID_L, ®val, + sizeof(regval)); + if (ret) + return dev_err_probe(regmap_get_device(data->regmap), ret, + "Failed to read ID\n"); + + part_id =3D le16_to_cpu(regval); + if (part_id !=3D data->chip->part_id) + dev_info(regmap_get_device(data->regmap), "Unknown ID %04x\n", part_id); + + return 0; +} + +static int veml6031x00_hw_init(struct iio_dev *iio) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + int ret; + + /* Max resolution =3D 6.9632 lx/cnt for gain =3D 0.125 and IT =3D 3.125ms= */ + ret =3D devm_iio_init_iio_gts(regmap_get_device(data->regmap), 6, 9632000= 00, + veml6031x00_gain_sel, + ARRAY_SIZE(veml6031x00_gain_sel), + veml6031x00_it_sel, + ARRAY_SIZE(veml6031x00_it_sel), + &data->gts); + if (ret) + return dev_err_probe(regmap_get_device(data->regmap), ret, + "failed to init IIO GTS\n"); + + return 0; +} + +static int veml6031x00_probe(struct i2c_client *i2c) +{ + struct veml6031x00_data *data; + struct iio_dev *iio; + int ret; + + iio =3D devm_iio_device_alloc(&i2c->dev, sizeof(*data)); + if (!iio) + return -ENOMEM; + + data =3D iio_priv(iio); + i2c_set_clientdata(i2c, iio); + + data->chip =3D i2c_get_match_data(i2c); + if (!data->chip) + return dev_err_probe(&i2c->dev, -EINVAL, "Failed to get chip data\n"); + + data->regmap =3D devm_regmap_init_i2c(i2c, &veml6031x00_regmap_config); + if (IS_ERR(data->regmap)) + return dev_err_probe(&i2c->dev, PTR_ERR(data->regmap), + "Failed to set regmap\n"); + + iio->name =3D data->chip->name; + iio->channels =3D veml6031x00_channels; + iio->num_channels =3D ARRAY_SIZE(veml6031x00_channels); + iio->modes =3D INDIO_DIRECT_MODE; + iio->info =3D &veml6031x00_info; + + ret =3D devm_mutex_init(&i2c->dev, &data->scale_lock); + if (ret) + return ret; + + ret =3D veml6031x00_regfield_init(data); + if (ret) + return dev_err_probe(&i2c->dev, ret, "Failed to init regfield\n"); + + ret =3D devm_regulator_get_enable(&i2c->dev, "vdd"); + if (ret) + return dev_err_probe(&i2c->dev, ret, "Failed to enable regulator\n"); + + /* The device starts in power down mode by default */ + ret =3D veml6031x00_set_power_state(data, true); + if (ret) + return dev_err_probe(&i2c->dev, ret, "Failed to power on the device\n"); + + ret =3D devm_add_action_or_reset(&i2c->dev, veml6031x00_als_shutdown_acti= on, data); + if (ret) + return dev_err_probe(&i2c->dev, ret, "Failed to add shutdown action\n"); + + pm_runtime_set_autosuspend_delay(&i2c->dev, 2000); + pm_runtime_use_autosuspend(&i2c->dev); + ret =3D devm_pm_runtime_set_active_enabled(&i2c->dev); + if (ret) + return dev_err_probe(&i2c->dev, ret, "Failed to enable runtime PM\n"); + + ret =3D devm_pm_runtime_get_noresume(&i2c->dev); + if (ret) + return dev_err_probe(&i2c->dev, ret, "Failed to get runtime PM\n"); + + ret =3D veml6031x00_validate_part_id(data); + if (ret) + return ret; + + ret =3D veml6031x00_hw_init(iio); + if (ret) + return ret; + + pm_runtime_put_autosuspend(&i2c->dev); + + ret =3D devm_iio_device_register(&i2c->dev, iio); + if (ret) + return dev_err_probe(&i2c->dev, ret, "Failed to register iio device\n"); + + return 0; +} + +static int veml6031x00_runtime_suspend(struct device *dev) +{ + struct veml6031x00_data *data =3D iio_priv(dev_get_drvdata(dev)); + + return veml6031x00_set_power_state(data, false); +} + +static int veml6031x00_runtime_resume(struct device *dev) +{ + struct veml6031x00_data *data =3D iio_priv(dev_get_drvdata(dev)); + + return veml6031x00_set_power_state(data, true); +} + +static DEFINE_RUNTIME_DEV_PM_OPS(veml6031x00_pm_ops, + veml6031x00_runtime_suspend, + veml6031x00_runtime_resume, + NULL); + +static const struct veml6031x00_chip veml6031x00_chip =3D { + .name =3D "veml6031x00", + .part_id =3D 0x0001, +}; + +static const struct veml6031x00_chip veml6031x01_chip =3D { + .name =3D "veml6031x01", + .part_id =3D 0x0001, +}; + +static const struct veml6031x00_chip veml60311x00_chip =3D { + .name =3D "veml60311x00", + .part_id =3D 0x1001, +}; + +static const struct veml6031x00_chip veml60311x01_chip =3D { + .name =3D "veml60311x01", + .part_id =3D 0x1001, +}; + +static const struct of_device_id veml6031x00_of_match[] =3D { + { + .compatible =3D "vishay,veml6031x00", + .data =3D &veml6031x00_chip, + }, + { + .compatible =3D "vishay,veml6031x01", + .data =3D &veml6031x01_chip, + }, + { + .compatible =3D "vishay,veml60311x00", + .data =3D &veml60311x00_chip, + }, + { + .compatible =3D "vishay,veml60311x01", + .data =3D &veml60311x01_chip, + }, + { } +}; +MODULE_DEVICE_TABLE(of, veml6031x00_of_match); + +static const struct i2c_device_id veml6031x00_id[] =3D { + { + .name =3D "veml6031x00", + .driver_data =3D (kernel_ulong_t)&veml6031x00_chip, + }, + { + .name =3D "veml6031x01", + .driver_data =3D (kernel_ulong_t)&veml6031x01_chip, + }, + { + .name =3D "veml60311x00", + .driver_data =3D (kernel_ulong_t)&veml60311x00_chip, + }, + { + .name =3D "veml60311x01", + .driver_data =3D (kernel_ulong_t)&veml60311x01_chip, + }, + { } +}; +MODULE_DEVICE_TABLE(i2c, veml6031x00_id); + +static struct i2c_driver veml6031x00_driver =3D { + .driver =3D { + .name =3D "veml6031x00", + .of_match_table =3D veml6031x00_of_match, + .pm =3D pm_ptr(&veml6031x00_pm_ops), + }, + .probe =3D veml6031x00_probe, + .id_table =3D veml6031x00_id, +}; +module_i2c_driver(veml6031x00_driver); + +MODULE_AUTHOR("Javier Carrasco "); +MODULE_DESCRIPTION("VEML6031X00 Ambient Light Sensor"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_GTS_HELPER"); --=20 2.43.0 From nobody Wed Sep 30 13:30:47 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 863563955EB for ; Fri, 7 Aug 2026 13:52:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786110753; cv=none; b=cC7OB56Z4F6hpH7cF48eme7I3j2DyeLC3PTc+AGpo5//+GZVb5Rdtdp6QWtfv2WwA/zTaeTqS/DRqvmWoT/HXNamzAEujED0JhREfYcZZOkV2Wms/n8vyeDS/fKSRYiGOr7LM6tLUDpOPC5UlpjkkCPBjV1dfjdfmJ48poCPV3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786110753; c=relaxed/simple; bh=nGPW/Xf9IcxxowoH00WX/4TQBZQa0xEMX/JkrGRyPu8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TbK9/w/KCQBtcbqTHBD8JRSCoyHSRV+0t4C6RLh5kpUUmbrNL6pLLzgoaxyvARIOmNR7UySNShUKtEd+byXVQGSmzY2aqTwgVYihGX3jsA8Hv2IYBg4qIo3OZc/H7/nrdNrc79ETe5Vruh/qd5zYDvJiWXW7bvFsYt1EzddemNM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KrUAB6SC; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KrUAB6SC" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-4807df69172so290019f8f.1 for ; Fri, 07 Aug 2026 06:52:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786110737; x=1786715537; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=p5hTRZ9L+NP9Zln6CIY1plhBe3Xn8XeTKDItuo0Wyks=; b=KrUAB6SCp/olbYXylJQ6Q8YgsFN0Iznll6U1YjDFEU5mutB7/++iG5VrIdiwxXbECM ddYA8UY/LpA6POPHPn8XiRJWo76G8cdeIWF2cmdJ+00wPJ/cr35oiTCZCB0VxbjAiPgX IXuB9T/ecuDNL7vkL+XGjrWnzj/TuQPcNru7qp9wP5N3+fUnrsoEcRm5UyKW2sxEo4M9 T1w4rOSYxvwFTVLXn0Tg2c645Laa59+HHp73akqEYaxt6lGFXk6hHLSOqYBQLEs0qx+j w8hZBOCP4UMnbioNObuu8N+6rY94KIfK7W/MQjzF1eNu8RsLcd5JhHAyJeIjKW4ln8EB lpaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786110737; x=1786715537; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=p5hTRZ9L+NP9Zln6CIY1plhBe3Xn8XeTKDItuo0Wyks=; b=EgkSt83S2f0AO7Ua69di+xaBqTxMKEeq38RgzYh5IcvmRbq2P11X+pwhlyeYWJaY++ Oeg7IRSW1raxtOvRfhNhnHBTOQXgVrKpFxB44Nu927QwOBe6uorU3WqYaX9Oc8AREUgq Wcl3Xl8DL0lDUyAlHkiAS6bDGmIVYoiUBhkvUe/RbdejBGGXjnDU3gAO73QRM77dEb2y jRNJI9TutLKHa7HgM/dgsvxrDpGxQ1KR8jvg9t1c5YHsJ9ckxIU4bqAnSgleWZ6oyGov KJ+99qoNbR+SRa4hnF58+YdxYUJqjeS9rZ+xD2UxbcUiQzKG1Pwlak6k0GdjiJsjNo4m mqqA== X-Forwarded-Encrypted: i=1; AHgh+RqW3Ntxy2E1NVn0T7lXTNDhVBTEJYeaA98h2ddMoibOMAtemSc4XmKXxrgMnyYdqnrrxtJlC6h5tHv6gNE=@vger.kernel.org X-Gm-Message-State: AOJu0YzbV5xfbhQRd7AdVLawrKyaqyK9+vAohyLsk0t6gEsSngfgnK0k n/5fat/2dKmbhD9MnObuKujTAqpoVEXZPDj23R/hYqzz4IaDe9t5/e5Q X-Gm-Gg: AR+sD12lpARV7Prk5mrtCzmIHjBJcdsMhbZVYeqGFLZ1am77jEjG3NUYMYBaEbV/0jI wHdBKM7dGlYA691VydfrftJvxgpxuz2a50bXODfz6RUYFhva2ZcjQf4REeZKqcyTZgFd0GsQaSo SMq7qAIN3lqpDApBQFXJ6j0VRv8GWZbhTC4O1sF3BchAoTfxCmtTems2FmDL69xihITkftHExCl v8PFo8Cschjxo0eXHvULgwJvUUCJCcapG51M0AkgqW9dje+9SFz2yE+E+HzPTtqqNd81AcIiqUf MAf0E1wn5OHE6KvnwnQZEhGpCVMThDdBk6j39Q63w55/bBXNzJ7Gr+kuNCRFKIVFx/NhgHAHxr2 pBm5S3SzkuEwqXSOZQKauHU0gC4BEVV/BwvRd3CTC2FgHw5MvsHxyC6R230mv5Kgy1oLwecuPlL 0i6fzcIwwXJBhBiI/ceOjNKNxWxQIjCl706lnFYMO1cu/ncMz/SVAsjL6BLNLBhmHNthVxIMWrO 5HTVWuzJcZdO0gVvotljMMOXL0u X-Received: by 2002:a05:6000:40dc:b0:47f:e7f7:370f with SMTP id ffacd0b85a97d-47ff4e5a82cmr22168039f8f.10.1786110737330; Fri, 07 Aug 2026 06:52:17 -0700 (PDT) Received: from [127.0.1.1] ([2001:4bb8:13c:7c2e:7f0a:5759:2e0d:bf8c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-480021e8b09sm6581333f8f.23.2026.08.07.06.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 06:52:16 -0700 (PDT) From: Javier Carrasco Date: Fri, 07 Aug 2026 15:51:54 +0200 Subject: [PATCH v5 3/4] iio: light: veml6031x00: add support for triggered buffers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-veml6031x00-v5-3-e60876fb3640@gmail.com> References: <20260807-veml6031x00-v5-0-e60876fb3640@gmail.com> In-Reply-To: <20260807-veml6031x00-v5-0-e60876fb3640@gmail.com> To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Javier Carrasco , Jonathan Cameron X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786110728; l=5240; i=javier.carrasco.cruz@gmail.com; s=20260111; h=from:subject:message-id; bh=nGPW/Xf9IcxxowoH00WX/4TQBZQa0xEMX/JkrGRyPu8=; b=ATbRd/h9NPsNfjL3VrLhq0JJwgOZbXPSgtOCDwxJSx+2YkakmbfIReoT9LajtrJhcEOcDQ/l9 WG+miWYxcZTA39BHuOeeWTUwDTemdvAww3Xl3Iniv3LhSnajhvLyR51 X-Developer-Key: i=javier.carrasco.cruz@gmail.com; a=ed25519; pk=Lge8w8xidNSf/INy7JAIbAW+Hezkp3nsBh2OjKL7lLU= Add triggered buffer functionality for the two channels the device provides (ALS and IR). Signed-off-by: Javier Carrasco --- drivers/iio/light/Kconfig | 2 + drivers/iio/light/veml6031x00.c | 100 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 102 insertions(+) diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig index 985b776e71d6..397b3e0d4408 100644 --- a/drivers/iio/light/Kconfig +++ b/drivers/iio/light/Kconfig @@ -742,6 +742,8 @@ config VEML6031X00 tristate "VEML6031X00 ambient light sensor series" select REGMAP_I2C select IIO_GTS_HELPER + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER depends on I2C help Say Y here if you want to build a driver for the Vishay VEML6031X00 diff --git a/drivers/iio/light/veml6031x00.c b/drivers/iio/light/veml6031x0= 0.c index 30cccda51ca0..0cccd40d729e 100644 --- a/drivers/iio/light/veml6031x00.c +++ b/drivers/iio/light/veml6031x00.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,8 @@ =20 #include #include +#include +#include =20 /* Device registers */ #define VEML6031X00_REG_CONF0 0x00 @@ -37,6 +40,12 @@ #define VEML6031X00_CONF0_SD BIT(0) #define VEML6031X00_CONF1_IR_SD BIT(7) =20 +enum veml6031x00_scan { + VEML6031X00_SCAN_ALS, + VEML6031X00_SCAN_IR, + VEML6031X00_SCAN_TIMESTAMP, +}; + struct veml6031x00_rf { struct regmap_field *gain; struct regmap_field *it; @@ -392,6 +401,10 @@ static int veml6031x00_single_read(struct iio_dev *iio= , enum iio_chan_type type, =20 guard(mutex)(&data->scale_lock); =20 + IIO_DEV_ACQUIRE_DIRECT_MODE(iio, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(regmap_get_device(data->regmap), pm); ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); if (ret) @@ -453,6 +466,10 @@ static int veml6031x00_write_raw(struct iio_dev *iio, struct iio_chan_spec const *chan, int val, int val2, long mask) { + IIO_DEV_ACQUIRE_DIRECT_MODE(iio, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + switch (mask) { case IIO_CHAN_INFO_INT_TIME: return veml6031x00_set_it(iio, val, val2); @@ -484,6 +501,81 @@ static const struct iio_info veml6031x00_info =3D { .write_raw_get_fmt =3D veml6031x00_write_raw_get_fmt, }; =20 +static int veml6031x00_buffer_preenable(struct iio_dev *iio) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + int ret, it_usec; + + ret =3D pm_runtime_resume_and_get(regmap_get_device(data->regmap)); + if (ret) + return ret; + + ret =3D veml6031x00_get_it(data, &it_usec); + if (ret < 0) { + pm_runtime_put_autosuspend(regmap_get_device(data->regmap)); + return ret; + } + + /* + * Wait one integration period + 10% margin so the first triggered + * read does not race with the sensor completing its first conversion + * after power-on. + */ + fsleep(it_usec + (it_usec / 10)); + + return 0; +} + +static int veml6031x00_buffer_postdisable(struct iio_dev *iio) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + + pm_runtime_put_autosuspend(regmap_get_device(data->regmap)); + + return 0; +} + +static const struct iio_buffer_setup_ops veml6031x00_buffer_setup_ops =3D { + .preenable =3D veml6031x00_buffer_preenable, + .postdisable =3D veml6031x00_buffer_postdisable, +}; + +static irqreturn_t veml6031x00_trig_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *iio =3D pf->indio_dev; + struct veml6031x00_data *data =3D iio_priv(iio); + IIO_DECLARE_BUFFER_WITH_TS(__le16, scan, 2); + unsigned int i =3D 0; + int ch, ret; + + if (test_bit(VEML6031X00_SCAN_ALS, iio->active_scan_mask) && + test_bit(VEML6031X00_SCAN_IR, iio->active_scan_mask)) { + ret =3D regmap_bulk_read(data->regmap, + VEML6031X00_REG_ALS_L, + scan, + 2 * sizeof(*scan)); + if (ret) + goto done; + } else { + iio_for_each_active_channel(iio, ch) { + ret =3D regmap_bulk_read(data->regmap, + iio->channels[ch].address, + &scan[i++], + sizeof(*scan)); + if (ret) + goto done; + } + } + + iio_push_to_buffers_with_ts(iio, scan, sizeof(scan), pf->timestamp); + +done: + iio_trigger_notify_done(iio->trig); + + return IRQ_HANDLED; +} + static int veml6031x00_validate_part_id(struct veml6031x00_data *data) { int part_id, ret; @@ -588,6 +680,14 @@ static int veml6031x00_probe(struct i2c_client *i2c) if (ret) return ret; =20 + ret =3D devm_iio_triggered_buffer_setup(regmap_get_device(data->regmap), = iio, + iio_pollfunc_store_time, + veml6031x00_trig_handler, + &veml6031x00_buffer_setup_ops); + if (ret) + return dev_err_probe(&i2c->dev, ret, + "Failed to register triggered buffer\n"); + pm_runtime_put_autosuspend(&i2c->dev); =20 ret =3D devm_iio_device_register(&i2c->dev, iio); --=20 2.43.0 From nobody Wed Sep 30 13:30:47 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27E4C33DEFE for ; Fri, 7 Aug 2026 13:52:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786110761; cv=none; b=Q77n1chzuK56fKm/rG8sqK4w5zG090smYxWA/fPC1N65a2Dm8xfVMYsMr+oWiMDTTZu10pgSZ6oGBE3THhfUDHU8Gxa3OAKnpOb84qJ0XBBUZw48WhcRLwyHzapvmSD2lKyYBW/HYogi7b6acpVB+tjB6zPw7CD6AMSsplzahts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786110761; c=relaxed/simple; bh=PJZhZEi1W4+Y2hMFwYNULOMEipGiY6VSurAAtC+vpWg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pX1ER4ws5sGLa6zquL6vLIFisGvbBu2rTjhTF5rWyN+nUywppucSPJVZL+og+ITg33XLX660pV8+HiJ+jUZF5t4nKKrZSezlt0qo3N9oSwr06wFpHRmoy9XkjYH3gH0hAAWlFQ6V2dj9MOTWtO3yis6muqn1ueWlk79LhUURwSo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QHCAmfRL; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QHCAmfRL" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4980dc26022so33833435e9.1 for ; Fri, 07 Aug 2026 06:52:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786110740; x=1786715540; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=q1iIB52Ggh7rCKXZKgQhlKYuhVA2prPvS2jFcH92T3A=; b=QHCAmfRL/zQx+4OJdCPa08gKR3lCa8RPV2DthMyeW2IugK9qVCcDE9Mjn3pCYDMaIG GU0tXlhkTuQ56SVivPvrZi0gdr+9mP+vG90Jucyc1L+urzMYxM1XB3OGSxduOYSuLCGo ckiSzBlx/W1K99u4oEtgO+JtM1kKNk45iokF/vWv3ehEVbujELgNR6O+VeKb2cQuHO+z 1vEGH7gZUGsN1RBF3BgXC1X/JfEQFik+g9KdvA37dMOlBaXQ+C9c5MXyIoDrDIDh+Gqg R3feZ5yTcURD8bNDcE4idAfN/V/uqi1qRnK4xByEEv6cvLQ9SBxi3+UN0JaMGLkRAV+G axOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786110740; x=1786715540; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=q1iIB52Ggh7rCKXZKgQhlKYuhVA2prPvS2jFcH92T3A=; b=SxHc29b26klVejCRiRRbeOhbaZRLIb4XyIeLlMH0s+ZhOcI2XRS+AP0/27rlikSjUI 7DyI6/yp2mrI3v7fJ96yOkPzVdll4fiqcMJqfSOLuLVJSHhH3RcGkqCh6g+4WtGDPEu+ TIqW1fdqIVljnIYH4oVMdNnQqDFzk9GKWAcanrMFtLuaJ7Dbphvr206n0yK4P9+8xW5J TnHTRwzJZRDKZ3uWccUHNWpJKmeLNdLT4WTWTik5o7YzP0nltxvvjzdJS6UV//IwcN2Z Pce/jbaJFrbRKnOOBqsNV6jfHtfLvSX5KmmwWBZkeNFd+6vVUhKXxMzOUMFqtVJDyDmy a2tQ== X-Forwarded-Encrypted: i=1; AHgh+Rrswc6c0lT2x9K97fp1A9cJfS4i9tk2QFgxTPfhk6PBglfmbuGApPPz0vMZIntK5oNTZsyAL2MefChFnpM=@vger.kernel.org X-Gm-Message-State: AOJu0YzOo/6e/k+QKiiD9yD1zuwlpR296rlGjGDKOxzI5KeZGaSPmGn+ cFBb4lEFdFjHuUCJ1S6JMFwKKXL0cIrbD2faePpWGupTEk86H3B5MGwi X-Gm-Gg: AR+sD12Up8FPsgWpurVRogXPmXQHPi7XMvoloaQyXzXF1uRvdayJ/Pgpqci7AgNEqtZ 1lwn5VgNnrsqypvJGLslHY27aCmy+YDcrRO0qpt/mPRB/kv5LP/xsmc/2fNY7GE1UBO/Js5WPNU /NsyOjN1on/HYSWbJ0j0EeaMXm0QLKJXxvwfDj0UaDBncIKsuKQ9PPVwPE4/NlPJ6I4u3uNOL5e zD2pbCXPMvqLmmhk8KUfVGNN4DnE+EgduWOmR9flQG7bNJiGnzRPyJuL6DvMg9A0Eglgo418QCl 9fXk7WY2vbETp2K3xBMYvDn24PE3yGvwmYHsv4yRXfaYyaPS2y6bHn52lBcj5ZP6paJstt2Q0FI b8dgaO3UWX+Eb+VyqVxLOx3qlJY/t+mC0W9TNK47jKqurqHXI4thb+O+LiwSxfGzkfQSa5QCOwC d0sVltUyzyID9vVFhyUWiEDE9QUaEs2kCT8bnT+8u7beq0ApghaTdNJ34vxtP5Wp59/Z6nL/ueS 01Pug== X-Received: by 2002:a05:600c:190d:b0:499:5a5e:f2f3 with SMTP id 5b1f17b1804b1-4995a5ef379mr102575185e9.5.1786110740178; Fri, 07 Aug 2026 06:52:20 -0700 (PDT) Received: from [127.0.1.1] ([2001:4bb8:13c:7c2e:7f0a:5759:2e0d:bf8c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-480021e8b09sm6581333f8f.23.2026.08.07.06.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 06:52:19 -0700 (PDT) From: Javier Carrasco Date: Fri, 07 Aug 2026 15:51:55 +0200 Subject: [PATCH v5 4/4] iio: light: veml6031x00: add support for events and trigger Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-veml6031x00-v5-4-e60876fb3640@gmail.com> References: <20260807-veml6031x00-v5-0-e60876fb3640@gmail.com> In-Reply-To: <20260807-veml6031x00-v5-0-e60876fb3640@gmail.com> To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Javier Carrasco , Jonathan Cameron X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786110728; l=22756; i=javier.carrasco.cruz@gmail.com; s=20260111; h=from:subject:message-id; bh=PJZhZEi1W4+Y2hMFwYNULOMEipGiY6VSurAAtC+vpWg=; b=nzIsl0qFy94d9yZG637ukhQkvARdfx9+Pcsmfj8fj0sKWUAZITmw5Ttz5nz/UU4mn4WA2H+w6 0WdCCQ578E2BKBk1wbn2CbmS6YHjIazTPWI/oiBeh1vHNExTSIK7VsE X-Developer-Key: i=javier.carrasco.cruz@gmail.com; a=ed25519; pk=Lge8w8xidNSf/INy7JAIbAW+Hezkp3nsBh2OjKL7lLU= The device provides a shared interrupt line for to notify events and data ready, which can be used as a trigger. The interrupt line is not a requirement for the device to work. Implement variants for the cases whether the interrupt line is provided or not. Signed-off-by: Javier Carrasco --- drivers/iio/light/veml6031x00.c | 538 ++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 532 insertions(+), 6 deletions(-) diff --git a/drivers/iio/light/veml6031x00.c b/drivers/iio/light/veml6031x0= 0.c index 0cccd40d729e..e193f87e6740 100644 --- a/drivers/iio/light/veml6031x00.c +++ b/drivers/iio/light/veml6031x00.c @@ -22,6 +22,9 @@ #include =20 #include +#include +#include +#include #include #include #include @@ -29,16 +32,29 @@ /* Device registers */ #define VEML6031X00_REG_CONF0 0x00 #define VEML6031X00_REG_CONF1 0x01 +#define VEML6031X00_REG_WH_L 0x04 +#define VEML6031X00_REG_WH_H 0x05 +#define VEML6031X00_REG_WL_L 0x06 +#define VEML6031X00_REG_WL_H 0x07 #define VEML6031X00_REG_ALS_L 0x10 #define VEML6031X00_REG_ALS_H 0x11 #define VEML6031X00_REG_IR_L 0x12 #define VEML6031X00_REG_IR_H 0x13 #define VEML6031X00_REG_ID_L 0x14 #define VEML6031X00_REG_ID_H 0x15 +#define VEML6031X00_REG_INT 0x17 =20 /* Bit masks for specific functionality */ #define VEML6031X00_CONF0_SD BIT(0) +#define VEML6031X00_CONF0_AF_TRIG BIT(2) +#define VEML6031X00_CONF0_AF BIT(3) #define VEML6031X00_CONF1_IR_SD BIT(7) +#define VEML6031X00_INT_TH_H BIT(1) +#define VEML6031X00_INT_TH_L BIT(2) +#define VEML6031X00_INT_DRDY BIT(3) +#define VEML6031X00_INT_MASK (VEML6031X00_INT_TH_L | \ + VEML6031X00_INT_TH_H | \ + VEML6031X00_INT_DRDY) =20 enum veml6031x00_scan { VEML6031X00_SCAN_ALS, @@ -48,8 +64,10 @@ enum veml6031x00_scan { =20 struct veml6031x00_rf { struct regmap_field *gain; + struct regmap_field *int_en; struct regmap_field *it; struct regmap_field *pd_div4; + struct regmap_field *pers; }; =20 struct veml6031x00_chip { @@ -60,6 +78,7 @@ struct veml6031x00_chip { struct veml6031x00_data { struct iio_gts gts; struct regmap *regmap; + struct iio_trigger *trig; struct veml6031x00_rf rf; const struct veml6031x00_chip *chip; /* @@ -68,6 +87,14 @@ struct veml6031x00_data { * consistent set. */ struct mutex scale_lock; + /* + * Serialize access to irq enable/disable by events and trigger + * (shared line) + */ + struct mutex irq_lock; + int int_users; + bool ev_en; + bool trig_en; }; =20 static const struct iio_itime_sel_mul veml6031x00_it_sel[] =3D { @@ -102,6 +129,17 @@ static const struct iio_gain_sel_pair veml6031x00_gain= _sel[] =3D { GAIN_SCALE_GAIN(16, VEML6031X00_SEL_GAIN_2_000), }; =20 +static IIO_CONST_ATTR(in_illuminance_thresh_either_period_available, "1 2 = 4 8"); + +static struct attribute *veml6031x00_event_attributes[] =3D { + &iio_const_attr_in_illuminance_thresh_either_period_available.dev_attr.at= tr, + NULL +}; + +static const struct attribute_group veml6031x00_event_attr_group =3D { + .attrs =3D veml6031x00_event_attributes, +}; + /* * The shutdown bits (SD and ALS_IR_SD) are in different registers, which * must be written together when configuring the device. @@ -139,6 +177,23 @@ static void veml6031x00_als_shutdown_action(void *data) "Failed to shut down device: %d\n", ret); } =20 +static const struct iio_event_spec veml6031x00_event_spec[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_separate =3D BIT(IIO_EV_INFO_VALUE), + }, { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_FALLING, + .mask_separate =3D BIT(IIO_EV_INFO_VALUE), + }, { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_EITHER, + .mask_separate =3D BIT(IIO_EV_INFO_PERIOD) | + BIT(IIO_EV_INFO_ENABLE), + }, +}; + static const struct iio_chan_spec veml6031x00_channels[] =3D { { .type =3D IIO_LIGHT, @@ -158,9 +213,47 @@ static const struct iio_chan_spec veml6031x00_channels= [] =3D { } }; =20 +static const struct iio_chan_spec veml6031x00_channels_irq[] =3D { + { + .type =3D IIO_LIGHT, + .address =3D VEML6031X00_REG_ALS_L, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_INT_TIME) | + BIT(IIO_CHAN_INFO_SCALE), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_INT_TIME) | + BIT(IIO_CHAN_INFO_SCALE), + .event_spec =3D veml6031x00_event_spec, + .num_event_specs =3D ARRAY_SIZE(veml6031x00_event_spec), + .scan_index =3D VEML6031X00_SCAN_ALS, + .scan_type =3D { + .format =3D IIO_SCAN_FORMAT_UNSIGNED_INT, + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_LE, + }, + }, + { + .type =3D IIO_INTENSITY, + .address =3D VEML6031X00_REG_IR_L, + .modified =3D 1, + .channel2 =3D IIO_MOD_LIGHT_IR, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), + .scan_index =3D VEML6031X00_SCAN_IR, + .scan_type =3D { + .format =3D IIO_SCAN_FORMAT_UNSIGNED_INT, + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_LE, + }, + }, + IIO_CHAN_SOFT_TIMESTAMP(VEML6031X00_SCAN_TIMESTAMP), +}; + static const struct regmap_range veml6031x00_readable_ranges[] =3D { regmap_reg_range(VEML6031X00_REG_CONF0, VEML6031X00_REG_CONF1), + regmap_reg_range(VEML6031X00_REG_WH_L, VEML6031X00_REG_WL_H), regmap_reg_range(VEML6031X00_REG_ALS_L, VEML6031X00_REG_ID_H), + regmap_reg_range(VEML6031X00_REG_INT, VEML6031X00_REG_INT), }; =20 static const struct regmap_access_table veml6031x00_readable_table =3D { @@ -169,7 +262,7 @@ static const struct regmap_access_table veml6031x00_rea= dable_table =3D { }; =20 static const struct regmap_range veml6031x00_writable_ranges[] =3D { - regmap_reg_range(VEML6031X00_REG_CONF0, VEML6031X00_REG_CONF1), + regmap_reg_range(VEML6031X00_REG_CONF0, VEML6031X00_REG_WL_H), }; =20 static const struct regmap_access_table veml6031x00_writable_table =3D { @@ -181,6 +274,7 @@ static const struct regmap_range veml6031x00_volatile_r= anges[] =3D { /* AF_TRIG in CONF0 is volatile */ regmap_reg_range(VEML6031X00_REG_CONF0, VEML6031X00_REG_CONF0), regmap_reg_range(VEML6031X00_REG_ALS_L, VEML6031X00_REG_IR_H), + regmap_reg_range(VEML6031X00_REG_INT, VEML6031X00_REG_INT), }; =20 static const struct regmap_access_table veml6031x00_volatile_table =3D { @@ -188,6 +282,15 @@ static const struct regmap_access_table veml6031x00_vo= latile_table =3D { .n_yes_ranges =3D ARRAY_SIZE(veml6031x00_volatile_ranges), }; =20 +static const struct regmap_range veml6031x00_precious_ranges[] =3D { + regmap_reg_range(VEML6031X00_REG_INT, VEML6031X00_REG_INT), +}; + +static const struct regmap_access_table veml6031x00_precious_table =3D { + .yes_ranges =3D veml6031x00_precious_ranges, + .n_yes_ranges =3D ARRAY_SIZE(veml6031x00_precious_ranges), +}; + static const struct regmap_config veml6031x00_regmap_config =3D { .name =3D "veml6031x00_regmap", .reg_bits =3D 8, @@ -195,13 +298,20 @@ static const struct regmap_config veml6031x00_regmap_= config =3D { .rd_table =3D &veml6031x00_readable_table, .wr_table =3D &veml6031x00_writable_table, .volatile_table =3D &veml6031x00_volatile_table, - .max_register =3D VEML6031X00_REG_ID_H, + .precious_table =3D &veml6031x00_precious_table, + .max_register =3D VEML6031X00_REG_INT, .cache_type =3D REGCACHE_MAPLE, }; =20 +static const struct reg_field veml6031x00_rf_int_en =3D + REG_FIELD(VEML6031X00_REG_CONF0, 1, 1); + static const struct reg_field veml6031x00_rf_it =3D REG_FIELD(VEML6031X00_REG_CONF0, 4, 6); =20 +static const struct reg_field veml6031x00_rf_pers =3D + REG_FIELD(VEML6031X00_REG_CONF1, 1, 2); + static const struct reg_field veml6031x00_rf_gain =3D REG_FIELD(VEML6031X00_REG_CONF1, 3, 4); =20 @@ -219,6 +329,12 @@ static int veml6031x00_regfield_init(struct veml6031x0= 0_data *data) return PTR_ERR(rm_field); rf->gain =3D rm_field; =20 + rm_field =3D devm_regmap_field_alloc(regmap_get_device(data->regmap), + data->regmap, veml6031x00_rf_int_en); + if (IS_ERR(rm_field)) + return PTR_ERR(rm_field); + rf->int_en =3D rm_field; + rm_field =3D devm_regmap_field_alloc(regmap_get_device(data->regmap), data->regmap, veml6031x00_rf_it); if (IS_ERR(rm_field)) @@ -231,6 +347,12 @@ static int veml6031x00_regfield_init(struct veml6031x0= 0_data *data) return PTR_ERR(rm_field); rf->pd_div4 =3D rm_field; =20 + rm_field =3D devm_regmap_field_alloc(regmap_get_device(data->regmap), + data->regmap, veml6031x00_rf_pers); + if (IS_ERR(rm_field)) + return PTR_ERR(rm_field); + rf->pers =3D rm_field; + return 0; } =20 @@ -327,6 +449,30 @@ static int veml6031x00_set_it(struct iio_dev *iio, int= val, int val2) return veml6031x00_write_gain(data, gain_sel); } =20 +static int veml6031x00_read_period(struct iio_dev *iio, int *val) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + int ret, regval; + + ret =3D regmap_field_read(data->rf.pers, ®val); + if (ret) + return ret; + + *val =3D 1 << regval; + + return IIO_VAL_INT; +} + +static int veml6031x00_write_period(struct iio_dev *iio, int val) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + + if (val < 0 || val > 8 || hweight8(val) !=3D 1) + return -EINVAL; + + return regmap_field_write(data->rf.pers, ffs(val) - 1); +} + static int veml6031x00_set_scale(struct iio_dev *iio, int val, int val2) { struct veml6031x00_data *data =3D iio_priv(iio); @@ -381,6 +527,52 @@ static int veml6031x00_get_scale(struct veml6031x00_da= ta *data, int *val, return IIO_VAL_INT_PLUS_NANO; } =20 +static int veml6031x00_read_th(struct iio_dev *iio, int *val, int *val2, i= nt dir) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + __le16 regval; + int ret; + + if (dir =3D=3D IIO_EV_DIR_RISING) + ret =3D regmap_bulk_read(data->regmap, VEML6031X00_REG_WH_L, + ®val, sizeof(regval)); + else + ret =3D regmap_bulk_read(data->regmap, VEML6031X00_REG_WL_L, + ®val, sizeof(regval)); + if (ret) + return ret; + + *val =3D le16_to_cpu(regval); + + return IIO_VAL_INT; +} + +static int veml6031x00_write_th(struct iio_dev *iio, int val, int val2, in= t dir) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + __le16 regval =3D cpu_to_le16(val); + int ret; + + if (val < 0 || val > U16_MAX || val2) + return -EINVAL; + + if (dir =3D=3D IIO_EV_DIR_RISING) { + ret =3D regmap_bulk_write(data->regmap, VEML6031X00_REG_WH_L, + ®val, sizeof(regval)); + if (ret) + dev_dbg(regmap_get_device(data->regmap), + "Failed to set high threshold %d\n", ret); + } else { + ret =3D regmap_bulk_write(data->regmap, VEML6031X00_REG_WL_L, + ®val, sizeof(regval)); + if (ret) + dev_dbg(regmap_get_device(data->regmap), + "Failed to set low threshold %d\n", ret); + } + + return ret; +} + static int veml6031x00_single_read(struct iio_dev *iio, enum iio_chan_type= type, int *val) { @@ -494,13 +686,205 @@ static int veml6031x00_write_raw_get_fmt(struct iio_= dev *indio_dev, } } =20 +static int veml6031x00_set_interrupt(struct veml6031x00_data *data, bool s= tate) + __must_hold(&data->irq_lock) +{ + int ret; + + if (state) { + data->int_users++; + if (data->int_users > 1) + return 0; + } else { + data->int_users--; + if (data->int_users > 0) + return 0; + } + + ret =3D regmap_field_write(data->rf.int_en, state); + if (ret) { + if (state) + data->int_users--; + else + data->int_users++; + } + + return ret; +} + +static int veml6031x00_read_event_val(struct iio_dev *iio, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int *val, int *val2) +{ + switch (type) { + case IIO_EV_TYPE_THRESH: + if (dir =3D=3D IIO_EV_DIR_EITHER && info =3D=3D IIO_EV_INFO_PERIOD) + return veml6031x00_read_period(iio, val); + + return veml6031x00_read_th(iio, val, val2, dir); + default: + return -EINVAL; + } +} + +static int veml6031x00_write_event_val(struct iio_dev *iio, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + switch (info) { + case IIO_EV_INFO_VALUE: + return veml6031x00_write_th(iio, val, val2, dir); + case IIO_EV_INFO_PERIOD: + return veml6031x00_write_period(iio, val); + default: + return -EINVAL; + } +} + +static int veml6031x00_read_event_config(struct iio_dev *iio, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + + guard(mutex)(&data->irq_lock); + + return data->ev_en; +} + +static int veml6031x00_write_event_config(struct iio_dev *iio, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + bool state) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + int ret; + + guard(mutex)(&data->irq_lock); + + /* avoid multiple increments/decrements from one source */ + if (state =3D=3D data->ev_en) + return 0; + + if (state) { + ret =3D pm_runtime_resume_and_get(regmap_get_device(data->regmap)); + if (ret) + return ret; + } + + ret =3D veml6031x00_set_interrupt(data, state); + if (ret) { + if (state) + pm_runtime_put_autosuspend(regmap_get_device(data->regmap)); + return ret; + } + + data->ev_en =3D state; + + if (!state) + pm_runtime_put_autosuspend(regmap_get_device(data->regmap)); + + return 0; +} + +static void veml6031x00_disable_event_action(void *arg) +{ + struct veml6031x00_data *data =3D arg; + int ret; + + guard(mutex)(&data->irq_lock); + + if (!data->ev_en) + return; + + ret =3D veml6031x00_set_interrupt(data, false); + if (ret) + dev_err(regmap_get_device(data->regmap), + "Failed to disable events: %d\n", ret); + + data->ev_en =3D false; + pm_runtime_put_autosuspend(regmap_get_device(data->regmap)); +} + static const struct iio_info veml6031x00_info =3D { .read_raw =3D veml6031x00_read_raw, .read_avail =3D veml6031x00_read_avail, .write_raw =3D veml6031x00_write_raw, .write_raw_get_fmt =3D veml6031x00_write_raw_get_fmt, + .read_event_value =3D veml6031x00_read_event_val, + .write_event_value =3D veml6031x00_write_event_val, + .read_event_config =3D veml6031x00_read_event_config, + .write_event_config =3D veml6031x00_write_event_config, + .event_attrs =3D &veml6031x00_event_attr_group, +}; + +static const struct iio_info veml6031x00_info_no_irq =3D { + .read_raw =3D veml6031x00_read_raw, + .read_avail =3D veml6031x00_read_avail, + .write_raw =3D veml6031x00_write_raw, + .write_raw_get_fmt =3D veml6031x00_write_raw_get_fmt, }; =20 +static irqreturn_t veml6031x00_interrupt(int irq, void *private) +{ + struct iio_dev *iio =3D private; + struct veml6031x00_data *data =3D iio_priv(iio); + s64 timestamp; + int regval, ret; + bool trigger_poll; + + scoped_guard(mutex, &data->irq_lock) { + ret =3D regmap_read(data->regmap, VEML6031X00_REG_INT, ®val); + if (ret) { + dev_dbg(regmap_get_device(data->regmap), + "Failed to read interrupt register %d\n", ret); + return IRQ_NONE; + } + + if (!(regval & VEML6031X00_INT_MASK)) + return IRQ_NONE; + + if ((regval & (VEML6031X00_INT_TH_H | VEML6031X00_INT_TH_L)) && + data->ev_en) { + timestamp =3D iio_get_time_ns(iio); + + if (regval & VEML6031X00_INT_TH_H) + iio_push_event(iio, + IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + timestamp); + if (regval & VEML6031X00_INT_TH_L) + iio_push_event(iio, + IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_FALLING), + timestamp); + } + + trigger_poll =3D (regval & VEML6031X00_INT_DRDY) && data->trig_en; + } + + /* + * iio_trigger_poll_nested() must be called with irq_lock released: + * iio_trigger_poll_nested() runs trig_handler() synchronously in this + * thread, which calls reenable() on completion, and that callback also + * takes irq_lock. + */ + if (trigger_poll) + iio_trigger_poll_nested(data->trig); + + return IRQ_HANDLED; +} + static int veml6031x00_buffer_preenable(struct iio_dev *iio) { struct veml6031x00_data *data =3D iio_priv(iio); @@ -535,11 +919,78 @@ static int veml6031x00_buffer_postdisable(struct iio_= dev *iio) return 0; } =20 +static int veml6031x00_set_trigger_state(struct iio_trigger *trig, bool st= ate) +{ + struct iio_dev *iio =3D iio_trigger_get_drvdata(trig); + struct veml6031x00_data *data =3D iio_priv(iio); + int ret; + + guard(mutex)(&data->irq_lock); + + if (state =3D=3D data->trig_en) + return 0; + + ret =3D veml6031x00_set_interrupt(data, state); + if (ret) + return ret; + + /* The AF bit must be set before setting AF_TRIG */ + ret =3D regmap_update_bits(data->regmap, VEML6031X00_REG_CONF0, + VEML6031X00_CONF0_AF, + FIELD_PREP(VEML6031X00_CONF0_AF, state)); + if (ret) { + veml6031x00_set_interrupt(data, !state); + + return ret; + } + + ret =3D regmap_update_bits(data->regmap, VEML6031X00_REG_CONF0, + VEML6031X00_CONF0_AF_TRIG, + FIELD_PREP(VEML6031X00_CONF0_AF_TRIG, state)); + if (ret) { + regmap_update_bits(data->regmap, VEML6031X00_REG_CONF0, + VEML6031X00_CONF0_AF, + FIELD_PREP(VEML6031X00_CONF0_AF, !state)); + veml6031x00_set_interrupt(data, !state); + + return ret; + } + + data->trig_en =3D state; + + return 0; +} + static const struct iio_buffer_setup_ops veml6031x00_buffer_setup_ops =3D { .preenable =3D veml6031x00_buffer_preenable, .postdisable =3D veml6031x00_buffer_postdisable, }; =20 +static void veml6031x00_trigger_reenable(struct iio_trigger *trig) +{ + struct iio_dev *iio =3D iio_trigger_get_drvdata(trig); + struct veml6031x00_data *data =3D iio_priv(iio); + int ret; + + guard(mutex)(&data->irq_lock); + + if (!data->trig_en) + return; + + ret =3D regmap_update_bits(data->regmap, VEML6031X00_REG_CONF0, + VEML6031X00_CONF0_AF_TRIG, + FIELD_PREP(VEML6031X00_CONF0_AF_TRIG, true)); + if (ret) + dev_err(regmap_get_device(data->regmap), + "Failed to reenable trigger: %d\n", ret); +} + +static const struct iio_trigger_ops veml6031x00_trigger_ops =3D { + .validate_device =3D iio_trigger_validate_own_device, + .set_trigger_state =3D veml6031x00_set_trigger_state, + .reenable =3D veml6031x00_trigger_reenable, +}; + static irqreturn_t veml6031x00_trig_handler(int irq, void *p) { struct iio_poll_func *pf =3D p; @@ -597,7 +1048,8 @@ static int veml6031x00_validate_part_id(struct veml603= 1x00_data *data) static int veml6031x00_hw_init(struct iio_dev *iio) { struct veml6031x00_data *data =3D iio_priv(iio); - int ret; + int ret, val; + __le16 regval; =20 /* Max resolution =3D 6.9632 lx/cnt for gain =3D 0.125 and IT =3D 3.125ms= */ ret =3D devm_iio_init_iio_gts(regmap_get_device(data->regmap), 6, 9632000= 00, @@ -610,6 +1062,60 @@ static int veml6031x00_hw_init(struct iio_dev *iio) return dev_err_probe(regmap_get_device(data->regmap), ret, "failed to init IIO GTS\n"); =20 + regval =3D 0; + ret =3D regmap_bulk_write(data->regmap, VEML6031X00_REG_WL_L, ®val, + sizeof(regval)); + if (ret) + return dev_err_probe(regmap_get_device(data->regmap), ret, + "Failed to set low threshold\n"); + + regval =3D cpu_to_le16(U16_MAX); + ret =3D regmap_bulk_write(data->regmap, VEML6031X00_REG_WH_L, ®val, + sizeof(regval)); + if (ret) + return dev_err_probe(regmap_get_device(data->regmap), ret, + "Failed to set high threshold\n"); + + ret =3D regmap_field_write(data->rf.int_en, 0); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, VEML6031X00_REG_INT, &val); + if (ret) + return dev_err_probe(regmap_get_device(data->regmap), ret, + "Failed to clear interrupts\n"); + + return 0; +} + +static int veml6031x00_setup_irq(struct i2c_client *i2c, struct iio_dev *i= io) +{ + struct veml6031x00_data *data =3D iio_priv(iio); + int ret; + + data->trig =3D devm_iio_trigger_alloc(regmap_get_device(data->regmap), + "%s-drdy%d", iio->name, iio_device_id(iio)); + if (!data->trig) + return -ENOMEM; + + data->trig->ops =3D &veml6031x00_trigger_ops; + iio_trigger_set_drvdata(data->trig, iio); + + ret =3D devm_iio_trigger_register(regmap_get_device(data->regmap), data->= trig); + if (ret) + return ret; + + iio->trig =3D iio_trigger_get(data->trig); + ret =3D devm_request_threaded_irq(regmap_get_device(data->regmap), + i2c->irq, NULL, + veml6031x00_interrupt, + IRQF_ONESHOT, + iio->name, iio); + if (ret) + return dev_err_probe(regmap_get_device(data->regmap), ret, + "Failed to request irq %d\n", + i2c->irq); + return 0; } =20 @@ -636,15 +1142,29 @@ static int veml6031x00_probe(struct i2c_client *i2c) "Failed to set regmap\n"); =20 iio->name =3D data->chip->name; - iio->channels =3D veml6031x00_channels; - iio->num_channels =3D ARRAY_SIZE(veml6031x00_channels); iio->modes =3D INDIO_DIRECT_MODE; - iio->info =3D &veml6031x00_info; + if (i2c->irq) { + iio->channels =3D veml6031x00_channels_irq; + iio->num_channels =3D ARRAY_SIZE(veml6031x00_channels_irq); + ret =3D veml6031x00_setup_irq(i2c, iio); + if (ret) + return ret; + + iio->info =3D &veml6031x00_info; + } else { + iio->channels =3D veml6031x00_channels; + iio->num_channels =3D ARRAY_SIZE(veml6031x00_channels); + iio->info =3D &veml6031x00_info_no_irq; + } =20 ret =3D devm_mutex_init(&i2c->dev, &data->scale_lock); if (ret) return ret; =20 + ret =3D devm_mutex_init(&i2c->dev, &data->irq_lock); + if (ret) + return ret; + ret =3D veml6031x00_regfield_init(data); if (ret) return dev_err_probe(&i2c->dev, ret, "Failed to init regfield\n"); @@ -672,6 +1192,12 @@ static int veml6031x00_probe(struct i2c_client *i2c) if (ret) return dev_err_probe(&i2c->dev, ret, "Failed to get runtime PM\n"); =20 + ret =3D devm_add_action_or_reset(&i2c->dev, + veml6031x00_disable_event_action, data); + if (ret) + return dev_err_probe(&i2c->dev, ret, + "Failed to add event cleanup action\n"); + ret =3D veml6031x00_validate_part_id(data); if (ret) return ret; --=20 2.43.0