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[144.178.202.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c90494sm19432266b.36.2026.08.07.00.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 00:46:17 -0700 (PDT) From: Luca Weiss Date: Fri, 07 Aug 2026 09:46:04 +0200 Subject: [PATCH RFT 1/3] clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-various-pcie-clk-fix-v1-1-5caf78a599d7@fairphone.com> References: <20260807-various-pcie-clk-fix-v1-0-5caf78a599d7@fairphone.com> In-Reply-To: <20260807-various-pcie-clk-fix-v1-0-5caf78a599d7@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio , Taniya Das , Abel Vesa , Dmitry Baryshkov , Vivek Aknurwar , Mike Tipton Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786088775; l=1636; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=xuFI5Q5PVaGG13a653oWxSPz1g51NAalhPKeOlwyekI=; b=OXG25V5ARtGUJVxIyXDW+USORGyOaj0s9wColp0IAl5AEuF1LG94pyjn+EuvGXuDY24NQTytp q6+8ZYpr5E4B3Cw6u9cCqMwEwftg4L1waHGPpbXfiHhvfwOujJ9vvS6 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= The critical_cbrcrs array will get qcom_branch_set_clk_en() called on each entry which will set BIT(0) to enable the clock. This is however wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set respectively to enable them. Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on= Eliza") Signed-off-by: Luca Weiss Reviewed-by: Abel Vesa Tested-by: Abel Vesa --- drivers/clk/qcom/gcc-eliza.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c index 3e26c7a1e5b5..fe18942a59ac 100644 --- a/drivers/clk/qcom/gcc-eliza.c +++ b/drivers/clk/qcom/gcc-eliza.c @@ -3010,8 +3010,6 @@ static const u32 gcc_eliza_critical_cbcrs[] =3D { 0x26034, /* GCC_CAMERA_XO_CLK */ 0x27004, /* GCC_DISP_AHB_CLK */ 0x71004, /* GCC_GPU_CFG_AHB_CLK */ - 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ - 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ 0x32004, /* GCC_VIDEO_AHB_CLK */ 0x32038, /* GCC_VIDEO_XO_CLK */ }; @@ -3045,6 +3043,10 @@ static const struct regmap_config gcc_eliza_regmap_c= onfig =3D { =20 static void clk_eliza_regs_configure(struct device *dev, struct regmap *re= gmap) { + /* Keep clocks always enabled */ + regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); /* GCC_PCIE_RSCC_C= FG_AHB_CLK */ + regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); /* GCC_PCIE_RSCC_X= O_CLK */ + /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); --=20 2.55.0 From nobody Wed Sep 30 13:56:22 2026 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 164BC466B03 for ; Fri, 7 Aug 2026 07:46:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786088782; cv=none; b=YFUTRtFWIrbaqwpF8Yrwk8UXJgvuxRn6r3uPDnOois+bKclH8sxeyC7gu0w7yDYIgOM+i41wWyw7UI72Yjy9zjF1lQopgjOUPss2PWY+xPbKSTE0NirI6t8mH6Ebd58AwBfcIgd4OtikBce8HjL3n9KgRXYe9vD3W91WaZ4aHLw= ARC-Message-Signature: i=1; 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[144.178.202.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c90494sm19432266b.36.2026.08.07.00.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 00:46:17 -0700 (PDT) From: Luca Weiss Date: Fri, 07 Aug 2026 09:46:05 +0200 Subject: [PATCH RFT 2/3] clk: qcom: gcc-hawi: Fix always-enabling PCIE_RSCC clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-various-pcie-clk-fix-v1-2-5caf78a599d7@fairphone.com> References: <20260807-various-pcie-clk-fix-v1-0-5caf78a599d7@fairphone.com> In-Reply-To: <20260807-various-pcie-clk-fix-v1-0-5caf78a599d7@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio , Taniya Das , Abel Vesa , Dmitry Baryshkov , Vivek Aknurwar , Mike Tipton Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786088775; l=1552; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=cBrRSZBzfiIs4w5x58DH2PbmvBIdxlF5csil5qzrDsE=; b=N5RK0Mk+vQJtchHvyGUtX0e274Zxm5t2vp/CvIfbeU1YsvlfMF5mLo3lZ/iCIWtnXm05kIMcH uoQK334M5w1D0lj2DhnDrrbXXfCqiyVYQFbYyD+r9H5o9vf9t23S7GE X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= The critical_cbrcrs array will get qcom_branch_set_clk_en() called on each entry which will set BIT(0) to enable the clock. This is however wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set respectively to enable them. Fixes: 67121dad6cba ("clk: qcom: Add support for global clock controller on= Hawi") Signed-off-by: Luca Weiss --- drivers/clk/qcom/gcc-hawi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-hawi.c b/drivers/clk/qcom/gcc-hawi.c index 6fb5a3db9586..f1b95753c3a3 100644 --- a/drivers/clk/qcom/gcc-hawi.c +++ b/drivers/clk/qcom/gcc-hawi.c @@ -3692,8 +3692,6 @@ static const u32 gcc_hawi_critical_cbcrs[] =3D { 0x67084, /* GCC_PCIE_1_RSC_CORE_CLK */ 0x43014, /* GCC_PCIE_LINK_XO_CLK */ 0x6b088, /* GCC_PCIE_RSC_CORE_CLK */ - 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ - 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ 0x32004, /* GCC_VIDEO_AHB_CLK */ 0x32028, /* GCC_VIDEO_XO_CLK */ }; @@ -3763,6 +3761,10 @@ static const struct regmap_config gcc_hawi_regmap_co= nfig =3D { =20 static void clk_hawi_regs_configure(struct device *dev, struct regmap *reg= map) { + /* Keep clocks always enabled */ + regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); /* GCC_PCIE_RSCC_C= FG_AHB_CLK */ + regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); 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[144.178.202.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c90494sm19432266b.36.2026.08.07.00.46.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 00:46:18 -0700 (PDT) From: Luca Weiss Date: Fri, 07 Aug 2026 09:46:06 +0200 Subject: [PATCH RFT 3/3] clk: qcom: gcc-kaanapali: Fix always-enabling PCIE_RSCC clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-various-pcie-clk-fix-v1-3-5caf78a599d7@fairphone.com> References: <20260807-various-pcie-clk-fix-v1-0-5caf78a599d7@fairphone.com> In-Reply-To: <20260807-various-pcie-clk-fix-v1-0-5caf78a599d7@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio , Taniya Das , Abel Vesa , Dmitry Baryshkov , Vivek Aknurwar , Mike Tipton Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786088775; l=1581; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=IzuyGpzwH+5W9XFy1kPfgzd/QVcGUIiyKRGNz+cEUck=; b=ibZFcqfvuGnha1lbV0ra4kA7Omqr82sT0bdZrYoXGclvGIcsj7X/ekS9Ykm5vVp6UAF5vbRSq nHdnSPRXZ0iC/7swoRIH1xUKLKPeZRD1lzVpjBd0/twKVSqQbr4I0ta X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= The critical_cbrcrs array will get qcom_branch_set_clk_en() called on each entry which will set BIT(0) to enable the clock. This is however wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set respectively to enable them. Fixes: d1919c375f21 ("clk: qcom: Add support for Global clock controller on= Kaanapali") Signed-off-by: Luca Weiss --- drivers/clk/qcom/gcc-kaanapali.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-kaanapali.c b/drivers/clk/qcom/gcc-kaanap= ali.c index 842c1a70c691..5bcbcd178657 100644 --- a/drivers/clk/qcom/gcc-kaanapali.c +++ b/drivers/clk/qcom/gcc-kaanapali.c @@ -3464,8 +3464,6 @@ static const u32 gcc_kaanapali_critical_cbcrs[] =3D { 0x9f004, /* GCC_EVA_AHB_CLK */ 0x9f024, /* GCC_EVA_XO_CLK */ 0x71004, /* GCC_GPU_CFG_AHB_CLK */ - 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ - 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ 0x32004, /* GCC_VIDEO_AHB_CLK */ 0x32040, /* GCC_VIDEO_XO_CLK */ }; @@ -3480,6 +3478,10 @@ static const struct regmap_config gcc_kaanapali_regm= ap_config =3D { =20 static void clk_kaanapali_regs_configure(struct device *dev, struct regmap= *regmap) { + /* Keep clocks always enabled */ + regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); /* GCC_PCIE_RSCC_C= FG_AHB_CLK */ + regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); /* GCC_PCIE_RSCC_X= O_CLK */ + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); } --=20 2.55.0