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[184.96.154.59]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae706cd5sm7353485b6e.11.2026.08.07.08.39.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 08:39:09 -0700 (PDT) From: James Hilliard Date: Fri, 07 Aug 2026 09:38:59 -0600 Subject: [PATCH v3 1/3] mtd: rawnand: sunxi: group controller delay tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-submit-sunxi-nand-h6-h616-timings-v3-1-91287b543f41@gmail.com> References: <20260807-submit-sunxi-nand-h6-h616-timings-v3-0-91287b543f41@gmail.com> In-Reply-To: <20260807-submit-sunxi-nand-h6-h616-timings-v3-0-91287b543f41@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Genoud Cc: linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard , stable@vger.kernel.org X-Mailer: b4 0.15.2 The tWB and tRHW timing field encodings are controller properties, but they currently live in standalone lookup tables. Group them in a timing descriptor selected through the controller capability data. Point every existing controller at the legacy values so this is a pure preparation change. Fixes: 88fd4e4deae8 ("mtd: rawnand: sunxi: Add support for H616 nand contro= ller") Cc: stable@vger.kernel.org Signed-off-by: James Hilliard --- drivers/mtd/nand/raw/sunxi_nand.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 02647565c8ba..9885248c9b85 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -237,6 +237,14 @@ struct sunxi_nand_hw_ecc { u32 ecc_ctl; }; =20 +#define SUNXI_NFC_TIMING_STEPS 4 + +/* Delay arrays contain internal NDFC clock cycles for field values 0 to 3= . */ +struct sunxi_nfc_timings { + s32 tWB[SUNXI_NFC_TIMING_STEPS]; + s32 tRHW[SUNXI_NFC_TIMING_STEPS]; +}; + /** * struct sunxi_nand_chip - stores NAND chip device related information * @@ -301,6 +309,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * bytes to write * @nuser_data_tab: Size of @user_data_len_tab * @sram_size: Size of the NAND controller SRAM + * @timings: Controller timing characteristics */ struct sunxi_nfc_caps { bool has_mdma; @@ -327,6 +336,7 @@ struct sunxi_nfc_caps { unsigned int nuser_data_tab; unsigned int max_ecc_steps; int sram_size; + const struct sunxi_nfc_timings *timings; }; =20 /** @@ -1667,8 +1677,10 @@ static int sunxi_nfc_hw_ecc_write_oob(struct nand_ch= ip *nand, int page) return nand_prog_page_end_op(nand); } =20 -static const s32 tWB_lut[] =3D {6, 12, 16, 20}; -static const s32 tRHW_lut[] =3D {4, 8, 12, 20}; +static const struct sunxi_nfc_timings sun4i_a10_nfc_timings =3D { + .tWB =3D { 6, 12, 16, 20 }, + .tRHW =3D { 4, 8, 12, 20 }, +}; =20 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 dur= ation, u32 clk_period) @@ -1693,6 +1705,7 @@ static int sunxi_nfc_setup_interface(struct nand_chip= *nand, int csline, { struct sunxi_nand_chip *sunxi_nand =3D to_sunxi_nand(nand); struct sunxi_nfc *nfc =3D to_sunxi_nfc(sunxi_nand->nand.controller); + const struct sunxi_nfc_timings *nfc_timings =3D nfc->caps->timings; const struct nand_sdr_timings *timings; u32 min_clk_period =3D 0; s32 tWB, tADL, tWHR, tRHW, tCAD; @@ -1763,8 +1776,10 @@ static int sunxi_nfc_setup_interface(struct nand_chi= p *nand, int csline, min_clk_period =3D DIV_ROUND_UP(timings->tWC_min, 2); =20 /* T16 - T19 + tCAD */ - if (timings->tWB_max > (min_clk_period * 20)) - min_clk_period =3D DIV_ROUND_UP(timings->tWB_max, 20); + if (timings->tWB_max > + (min_clk_period * nfc_timings->tWB[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period =3D DIV_ROUND_UP(timings->tWB_max, + nfc_timings->tWB[SUNXI_NFC_TIMING_STEPS - 1]); =20 if (timings->tADL_min > (min_clk_period * 32)) min_clk_period =3D DIV_ROUND_UP(timings->tADL_min, 32); @@ -1772,8 +1787,10 @@ static int sunxi_nfc_setup_interface(struct nand_chi= p *nand, int csline, if (timings->tWHR_min > (min_clk_period * 32)) min_clk_period =3D DIV_ROUND_UP(timings->tWHR_min, 32); =20 - if (timings->tRHW_min > (min_clk_period * 20)) - min_clk_period =3D DIV_ROUND_UP(timings->tRHW_min, 20); + if (timings->tRHW_min > + (min_clk_period * nfc_timings->tRHW[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period =3D DIV_ROUND_UP(timings->tRHW_min, + nfc_timings->tRHW[SUNXI_NFC_TIMING_STEPS - 1]); =20 /* * In non-EDO, tREA should be less than tRP to guarantee that the @@ -1789,7 +1806,7 @@ static int sunxi_nfc_setup_interface(struct nand_chip= *nand, int csline, if (timings->tREA_max > min_clk_period && !timings->tRLOH_min) min_clk_period =3D timings->tREA_max; =20 - tWB =3D sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, + tWB =3D sunxi_nand_lookup_timing(nfc_timings->tWB, timings->tWB_max, min_clk_period); if (tWB < 0) { dev_err(nfc->dev, "unsupported tWB\n"); @@ -1808,7 +1825,7 @@ static int sunxi_nfc_setup_interface(struct nand_chip= *nand, int csline, return -EINVAL; } =20 - tRHW =3D sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min, + tRHW =3D sunxi_nand_lookup_timing(nfc_timings->tRHW, timings->tRHW_min, min_clk_period); if (tRHW < 0) { dev_err(nfc->dev, "unsupported tRHW\n"); @@ -2595,6 +2612,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), .max_ecc_steps =3D 16, .sram_size =3D 1024, + .timings =3D &sun4i_a10_nfc_timings, }; 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[184.96.154.59]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae706cd5sm7353485b6e.11.2026.08.07.08.39.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 08:39:10 -0700 (PDT) From: James Hilliard Date: Fri, 07 Aug 2026 09:39:00 -0600 Subject: [PATCH v3 2/3] mtd: rawnand: sunxi: describe tADL and tWHR delays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-submit-sunxi-nand-h6-h616-timings-v3-2-91287b543f41@gmail.com> References: <20260807-submit-sunxi-nand-h6-h616-timings-v3-0-91287b543f41@gmail.com> In-Reply-To: <20260807-submit-sunxi-nand-h6-h616-timings-v3-0-91287b543f41@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Genoud Cc: linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard , stable@vger.kernel.org X-Mailer: b4 0.15.2 The tADL and tWHR timing fields use four encoded delays, but the driver currently derives their values with a shift. This hides the actual controller timing characteristics and lets the clock solver select a 32-cycle delay that the fields cannot encode. Describe the legacy 7, 15, 23 and 31 cycle thresholds explicitly and use the tables for both clock selection and field lookup. This prepares the driver for controllers with different encodings. Fixes: 88fd4e4deae8 ("mtd: rawnand: sunxi: Add support for H616 nand contro= ller") Cc: stable@vger.kernel.org Signed-off-by: James Hilliard --- drivers/mtd/nand/raw/sunxi_nand.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 9885248c9b85..df52501c1285 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -242,6 +242,8 @@ struct sunxi_nand_hw_ecc { /* Delay arrays contain internal NDFC clock cycles for field values 0 to 3= . */ struct sunxi_nfc_timings { s32 tWB[SUNXI_NFC_TIMING_STEPS]; + s32 tADL[SUNXI_NFC_TIMING_STEPS]; + s32 tWHR[SUNXI_NFC_TIMING_STEPS]; s32 tRHW[SUNXI_NFC_TIMING_STEPS]; }; =20 @@ -1679,6 +1681,8 @@ static int sunxi_nfc_hw_ecc_write_oob(struct nand_chi= p *nand, int page) =20 static const struct sunxi_nfc_timings sun4i_a10_nfc_timings =3D { .tWB =3D { 6, 12, 16, 20 }, + .tADL =3D { 7, 15, 23, 31 }, + .tWHR =3D { 7, 15, 23, 31 }, .tRHW =3D { 4, 8, 12, 20 }, }; =20 @@ -1781,11 +1785,15 @@ static int sunxi_nfc_setup_interface(struct nand_ch= ip *nand, int csline, min_clk_period =3D DIV_ROUND_UP(timings->tWB_max, nfc_timings->tWB[SUNXI_NFC_TIMING_STEPS - 1]); =20 - if (timings->tADL_min > (min_clk_period * 32)) - min_clk_period =3D DIV_ROUND_UP(timings->tADL_min, 32); + if (timings->tADL_min > + (min_clk_period * nfc_timings->tADL[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period =3D DIV_ROUND_UP(timings->tADL_min, + nfc_timings->tADL[SUNXI_NFC_TIMING_STEPS - 1]); =20 - if (timings->tWHR_min > (min_clk_period * 32)) - min_clk_period =3D DIV_ROUND_UP(timings->tWHR_min, 32); + if (timings->tWHR_min > + (min_clk_period * nfc_timings->tWHR[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period =3D DIV_ROUND_UP(timings->tWHR_min, + nfc_timings->tWHR[SUNXI_NFC_TIMING_STEPS - 1]); =20 if (timings->tRHW_min > (min_clk_period * nfc_timings->tRHW[SUNXI_NFC_TIMING_STEPS - 1])) @@ -1813,16 +1821,18 @@ static int sunxi_nfc_setup_interface(struct nand_ch= ip *nand, int csline, return tWB; } =20 - tADL =3D DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3; - if (tADL > 3) { + tADL =3D sunxi_nand_lookup_timing(nfc_timings->tADL, + timings->tADL_min, min_clk_period); + if (tADL < 0) { dev_err(nfc->dev, "unsupported tADL\n"); - return -EINVAL; + return tADL; } =20 - tWHR =3D DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3; - if (tWHR > 3) { + tWHR =3D sunxi_nand_lookup_timing(nfc_timings->tWHR, + timings->tWHR_min, min_clk_period); + if (tWHR < 0) { dev_err(nfc->dev, "unsupported tWHR\n"); - return -EINVAL; + return tWHR; } =20 tRHW =3D sunxi_nand_lookup_timing(nfc_timings->tRHW, timings->tRHW_min, --=20 2.53.0 From nobody Tue Sep 29 11:58:36 2026 Received: from mail-oi1-f181.google.com (mail-oi1-f181.google.com [209.85.167.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EFDA4779A1 for ; Fri, 7 Aug 2026 15:39:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[184.96.154.59]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae706cd5sm7353485b6e.11.2026.08.07.08.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 08:39:11 -0700 (PDT) From: James Hilliard Date: Fri, 07 Aug 2026 09:39:01 -0600 Subject: [PATCH v3 3/3] mtd: rawnand: sunxi: fix H6/H616 controller timings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-submit-sunxi-nand-h6-h616-timings-v3-3-91287b543f41@gmail.com> References: <20260807-submit-sunxi-nand-h6-h616-timings-v3-0-91287b543f41@gmail.com> In-Reply-To: <20260807-submit-sunxi-nand-h6-h616-timings-v3-0-91287b543f41@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Genoud Cc: linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard , stable@vger.kernel.org X-Mailer: b4 0.15.2 The NAND timing calculation assumes that command and address setup and hold intervals T1-T4, T7 and T11 each take one controller clock. It also uses the original A10 delay encodings for tWB, tADL, tWHR and tRHW. The H6/H616 NDFC defines the setup and hold intervals as two internal clock cycles and uses different delay encodings. Add the H616 timing characteristics and select them through the controller capability data so the clock solver and timing fields match the hardware. Fixes: 88fd4e4deae8 ("mtd: rawnand: sunxi: Add support for H616 nand contro= ller") Cc: stable@vger.kernel.org Signed-off-by: James Hilliard --- drivers/mtd/nand/raw/sunxi_nand.c | 49 ++++++++++++++++++++++++++++-------= ---- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index df52501c1285..ca74c9c333e7 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -241,6 +241,8 @@ struct sunxi_nand_hw_ecc { =20 /* Delay arrays contain internal NDFC clock cycles for field values 0 to 3= . */ struct sunxi_nfc_timings { + /* Internal clock cycles used by T1-T4, T7 and T11. */ + u8 setup_cycles; s32 tWB[SUNXI_NFC_TIMING_STEPS]; s32 tADL[SUNXI_NFC_TIMING_STEPS]; s32 tWHR[SUNXI_NFC_TIMING_STEPS]; @@ -1680,12 +1682,21 @@ static int sunxi_nfc_hw_ecc_write_oob(struct nand_c= hip *nand, int page) } =20 static const struct sunxi_nfc_timings sun4i_a10_nfc_timings =3D { + .setup_cycles =3D 1, .tWB =3D { 6, 12, 16, 20 }, .tADL =3D { 7, 15, 23, 31 }, .tWHR =3D { 7, 15, 23, 31 }, .tRHW =3D { 4, 8, 12, 20 }, }; =20 +static const struct sunxi_nfc_timings sun50i_h616_nfc_timings =3D { + .setup_cycles =3D 2, + .tWB =3D { 28, 44, 60, 76 }, + .tADL =3D { 0, 12, 28, 44 }, + .tWHR =3D { 0, 12, 28, 44 }, + .tRHW =3D { 8, 24, 40, 56 }, +}; + static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 dur= ation, u32 clk_period) { @@ -1720,20 +1731,28 @@ static int sunxi_nfc_setup_interface(struct nand_ch= ip *nand, int csline, return -ENOTSUPP; =20 /* T1 <=3D> tCLS */ - if (timings->tCLS_min > min_clk_period) - min_clk_period =3D timings->tCLS_min; + if (timings->tCLS_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tCLS_min, + nfc_timings->setup_cycles); =20 /* T2 <=3D> tCLH */ - if (timings->tCLH_min > min_clk_period) - min_clk_period =3D timings->tCLH_min; + if (timings->tCLH_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tCLH_min, + nfc_timings->setup_cycles); =20 /* T3 <=3D> tCS */ - if (timings->tCS_min > min_clk_period) - min_clk_period =3D timings->tCS_min; + if (timings->tCS_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tCS_min, + nfc_timings->setup_cycles); =20 /* T4 <=3D> tCH */ - if (timings->tCH_min > min_clk_period) - min_clk_period =3D timings->tCH_min; + if (timings->tCH_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tCH_min, + nfc_timings->setup_cycles); =20 /* T5 <=3D> tWP */ if (timings->tWP_min > min_clk_period) @@ -1744,8 +1763,10 @@ static int sunxi_nfc_setup_interface(struct nand_chi= p *nand, int csline, min_clk_period =3D timings->tWH_min; =20 /* T7 <=3D> tALS */ - if (timings->tALS_min > min_clk_period) - min_clk_period =3D timings->tALS_min; + if (timings->tALS_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tALS_min, + nfc_timings->setup_cycles); =20 /* T8 <=3D> tDS */ if (timings->tDS_min > min_clk_period) @@ -1760,8 +1781,10 @@ static int sunxi_nfc_setup_interface(struct nand_chi= p *nand, int csline, min_clk_period =3D DIV_ROUND_UP(timings->tRR_min, 3); =20 /* T11 <=3D> tALH */ - if (timings->tALH_min > min_clk_period) - min_clk_period =3D timings->tALH_min; + if (timings->tALH_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tALH_min, + nfc_timings->setup_cycles); =20 /* T12 <=3D> tRP */ if (timings->tRP_min > min_clk_period) @@ -2670,7 +2693,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_h616_cap= s =3D { .nuser_data_tab =3D ARRAY_SIZE(sunxi_user_data_len_h6), .max_ecc_steps =3D 32, .sram_size =3D 8192, - .timings =3D &sun4i_a10_nfc_timings, + .timings =3D &sun50i_h616_nfc_timings, }; =20 static const struct of_device_id sunxi_nfc_ids[] =3D { --=20 2.53.0