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Fri, 07 Aug 2026 03:13:31 -0700 (PDT) From: James Clark Date: Fri, 07 Aug 2026 11:13:22 +0100 Subject: [PATCH v2] coresight: trbe: Hide enable_sink sysfs file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260807-james-cs-hide-trbe-enable-v2-1-0b2af223feed@linaro.org> X-B4-Tracking: v=1; b=H4sIAMGvdWoC/32NQQ6CMBBFr0K6dkwpFdCV9zAsSjvAGGzNlBAN6 d2tJG5dvpf89zcRkQmjuBSbYFwpUvAZ1KEQdjJ+RCCXWSipanmSNdzNAyPYCBM5hIV7BPSmnxE q27qm1dgo14q8fzIO9Nrbty7zRHEJ/N6v1vJrf9XmT3UtoYReo5a6Og9a2+tM3nA4Bh5Fl1L6A OoTbkHDAAAA X-Change-ID: 20260506-james-cs-hide-trbe-enable-3c8d784e72d8 To: Suzuki K Poulose , Mike Leach , Leo Yan , Yeoreum Yun Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.15.2 TRBE doesn't support sysfs mode, but the enable_sink file can still be successfully written to enable the device, and only attempting to enable the source would later fail. Avoid misleading users by adding a flag that devices can use to hide either the enable_sink or enable_source files, and set it for TRBE. Don't set it for ETE as it's possible that ETE could appear on the legacy bus and work with sysfs, and writing to enable_source already reports EINVAL if the device doesn't support sysfs mode. Signed-off-by: James Clark Reviewed-by: Leo Yan --- Changes in v2: - Re-use CORESIGHT_DESC flags in csdev instead of converting to bool. - Hide all remaining attrs after label instead of only source and sink attrs as there aren't any others anyway (Leo). - Link to v1: https://lore.kernel.org/r/20260507-james-cs-hide-trbe-enable-= v1-1-b4e40439f44c@linaro.org --- drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-sysfs.c | 15 +++++++++------ drivers/hwtracing/coresight/coresight-trbe.c | 7 +++++++ include/linux/coresight.h | 4 ++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index f7b1308a759c..a0c098980096 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1543,6 +1543,7 @@ coresight_init_device(struct coresight_desc *desc) csdev->ops =3D desc->ops; csdev->access =3D desc->access; csdev->orphan =3D true; + csdev->flags =3D desc->flags; =20 if (desc->flags & CORESIGHT_DESC_CPU_BOUND) { csdev->cpu =3D desc->cpu; diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtrac= ing/coresight/coresight-sysfs.c index 4b010f8bc4c0..75000fe64fda 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -346,16 +346,19 @@ static ssize_t label_show(struct device *dev, } static DEVICE_ATTR_RO(label); =20 -static umode_t label_is_visible(struct kobject *kobj, - struct attribute *attr, int n) +static umode_t coresight_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int n) { struct device *dev =3D kobj_to_dev(kobj); + struct coresight_device *csdev =3D to_coresight_device(dev); =20 if (attr =3D=3D &dev_attr_label.attr) { if (fwnode_property_present(dev_fwnode(dev), "label")) return attr->mode; else return 0; + } else if (csdev->flags & CORESIGHT_DESC_NO_SYSFS_MODE) { + return 0; } =20 return attr->mode; @@ -369,7 +372,7 @@ static struct attribute *coresight_sink_attrs[] =3D { =20 static struct attribute_group coresight_sink_group =3D { .attrs =3D coresight_sink_attrs, - .is_visible =3D label_is_visible, + .is_visible =3D coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_sink); =20 @@ -381,7 +384,7 @@ static struct attribute *coresight_source_attrs[] =3D { =20 static struct attribute_group coresight_source_group =3D { .attrs =3D coresight_source_attrs, - .is_visible =3D label_is_visible, + .is_visible =3D coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_source); =20 @@ -392,7 +395,7 @@ static struct attribute *coresight_link_attrs[] =3D { =20 static struct attribute_group coresight_link_group =3D { .attrs =3D coresight_link_attrs, - .is_visible =3D label_is_visible, + .is_visible =3D coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_link); =20 @@ -403,7 +406,7 @@ static struct attribute *coresight_helper_attrs[] =3D { =20 static struct attribute_group coresight_helper_group =3D { .attrs =3D coresight_helper_attrs, - .is_visible =3D label_is_visible, + .is_visible =3D coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_helper); =20 diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index c7cbca45f2de..eca8e13a9744 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1348,6 +1348,13 @@ static void arm_trbe_register_coresight_cpu(struct t= rbe_drvdata *drvdata, int cp desc.dev =3D dev; desc.cpu =3D cpu; desc.flags =3D CORESIGHT_DESC_CPU_BOUND; + /* + * ETE isn't connected to TRBE with a link like other Coresight devices + * and the TRBE driver has been written to always assume Perf mode, so + * Prevent sysfs from being used. + */ + desc.flags |=3D CORESIGHT_DESC_NO_SYSFS_MODE; + trbe_csdev =3D coresight_register(&desc); if (IS_ERR(trbe_csdev)) goto cpu_clear; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index add0579cad88..6cd1d01b843b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -142,6 +142,8 @@ struct csdev_access { }) =20 #define CORESIGHT_DESC_CPU_BOUND BIT(0) +/* Device can't be activated from sysfs, only via Perf. */ +#define CORESIGHT_DESC_NO_SYSFS_MODE BIT(1) =20 /** * struct coresight_desc - description of a component required from drivers @@ -310,6 +312,8 @@ struct coresight_device { struct list_head config_csdev_list; raw_spinlock_t cscfg_csdev_lock; void *active_cscfg_ctxt; + /* CORESIGHT_DESC_[x] flags */ + u32 flags; }; =20 /* --- base-commit: c8eb4a8dd259fb2b215da32764fa8c6c76519896 change-id: 20260506-james-cs-hide-trbe-enable-3c8d784e72d8 Best regards, -- =20 James Clark