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[108.228.232.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141009ab943sm666233c88.7.2026.08.06.12.04.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 12:04:42 -0700 (PDT) From: "Derek J. Clark" To: Bjorn Helgaas Cc: "Pierre-Loup A . Griffais" , "Derek J . Clark" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] pci: quirks: Disable native PCIe hotplug on MSI Claw A8 root bridge Date: Thu, 6 Aug 2026 12:04:39 -0700 Message-ID: <20260806190439.12022-1-derekjohn.clark@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MSI Claw A8 (MS-1T8K) hard-locks on resume from s2idle whenever an SD/MMC card is present in the onboard Realtek RTS525A card reader (10ec:525a), which sits behind root port 0000:00:02.2. The reader's PCIe endpoint is fixed/soldered and not user-hotpluggable. Firmware advertises this root port as PCIe hotplug-capable, and _OSC grants the OS native hotplug control. When native hotplug is OS-owned, resuming from s2idle races the port's hotplug/PME resume handling against the RTS525A's own resume sequence when a card is present, hard-locking the system. Two kernel command line parameters were confirmed to prevent the hang: pcie_aspm=3Doff and pcie_ports=3Dcompat. Both stop the OS from running its own hotplug/PME resume path against this port. The former does so by dropping _OSC negotiation during boot, skipping the path that enables PCIeHotPlug. The latter prevents the PME service resume handling by aborting registration of the ports native services. Testing different kernel boot commands, including pciehp=3Doff and pcie_pme=3Doff did not resolve the issue. AER, DPC, SHPC, and LTR flags were not tested because the hardware reports that the platform doesn't support those features. This quirk implements as narrow a fix as possible, clearing native_pcie_hotplug on the host bridge, scoped by DMI board name and this root port's bus/device/function, so the port driver never registers a native hotplug service against it. As native_pcie_hotplug is a struct pci_host_bridge field shared by every port under this root's domain I also verified this to be the only slot under this root bridge reporting HotPlug+. SD card insertion is handled entirely by rtsx_pci's own card-detect logic, so is unaffected by this quirk. Signed-off-by: Derek J. Clark --- drivers/pci/quirks.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 6501c949c5b7..8218f423fd2a 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -6420,3 +6420,29 @@ static void pci_mask_replay_timer_timeout(struct pci= _dev *pdev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_t= imeout); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_t= imeout); #endif + +/* + * The MSI Claw A8 firmware advertises native PCIe hotplug support for + * this root bridge, but native hotplug handling causes resume failures. + * Prevent the PCIe port driver from claiming native hotplug ownership. + */ +static void quirk_claw_a8_no_native_hotplug(struct pci_dev *pdev) +{ + struct pci_host_bridge *bridge; + + if (!dmi_match(DMI_BOARD_NAME, "MS-1T8K")) + return; + + if (pdev->bus->number !=3D 0 || + PCI_SLOT(pdev->devfn) !=3D 2 || + PCI_FUNC(pdev->devfn) !=3D 2) + return; + + bridge =3D pci_find_host_bridge(pdev->bus); + if (!bridge) + return; + dev_info(&pdev->dev, "disabling native PCIe hotplug\n"); + bridge->native_pcie_hotplug =3D false; +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x150b, + quirk_claw_a8_no_native_hotplug); --=20 2.55.0