From nobody Tue Sep 29 14:54:54 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011009.outbound.protection.outlook.com [52.101.57.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62DBB239E60; Thu, 6 Aug 2026 18:12:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.9 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039953; cv=fail; b=DC9Zv+vsmyuAIY6dUB2nZ3mOGkCJ05IivFC9PBPHez/N4+KeaOBVg/b9asJbrVFem/54XL62Pb73A09Ljxrx6lhVr9VZrc8rmiRWFpPF1JZGE2Xc6Bt4C4pXgOY7Aph3fDP702IA7KEB/3+eDs7fD4qVRVXUO+tj/qxxKvHPRps= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039953; c=relaxed/simple; bh=u8ETwGFYW0RTArdZboEhfho14Mh9blXrrFXdiXdhYWU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VAvKaLXVzuGOP5TZ67ONcPCLlBeqUKvbhhNDHyuYdnMTz8DAj7ELIUYxLXF4geuuqWXoSWB/p9jkHtpaWOg7LPTqV1kGHS7SYk8b2BnzjjVJWAor6JopCL0jTWADeR7bJprPXn+26y0hr6WqDdunIG9B9u+rAxABQKZ06BJHQ9I= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=EB8GBR6F; arc=fail smtp.client-ip=52.101.57.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="EB8GBR6F" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=lZjxWYRfRJlpPmsQ4l40DbXEd1ZjY6YxDOKMxtXXArtyE+JopftDH2rGTz5u++fvHUesB3NOcRSebxTbWzw6JYaNR7Fc/0p4RUP7V23YGhIXULFwOAwcM5GRlCKCL6iFekK3c4e55RBThmtQ5brznqcEH6DBct7OMXcykHDvP2SsDFYaEkVK48EOXwSItvjyulZfVs2mxIpS5+6h70xTvHFLNeUseWuJhNmoMSgrjSwk0fcpSbOKF7grVJWsY4B3D2paQv517N0gXeK6X1lwr9L0+RBlUkWqJDfI59fppKNv5M5vQYmYUkCsYK18a23QiDo2ojtdG/9XSPhYHerOnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=82TTsPol7pywyMi5IzCCAEOAzelDKwD06oN9jnjHe1U=; b=xWF/l2+xrYSw9MLkqdVH5lQ5wTbG90lK4yNoxE0xvGVJN9EVcV+ufNy4Nyn2NzyaD+SAotsTCIZ8ZvaHwWrgXvhpCL3Wh2vXpQm5e/+s/Dg0LaLJQzK8izyWoU3JecRYoNz4etAvyvTl2rGDUPAWX37X6KMxoJLJ7qKHy76vcyNlQJ4KTcGpVXkl+N8Ggo71+ozXWF7v4aXyINIYi+M+pI6P2G12RWyHCWedBAhzl6EgPYPYsfzhTH/7KjtemJtxiiZbj3YD2HHd/DhFvNQBCWmKB7U43lRSA64Hc6KVSvcEO4J+yBaZ+ZZQB7UiO0/Wl17iR34y3RkjIeLrA87gng== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lunn.ch smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=82TTsPol7pywyMi5IzCCAEOAzelDKwD06oN9jnjHe1U=; b=EB8GBR6FHZnJhTmTB1PifRUXCKlT5GGyiiLxqqYEZMFwk9nU4OwoOIGDF9P+fvN4ElDKJFLL6EPsuVNsVHfr7NLY/r4G0gQp5EGQjXflL6W2rSSeldfSkhepn8FtHZ3YoHmOypKHFIzAcTjz0d239H1pDCjNJKPXYdoGVbwTS5s= Received: from CH5P223CA0019.NAMP223.PROD.OUTLOOK.COM (2603:10b6:610:1f3::6) by CH3PR12MB9123.namprd12.prod.outlook.com (2603:10b6:610:1a4::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.20; Thu, 6 Aug 2026 18:12:25 +0000 Received: from CH3PEPF0000000A.namprd04.prod.outlook.com (2603:10b6:610:1f3:cafe::57) by CH5P223CA0019.outlook.office365.com (2603:10b6:610:1f3::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.21 via Frontend Transport; Thu, 6 Aug 2026 18:12:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by CH3PEPF0000000A.mail.protection.outlook.com (10.167.244.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Thu, 6 Aug 2026 18:12:25 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 13:12:12 -0500 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 6 Aug 2026 13:12:05 -0500 From: Suraj Gupta To: Radhey Shyam Pandey , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Michal Simek , Rob Herring , Brian Masney , Stephen Boyd , Greg Kroah-Hartman , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Danilo Krummrich , "Michael Turquette" , "Rafael J . Wysocki" , Russell King , Shuah Khan , Jonathan Corbet Subject: [PATCH net-next v2 1/7] clk: Add devm_clk_bulk_get_enable() Date: Thu, 6 Aug 2026 23:41:47 +0530 Message-ID: <20260806181153.1213996-2-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260806181153.1213996-1-suraj.gupta2@amd.com> References: <20260723123838.125145-1-suraj.gupta2@amd.com> <20260806181153.1213996-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000A:EE_|CH3PR12MB9123:EE_ X-MS-Office365-Filtering-Correlation-Id: fdb63567-1168-4a11-3c99-08def3e644a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|7416014|376014|23010399003|22082099003|18002099003|4143699003|11063799006|56012099006|10067099003|921020; X-Microsoft-Antispam-Message-Info: r5qf5uBdLu4WmH19bbTFY7mSFXMzSQaBOjPJQPsgpE3dv3W0WVfQiT137/5UjIu+ZiRlpMNdMDpVIxT3hbG3FU7hUF0da86y3dKfpeSiFjn1YdmxXG+KR4qbYwgGdw0RL3+ufj02LQSmqrMyqp06RSotFykRANd19GaqrjjFrofYwcnqtFd+y06i99QP3KDBw+6BlkeUt1cYnd7H4QMZE3xQfYNTxy6PhKSq+5SQlGVbhSs19WzM4LPvBp76995yZGsOvIlwgYcXVEglTW7GgFvk8DBvA5RojKD5cKAjRY+bYU1fhGaKkIp2bLaQpdEiOrOybycx9ajF1AcR17bPbNSqxOa0xYGshlA2Y+uMPhS8HRFqybnMqnSQmziuaJSLYKMzNblhrJxSYg+T5HaJzXtC+nOEcq4HlMN8EHLvufPDadzeV8RcH1EYQuBGiF2dPPIj8xnEn/HtC9haQQ46grzQL9OtsdYU4JatZT5NDfP/cT9Rhbz8Q+FlH+zgzXFI++SbunvNxwBWiNzTIwRefWRCW27P92r2c6T3z79rhiWonuTd5k3BAEpTogrkUU83HwIAabFQ2DmWNoMLUy8xQ1AQTnmq0uGZAv9BNVHiIBxmxvQc0LYEZPjXsmxr6NbeKjbx9i6Xu0ZFoafjZPhP+lfL2369xwXUDgJavOlU6iM8Xpwjg658BphioBU/NCRUl6Sa+G0muh3SfPoaRUfchjnQTYXjMf6OFVaMyGEgBe8DGjvDJEysI+K3nALPaU8R X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(7416014)(376014)(23010399003)(22082099003)(18002099003)(4143699003)(11063799006)(56012099006)(10067099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ixiIEXKdjDUnX0BKwix+UW8KpQo5pvjbDzR4yLLSgcjXIuAWRLXhNWK7PRl85kAkdbGjRymo40IuL19PO/ocoLJxUl3EjOL5M84q7Ob3+DQ4jKJn+JnTcH3xghOWcig880Gke75x28CE8ACCdr/eiNyAD41pD9Yn8UGQkHFeVIftb8U7pV8HBinxrZ+HIqyCc368A/bC4G4Jw8ZKiEnSk6E+XyYne+nVBnuoOXLw6xfCUzQjvHHDsn1jSPKuXVTbTEhOq5vr1v8t9XmQY0D7p7pvP7H12d9SJJDGcQHn//Ok4S5PBWWV4MP6PwIJUdP34pKN83D3YgcmeFJftQ0Ko8ZtFTmfrHuCh0nHZlXo0hEAFOJWbKxiNH+SDH2rM5XIg5V4icY8F9jtwSsp8upk+nvCWW3FL1/qrBVy4GprmRzpIWUpNrDUyOu/wZQaIKBC X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 18:12:25.2280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fdb63567-1168-4a11-3c99-08def3e644a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9123 Content-Type: text/plain; charset="utf-8" devm_clk_bulk_get_optional_enable() gets, prepares and enables a set of clocks with device-managed cleanup, but treats every clock as optional: a missing clock is silently returned as NULL instead of failing. Consumers that need a fixed set of mandatory clocks enabled for the lifetime of the device currently have to open-code devm_clk_bulk_get() followed by clk_bulk_prepare_enable(), which loses the managed disable on unbind, or fall back to per-clock devm_clk_get_enabled() calls. Add devm_clk_bulk_get_enable() as the non-optional counterpart. The underlying __devm_clk_bulk_get_enable() helper already supports the required (optional =3D false) path, so only export a thin wrapper for it. Signed-off-by: Suraj Gupta Reviewed-by: Brian Masney --- .../driver-api/driver-model/devres.rst | 1 + drivers/clk/clk-devres.c | 7 ++++++ include/linux/clk.h | 23 +++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/Documentation/driver-api/driver-model/devres.rst b/Documentati= on/driver-api/driver-model/devres.rst index 017fb155a5bc..5067500ded5c 100644 --- a/Documentation/driver-api/driver-model/devres.rst +++ b/Documentation/driver-api/driver-model/devres.rst @@ -248,6 +248,7 @@ CLOCK devm_clk_put() devm_clk_bulk_get() devm_clk_bulk_get_all() + devm_clk_bulk_get_enable() devm_clk_bulk_get_optional() devm_get_clk_from_child() devm_clk_hw_register() diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c index 994d5bc5168b..49d4782991eb 100644 --- a/drivers/clk/clk-devres.c +++ b/drivers/clk/clk-devres.c @@ -222,6 +222,13 @@ static int __devm_clk_bulk_get_enable(struct device *d= ev, int num_clks, return ret; } =20 +int __must_check devm_clk_bulk_get_enable(struct device *dev, int num_clks, + struct clk_bulk_data *clks) +{ + return __devm_clk_bulk_get_enable(dev, num_clks, clks, false); +} +EXPORT_SYMBOL_GPL(devm_clk_bulk_get_enable); + int __must_check devm_clk_bulk_get_optional_enable(struct device *dev, int= num_clks, struct clk_bulk_data *clks) { diff --git a/include/linux/clk.h b/include/linux/clk.h index 998ba3f261da..0289ac4c6e48 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -502,6 +502,22 @@ int __must_check devm_clk_bulk_get(struct device *dev,= int num_clks, */ int __must_check devm_clk_bulk_get_optional(struct device *dev, int num_cl= ks, struct clk_bulk_data *clks); +/** + * devm_clk_bulk_get_enable - Get and enable bulk clocks (managed) + * @dev: device for clock "consumer" + * @num_clks: the number of clk_bulk_data + * @clks: pointer to the clk_bulk_data table of consumer + * + * Behaves the same as devm_clk_bulk_get() but also prepares and enables t= he + * clocks in one operation with management. The clks will automatically be + * disabled, unprepared and freed when the device is unbound. + * + * Return: 0 if all clocks specified in clk_bulk_data table are obtained a= nd + * enabled successfully. Otherwise returns valid IS_ERR() condition contai= ning + * errno. + */ +int __must_check devm_clk_bulk_get_enable(struct device *dev, int num_clks, + struct clk_bulk_data *clks); /** * devm_clk_bulk_get_optional_enable - Get and enable optional bulk clocks= (managed) * @dev: device for clock "consumer" @@ -1052,6 +1068,13 @@ static inline int __must_check devm_clk_bulk_get_opt= ional(struct device *dev, return 0; } =20 +static inline int __must_check devm_clk_bulk_get_enable(struct device *dev, + int num_clks, + struct clk_bulk_data *clks) +{ + return 0; +} + static inline int __must_check devm_clk_bulk_get_optional_enable(struct de= vice *dev, int num_clks, struct clk_bulk_data *clks) --=20 2.25.1 From nobody Tue Sep 29 14:54:54 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011032.outbound.protection.outlook.com [52.101.52.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F0B548A2C3; Thu, 6 Aug 2026 18:12:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.52.32 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039956; cv=fail; b=EupUH9GFc1glKOJE9+iDeLLY0hU8dC9m2b7frs2bkFvDdlWKUCf38eOyuFqEBJu+YVmHj39y/euVsGVGstoAi5eU1ZHNiDg6sgjmTMC1PR12gUycyavMgl8a6Jg7E/E9Dd/pExAueXBLDVx2pY3nWTSUQM3+NOXcCHaUZyrF+0A= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039956; c=relaxed/simple; bh=NZXG35c8H5uRRWe4b1J5BA/X1XXitzy9kjdj3ZE+W3E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jfaRcKPr3GhyFLohcYZs8rQwL00Y1kuXH+RB6jGlffCcsITya68DoXx7AQEcB3waY7859stJ7mXUDXokdhDDy6o7D0MX8U/XCDaAsYTX50Wub+kbHqaeR8y0cmQ6MXEG4ApbRnC9j7ZtEIfbaNVrQBl7prQxKCipeWNTsP2ibKU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=SPkXXq/2; arc=fail smtp.client-ip=52.101.52.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="SPkXXq/2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=MC8ZiSRAGQp3k02+gr7rXwTlsEAwQpe3E6BIdbQGWEPkAj/+zm/5LVbiOP9Td3xBgJlngtJWVFrdsZkNJxYJckIoxYxLOGuWjFWJnAegFwRp0IeMHgzIpemGUOxKGnrrJTOLec7pVRhLz7X4Q6Y1i9a+y4ffPzlTvXl+DScZaUHhihimlDGUsMe0nnrhd1lfAJKegUfim5Wy6BaG8DMS9wtJRlkPf1eTXl1erXPzt9tNmWH8S9sj5AT2ZmebU7p/kkDHJxeFpTdZbXcSH+PHyMcFst5YGcVR46aINq32TgZK/uMOue37BfQOD2FCDSxsUgYQTLbYkclyQxD7y2JbWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GT55Hvmm2/JZAOAZlYrRj07fOuazW0zYIN28WEzCJmA=; b=nMkVVWPkCmHHppL1FYrblHKqNIU0/kSqRSqQwoIHYvp+IDBgzngQlR8xcdeoTy6DtcLeS8C6PuC0deGtwzDfdPJPSwKkSPWTr2/JkNUHz20pz8+psJL8SRDsVs+Yan5aEdfkvSqJkOSx4ERtzHNxkkBVqc+SAXJZ68UfgRjKDH7yp/BoKrENMJaFQGZuLzRMKriITfmt+ycArXZId8aS7Up5rcgaAedSXZOLoMuIuyWB5O6+vIfJivDGqFIfNgUlOlr8c+kNH3eJ7AjfCv/Bvw/2MBjxM3ppJpP3jdoCmilGmSSEfYT6E+Mqd9BsK6qSTxBf50OCXRggfn8YeDFKjQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lunn.ch smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GT55Hvmm2/JZAOAZlYrRj07fOuazW0zYIN28WEzCJmA=; b=SPkXXq/2vdF88bVU3J3sijUQr3CPxtfmfbsNOd4XuXc63fOxFUzHWK/YzbhubZrsmA+F/4qi82oV3aFE0YYEBpO7wEi0dSNmHvkI6P8ufbs7un2pvwMkc94zPmm6dHJWodVHTThSnIUMmtXp0BabyOWFL9NqRcsdFwxUvsgKbXs= Received: from BN9PR03CA0748.namprd03.prod.outlook.com (2603:10b6:408:110::33) by SA1PR12MB7248.namprd12.prod.outlook.com (2603:10b6:806:2be::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.19; Thu, 6 Aug 2026 18:12:25 +0000 Received: from BN1PEPF00004685.namprd03.prod.outlook.com (2603:10b6:408:110:cafe::c) by BN9PR03CA0748.outlook.office365.com (2603:10b6:408:110::33) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.21 via Frontend Transport; Thu, 6 Aug 2026 18:12:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN1PEPF00004685.mail.protection.outlook.com (10.167.243.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Thu, 6 Aug 2026 18:12:25 +0000 Received: from Satlexmb09.amd.com (10.181.42.218) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 13:12:19 -0500 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 11:12:19 -0700 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 6 Aug 2026 13:12:12 -0500 From: Suraj Gupta To: Radhey Shyam Pandey , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Michal Simek , Rob Herring , Brian Masney , Stephen Boyd , Greg Kroah-Hartman , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Danilo Krummrich , "Michael Turquette" , "Rafael J . Wysocki" , Russell King , Shuah Khan , Jonathan Corbet Subject: [PATCH net-next v2 2/7] net: xilinx: axienet: Introduce axienet_config for MAC-specific ops Date: Thu, 6 Aug 2026 23:41:48 +0530 Message-ID: <20260806181153.1213996-3-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260806181153.1213996-1-suraj.gupta2@amd.com> References: <20260723123838.125145-1-suraj.gupta2@amd.com> <20260806181153.1213996-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004685:EE_|SA1PR12MB7248:EE_ X-MS-Office365-Filtering-Correlation-Id: b43c25ff-8355-4ec3-e306-08def3e64489 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|36860700016|1800799024|82310400026|921020|10063799003|6133799003|10067099003|56012099006|11063799006|5023799004|4143699003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: K/8ga/Dd3615tLiKdFmFvf6jECO3kOwxw2evB80f2l78PGPEJ5tR1PCYynP50MqbdnPmiOni34LhRXT35HIa3lLTt7zc/H+CmzJ8+68mJWdv6mGE3bTLfbRR6/5Q5dX0QLDwdCnlWHXz3OgdCqaY5w6sbui7rgf7kQTg6sJDb1mfBAhAzWGSPV3EEbvuwmMgDSUWzcVwQPthqTLahZZC3uSyaendEZWiy6osY+PHR2PmNSFvMAqchzWRRPB2GTWrePx8x9vfqNpXJAwmNp22N1JMiXNYzRkm4BZKjH/7VPla4mArAG9vJxI9hFa5wN7p1eHGLJ3LQnkziDUxeucl4CkZec0Oqf7omx39sstpeYtxi056YhFmYt+bR4mQx098b+8eoY/641OXcWnJLggZWp2A7KUE6/TYmKmD5WFkSgfW5L2c8jMcUTH2AofO3fxiB8WrGfKSYEp6Tf//Ji0Yn0gSZv5O2xgU/wJ6IU4mc01V92d5CT5xJP3XGokhBSEE/ogRqTHV3Up99Xz8DwPZQBK5ufFSXdBThtyg0rWTyr0gyhsXEwCqSCDQm9ZLKfhrbh+SL+Pg+FtWNjK/U3+w35fa7PwczlkZQTgRoVouZKYU86wrPGy4mr68RroHTdO9T2/EayC1flL2pSX1pbJjUEa05OJozR5M5LXBqR1k6UMVNlzo7NS2cVMKV7j//ybIuKN7nelWWVB7+drnxfeqQbmrQZY23g5SImTdq5ow/SaYmJD2IPeR6sXWsTuR6Flv X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(23010399003)(36860700016)(1800799024)(82310400026)(921020)(10063799003)(6133799003)(10067099003)(56012099006)(11063799006)(5023799004)(4143699003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3M8sLLtIIfhFTjlfnsvh9+Ktpyxat49y5dnX3vYrhm79zDjhR8kb4NRYQPPLuk+MxwB6Cpn/CAaKRHUng9pATlVjU9RDiE/LNJx3Lpdtn6lpi/kttwc0KFci5yN8/MT/sY2zso92w1JHzTFALn4sdC7/EQBdzEpf+YrXp1mPwM/V63x9liBk/RFpEq2NluPqOpScqJIHMZreEBiFZ5oprcZNGXkVd28sv/DEYSQNhLTapKNZSHe3lH/t+lXnr9++Klzj5ix2CIClTKnEnE4XKOu8tNVqXxTMjzsLT6gq/O/X6lZIZ7BByERycNqjEFdqmkPm5C8t8ojQOwtit7ZV7+kusssKw4hJlrf6rZnEey+plycgd7ArCXt9Qnx0RkoY/Bv13Qk4+jaRY/TWeZ5aLLeqacgy4LxEMsFyoWVfaYojnNIDQC3HI/AJ5E4zJRAr X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 18:12:25.0715 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b43c25ff-8355-4ec3-e306-08def3e64489 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7248 Content-Type: text/plain; charset="utf-8" Introduce an axienet_config structure to abstract MAC-type-specific operations, preparing the driver for supporting additional MAC types beyond the existing 1G Ethernet. Add axienet_config with capability flags (mdio, mac_irq, legacy_dma, uc_filter, mc_filter, vlan, jumbo, dma_tx_csum, sw_padding, internal_pcs), the register-dump count and callbacks (clk_init, setoptions, probe_init, gt_reset, mac_init, mac_link_up, get_regs, phylink_set_caps, pcs_ops, stats_update), and populate it from the OF match table. Convert the common code to consult these capabilities and callbacks instead of open-coding 1G behavior, so a new MAC type can be added without adding MAC-specific conditionals to the shared paths. No functional change intended for the existing 1G path. Signed-off-by: Suraj Gupta --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 52 +++ .../net/ethernet/xilinx/xilinx_axienet_main.c | 391 ++++++++++++------ 2 files changed, 319 insertions(+), 124 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index fcd3aaef27fc..40f03c9eb382 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -545,6 +545,7 @@ struct skbuf_dma_descriptor { * @tx_ring_tail: TX skb ring buffer tail index. * @rx_ring_head: RX skb ring buffer head index. * @rx_ring_tail: RX skb ring buffer tail index. + * @axienet_config: MAC-type specific configuration and operations. */ struct axienet_local { struct net_device *ndev; @@ -626,6 +627,57 @@ struct axienet_local { int tx_ring_tail; int rx_ring_head; int rx_ring_tail; + const struct axienet_config *axienet_config; +}; + +/** + * struct axienet_config - MAC-type specific configuration and operations + * @mdio: MAC has an MDIO bus for external PHY management + * @mac_irq: MAC has a dedicated core interrupt + * @legacy_dma: MAC supports the legacy (non-dmaengine) DMA mode + * @uc_filter: MAC has unicast address filter registers + * @mc_filter: MAC has multicast address filter registers + * @vlan: MAC supports VLAN frames by default + * @jumbo: MAC supports jumbo frames + * @dma_tx_csum: MAC supports TX checksum offload + * @sw_padding: Short frames must be padded in software before transmit + * @internal_pcs: MAC always drives an internal PCS + * @regs_n: Number of MAC registers exposed through ethtool -d + * @clk_init: Callback to get and enable the MAC-specific clocks + * @setoptions: Callback to program MAC hardware options + * @probe_init: Callback for MAC-specific probe-time init, or NULL if unus= ed + * @gt_reset: Callback to reset the serial transceiver (GT), or NULL if un= used + * @mac_init: Callback for MAC-specific bring-up after the DMA reset + * @mac_link_up: Callback to program link speed and pause on link up, or N= ULL + * @get_regs: Callback to dump the MAC registers for ethtool -d + * @phylink_set_caps: Callback to set phylink MAC capabilities + * @pcs_ops: phylink PCS operations for this MAC, or NULL if unused + * @stats_update: Callback to latch/accumulate the periodic MAC counters + */ +struct axienet_config { + bool mdio; + bool mac_irq; + bool legacy_dma; + bool uc_filter; + bool mc_filter; + bool vlan; + bool jumbo; + bool dma_tx_csum; + bool sw_padding; + bool internal_pcs; + unsigned int regs_n; + int (*clk_init)(struct axienet_local *lp); + void (*setoptions)(struct net_device *ndev, u32 options); + void (*probe_init)(struct axienet_local *lp); + void (*gt_reset)(struct axienet_local *lp); + int (*mac_init)(struct net_device *ndev); + void (*mac_link_up)(struct net_device *ndev, int speed, + bool tx_pause, bool rx_pause); + void (*get_regs)(struct axienet_local *lp, u32 *data); + void (*phylink_set_caps)(struct axienet_local *lp, + struct phylink_config *config); + const struct phylink_pcs_ops *pcs_ops; + void (*stats_update)(struct axienet_local *lp); }; =20 /** diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 67d1b8e91d68..5c59423bd778 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -64,16 +65,6 @@ =20 static void axienet_rx_submit_desc(struct net_device *ndev); =20 -/* Match table for of_platform binding */ -static const struct of_device_id axienet_of_match[] =3D { - { .compatible =3D "xlnx,axi-ethernet-1.00.a", }, - { .compatible =3D "xlnx,axi-ethernet-1.01.a", }, - { .compatible =3D "xlnx,axi-ethernet-2.01.a", }, - {}, -}; - -MODULE_DEVICE_TABLE(of, axienet_of_match); - /* Option table for setting up Axi Ethernet hardware options */ static struct axienet_option axienet_options[] =3D { /* Turn on jumbo packet support for both Rx and Tx */ @@ -418,6 +409,9 @@ static void axienet_set_mac_address(struct net_device *= ndev, if (!is_valid_ether_addr(ndev->dev_addr)) eth_hw_addr_random(ndev); =20 + if (!lp->axienet_config->uc_filter) + return; + /* Set up unicast MAC address filter set its mac address */ axienet_iow(lp, XAE_UAW0_OFFSET, (ndev->dev_addr[0]) | @@ -467,6 +461,9 @@ static void axienet_set_multicast_list(struct net_devic= e *ndev) u32 reg, af0reg, af1reg; struct axienet_local *lp =3D netdev_priv(ndev); =20 + if (!lp->axienet_config->mc_filter) + return; + reg =3D axienet_ior(lp, XAE_FMI_OFFSET); reg &=3D ~XAE_FMI_PM_MASK; if (ndev->flags & IFF_PROMISC) @@ -575,14 +572,25 @@ static void axienet_stats_update(struct axienet_local= *lp, bool reset) write_seqcount_end(&lp->hw_stats_seqcount); } =20 +/** + * axienet_1g_stats_update - Refresh 1G MAC hardware statistics + * @lp: Pointer to the axienet_local structure + */ +static void axienet_1g_stats_update(struct axienet_local *lp) +{ + axienet_stats_update(lp, false); +} + static void axienet_refresh_stats(struct work_struct *work) { struct axienet_local *lp =3D container_of(work, struct axienet_local, stats_work.work); =20 - mutex_lock(&lp->stats_lock); - axienet_stats_update(lp, false); - mutex_unlock(&lp->stats_lock); + if (lp->axienet_config->stats_update) { + mutex_lock(&lp->stats_lock); + lp->axienet_config->stats_update(lp); + mutex_unlock(&lp->stats_lock); + } =20 /* Just less than 2^32 bytes at 2.5 GBit/s */ schedule_delayed_work(&lp->stats_work, 13 * HZ); @@ -693,6 +701,32 @@ static void axienet_dma_stop(struct axienet_local *lp) axienet_unlock_mii(lp); } =20 +/** + * axienet_1g_mac_init - 1G MAC-specific bring-up after the DMA reset + * @ndev: Pointer to the net_device structure + * + * Return: 0 on success or a negative error number otherwise. + */ +static int axienet_1g_mac_init(struct net_device *ndev) +{ + struct axienet_local *lp =3D netdev_priv(ndev); + u32 axienet_status; + + axienet_status =3D axienet_ior(lp, XAE_RCW1_OFFSET); + axienet_status &=3D ~XAE_RCW1_RX_MASK; + axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status); + + axienet_status =3D axienet_ior(lp, XAE_IP_OFFSET); + if (axienet_status & XAE_INT_RXRJECT_MASK) + axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK); + axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ? + XAE_INT_RECV_ERROR_MASK : 0); + + axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK); + + return 0; +} + /** * axienet_device_reset - Reset and initialize the Axi Ethernet hardware. * @ndev: Pointer to the net_device structure @@ -708,19 +742,23 @@ static void axienet_dma_stop(struct axienet_local *lp) */ static int axienet_device_reset(struct net_device *ndev) { - u32 axienet_status; struct axienet_local *lp =3D netdev_priv(ndev); int ret; =20 + if (lp->axienet_config->gt_reset) + lp->axienet_config->gt_reset(lp); + lp->max_frm_size =3D XAE_MAX_VLAN_FRAME_SIZE; - lp->options |=3D XAE_OPTION_VLAN; + + if (lp->axienet_config->vlan) + lp->options |=3D XAE_OPTION_VLAN; lp->options &=3D (~XAE_OPTION_JUMBO); =20 if (ndev->mtu > XAE_MTU && ndev->mtu <=3D XAE_JUMBO_MTU) { lp->max_frm_size =3D ndev->mtu + VLAN_ETH_HLEN + XAE_TRL_SIZE; =20 - if (lp->max_frm_size <=3D lp->rxmem) + if (lp->max_frm_size <=3D lp->rxmem && lp->axienet_config->jumbo) lp->options |=3D XAE_OPTION_JUMBO; } =20 @@ -737,26 +775,18 @@ static int axienet_device_reset(struct net_device *nd= ev) } } =20 - axienet_status =3D axienet_ior(lp, XAE_RCW1_OFFSET); - axienet_status &=3D ~XAE_RCW1_RX_MASK; - axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status); - - axienet_status =3D axienet_ior(lp, XAE_IP_OFFSET); - if (axienet_status & XAE_INT_RXRJECT_MASK) - axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK); - axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ? - XAE_INT_RECV_ERROR_MASK : 0); - - axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK); + ret =3D lp->axienet_config->mac_init(ndev); + if (ret) + return ret; =20 /* Sync default options with HW but leave receiver and * transmitter disabled. */ - axienet_setoptions(ndev, lp->options & - ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); + lp->axienet_config->setoptions(ndev, lp->options & + ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); axienet_set_mac_address(ndev, NULL); axienet_set_multicast_list(ndev); - axienet_setoptions(ndev, lp->options); + lp->axienet_config->setoptions(ndev, lp->options); =20 netif_trans_update(ndev); =20 @@ -914,6 +944,13 @@ axienet_start_xmit_dmaengine(struct sk_buff *skb, stru= ct net_device *ndev) int sg_len; int ret; =20 + if (lp->axienet_config->sw_padding && eth_skb_pad(skb)) { + /* Pad short frames; the MAC does not append Ethernet padding. */ + ndev->stats.tx_dropped++; + ndev->stats.tx_errors++; + return NETDEV_TX_OK; + } + dma_dev =3D lp->tx_chan->device; sg_len =3D skb_shinfo(skb)->nr_frags + 1; if (CIRC_SPACE(lp->tx_ring_head, lp->tx_ring_tail, TX_BD_NUM_MAX) <=3D 1)= { @@ -938,19 +975,21 @@ axienet_start_xmit_dmaengine(struct sk_buff *skb, str= uct net_device *ndev) goto xmit_error_drop_skb; =20 /* Fill up app fields for checksum */ - if (skb->ip_summed =3D=3D CHECKSUM_PARTIAL) { - if (lp->features & XAE_FEATURE_FULL_TX_CSUM) { - /* Tx Full Checksum Offload Enabled */ - app_metadata[0] |=3D 2; - } else if (lp->features & XAE_FEATURE_PARTIAL_TX_CSUM) { - csum_start_off =3D skb_transport_offset(skb); - csum_index_off =3D csum_start_off + skb->csum_offset; - /* Tx Partial Checksum Offload Enabled */ - app_metadata[0] |=3D 1; - app_metadata[1] =3D (csum_start_off << 16) | csum_index_off; + if (lp->axienet_config->dma_tx_csum) { + if (skb->ip_summed =3D=3D CHECKSUM_PARTIAL) { + if (lp->features & XAE_FEATURE_FULL_TX_CSUM) { + /* Tx Full Checksum Offload Enabled */ + app_metadata[0] |=3D 2; + } else if (lp->features & XAE_FEATURE_PARTIAL_TX_CSUM) { + csum_start_off =3D skb_transport_offset(skb); + csum_index_off =3D csum_start_off + skb->csum_offset; + /* Tx Partial Checksum Offload Enabled */ + app_metadata[0] |=3D 1; + app_metadata[1] =3D (csum_start_off << 16) | csum_index_off; + } + } else if (skb->ip_summed =3D=3D CHECKSUM_UNNECESSARY) { + app_metadata[0] |=3D 2; /* Tx Full Checksum Offload Enabled */ } - } else if (skb->ip_summed =3D=3D CHECKSUM_UNNECESSARY) { - app_metadata[0] |=3D 2; /* Tx Full Checksum Offload Enabled */ } =20 dma_tx_desc =3D dma_dev->device_prep_slave_sg(lp->tx_chan, skbuf_dma->sgl, @@ -1738,8 +1777,8 @@ static int axienet_stop(struct net_device *ndev) phylink_stop(lp->phylink); phylink_disconnect_phy(lp->phylink); =20 - axienet_setoptions(ndev, lp->options & - ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); + lp->axienet_config->setoptions(ndev, lp->options & + ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); =20 if (!lp->use_dmaengine) { axienet_dma_stop(lp); @@ -1765,7 +1804,8 @@ static int axienet_stop(struct net_device *ndev) } =20 netdev_reset_queue(ndev); - axienet_iow(lp, XAE_IE_OFFSET, 0); + if (lp->axienet_config->mac_irq) + axienet_iow(lp, XAE_IE_OFFSET, 0); =20 if (lp->eth_irq > 0) free_irq(lp->eth_irq, ndev); @@ -1934,30 +1974,18 @@ static void axienet_ethtools_get_drvinfo(struct net= _device *ndev, */ static int axienet_ethtools_get_regs_len(struct net_device *ndev) { - return sizeof(u32) * AXIENET_REGS_N; + struct axienet_local *lp =3D netdev_priv(ndev); + + return sizeof(u32) * lp->axienet_config->regs_n; } =20 /** - * axienet_ethtools_get_regs - Dump the contents of all registers present - * in AxiEthernet core. - * @ndev: Pointer to net_device structure - * @regs: Pointer to ethtool_regs structure - * @ret: Void pointer used to return the contents of the registers. - * - * This implements ethtool command for getting the Axi Ethernet register d= ump. - * Issue "ethtool -d ethX" to execute this function. + * axienet_1g_get_regs - Dump 1G MAC registers for ethtool + * @lp: Pointer to the axienet_local structure + * @data: Buffer for register values (zeroed and sized by the caller) */ -static void axienet_ethtools_get_regs(struct net_device *ndev, - struct ethtool_regs *regs, void *ret) +static void axienet_1g_get_regs(struct axienet_local *lp, u32 *data) { - u32 *data =3D (u32 *)ret; - size_t len =3D sizeof(u32) * AXIENET_REGS_N; - struct axienet_local *lp =3D netdev_priv(ndev); - - regs->version =3D 0; - regs->len =3D len; - - memset(data, 0, len); data[0] =3D axienet_ior(lp, XAE_RAF_OFFSET); data[1] =3D axienet_ior(lp, XAE_TPF_OFFSET); data[2] =3D axienet_ior(lp, XAE_IFGP_OFFSET); @@ -1998,6 +2026,31 @@ static void axienet_ethtools_get_regs(struct net_dev= ice *ndev, } } =20 +/** + * axienet_ethtools_get_regs - Dump the contents of all registers present + * in AxiEthernet core. + * @ndev: Pointer to net_device structure + * @regs: Pointer to ethtool_regs structure + * @ret: Void pointer used to return the contents of the registers. + * + * This implements ethtool command for getting the Axi Ethernet register d= ump. + * Issue "ethtool -d ethX" to execute this function. + */ +static void axienet_ethtools_get_regs(struct net_device *ndev, + struct ethtool_regs *regs, void *ret) +{ + struct axienet_local *lp =3D netdev_priv(ndev); + u32 *data =3D (u32 *)ret; + size_t len; + + len =3D sizeof(u32) * lp->axienet_config->regs_n; + regs->version =3D 0; + regs->len =3D len; + + memset(data, 0, len); + lp->axienet_config->get_regs(lp, data); +} + static void axienet_ethtools_get_ringparam(struct net_device *ndev, struct ethtool_ringparam *ering, @@ -2634,13 +2687,9 @@ static void axienet_mac_link_down(struct phylink_con= fig *config, /* nothing meaningful to do */ } =20 -static void axienet_mac_link_up(struct phylink_config *config, - struct phy_device *phy, - unsigned int mode, phy_interface_t interface, - int speed, int duplex, - bool tx_pause, bool rx_pause) +static void axienet_1g_mac_link_up(struct net_device *ndev, int speed, + bool tx_pause, bool rx_pause) { - struct net_device *ndev =3D to_net_dev(config->dev); struct axienet_local *lp =3D netdev_priv(ndev); u32 emmc_reg, fcc_reg; =20 @@ -2677,6 +2726,19 @@ static void axienet_mac_link_up(struct phylink_confi= g *config, axienet_iow(lp, XAE_FCC_OFFSET, fcc_reg); } =20 +static void axienet_mac_link_up(struct phylink_config *config, + struct phy_device *phy, + unsigned int mode, phy_interface_t interface, + int speed, int duplex, + bool tx_pause, bool rx_pause) +{ + struct net_device *ndev =3D to_net_dev(config->dev); + struct axienet_local *lp =3D netdev_priv(ndev); + + if (lp->axienet_config->mac_link_up) + lp->axienet_config->mac_link_up(ndev, speed, tx_pause, rx_pause); +} + static const struct phylink_mac_ops axienet_phylink_ops =3D { .mac_select_pcs =3D axienet_mac_select_pcs, .mac_config =3D axienet_mac_config, @@ -2694,7 +2756,6 @@ static const struct phylink_mac_ops axienet_phylink_o= ps =3D { static void axienet_dma_err_handler(struct work_struct *work) { u32 i; - u32 axienet_status; struct axidma_bd *cur_p; struct axienet_local *lp =3D container_of(work, struct axienet_local, dma_err_task); @@ -2707,8 +2768,8 @@ static void axienet_dma_err_handler(struct work_struc= t *work) napi_disable(&lp->napi_tx); napi_disable(&lp->napi_rx); =20 - axienet_setoptions(ndev, lp->options & - ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); + lp->axienet_config->setoptions(ndev, lp->options & + ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); =20 axienet_dma_stop(lp); netdev_reset_queue(ndev); @@ -2753,29 +2814,114 @@ static void axienet_dma_err_handler(struct work_st= ruct *work) =20 axienet_dma_start(lp); =20 - axienet_status =3D axienet_ior(lp, XAE_RCW1_OFFSET); - axienet_status &=3D ~XAE_RCW1_RX_MASK; - axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status); - - axienet_status =3D axienet_ior(lp, XAE_IP_OFFSET); - if (axienet_status & XAE_INT_RXRJECT_MASK) - axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK); - axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ? - XAE_INT_RECV_ERROR_MASK : 0); - axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK); + lp->axienet_config->mac_init(ndev); =20 /* Sync default options with HW but leave receiver and * transmitter disabled. */ - axienet_setoptions(ndev, lp->options & - ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); + lp->axienet_config->setoptions(ndev, lp->options & + ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); axienet_set_mac_address(ndev, NULL); axienet_set_multicast_list(ndev); napi_enable(&lp->napi_rx); napi_enable(&lp->napi_tx); - axienet_setoptions(ndev, lp->options); + lp->axienet_config->setoptions(ndev, lp->options); } =20 +/** + * axienet_1g_phylink_set_caps - Set 1G phylink capabilities and interfaces + * @lp: Pointer to the axienet_local structure + * @config: Pointer to the phylink_config structure + */ +static void axienet_1g_phylink_set_caps(struct axienet_local *lp, + struct phylink_config *config) +{ + config->mac_capabilities |=3D MAC_10FD | MAC_100FD | MAC_1000FD; + __set_bit(lp->phy_mode, config->supported_interfaces); + if (lp->switch_x_sgmii) { + __set_bit(PHY_INTERFACE_MODE_1000BASEX, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_SGMII, + config->supported_interfaces); + } +} + +/** + * axienet_1g_clk_init - Get and enable the 1G MAC clocks + * @lp: Pointer to the axienet_local structure + * + * Return: 0 on success or a negative error number otherwise. + */ +static int axienet_1g_clk_init(struct axienet_local *lp) +{ + struct device *dev =3D lp->dev; + int ret; + + lp->axi_clk =3D devm_clk_get_optional_enabled(dev, "s_axi_lite_clk"); + if (!lp->axi_clk) { + /* For backward compatibility, if named AXI clock is not + * present, treat the first clock specified as the AXI clock. + */ + lp->axi_clk =3D devm_clk_get_optional_enabled(dev, NULL); + } + if (IS_ERR(lp->axi_clk)) + return dev_err_probe(dev, PTR_ERR(lp->axi_clk), + "could not get AXI clock\n"); + + lp->misc_clks[0].id =3D "axis_clk"; + lp->misc_clks[1].id =3D "ref_clk"; + lp->misc_clks[2].id =3D "mgt_clk"; + + ret =3D devm_clk_bulk_get_optional_enable(dev, XAE_NUM_MISC_CLOCKS, + lp->misc_clks); + if (ret) + return dev_err_probe(dev, ret, + "could not get/enable misc. clocks\n"); + + return 0; +} + +/** + * axienet_1g_probe_init - 1G MAC-specific probe-time initialization + * @lp: Pointer to the axienet_local structure + */ +static void axienet_1g_probe_init(struct axienet_local *lp) +{ + if (axienet_ior(lp, XAE_ABILITY_OFFSET) & XAE_ABILITY_STATS) + lp->features |=3D XAE_FEATURE_STATS; +} + +static const struct axienet_config axienet_1g_config =3D { + .mdio =3D true, + .mac_irq =3D true, + .legacy_dma =3D true, + .uc_filter =3D true, + .mc_filter =3D true, + .vlan =3D true, + .jumbo =3D true, + .dma_tx_csum =3D true, + .regs_n =3D AXIENET_REGS_N, + .clk_init =3D axienet_1g_clk_init, + .setoptions =3D axienet_setoptions, + .probe_init =3D axienet_1g_probe_init, + .mac_init =3D axienet_1g_mac_init, + .mac_link_up =3D axienet_1g_mac_link_up, + .get_regs =3D axienet_1g_get_regs, + .phylink_set_caps =3D axienet_1g_phylink_set_caps, + .pcs_ops =3D &axienet_pcs_ops, + .stats_update =3D axienet_1g_stats_update, +}; + +/* Match table for of_platform binding */ +static const struct of_device_id axienet_of_match[] =3D { + { .compatible =3D "xlnx,axi-ethernet-1.00.a", .data =3D &axienet_1g_confi= g }, + { .compatible =3D "xlnx,axi-ethernet-1.01.a", .data =3D &axienet_1g_confi= g }, + { .compatible =3D "xlnx,axi-ethernet-2.01.a", .data =3D &axienet_1g_confi= g }, + {}, +}; + +MODULE_DEVICE_TABLE(of, axienet_of_match); + /** * axienet_probe - Axi Ethernet probe function. * @pdev: Pointer to platform device structure. @@ -2826,27 +2972,13 @@ static int axienet_probe(struct platform_device *pd= ev) seqcount_mutex_init(&lp->hw_stats_seqcount, &lp->stats_lock); INIT_DEFERRABLE_WORK(&lp->stats_work, axienet_refresh_stats); =20 - lp->axi_clk =3D devm_clk_get_optional_enabled(&pdev->dev, - "s_axi_lite_clk"); - if (!lp->axi_clk) { - /* For backward compatibility, if named AXI clock is not present, - * treat the first clock specified as the AXI clock. - */ - lp->axi_clk =3D devm_clk_get_optional_enabled(&pdev->dev, NULL); - } - if (IS_ERR(lp->axi_clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(lp->axi_clk), - "could not get AXI clock\n"); + lp->axienet_config =3D device_get_match_data(&pdev->dev); + if (!lp->axienet_config) + return -ENODEV; =20 - lp->misc_clks[0].id =3D "axis_clk"; - lp->misc_clks[1].id =3D "ref_clk"; - lp->misc_clks[2].id =3D "mgt_clk"; - - ret =3D devm_clk_bulk_get_optional_enable(&pdev->dev, XAE_NUM_MISC_CLOCKS, - lp->misc_clks); + ret =3D lp->axienet_config->clk_init(lp); if (ret) - return dev_err_probe(&pdev->dev, ret, - "could not get/enable misc. clocks\n"); + return ret; =20 /* Map device registers */ lp->regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, ðres); @@ -2857,9 +2989,6 @@ static int axienet_probe(struct platform_device *pdev) /* Setup checksum offload, but default to off if not specified */ lp->features =3D 0; =20 - if (axienet_ior(lp, XAE_ABILITY_OFFSET) & XAE_ABILITY_STATS) - lp->features |=3D XAE_FEATURE_STATS; - ret =3D of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value); if (!ret) { switch (value) { @@ -2933,7 +3062,17 @@ static int axienet_probe(struct platform_device *pde= v) return -EINVAL; } =20 + if (lp->axienet_config->probe_init) + lp->axienet_config->probe_init(lp); + if (!of_property_present(pdev->dev.of_node, "dmas")) { + /* Non-dmaengine (legacy DMA) mode is only supported by some MACs */ + if (!lp->axienet_config->legacy_dma) { + dev_err(&pdev->dev, + "Legacy DMA mode not supported by this MAC, use dmaengine\n"); + return -EINVAL; + } + /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ np =3D of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); =20 @@ -3013,7 +3152,10 @@ static int axienet_probe(struct platform_device *pde= v) struct xilinx_vdma_config cfg; struct dma_chan *tx_chan; =20 - lp->eth_irq =3D platform_get_irq_optional(pdev, 0); + if (lp->axienet_config->mac_irq) + lp->eth_irq =3D platform_get_irq_optional(pdev, 0); + else + lp->eth_irq =3D -ENXIO; if (lp->eth_irq < 0 && lp->eth_irq !=3D -ENXIO) { return lp->eth_irq; } @@ -3066,10 +3208,12 @@ static int axienet_probe(struct platform_device *pd= ev) lp->tx_dma_cr =3D axienet_calc_cr(lp, XAXIDMA_DFT_TX_THRESHOLD, XAXIDMA_DFT_TX_USEC); =20 - ret =3D axienet_mdio_setup(lp); - if (ret) - dev_warn(&pdev->dev, - "error registering MDIO bus: %d\n", ret); + if (lp->axienet_config->mdio) { + ret =3D axienet_mdio_setup(lp); + if (ret) + dev_warn(&pdev->dev, + "error registering MDIO bus: %d\n", ret); + } =20 if (lp->phy_mode =3D=3D PHY_INTERFACE_MODE_SGMII || lp->phy_mode =3D=3D PHY_INTERFACE_MODE_1000BASEX) { @@ -3093,23 +3237,21 @@ static int axienet_probe(struct platform_device *pd= ev) goto cleanup_mdio; } of_node_put(np); - lp->pcs.ops =3D &axienet_pcs_ops; + lp->pcs.ops =3D lp->axienet_config->pcs_ops; + lp->pcs.poll =3D true; + } + + if (lp->axienet_config->internal_pcs) { + lp->pcs.ops =3D lp->axienet_config->pcs_ops; lp->pcs.poll =3D true; } =20 lp->phylink_config.dev =3D &ndev->dev; lp->phylink_config.type =3D PHYLINK_NETDEV; lp->phylink_config.mac_managed_pm =3D true; - lp->phylink_config.mac_capabilities =3D MAC_SYM_PAUSE | MAC_ASYM_PAUSE | - MAC_10FD | MAC_100FD | MAC_1000FD; + lp->phylink_config.mac_capabilities =3D MAC_SYM_PAUSE | MAC_ASYM_PAUSE; =20 - __set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces); - if (lp->switch_x_sgmii) { - __set_bit(PHY_INTERFACE_MODE_1000BASEX, - lp->phylink_config.supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_SGMII, - lp->phylink_config.supported_interfaces); - } + lp->axienet_config->phylink_set_caps(lp, &lp->phylink_config); =20 lp->phylink =3D phylink_create(&lp->phylink_config, pdev->dev.fwnode, lp->phy_mode, @@ -3152,7 +3294,8 @@ static void axienet_remove(struct platform_device *pd= ev) if (lp->pcs_phy) put_device(&lp->pcs_phy->dev); =20 - axienet_mdio_teardown(lp); + if (lp->mii_bus) + axienet_mdio_teardown(lp); } =20 static void axienet_shutdown(struct platform_device *pdev) --=20 2.25.1 From nobody Tue Sep 29 14:54:54 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010017.outbound.protection.outlook.com [52.101.193.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4224A239E60; Thu, 6 Aug 2026 18:12:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.193.17 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039960; cv=fail; b=TGyiBlROhOIhgTXDV1FGbYAboEnPEA8fLOV08FSVnrEXjclkdVPzGtAFCIzQ2CmXplSzWK+N7l98sNyruIpw+ohSgMasaf5bYf2A+gif2xpD33OWO4goWrSR+SGWRVu6DKV0uoDg0nTPnMoZZXbFCXV/x5Lx6piMQCPXOdnTdOQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039960; c=relaxed/simple; bh=WcFZ3Nd3iiNHYzMuii4yW9T1Xs+BAwzvRdxN5+t+Fbg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=snUuqdT2pmxIHv3WYlDaSKm1DMtrMaAcPpC/1U8bBJnfPWmMJD2zH8SAV101A88oPzqK5QyxeW/m3wOXxFOMLwp/QOA0jcJeC854YkKHmeZxLno3dui2nBN6W57X45PHEjLPU41p0DzuEF1uJ/X/UsYlE4sYfXrdI45m7PoUDo4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=FXBmsjBS; arc=fail smtp.client-ip=52.101.193.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="FXBmsjBS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=R2qq1REgZPmUsY20LhyTbORSu4If1zy5Q2wl/T4i9YVNf3s/r8BB83ZnbSGL3pO+nkJRF+ew5EnVmMy9lcxoRU9OwpDdEuvjfvNi12bDsf+30sscC04KBJ4pMqMxrYtdWeydw1l2cY2QVf58HIS7oeriIsLY2NweJTJJSJDhC1UuYfLWkXj3O9AhH6w54oNv2e+rCN4hZWveGDk/XyZfvAW+0B9g7LMUevjdTc1IsIXUt/J5hhf/K0gQ/gwnt3BbY1OCFFx3w5empTaWfnMDbOda26aZRKnvS8r/ftQbvdS/wjThMP1FMaeuV1yAf7co10B6sBK8oK2rywAVGM30jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hcTpqzBlIXTP9JAEEYtU+o3yT41WptoxcbiGlA2VzwI=; b=Olx9L5LMm0V3CyDfAkUCukOn3mA5ISzD6/oS6mWy9eQPATbQgibRzOnl4sOS/AChD5C87wlpfuPWx/q6yvJWaio0QhD9/0QJfisR26ewZhLADOp8w81YO8QpPRkcgWQDvzO/uYW8EqJcwICnbOkSV9mSZqH9napgNYHYc6UGTXfP8Wjeojx76cjpU6sHJOt7K8lYxSMXvy2tl6bRg2XRL2v0PI9R8vX2F7CcfR80wpVXamRpm+PAwgMvraK4WC03RzEJ1W431E/ERS9mHiU5+g4DdYvz0D4KKmTOWmdtrmxvs1hlIC5MtErpiIThFIEdzcsNjrfanAGblBQl9RDXCw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lunn.ch smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hcTpqzBlIXTP9JAEEYtU+o3yT41WptoxcbiGlA2VzwI=; b=FXBmsjBSobRptW4SdUxclKQCxZw4xiluPp4Fl1Xxkx64p9PRxKIGlyr5yAZ10jOXfF3jAtGRylbP0xzGW/BHrxI+hL8pV8+/z0zIBi4HZZDOPkdyBSSqqgBDurH57asKoyxO6SBSp2trsqsXjJRkMseiHlFsDtyLWzsiCd6a5jw= Received: from BN9PR03CA0489.namprd03.prod.outlook.com (2603:10b6:408:130::14) by EAYPR12MB999134.namprd12.prod.outlook.com (2603:10b6:303:2c0::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.19; Thu, 6 Aug 2026 18:12:29 +0000 Received: from BN1PEPF00004683.namprd03.prod.outlook.com (2603:10b6:408:130:cafe::9e) by BN9PR03CA0489.outlook.office365.com (2603:10b6:408:130::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.21 via Frontend Transport; Thu, 6 Aug 2026 18:12:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN1PEPF00004683.mail.protection.outlook.com (10.167.243.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Thu, 6 Aug 2026 18:12:28 +0000 Received: from satlexmb10.amd.com (10.181.42.219) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 13:12:26 -0500 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 13:12:26 -0500 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 6 Aug 2026 13:12:19 -0500 From: Suraj Gupta To: Radhey Shyam Pandey , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Michal Simek , Rob Herring , Brian Masney , Stephen Boyd , Greg Kroah-Hartman , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Danilo Krummrich , "Michael Turquette" , "Rafael J . Wysocki" , Russell King , Shuah Khan , Jonathan Corbet Subject: [PATCH net-next v2 3/7] dt-bindings: net: xlnx,xxv-ethernet: Add Xilinx XXV 10G/25G Ethernet Date: Thu, 6 Aug 2026 23:41:49 +0530 Message-ID: <20260806181153.1213996-4-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260806181153.1213996-1-suraj.gupta2@amd.com> References: <20260723123838.125145-1-suraj.gupta2@amd.com> <20260806181153.1213996-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004683:EE_|EAYPR12MB999134:EE_ X-MS-Office365-Filtering-Correlation-Id: 1d984f0a-fa41-4da3-039b-08def3e646da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|23010399003|36860700016|376014|7416014|22082099003|18002099003|11063799006|4143699003|3023799007|13003099007|10067099003|56012099006|921020; X-Microsoft-Antispam-Message-Info: pK6Pb6Ka3ey9v/+tKdQsrvh2bUw7ROE9/HaA09migXJYhZxZXojh0nGSsiJcX/5nzffgnBYMS5xAIwk1clJRtpyY1jsOnUpm7E1+9aXNW2NDpk9emmzJVr3w3GuHMq1cnOjcMYV7NhsGO4HQg5ECEJrfUzZjLRPtZHs0UR8SDlKtBpN2L6jnh3v3VCJHzYDku7UtFxHBGZllhZOC7qn6qhnMQwC+lzNW86Xlg07CDM3fDwirtTSEkIB+Qnlp5d7/agGewloOIFL4+KreySyavJLAhig+dENZ5MfnkddDIIRzD6m7QxDiRtNpo9mARdlLr5HXmB8uStqt8DgMbYueahGVFNEZ1mheGDJdz/wDv2PslfRwBsPOg/VF51HK8Wx8x98hfvei5KRywPsfhEtFgiLqovD/CT6HMPRAUok1TYvPQoDq+OI+egwcyu88H9KMg+p8ZcFobc5RZA/a4aEtjKbaeZuaGsL0yxB48XSh3Vbw87E8n3r2X5/3fh7TWHGj8mtI7418fJdNcwY9pJlLYzdccp5+pn1qy7QOwEb2vR94GFUhBJDzcJL0FP9uM739a5YRK+cOm5Ln3sIV+PmCJq6Oc49iEfCi3fXs7541A0sHeA2PXbjkNhtAqrTlLMlLQuYyDywQP4leURVMSLOMZJAH38xfh4SKUognPk7rjp31fcChF9TkebcLlhIwzfko2aQQL1TVoKjLCZD0Rj+ak3R30TxLVZs85Exh+PPjkwUdbo8sgbY9CBUNlQmIfXzN X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(23010399003)(36860700016)(376014)(7416014)(22082099003)(18002099003)(11063799006)(4143699003)(3023799007)(13003099007)(10067099003)(56012099006)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kUtF92D6rfwvVnxSnViU6IYutn9DrFo4ofoSuZChGybEUFrzWDGzBGNQTE3ZYl4tKCMi3wMB2TCs18sCPL1fowYfWg58DiZfTbGpQagiIfHL01QKwoWsk0kyRpqjMRcdjXvkfHyX3jHktO5nnUUD+Vz0MiUBc3paAMTkfBlwhVi33bqenXb5bl0DD8KLfRilcTiR6RUO5eGFQUnzqZsD1jhoXSSYTrZlTx71T1JKLaXlJ0N61RZBnZWju8zf9z8REL8ag2yNwvVIKAyXIi6r2tjA62yvaK7qw8yqKeWL7fhj7cI0iglEDB/MVI/DXWsG75Z9Z20Uj14W7jOiluM45++NpPw3LRx2aT7xpq2Sq9DBio50rIK7P0k028a4R1fZM0slYRr7RhXinKMHCcOwZ4O2cKnYA+87bfms+RSPhT1I1ORa5poxZQhUIeHorXmM X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 18:12:28.9502 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d984f0a-fa41-4da3-039b-08def3e646da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004683.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: EAYPR12MB999134 Content-Type: text/plain; charset="utf-8" The XXV Ethernet IP integrates a 10G/25G Ethernet MAC with an in-core PCS/PMA driving a high-speed serial transceiver. Its payload is moved by an external AXI DMA (or multichannel DMA) controller referenced through the dmas/dma-names properties. Document the IP in a dedicated schema file. Add the "xlnx,xxv-ethernet-1.0" compatible with the 10gbase-r and 25gbase-r phy-modes, the rx_core/drp/s_axi clocks and the AXI DMA channel properties. Signed-off-by: Suraj Gupta Reviewed-by: Rob Herring (Arm) --- .../bindings/net/xlnx,xxv-ethernet.yaml | 107 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/xlnx,xxv-ethernet= .yaml diff --git a/Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml b= /Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml new file mode 100644 index 000000000000..2be3ade11d46 --- /dev/null +++ b/Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/xlnx,xxv-ethernet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XXV 10G/25G Ethernet Subsystem + +maintainers: + - Radhey Shyam Pandey + - Suraj Gupta + +description: + The Xilinx XXV Ethernet Subsystem implements a 10G/25G Ethernet MAC with= an + in-core PCS/PMA driving a high-speed serial transceiver. It supports the + 10GBASE-R and 25GBASE-R line rates, with 25G operation following the 25G + Ethernet Consortium specification. It has no external MDIO PHY, and its + payload is moved by an external AXI DMA (or multichannel DMA) controller + referenced through the "dmas" property. + +properties: + compatible: + const: xlnx,xxv-ethernet-1.0 + + reg: + maxItems: 1 + description: MAC control and status register space. + + clocks: + items: + - description: RX AXI4-Stream clock. + - description: GT DRP clock. + - description: AXI4-Lite register clock. + + clock-names: + items: + - const: rx_core + - const: drp + - const: s_axi + + phy-mode: + enum: + - 10gbase-r + - 25gbase-r + + xlnx,rxmem: + description: + Size in bytes of the Rx/Tx packet buffer memory built into the IP. I= t is + fixed by the hardware design and bounds the largest frame (jumbo MTU= ) the + device can accept. + $ref: /schemas/types.yaml#/definitions/uint32 + + dmas: + minItems: 2 + maxItems: 32 + description: TX and RX DMA channel phandle. + + dma-names: + items: + pattern: "^[tr]x_chan([0-9]|1[0-5])$" + description: + Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel = and + "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel. + minItems: 2 + maxItems: 32 + +required: + - compatible + - reg + - clocks + - clock-names + - phy-mode + - xlnx,rxmem + - dmas + - dma-names + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + +unevaluatedProperties: false + +examples: + # Single AXI DMA channel pair + - | + ethernet@80000000 { + compatible =3D "xlnx,xxv-ethernet-1.0"; + reg =3D <0x80000000 0x10000>; + clock-names =3D "rx_core", "drp", "s_axi"; + clocks =3D <&rx_clk>, <&drp_clk>, <&axi_clk>; + dma-names =3D "tx_chan0", "rx_chan0"; + dmas =3D <&axi_dma 0>, <&axi_dma 1>; + phy-mode =3D "25gbase-r"; + xlnx,rxmem =3D <0x8000>; + }; + # Multichannel DMA (MCDMA) with multiple Tx/Rx channels + - | + ethernet@80010000 { + compatible =3D "xlnx,xxv-ethernet-1.0"; + reg =3D <0x80010000 0x10000>; + clock-names =3D "rx_core", "drp", "s_axi"; + clocks =3D <&rx_clk>, <&drp_clk>, <&axi_clk>; + dma-names =3D "tx_chan0", "tx_chan1", "rx_chan0", "rx_chan1"; + dmas =3D <&axi_mcdma 0>, <&axi_mcdma 1>, + <&axi_mcdma 16>, <&axi_mcdma 17>; + phy-mode =3D "10gbase-r"; + xlnx,rxmem =3D <0x8000>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 2d420d40782e..8160a8ddec65 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -29557,6 +29557,7 @@ XILINX AXI ETHERNET DRIVER M: Radhey Shyam Pandey S: Maintained F: Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +F: Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml F: drivers/net/ethernet/xilinx/xilinx_axienet* =20 XILINX CAN DRIVER --=20 2.25.1 From nobody Tue Sep 29 14:54:54 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010011.outbound.protection.outlook.com [52.101.56.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 744AA48A8C1; Thu, 6 Aug 2026 18:12:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.11 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039966; cv=fail; b=rihK0rOqE87M+SXkkZXJFpiV+CXlSPYKRAI6rWkoRC57bPynPBOiW7yBL5vCVqjYMh55/S733+ANESyorOs7lmBHAHODnn3D+YgDC8lOK6zOmSIky+/c4YlgSYJ/66vdbkApjXZ1LjjgfBveSiLe9j9oNSt1fXFnvSI3B4F2Z4E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039966; c=relaxed/simple; bh=e/aL97+F7J+eK0HojbSx0xEmxQbxm/ZYrlupoGG0cBA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kAsUJJ3G3FS2GMeuC/5Uk67rpr9xHefiLSkHPQGi3gix36H+32CmceMYv4ZCdl6TJ+dluCECt5jrfI4K5IHe1bew6JP+fCkwzkswozMCFXC3KjBFNgUYR3OFRSk1hCTZXuX2coJXnDEfXQ0RTWz3QqL1KC844QX+EriboQPVb40= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=4zRpg954; arc=fail smtp.client-ip=52.101.56.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="4zRpg954" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PqODVEw6fkFmRUclXfnMQzJdmafEuf2hCAfcJgJgJwFW+ZJiCb9PZJ0PTmcHvpJrg0mICdW5SN0/8CCp4ObSw6qD6y8QGEfx+67zg+TSou0pgIdDjX11tSVwSmnSUa8P5S6MKsoLXtaN+tNRlkFyqW1+VBYzlWnJsshEgbqaix7ie6DfsPyj4hnsR3AJ3+qKgMnglw9y/PTVRNbGzA4lPQNhunq58IAczSUpowsAVSsuEc/zQhBue4D4p1C0sL1rnr9JFNa8Vl/wdmsih8W4MrKwW62T9m1u5z0GMIpyHqCScpCgQ7VsfvwIoiH4EJDGZnVU7UaJdoSJ/w+cwjB6cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jhBbMZhUSBavGmKY87Aokbcw6sn558H0rez4WXJpnv8=; b=VoZprNnqc2AQ33q6XxP77gE3At5MYYd6X4oHaqkEof56cQlJgKQHWSLVPuuHPV+FHuAZ5IDJGoP+xj4Jf3F+WRoJJAQVifGP0Df9mE0Y7mmYVl26lOZbpDYE1zzcjDh8WOtlUToRqp1EMq9GR4kT3Lt9+31ejdTiNW/C6JIlweapgEpyu83/8GuOnv5cIpYD7uEkXLY1oTvNNep6FFcMFxtqUkriCNaf8YfiJD3Nq1wbxrz119UQcsywHb6jA/DlElWh/24Z/CoAGiKXQww4Osu3kMVgi2ejDFl4nyB4cOh0IZRqyq6lwb5nhVu68RiEKIX8FP65xrH6+RnenlTNIw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lunn.ch smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jhBbMZhUSBavGmKY87Aokbcw6sn558H0rez4WXJpnv8=; b=4zRpg954JzD1akYeOM++pT9HsjUM0mIkSRU6ebaHKnOSI6GzJFBiurNMbooWC6WpN3je+K1bLgbPkU8qLcXsaBt6a3yk6YJWMjywKRR3fsmbo6e0jd7JNh68ATLK05Lv86NuKeF971DREuGQgNeax6Ee7aeG39JopaeHQfMd2aw= Received: from CH0PR03CA0234.namprd03.prod.outlook.com (2603:10b6:610:e7::29) by SA1PR12MB7320.namprd12.prod.outlook.com (2603:10b6:806:2b7::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.19; Thu, 6 Aug 2026 18:12:34 +0000 Received: from CH3PEPF0000000C.namprd04.prod.outlook.com (2603:10b6:610:e7:cafe::9) by CH0PR03CA0234.outlook.office365.com (2603:10b6:610:e7::29) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.21 via Frontend Transport; Thu, 6 Aug 2026 18:12:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by CH3PEPF0000000C.mail.protection.outlook.com (10.167.244.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Thu, 6 Aug 2026 18:12:33 +0000 Received: from Satlexmb09.amd.com (10.181.42.218) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 13:12:33 -0500 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 11:12:32 -0700 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 6 Aug 2026 13:12:26 -0500 From: Suraj Gupta To: Radhey Shyam Pandey , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Michal Simek , Rob Herring , Brian Masney , Stephen Boyd , Greg Kroah-Hartman , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Danilo Krummrich , "Michael Turquette" , "Rafael J . Wysocki" , Russell King , Shuah Khan , Jonathan Corbet Subject: [PATCH net-next v2 4/7] net: xilinx: axienet: Add 10G/25G (XXV) ethernet support Date: Thu, 6 Aug 2026 23:41:50 +0530 Message-ID: <20260806181153.1213996-5-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260806181153.1213996-1-suraj.gupta2@amd.com> References: <20260723123838.125145-1-suraj.gupta2@amd.com> <20260806181153.1213996-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000C:EE_|SA1PR12MB7320:EE_ X-MS-Office365-Filtering-Correlation-Id: 925851c7-1147-457d-46ee-08def3e649da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|23010399003|7416014|1800799024|13003099007|921020|6133799003|56012099006|4143699003|10067099003|18002099003|22082099003|11063799006; X-Microsoft-Antispam-Message-Info: v/D+oELLs0/MsfYUQ7fcpzx9l35CzWsIJFS1F/XRr9BhOVD9XnhHX3jwDCMnIlJSh9NGCXybmDtcYotknCuj7ctcwy/te9Tw7beeYJygRyAPDrCrurI3kcI3oqcuZQ5Lybdusr16rYnbWSZkC5kRDRryTPAJ6HsgTefMPhxdqXXtYHpxil9nzF5WsESYqdnRi1nLvc1VTYa7dPrNwaILbv/OaPhcuFPhgn3lF5wP88ZJGR41KGP0WYDMuuekFh6FiUtdlkzQdjEjNeIwQ+SOmI4gfVZ97f+2Qu+MWUN7l74awuG75G7OkWWZwjldyXzuwUPlSmnRLTp3hauyN3feQjop886wMxZzgfaagrjAeJWVjDt7QrsimbhPKH91FTq1IelrgldE6e5N2Ti2qH8Qu1YUhQGUgZok+FDU/lr7+jZPeJAXq3nfZoemyoj8F/Snj0xHn+APvj34yp4DnwYFvGvT9O3zvM38Hu5BLa33lmwEIFKbTw9wK/dyZvE+n/OYwFo4fW71T8zs130KWD4nAyRrEjR83nm3Vku/H1BQPPwH1RU8xMTznNnESl27cVRCWrCq3bLY+HdWOAte8gAOC2R3gR50zhvUbnykE2BQhH0mFtAzuxO9a3rTcszIz341SrCKZYlYcWdlfI60mbAl7PP5E8LppM3KTpCBMF4UgE/jSqeZBB/b+qNRVr2poN88wIod6wnh9MLSr7e4p2YzHJ1QP2aT77LGGkF2jhSDx1Pqiltn0sjxvtXBIPJtXarz X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700016)(23010399003)(7416014)(1800799024)(13003099007)(921020)(6133799003)(56012099006)(4143699003)(10067099003)(18002099003)(22082099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5SdtO57tFxpxuNd3sq1QyaZrN0Xmo9Br4Gqp+IGnEzxuCyyeZICWn+IvTjIlZw9IQTPSn+hZUGJmI67oZMeX0Roh4S3xuYr+0n2CZsvOxVQokzIFgykrcRVC6D+4IJj4pI9/tW4sE0QhxWZjOkIAEssSwAyU9nHYzefe9lbEOjgVDqhRiVT7OMvecvqmfYaA8+hiH0HsEUtRChoTLjb4oI7vYrqSUT3d9jAjTFUkKwt75UAWO/TZYZlchJW1yHAX4Ubb+/KaPuuZ5SLtwG285f67kGBeuKdeDV0ttvAX352j7x5/g8dOYNAmUk14f1Brk8pMV+wmMpsQVkUdv5m4q9deH0ytzTtDrxJwjQFfzEQD4+RX4tueOoNepmiSScb7TpTOCVn2ktwPf9+3p3aHL49IRLnnr3tnjxejBw8rEqAgSeMZkx4JSInv9tDcHDWh X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 18:12:33.9526 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 925851c7-1147-457d-46ee-08def3e649da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7320 Content-Type: text/plain; charset="utf-8" The AXI Ethernet driver currently supports only the AXI 1G Ethernet IP. Add support for the Xilinx XXV Ethernet IP[1], which implements a 10G/25G Ethernet MAC with PCS/PMA driving a high-speed serial transceiver, as specified by the 25G Ethernet Consortium. Add the XXV-specific logic in new xilinx_axienet_xxv.c/.h files and describe the MAC through an axienet_10g25g_config that provides the capability flags and callbacks (GT reset, link-ready polling, options programming, phylink caps, PCS ops, register dump and probe-time init). No MAC-specific conditionals are added to the shared paths. Also propagate the axienet_device_reset() failure in axienet_open(), which was previously overwritten by phylink_of_phy_connect() before being checked. This matters for XXV, whose mac_init() can fail on a GT reset-done timeout. [1]: https://docs.amd.com/r/en-US/pg210-25g-ethernet Signed-off-by: Suraj Gupta --- drivers/net/ethernet/xilinx/Makefile | 3 +- drivers/net/ethernet/xilinx/xilinx_axienet.h | 9 + .../net/ethernet/xilinx/xilinx_axienet_main.c | 17 +- .../net/ethernet/xilinx/xilinx_axienet_xxv.c | 329 ++++++++++++++++++ .../net/ethernet/xilinx/xilinx_axienet_xxv.h | 86 +++++ 5 files changed, 437 insertions(+), 7 deletions(-) create mode 100644 drivers/net/ethernet/xilinx/xilinx_axienet_xxv.c create mode 100644 drivers/net/ethernet/xilinx/xilinx_axienet_xxv.h diff --git a/drivers/net/ethernet/xilinx/Makefile b/drivers/net/ethernet/xi= linx/Makefile index 7d7dc1771423..db90e691fec5 100644 --- a/drivers/net/ethernet/xilinx/Makefile +++ b/drivers/net/ethernet/xilinx/Makefile @@ -6,5 +6,6 @@ ll_temac-objs :=3D ll_temac_main.o ll_temac_mdio.o obj-$(CONFIG_XILINX_LL_TEMAC) +=3D ll_temac.o obj-$(CONFIG_XILINX_EMACLITE) +=3D xilinx_emaclite.o -xilinx_emac-objs :=3D xilinx_axienet_main.o xilinx_axienet_mdio.o +xilinx_emac-objs :=3D xilinx_axienet_main.o xilinx_axienet_mdio.o \ + xilinx_axienet_xxv.o obj-$(CONFIG_XILINX_AXI_EMAC) +=3D xilinx_emac.o diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index 40f03c9eb382..295a1b835165 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -17,6 +17,8 @@ #include #include =20 +#include "xilinx_axienet_xxv.h" + /* Packet size info */ #define XAE_HDR_SIZE 14 /* Size of Ethernet header */ #define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */ @@ -545,6 +547,7 @@ struct skbuf_dma_descriptor { * @tx_ring_tail: TX skb ring buffer tail index. * @rx_ring_head: RX skb ring buffer head index. * @rx_ring_tail: RX skb ring buffer tail index. + * @xxv_ip_version: XXV IP version. * @axienet_config: MAC-type specific configuration and operations. */ struct axienet_local { @@ -627,6 +630,7 @@ struct axienet_local { int tx_ring_tail; int rx_ring_head; int rx_ring_tail; + u32 xxv_ip_version; const struct axienet_config *axienet_config; }; =20 @@ -680,6 +684,11 @@ struct axienet_config { void (*stats_update)(struct axienet_local *lp); }; =20 +static inline struct axienet_local *pcs_to_axienet_local(struct phylink_pc= s *pcs) +{ + return container_of(pcs, struct axienet_local, pcs); +} + /** * struct axienet_option - Used to set axi ethernet hardware options * @opt: Option to be set. diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 5c59423bd778..5bffa5b9d0b4 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -1705,6 +1705,10 @@ static int axienet_open(struct net_device *ndev) axienet_lock_mii(lp); ret =3D axienet_device_reset(ndev); axienet_unlock_mii(lp); + if (ret) { + dev_err(lp->dev, "axienet_device_reset() failed: %d\n", ret); + return ret; + } =20 ret =3D phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0); if (ret) { @@ -2604,11 +2608,6 @@ static const struct ethtool_ops axienet_ethtool_dmae= ngine_ops =3D { .get_rmon_stats =3D axienet_ethtool_get_rmon_stats, }; =20 -static struct axienet_local *pcs_to_axienet_local(struct phylink_pcs *pcs) -{ - return container_of(pcs, struct axienet_local, pcs); -} - static void axienet_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, struct phylink_link_state *state) @@ -2668,7 +2667,9 @@ static struct phylink_pcs *axienet_mac_select_pcs(str= uct phylink_config *config, struct axienet_local *lp =3D netdev_priv(ndev); =20 if (interface =3D=3D PHY_INTERFACE_MODE_1000BASEX || - interface =3D=3D PHY_INTERFACE_MODE_SGMII) + interface =3D=3D PHY_INTERFACE_MODE_SGMII || + interface =3D=3D PHY_INTERFACE_MODE_10GBASER || + interface =3D=3D PHY_INTERFACE_MODE_25GBASER) return &lp->pcs; =20 return NULL; @@ -2814,6 +2815,9 @@ static void axienet_dma_err_handler(struct work_struc= t *work) =20 axienet_dma_start(lp); =20 + /* This error handler runs only for the legacy embedded-DMA (1G) path, + * whose mac_init() cannot fail, so its return value is not checked. + */ lp->axienet_config->mac_init(ndev); =20 /* Sync default options with HW but leave receiver and @@ -2917,6 +2921,7 @@ static const struct of_device_id axienet_of_match[] = =3D { { .compatible =3D "xlnx,axi-ethernet-1.00.a", .data =3D &axienet_1g_confi= g }, { .compatible =3D "xlnx,axi-ethernet-1.01.a", .data =3D &axienet_1g_confi= g }, { .compatible =3D "xlnx,axi-ethernet-2.01.a", .data =3D &axienet_1g_confi= g }, + { .compatible =3D "xlnx,xxv-ethernet-1.0", .data =3D &axienet_10g25g_conf= ig }, {}, }; =20 diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.c b/drivers/net= /ethernet/xilinx/xilinx_axienet_xxv.c new file mode 100644 index 000000000000..46b48a773c15 --- /dev/null +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * XXV (10G/25G) support + * + * Copyright (C) 2026 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include "xilinx_axienet.h" +#include "xilinx_axienet_xxv.h" + +/* readl_poll_timeout() sleep interval (us) and 1 ms total timeout for GT + * reset-done and PCS block-lock polls. Values from ZynqMP/Versal bring-up; + * PG210 does not specify these bounds. + */ +#define XXV_LINK_POLL_INTERVAL_US 10 + +/* Number of XXV (10G/25G) MAC registers exposed via ethtool -d. + * Covers configuration and status registers per Xilinx PG210. + */ +static const u32 axienet_xxv_reg_dump_offsets[XXV_REGS_N] =3D { + XXV_GT_RESET_OFFSET, + XXV_RESET_OFFSET, + XXV_MODE_OFFSET, + XXV_TC_OFFSET, + XXV_RCW1_OFFSET, + XXV_JUM_OFFSET, + XXV_VL_LENGTH_OFFSET, + XXV_TICKREG_OFFSET, + XXV_CONFIG_REVISION, + XXV_CONFIG_1588_OFFSET, + XXV_CONFIG_TX_FLOW_CTRL1_OFFSET, + XXV_CONFIG_RX_FLOW_CTRL1_OFFSET, + XXV_CONFIG_RX_FLOW_CTRL2_OFFSET, + XXV_CONFIG_RSFEC_OFFSET, + XXV_CONFIG_FEC_OFFSET, + XXV_AN_CTL1_OFFSET, + XXV_AN_CTL2_OFFSET, + XXV_AN_ABILITY_OFFSET, + XXV_LT_CTL1_OFFSET, + XXV_SWITCH_CORE_SPEED_OFFSET, + XXV_CONFIG_1588_32BIT_OFFSET, + XXV_TX_CONFIG_1588_OFFSET, + XXV_RX_CONFIG_1588_OFFSET, + XXV_GTWIZ_CTRL_OFFSET, + XXV_STATRX_STATUS0_OFFSET, + XXV_RX_STATUS_REG1, + XXV_STATRX_STATUS2_OFFSET, + XXV_STATRX_BLKLCK_OFFSET, + XXV_STAT_RX_RSFEC_STATUS_OFFSET, + XXV_STAT_RX_FEC_STATUS_OFFSET, + XXV_STAT_TX_RSFEC_STATUS_OFFSET, + XXV_STAT_TX_FLOW_CTRL1_OFFSET, + XXV_STAT_RX_FLOW_CTRL1_OFFSET, + XXV_STAT_AN_STS_OFFSET, + XXV_STAT_AN_LP_STATUS_OFFSET, + XXV_STAT_AN_LINK_CTL_OFFSET, + XXV_STAT_LT_STATUS1_OFFSET, + XXV_STAT_LT_STATUS2_OFFSET, + XXV_STAT_LT_STATUS3_OFFSET, + XXV_STAT_LT_STATUS4_OFFSET, + XXV_STAT_LT_COEFF0_OFFSET, + XXV_STAT_RX_VALID_CTRL_CODE_OFFSET, + XXV_STAT_CORE_SPEED_OFFSET, + XXV_STAT_TSN_OFFSET, + XXV_STAT_GTWIZ_OFFSET, + XXV_STAT_AN_LINK_CTL2_OFFSET, +}; + +/* Option table for setting up XXV Ethernet hardware options */ +static struct axienet_option xxvenet_options[] =3D { + { /* Turn on FCS stripping on receive packets */ + .opt =3D XAE_OPTION_FCS_STRIP, + .reg =3D XXV_RCW1_OFFSET, + .m_or =3D XXV_RCW1_FCS_MASK, + }, { /* Turn on FCS insertion on transmit packets */ + .opt =3D XAE_OPTION_FCS_INSERT, + .reg =3D XXV_TC_OFFSET, + .m_or =3D XXV_TC_FCS_MASK, + }, { /* Enable transmitter */ + .opt =3D XAE_OPTION_TXEN, + .reg =3D XXV_TC_OFFSET, + .m_or =3D XXV_TC_TX_MASK, + }, { /* Enable receiver */ + .opt =3D XAE_OPTION_RXEN, + .reg =3D XXV_RCW1_OFFSET, + .m_or =3D XXV_RCW1_RX_MASK, + }, + {} +}; + +static bool axienet_xxv_ip_has_gtwiz_status(u32 ip_version) +{ + u8 minor =3D FIELD_GET(XXV_MIN_MASK, ip_version); + u8 maj =3D FIELD_GET(XXV_MAJ_MASK, ip_version); + + if (maj =3D=3D XXV_IP_VER_GTWIZ_MAJ_MIN) + return minor >=3D XXV_IP_VER_GTWIZ_MIN_MIN; + return maj > XXV_IP_VER_GTWIZ_MAJ_MIN; +} + +/** + * axienet_xxv_setoptions - Set XXV MAC options from the option table + * @ndev: Pointer to the net_device structure + * @options: Option flags to apply + */ +static void axienet_xxv_setoptions(struct net_device *ndev, u32 options) +{ + struct axienet_local *lp =3D netdev_priv(ndev); + struct axienet_option *tp =3D xxvenet_options; + u32 reg; + + while (tp->opt) { + reg =3D axienet_ior(lp, tp->reg) & ~tp->m_or; + if (options & tp->opt) + reg |=3D tp->m_or; + axienet_iow(lp, tp->reg, reg); + tp++; + } + + lp->options |=3D options; +} + +/** + * axienet_xxv_probe_init - Initialize XXV-specific state at probe time + * @lp: Pointer to the axienet_local structure + */ +static void axienet_xxv_probe_init(struct axienet_local *lp) +{ + lp->xxv_ip_version =3D axienet_ior(lp, XXV_CONFIG_REVISION); +} + +/** + * axienet_xxv_gt_reset - Pulse the XXV GT reset line + * @lp: Pointer to the axienet_local structure + */ +static void axienet_xxv_gt_reset(struct axienet_local *lp) +{ + u32 val; + + /* Reset GT */ + val =3D axienet_ior(lp, XXV_GT_RESET_OFFSET); + val |=3D XXV_GT_RESET_MASK; + axienet_iow(lp, XXV_GT_RESET_OFFSET, val); + /* Allow 1 ms for the GT reset to settle (see timeout note above) */ + usleep_range(1000, 2000); + val =3D axienet_ior(lp, XXV_GT_RESET_OFFSET); + val &=3D ~XXV_GT_RESET_MASK; + axienet_iow(lp, XXV_GT_RESET_OFFSET, val); +} + +/** + * axienet_xxv_poll_link_ready - Wait for XXV GT and PCS block lock + * @ndev: Pointer to the net_device structure + * + * Poll GT wizard reset-done on IP v3.2+, then RX PCS block lock. Block-lo= ck + * failure is logged but not propagated: it depends on a live link partner= and + * reference clock, so an unplugged cable must not fail device bring-up. + * + * Return: 0 on success, or a negative error if GT reset-done times out. + */ +static int axienet_xxv_poll_link_ready(struct net_device *ndev) +{ + struct axienet_local *lp =3D netdev_priv(ndev); + u32 val; + int ret; + + /* Confirm XXV Ethernet is up: on IP v3.2+, wait for GT + * reset-done before further register access, then poll until + * RX PCS block lock is asserted. + */ + if (axienet_xxv_ip_has_gtwiz_status(lp->xxv_ip_version)) { + ret =3D readl_poll_timeout(lp->regs + XXV_STAT_GTWIZ_OFFSET, + val, + (val & XXV_GTWIZ_RESET_DONE) =3D=3D XXV_GTWIZ_RESET_DONE, + XXV_LINK_POLL_INTERVAL_US, + DELAY_OF_ONE_MILLISEC); + if (ret) { + netdev_err(ndev, "XXV MAC GT reset not complete! Cross-check the MAC re= f clock configuration\n"); + return ret; + } + } + + ret =3D readl_poll_timeout(lp->regs + XXV_STATRX_BLKLCK_OFFSET, + val, (val & XXV_RX_BLKLCK_MASK), + XXV_LINK_POLL_INTERVAL_US, + DELAY_OF_ONE_MILLISEC); + if (ret) + netdev_err(ndev, "XXV MAC block lock not complete! Cross-check the MAC r= ef clock configuration\n"); + + return 0; +} + +/** + * axienet_xxv_mac_init - XXV MAC-specific bring-up after the DMA reset + * @ndev: Pointer to the net_device structure + * + * Return: 0 on success or a negative error number otherwise. + */ +static int axienet_xxv_mac_init(struct net_device *ndev) +{ + struct axienet_local *lp =3D netdev_priv(ndev); + int ret; + + ret =3D axienet_xxv_poll_link_ready(ndev); + if (ret) + return ret; + + lp->options |=3D XAE_OPTION_FCS_STRIP; + lp->options |=3D XAE_OPTION_FCS_INSERT; + + return 0; +} + +static void axienet_xxv_phylink_set_capabilities(struct axienet_local *lp, + struct phylink_config *cfg) +{ + u32 core_speed; + bool rtsw; + + core_speed =3D axienet_ior(lp, XXV_STAT_CORE_SPEED_OFFSET); + /* Bit[1:0]: 00=3D25G, 01=3D10G, 10=3Druntime-switchable 25G, + * 11=3Druntime-switchable 10G. A runtime-switchable core can operate at + * either speed, so advertise both; a fixed core advertises only its + * configured speed. + */ + rtsw =3D core_speed & XXV_STAT_CORE_SPEED_RTSW_MASK; + + if (rtsw || (core_speed & XXV_STAT_CORE_SPEED_10G_MASK)) { + cfg->mac_capabilities |=3D MAC_10000FD; + __set_bit(PHY_INTERFACE_MODE_10GBASER, + cfg->supported_interfaces); + } + + if (rtsw || !(core_speed & XXV_STAT_CORE_SPEED_10G_MASK)) { + cfg->mac_capabilities |=3D MAC_25000FD; + __set_bit(PHY_INTERFACE_MODE_25GBASER, + cfg->supported_interfaces); + } +} + +static void axienet_xxv_pcs_get_state(struct phylink_pcs *pcs, + unsigned int neg_mode, + struct phylink_link_state *state) +{ + struct axienet_local *lp =3D pcs_to_axienet_local(pcs); + + state->duplex =3D DUPLEX_FULL; + state->an_complete =3D !!(axienet_ior(lp, XXV_STAT_AN_STS_OFFSET) & + XXV_AN_COMPLETE_MASK); + state->link =3D axienet_ior(lp, XXV_RX_STATUS_REG1) & + XXV_RX_STATUS_MASK; + + if (axienet_ior(lp, XXV_STAT_CORE_SPEED_OFFSET) & + XXV_STAT_CORE_SPEED_10G_MASK) + state->speed =3D SPEED_10000; + else + state->speed =3D SPEED_25000; +} + +static int axienet_xxv_pcs_config(struct phylink_pcs *pcs, unsigned int ne= g_mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + return 0; +} + +static const struct phylink_pcs_ops axienet_xxv_pcs_ops =3D { + .pcs_get_state =3D axienet_xxv_pcs_get_state, + .pcs_config =3D axienet_xxv_pcs_config, +}; + +/** + * axienet_xxv_get_regs - Dump XXV MAC registers for ethtool + * @lp: Pointer to the axienet_local structure + * @data: Buffer for register values (zeroed and sized by the caller) + */ +static void axienet_xxv_get_regs(struct axienet_local *lp, u32 *data) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(axienet_xxv_reg_dump_offsets); i++) + data[i] =3D axienet_ior(lp, axienet_xxv_reg_dump_offsets[i]); +} + +static int axienet_10g25g_clk_init(struct axienet_local *lp) +{ + struct device *dev =3D lp->dev; + int ret; + + /* The register, RX and GT DRP clocks are mandatory for MAC+PCS + * operation, so fetch them as required. + */ + lp->axi_clk =3D devm_clk_get_enabled(dev, "s_axi"); + if (IS_ERR(lp->axi_clk)) + return dev_err_probe(dev, PTR_ERR(lp->axi_clk), + "could not get AXI clock\n"); + + lp->misc_clks[0].id =3D "rx_core"; + lp->misc_clks[1].id =3D "drp"; + + ret =3D devm_clk_bulk_get_enable(dev, 2, lp->misc_clks); + if (ret) + return dev_err_probe(dev, ret, + "could not get/enable XXV clocks\n"); + + return 0; +} + +const struct axienet_config axienet_10g25g_config =3D { + .sw_padding =3D true, + .internal_pcs =3D true, + .regs_n =3D XXV_REGS_N, + .clk_init =3D axienet_10g25g_clk_init, + .setoptions =3D axienet_xxv_setoptions, + .probe_init =3D axienet_xxv_probe_init, + .gt_reset =3D axienet_xxv_gt_reset, + .mac_init =3D axienet_xxv_mac_init, + .get_regs =3D axienet_xxv_get_regs, + .phylink_set_caps =3D axienet_xxv_phylink_set_capabilities, + .pcs_ops =3D &axienet_xxv_pcs_ops, +}; diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.h b/drivers/net= /ethernet/xilinx/xilinx_axienet_xxv.h new file mode 100644 index 000000000000..15a323ee05b2 --- /dev/null +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * XXV (10G/25G) support + * + * Copyright (C) 2026 Advanced Micro Devices, Inc. + */ + +#ifndef XILINX_AXIENET_XXV_H +#define XILINX_AXIENET_XXV_H + +#include + +struct axienet_local; +struct axienet_config; + +#define XXV_REGS_N 46 + +/* XXV MAC Register Definitions */ +#define XXV_GT_RESET_OFFSET 0x00000000 +#define XXV_RESET_OFFSET 0x00000004 +#define XXV_MODE_OFFSET 0x00000008 +#define XXV_TC_OFFSET 0x0000000C +#define XXV_RCW1_OFFSET 0x00000014 +#define XXV_JUM_OFFSET 0x00000018 +#define XXV_VL_LENGTH_OFFSET 0x0000001C +#define XXV_TICKREG_OFFSET 0x00000020 +#define XXV_CONFIG_REVISION 0x00000024 +#define XXV_CONFIG_1588_OFFSET 0x00000038 +#define XXV_CONFIG_TX_FLOW_CTRL1_OFFSET 0x00000040 +#define XXV_CONFIG_RX_FLOW_CTRL1_OFFSET 0x00000094 +#define XXV_CONFIG_RX_FLOW_CTRL2_OFFSET 0x00000098 +#define XXV_CONFIG_RSFEC_OFFSET 0x000000D0 +#define XXV_CONFIG_FEC_OFFSET 0x000000D4 +#define XXV_AN_CTL1_OFFSET 0x000000E0 +#define XXV_AN_CTL2_OFFSET 0x000000E4 +#define XXV_AN_ABILITY_OFFSET 0x000000F8 +#define XXV_LT_CTL1_OFFSET 0x00000100 +#define XXV_SWITCH_CORE_SPEED_OFFSET 0x00000138 +#define XXV_CONFIG_1588_32BIT_OFFSET 0x0000013C +#define XXV_TX_CONFIG_1588_OFFSET 0x00000140 +#define XXV_RX_CONFIG_1588_OFFSET 0x00000144 +#define XXV_GTWIZ_CTRL_OFFSET 0x00000154 +#define XXV_STATRX_STATUS0_OFFSET 0x00000400 +#define XXV_RX_STATUS_REG1 0x00000404 +#define XXV_STATRX_STATUS2_OFFSET 0x00000408 +#define XXV_STATRX_BLKLCK_OFFSET 0x0000040C +#define XXV_STAT_RX_RSFEC_STATUS_OFFSET 0x0000043C +#define XXV_STAT_RX_FEC_STATUS_OFFSET 0x00000448 +#define XXV_STAT_TX_RSFEC_STATUS_OFFSET 0x0000044C +#define XXV_STAT_TX_FLOW_CTRL1_OFFSET 0x00000450 +#define XXV_STAT_RX_FLOW_CTRL1_OFFSET 0x00000454 +#define XXV_STAT_AN_STS_OFFSET 0x00000458 +#define XXV_STAT_AN_LP_STATUS_OFFSET 0x0000045C +#define XXV_STAT_AN_LINK_CTL_OFFSET 0x00000460 +#define XXV_STAT_LT_STATUS1_OFFSET 0x00000464 +#define XXV_STAT_LT_STATUS2_OFFSET 0x00000468 +#define XXV_STAT_LT_STATUS3_OFFSET 0x0000046C +#define XXV_STAT_LT_STATUS4_OFFSET 0x00000470 +#define XXV_STAT_LT_COEFF0_OFFSET 0x00000474 +#define XXV_STAT_RX_VALID_CTRL_CODE_OFFSET 0x00000494 +#define XXV_STAT_CORE_SPEED_OFFSET 0x00000498 +#define XXV_STAT_TSN_OFFSET 0x0000049C +#define XXV_STAT_GTWIZ_OFFSET 0x000004A0 +#define XXV_STAT_AN_LINK_CTL2_OFFSET 0x000009F0 + +/* XXV MAC Register Mask Definitions */ +#define XXV_GT_RESET_MASK BIT(0) +#define XXV_TC_TX_MASK BIT(0) +#define XXV_RCW1_RX_MASK BIT(0) +#define XXV_RCW1_FCS_MASK BIT(1) +#define XXV_TC_FCS_MASK BIT(1) +#define XXV_RX_BLKLCK_MASK BIT(0) +#define XXV_GTWIZ_RESET_DONE (BIT(0) | BIT(1)) +#define XXV_MAJ_MASK GENMASK(7, 0) +#define XXV_MIN_MASK GENMASK(15, 8) +/* IP v3.2+ exposes GT wizard status before other register access (PG210).= */ +#define XXV_IP_VER_GTWIZ_MAJ_MIN 3 +#define XXV_IP_VER_GTWIZ_MIN_MIN 2 +#define XXV_AN_COMPLETE_MASK BIT(2) +#define XXV_STAT_CORE_SPEED_RTSW_MASK BIT(1) +#define XXV_STAT_CORE_SPEED_10G_MASK BIT(0) +#define XXV_RX_STATUS_MASK BIT(0) + +extern const struct axienet_config axienet_10g25g_config; + +#endif /* XILINX_AXIENET_XXV_H */ --=20 2.25.1 From nobody Tue Sep 29 14:54:54 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010040.outbound.protection.outlook.com [52.101.85.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 856C348A8BE; Thu, 6 Aug 2026 18:12:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.85.40 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039966; cv=fail; b=GMzM6ZL6oJCrN14rKDq3bXd2BoFYOytWz3c9RlcNEobitwyaNDAIh7fmY+zcf47B9xgsWQgTZTOGxo7gK/nMCmnCiSU2rm1KVQ0vTjhGidouBSRVar72UeHnVXhcZZ5QKu2z+y2F3aMMjd0MMYJgC4D/Lz4/wcmfjqAqGgmqIT0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039966; c=relaxed/simple; bh=hvtCyXwKAUjo3G8xxB2TQq62cZaiGVgLl0xjYiO5KRs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CeeGzlFXSUBb93GEnGsBJLpxOswJ9aYKIGc3i1RhsUoaPcyQdmIPn1WHbRgIJ1ElukukkW/gK/exJcNvcqPruMwNi9QijSJ04co+4sIkvHsFJLmdTZdP60DpmfBVPpYFsc7C9sis9+WLK8NCyNAiUUjRZ+9cnE4HoKMDBC3SmbI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=iKcofA2n; arc=fail smtp.client-ip=52.101.85.40 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="iKcofA2n" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wK8AYc5Sx0DtHw9huwWEtg01axlrVVH6EURuG3c8uxCcJJ0i+EWA01JGB1d/Whtokph3/m3EQ9d8+vXogFacCHyP9vLEcl2T2Wt1sy5bsTKGEfABfPXFZJjxr7xHO1V+vgRL2NEbS+hrWZbiuZSru0HPnN1No43mhX7QamJR/RF2Q7MNZsPj9nx8eE7V+/Xfjh3U79XgO7t4KijORXzUCqRLG1mUrPjgteKKjC9aFe1wcbo4+//DeekITsYsKkyon5GwDzt1Q5xpvJdtiFiqqlfrNYNLpSHPk6uK0zLRKr6NkIcI6XsK5kHlKz6M+QCpIHX+Rim3BJh5z0G1GJKoVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nU3YM/BXNkpa6X8NBlT3MYByrBCoqp2orspy7P608Qk=; b=u+PAYWdLYxs4sMggfut0QdejHcXN3NTxb9VWfwYWRZzvOXs4ZbUM8BmEpTBr72ZPV0UuWaMBwABm0kMW4dL8VZ2npNzE8gDIFqCEzZwZexuq+QKJblFJinzVej0fi78/U+7yw3l5lov1q/T2MlrEAPurACr581a9eBk6VpJjun4bJc/61u5X8g3oviaU/g5QocCYypf7mh2jclTaxhmmrd6nGfxdh8HLtGnML6DchkdxKAfYBObLF3WVUOTsGo5EdwadEXE3eZrpUj/3EpLp4LCrd3ebIJLPUaZJW5h2aXxJH/J+vwAFT6ln7PJPdFZZcf4d9Ohnko4lu3Rp41I9Tw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lunn.ch smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nU3YM/BXNkpa6X8NBlT3MYByrBCoqp2orspy7P608Qk=; b=iKcofA2nsVAoEYFXM2UzwWVqNgghNhZea6CRRUZwLFBbZFCo6aRm8OkSW03VKm+ofCT0Tab1v9OUJ+BKIiUfAiXaWT/SV23wTSgh6mEary4NMhSr+QLPyVgN9OgLB10sVrBYtUj1wILmouJ/wzYtiKqDtY+4xL+Ztp4HOhkuHys= Received: from CH0PR03CA0218.namprd03.prod.outlook.com (2603:10b6:610:e7::13) by SA3PR12MB8762.namprd12.prod.outlook.com (2603:10b6:806:31f::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.19; Thu, 6 Aug 2026 18:12:40 +0000 Received: from CH3PEPF0000000F.namprd04.prod.outlook.com (2603:10b6:610:e7:cafe::3f) by CH0PR03CA0218.outlook.office365.com (2603:10b6:610:e7::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.20 via Frontend Transport; Thu, 6 Aug 2026 18:12:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by CH3PEPF0000000F.mail.protection.outlook.com (10.167.244.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Thu, 6 Aug 2026 18:12:40 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 13:12:39 -0500 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 6 Aug 2026 13:12:33 -0500 From: Suraj Gupta To: Radhey Shyam Pandey , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Michal Simek , Rob Herring , Brian Masney , Stephen Boyd , Greg Kroah-Hartman , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Danilo Krummrich , "Michael Turquette" , "Rafael J . Wysocki" , Russell King , Shuah Khan , Jonathan Corbet Subject: [PATCH net-next v2 5/7] net: xilinx: axienet: Make axienet_rmon_ranges non-static for reuse Date: Thu, 6 Aug 2026 23:41:51 +0530 Message-ID: <20260806181153.1213996-6-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260806181153.1213996-1-suraj.gupta2@amd.com> References: <20260723123838.125145-1-suraj.gupta2@amd.com> <20260806181153.1213996-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|SA3PR12MB8762:EE_ X-MS-Office365-Filtering-Correlation-Id: 84b613f6-cdcc-44b9-3798-08def3e64dc0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|36860700016|1800799024|82310400026|921020|10067099003|4143699003|11063799006|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: 9Y6wN6NP8cdyWcl6+F08TyZlfKXoxG1RalelC5HqlgU8LOWjMQRBU+6U3CQISPZI6UVIFJX+mQCa4O7kveF2ObHxOLruCfThduAnUD9hpAWjv/M4GoB7BRSnDwuk4PI1l5GpBDx7hxN/CMTgsoNTvYrrd0IyQGHjv4JhfC3Rm9FqzJC8hkZ3V49Xhk3uFLGMYH1G7i3KW+19gNZfzsUzVWRC7EDHNZ4Ohs5chtTTO6rX0W+bBuwOfl3WK1rUyFYp6D3DPsQ3TPJbZjAhTapkbnqUxW5IuVUYdmj3j+M0CVW9zO3GHYHs7PMJKtkixoWoFF98GXrsAm2xMfTlOdASsdhXKx405DHYzGhZHe7pTs0fGwbKb4CVdMgEFqfE7oRhNgy/yzub5BdMPc8InkeY21bQtvBfQY7KD4ofJAbUaTzTFsFm8t+Jq/O2PkElWovUZtqvJS/pKQjxPy7GVW5ve7OyFIe/4Qv+dktamBRsLgUC9Nmtk1EhHtYMNw94vw3ybocQIBOfwAQEXyQZ5aRDJlxpIaeCns9+/Mb3EylS/B7VsdgVdIP7vCHVx5tkfPIa6/OAcpQvSNVd8kUTbB5+l0CKhSmOffo2x9hyUZ1CjvYC7spVH5nM5xMEqTCAst5D4ojxugtxbrQ3RKrnkQHs3rAzI42nBSy1Ntzs6cr8WD6zM96bKlmYT9j3OunnUXOD6R/s4VK1SQPkdANrzQ1zJb/bQIybHJKbh75MfZl344RdKgHjgaY73qTL/uJSJm6j X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(23010399003)(36860700016)(1800799024)(82310400026)(921020)(10067099003)(4143699003)(11063799006)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FeN2hg47TTpU1OfADrY9TUI81+HzOvSUcJifL6xdmOd9Hy5RxcG8g8Oyv11Cg4ujatFyzrekw++zpcGsnWvZB0safrr4mwq67/aMIr00fgBU3KYMHCZGi9ErL+oFKabuKQocJXQXYubGa2bbxDuiUz47qjnJHlygomq5Cx4JjYKPm8jUV2yaVZMMAHZORm9l0Rwx6szP/0PObvIKji3eIIvOH7MpHfJCATcwgIY+qRznRXLTAby6Uy/Sw0ZsPAdf+fVWHUJFd2uAKxVwiIjwA4pnblGiXoOvD1PgKAeRcpdypEP6MBqZPECETpXesN95VTZDE29T/I45UChlpo9u95x9rQxkYAWlvq6Tj1wWcuu+gjwrhcpNKHroTO3rq8kGZp2tNshpzXj3ex4NuNdFJjlGPtdPMEIS0UvCetxbAL5V4tmtR0MSFNaTaPjaDsc1 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 18:12:40.5025 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 84b613f6-cdcc-44b9-3798-08def3e64dc0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8762 Content-Type: text/plain; charset="utf-8" The RMON histogram range table axienet_rmon_ranges[] is MAC-agnostic. Make it non-static and declare it in the shared xilinx_axienet.h so the upcoming XXV RMON callback can reuse the same table instead of duplicating it. Include for the range element type. No functional change intended. Signed-off-by: Suraj Gupta --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 4 ++++ drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index 295a1b835165..a1d15b4797ce 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -10,6 +10,7 @@ #define XILINX_AXIENET_H =20 #include +#include #include #include #include @@ -802,4 +803,7 @@ static inline void axienet_dma_out_addr(struct axienet_= local *lp, off_t reg, int axienet_mdio_setup(struct axienet_local *lp); void axienet_mdio_teardown(struct axienet_local *lp); =20 +/* RMON histogram ranges shared by all MAC types */ +extern const struct ethtool_rmon_hist_range axienet_rmon_ranges[]; + #endif /* XILINX_AXI_ENET_H */ diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 5bffa5b9d0b4..19fe2fd81f3a 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -2498,7 +2498,7 @@ axienet_ethtool_get_eth_ctrl_stats(struct net_device = *dev, } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); } =20 -static const struct ethtool_rmon_hist_range axienet_rmon_ranges[] =3D { +const struct ethtool_rmon_hist_range axienet_rmon_ranges[] =3D { { 64, 64 }, { 65, 127 }, { 128, 255 }, --=20 2.25.1 From nobody Tue Sep 29 14:54:54 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010071.outbound.protection.outlook.com [52.101.85.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 292C937D133; Thu, 6 Aug 2026 18:12:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.85.71 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039981; cv=fail; b=r7WYscm2pHlTob8jzjfUFcJgKKLK5hgmP9rCVcYCZqsHCGGOfLBHJYdc49tjTDgv3RBfH6qqMHTpZ7ZaTYvQuus27CeuMVK12RhLBSD6RvwDdzNSX3AjgEH1TZwQcFsSaqdUskYGcLfuqvcqkDUDYi/qvIMUZig0zSBxPTmygRw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039981; c=relaxed/simple; bh=UmcKNJjcpQo04U88CulqXHN5wLnBfMmTce8MmY16LN8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eCfk7WTC9GpdIJmEuV8WZ+aqsSg7kKEhqv/DCkkvREsYWJ+JiLm+jj27V0UazvoqvBNOrGgM8Mf5Orgp0E6qX/oQgH3PArrjL8E1QKBivOuVVHNBhbigctuxNYZpnTgKm9mKF9RBiJRKiNABCP30DxdS0Po48DCQrQ3hwPfsbs4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=RUmqjZNI; arc=fail smtp.client-ip=52.101.85.71 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="RUmqjZNI" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wocl7IBP+PLOCB2aEa/SV4EO9Nm6aQ/NKPrAHmal5HCg3gqsk3rFSQY0/5pEfw98GFdzxiiHv97RwYKYaD+T9mU2317z5Ho095zCx9V2D/KKTolblnrlPTpBL5xG5JoWjY6b5pSWD6NV488sclS+9Hl8vmIpI03cWHsnMnZuElOBpp8Gljqa/VDzgGwSSZpiNq6rOr99+R90UOTxtzZ7WlA3sjREgQa7X/kHj0SP8ryOFmUbrrgL9zna5f7xOd8Jv/g8eftjl2QWZzaHqCwA1MsNmRCGcbZx64fvKFvtB4ZswbNnzb1g1KKIfBlXi7GBy8luPiX6RfXLVp6Z8WpMaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TmcDYc7H0S6bH9oEkvwHBJoAArjFlGnTjn1pOTdkzQg=; b=oxwzXukNu/iBXTy09I+XkHB2/Q9kE8uNjHHmjtPTmVZxuPU88h1td5mVeVS3LyestkiAgMNy5wG/x6s0CiWLOPDqcSSvPcmqn+LZ5q2KogsixO0ibbixtSBq4XcyOZMP+3WhyfLHeoZqFAGqgKe59b1rXEpDtJ37qH5eYnKfuER5oG01vwfzZecv16n7Bls/P65qgw+1sXizZLzXW4TNVG5UIAjS5UXIokOj+Z9LjSe06YZL4X/uxaPKAP4QD1ftbZdGcodJxk001p3DOyKrvblQwRbt7OxUZAaCG8s6lntHyLfn6fQ7Q8IFSPUQ/+rs6y+2xIRAOvxN87HBLtN9gA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lunn.ch smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TmcDYc7H0S6bH9oEkvwHBJoAArjFlGnTjn1pOTdkzQg=; b=RUmqjZNI1r2qqUedTUxGlEZpyILbt4bD8XpSzFNba03GMml7bJbNsA7FjeHAXImAPx4cC6YnajANjhdjurJkJhPKRZNhZwJ06DHqFQE1z08Jughg8486AXJAFXKTbCXSJ73X/E6BpIWJHR5mk6ZS1RwxTFVNDVPHfP9pP74bW08= Received: from CH5P223CA0009.NAMP223.PROD.OUTLOOK.COM (2603:10b6:610:1f3::7) by DM4PR12MB6256.namprd12.prod.outlook.com (2603:10b6:8:a3::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.20; Thu, 6 Aug 2026 18:12:47 +0000 Received: from CH3PEPF0000000A.namprd04.prod.outlook.com (2603:10b6:610:1f3:cafe::21) by CH5P223CA0009.outlook.office365.com (2603:10b6:610:1f3::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.21 via Frontend Transport; Thu, 6 Aug 2026 18:12:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by CH3PEPF0000000A.mail.protection.outlook.com (10.167.244.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Thu, 6 Aug 2026 18:12:47 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 13:12:46 -0500 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 6 Aug 2026 13:12:40 -0500 From: Suraj Gupta To: Radhey Shyam Pandey , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Michal Simek , Rob Herring , Brian Masney , Stephen Boyd , Greg Kroah-Hartman , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Danilo Krummrich , "Michael Turquette" , "Rafael J . Wysocki" , Russell King , Shuah Khan , Jonathan Corbet Subject: [PATCH net-next v2 6/7] net: xilinx: axienet: Dispatch statistics through axienet_config ops Date: Thu, 6 Aug 2026 23:41:52 +0530 Message-ID: <20260806181153.1213996-7-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260806181153.1213996-1-suraj.gupta2@amd.com> References: <20260723123838.125145-1-suraj.gupta2@amd.com> <20260806181153.1213996-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000A:EE_|DM4PR12MB6256:EE_ X-MS-Office365-Filtering-Correlation-Id: fb0bd34c-7e60-4cc1-75c1-08def3e651fd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|23010399003|36860700016|11063799006|56012099006|10067099003|6133799003|18002099003|22082099003|4143699003|921020; X-Microsoft-Antispam-Message-Info: eOfy4Vf5dgOP658xO3S7uZmgk0KGGT4uLYJYgc6EK0AWfsFW4rCnl0LtJe2s47rUKXUR2APONHimtOS3GUwLj2ewoSdNoxE4hXlLTxykflBcwKebGIiu+YDEmHm+D1TH3/32qEI2Ew62egPBWpAIhWAvYHqx4oZmQ0mFBM1O05WN9EWbDHId49nJOoVxsDTfxJFeiK3brgALi1nJgbDpzv/kWLr8M+DFICsryeBN95s6gZzPoqTS1gBo51KTqUKxmidLD5/28C05L9+u3qmkTcablZRKWNGwumAjW0KTxXLufPAyXe1ale1EoDMOEMzAm3e6tq8YvN/Fsg/rm3fPfSH8xFqOweWsXdIGEEJMPMk3koVkpGd9T+4t/nF3eJ6ToDJUwPP9+8SNOnz0vlb7Vl12I3mc9TuytqRv1bi1c2biQ77aaKE+1CFwk/BkCxgjEfRFR1/TrCSFu6ly67oPP/hhtQXpjtp9ZQY8pa+15TfJ7lg7Xmkup6n1vX2Fp4GfMUUla84SheD/4qW63LsErKTbDRT79PdSP/ucaqwqJNCRXUPRivgyMdqXiOsNuvoCoianfmIapmC76f98KhhjSvgn+cNNIM7xTRhLOvFXwHrOD/DwjiIZJdXvwOcK8U+slyI0LUlPQCGKjekpxwAqs6XawulOkMsP0CYE6BBP3mrw77asJu5FDs1NxVjH79idMj+tTX4sdhXWMIpSiUk2WnImrCM4ck5ewyvtqp9f6yDF1LqnwPnYsaIWmGekQh9v X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(23010399003)(36860700016)(11063799006)(56012099006)(10067099003)(6133799003)(18002099003)(22082099003)(4143699003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hJ51MPoQwQqzaxjrpsnosgxg9WqhwG87rGCGd7GOeJbzRgexDiAlNFJFvInA25kd9tA8u8Jyyw/n+0yvyR3/t2ZcJposYwHUj8dPH6Oj4uYjKsT1CDJ3uXqAZxKwK/oMtAk+tDidwUOQs0+tVyNJhH9hvHRTx/LRkx8nicMIIxKVso0GPalmP1KiPZ/K3EkQfvLkVh+B9DP5IsLnfpUjYk605oQT1L8lw0p3aD0IOpaxPhclY+AHoB7AEH3SWWdWP7Se0rAdQM6FSUrgW85mmgsWigoRX6NVuU5m7uQf/GEUatq+lE+xx2opTqVFz4S2ITuOgM0ZBqlTyAdDlfKwY4xWbxwY5g55sewoRY6kgt9E0Lf11AQ6TsnAX/JaEp1DGgUFNE7q9NGuQMKB7Oi3VXvhpByvBN0phsVVoyKte0zFD5U4656MKZDN7ISUbYAt X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 18:12:47.6149 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb0bd34c-7e60-4cc1-75c1-08def3e651fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6256 Content-Type: text/plain; charset="utf-8" The ndo_get_stats64() and ethtool statistics callbacks read the 1G MAC hardware counters directly. Supporting a second MAC type this way would require an "if (mactype =3D=3D ...)" dispatch branch in each of the eight statistics callbacks. Add statistics operation function pointers to struct axienet_config and route get_stats64, get_ethtool_stats, get_strings, get_sset_count, get_pause_stats, get_eth_mac_stats, get_eth_ctrl_stats and get_rmon_stats through them. Factor the existing 1G counter reads into axienet_1g_*() helpers and populate axienet_1g_config with them. A NULL op means the MAC does not expose that statistics group, so a MAC without control-frame counters simply leaves get_eth_ctrl_stats unset instead of open-coding the special case in the callback. No functional change intended. Signed-off-by: Suraj Gupta --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 23 +++ .../net/ethernet/xilinx/xilinx_axienet_main.c | 171 +++++++++++++----- 2 files changed, 146 insertions(+), 48 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index a1d15b4797ce..f286c428343f 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -658,6 +658,15 @@ struct axienet_local { * @phylink_set_caps: Callback to set phylink MAC capabilities * @pcs_ops: phylink PCS operations for this MAC, or NULL if unused * @stats_update: Callback to latch/accumulate the periodic MAC counters + * @get_stats64: Callback to read MAC counters into rtnl_link_stats64 + * @get_ethtool_stats: Callback to read MAC counters for ethtool -S + * @get_strings: Callback to fill the ethtool -S statistic name strings + * @get_sset_count: Callback returning the number of ethtool -S statistics + * @get_pause_stats: Callback to read MAC pause-frame counters + * @get_eth_mac_stats: Callback to read IEEE 802.3 MAC counters + * @get_eth_ctrl_stats: Callback to read MAC-control frame counters, or NU= LL + * if the MAC exposes no control-frame counters + * @get_rmon_stats: Callback to read RMON counters and histogram ranges */ struct axienet_config { bool mdio; @@ -683,6 +692,20 @@ struct axienet_config { struct phylink_config *config); const struct phylink_pcs_ops *pcs_ops; void (*stats_update)(struct axienet_local *lp); + void (*get_stats64)(struct axienet_local *lp, + struct rtnl_link_stats64 *stats); + void (*get_ethtool_stats)(struct axienet_local *lp, u64 *data); + void (*get_strings)(u8 *data); + int (*get_sset_count)(void); + void (*get_pause_stats)(struct axienet_local *lp, + struct ethtool_pause_stats *pause_stats); + void (*get_eth_mac_stats)(struct axienet_local *lp, + struct ethtool_eth_mac_stats *mac_stats); + void (*get_eth_ctrl_stats)(struct axienet_local *lp, + struct ethtool_eth_ctrl_stats *ctrl_stats); + void (*get_rmon_stats)(struct axienet_local *lp, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges); }; =20 static inline struct axienet_local *pcs_to_axienet_local(struct phylink_pc= s *pcs) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 19fe2fd81f3a..198de353372a 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -1874,29 +1874,11 @@ static int axienet_ioctl(struct net_device *dev, st= ruct ifreq *rq, int cmd) return phylink_mii_ioctl(lp->phylink, rq, cmd); } =20 -static void -axienet_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stat= s) +static void axienet_1g_get_stats64(struct axienet_local *lp, + struct rtnl_link_stats64 *stats) { - struct axienet_local *lp =3D netdev_priv(dev); unsigned int start; =20 - netdev_stats_to_stats64(stats, &dev->stats); - - do { - start =3D u64_stats_fetch_begin(&lp->rx_stat_sync); - stats->rx_packets =3D u64_stats_read(&lp->rx_packets); - stats->rx_bytes =3D u64_stats_read(&lp->rx_bytes); - } while (u64_stats_fetch_retry(&lp->rx_stat_sync, start)); - - do { - start =3D u64_stats_fetch_begin(&lp->tx_stat_sync); - stats->tx_packets =3D u64_stats_read(&lp->tx_packets); - stats->tx_bytes =3D u64_stats_read(&lp->tx_bytes); - } while (u64_stats_fetch_retry(&lp->tx_stat_sync, start)); - - if (!(lp->features & XAE_FEATURE_STATS)) - return; - do { start =3D read_seqcount_begin(&lp->hw_stats_seqcount); stats->rx_length_errors =3D @@ -1924,6 +1906,33 @@ axienet_get_stats64(struct net_device *dev, struct r= tnl_link_stats64 *stats) } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); } =20 +static void +axienet_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stat= s) +{ + struct axienet_local *lp =3D netdev_priv(dev); + unsigned int start; + + netdev_stats_to_stats64(stats, &dev->stats); + + do { + start =3D u64_stats_fetch_begin(&lp->rx_stat_sync); + stats->rx_packets =3D u64_stats_read(&lp->rx_packets); + stats->rx_bytes =3D u64_stats_read(&lp->rx_bytes); + } while (u64_stats_fetch_retry(&lp->rx_stat_sync, start)); + + do { + start =3D u64_stats_fetch_begin(&lp->tx_stat_sync); + stats->tx_packets =3D u64_stats_read(&lp->tx_packets); + stats->tx_bytes =3D u64_stats_read(&lp->tx_bytes); + } while (u64_stats_fetch_retry(&lp->tx_stat_sync, start)); + + if (!(lp->features & XAE_FEATURE_STATS)) + return; + + if (lp->axienet_config->get_stats64) + lp->axienet_config->get_stats64(lp, stats); +} + static const struct net_device_ops axienet_netdev_ops =3D { .ndo_open =3D axienet_open, .ndo_stop =3D axienet_stop, @@ -2356,11 +2365,8 @@ static int axienet_ethtools_nway_reset(struct net_de= vice *dev) return phylink_ethtool_nway_reset(lp->phylink); } =20 -static void axienet_ethtools_get_ethtool_stats(struct net_device *dev, - struct ethtool_stats *stats, - u64 *data) +static void axienet_1g_get_ethtool_stats(struct axienet_local *lp, u64 *da= ta) { - struct axienet_local *lp =3D netdev_priv(dev); unsigned int start; =20 do { @@ -2377,6 +2383,17 @@ static void axienet_ethtools_get_ethtool_stats(struc= t net_device *dev, } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); } =20 +static void axienet_ethtools_get_ethtool_stats(struct net_device *dev, + struct ethtool_stats *stats, + u64 *data) +{ + struct axienet_local *lp =3D netdev_priv(dev); + + if (lp->features & XAE_FEATURE_STATS && + lp->axienet_config->get_ethtool_stats) + lp->axienet_config->get_ethtool_stats(lp, data); +} + static const char axienet_ethtool_stats_strings[][ETH_GSTRING_LEN] =3D { "Received bytes", "Transmitted bytes", @@ -2389,12 +2406,26 @@ static const char axienet_ethtool_stats_strings[][E= TH_GSTRING_LEN] =3D { "User Defined Counter 2", }; =20 +static void axienet_1g_get_strings(u8 *data) +{ + memcpy(data, axienet_ethtool_stats_strings, + sizeof(axienet_ethtool_stats_strings)); +} + +static int axienet_1g_get_sset_count(void) +{ + return ARRAY_SIZE(axienet_ethtool_stats_strings); +} + static void axienet_ethtools_get_strings(struct net_device *dev, u32 strin= gset, u8 *data) { + struct axienet_local *lp =3D netdev_priv(dev); + switch (stringset) { case ETH_SS_STATS: - memcpy(data, axienet_ethtool_stats_strings, - sizeof(axienet_ethtool_stats_strings)); + if (lp->features & XAE_FEATURE_STATS && + lp->axienet_config->get_strings) + lp->axienet_config->get_strings(data); break; } } @@ -2405,24 +2436,20 @@ static int axienet_ethtools_get_sset_count(struct n= et_device *dev, int sset) =20 switch (sset) { case ETH_SS_STATS: - if (lp->features & XAE_FEATURE_STATS) - return ARRAY_SIZE(axienet_ethtool_stats_strings); + if (lp->features & XAE_FEATURE_STATS && + lp->axienet_config->get_sset_count) + return lp->axienet_config->get_sset_count(); fallthrough; default: return -EOPNOTSUPP; } } =20 -static void -axienet_ethtools_get_pause_stats(struct net_device *dev, - struct ethtool_pause_stats *pause_stats) +static void axienet_1g_get_pause_stats(struct axienet_local *lp, + struct ethtool_pause_stats *pause_stats) { - struct axienet_local *lp =3D netdev_priv(dev); unsigned int start; =20 - if (!(lp->features & XAE_FEATURE_STATS)) - return; - do { start =3D read_seqcount_begin(&lp->hw_stats_seqcount); pause_stats->tx_pause_frames =3D @@ -2433,15 +2460,23 @@ axienet_ethtools_get_pause_stats(struct net_device = *dev, } =20 static void -axienet_ethtool_get_eth_mac_stats(struct net_device *dev, - struct ethtool_eth_mac_stats *mac_stats) +axienet_ethtools_get_pause_stats(struct net_device *dev, + struct ethtool_pause_stats *pause_stats) { struct axienet_local *lp =3D netdev_priv(dev); - unsigned int start; =20 if (!(lp->features & XAE_FEATURE_STATS)) return; =20 + if (lp->axienet_config->get_pause_stats) + lp->axienet_config->get_pause_stats(lp, pause_stats); +} + +static void axienet_1g_get_eth_mac_stats(struct axienet_local *lp, + struct ethtool_eth_mac_stats *mac_stats) +{ + unsigned int start; + do { start =3D read_seqcount_begin(&lp->hw_stats_seqcount); mac_stats->FramesTransmittedOK =3D @@ -2478,15 +2513,24 @@ axienet_ethtool_get_eth_mac_stats(struct net_device= *dev, } =20 static void -axienet_ethtool_get_eth_ctrl_stats(struct net_device *dev, - struct ethtool_eth_ctrl_stats *ctrl_stats) +axienet_ethtool_get_eth_mac_stats(struct net_device *dev, + struct ethtool_eth_mac_stats *mac_stats) { struct axienet_local *lp =3D netdev_priv(dev); - unsigned int start; =20 if (!(lp->features & XAE_FEATURE_STATS)) return; =20 + if (lp->axienet_config->get_eth_mac_stats) + lp->axienet_config->get_eth_mac_stats(lp, mac_stats); +} + +static void +axienet_1g_get_eth_ctrl_stats(struct axienet_local *lp, + struct ethtool_eth_ctrl_stats *ctrl_stats) +{ + unsigned int start; + do { start =3D read_seqcount_begin(&lp->hw_stats_seqcount); ctrl_stats->MACControlFramesTransmitted =3D @@ -2498,6 +2542,19 @@ axienet_ethtool_get_eth_ctrl_stats(struct net_device= *dev, } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); } =20 +static void +axienet_ethtool_get_eth_ctrl_stats(struct net_device *dev, + struct ethtool_eth_ctrl_stats *ctrl_stats) +{ + struct axienet_local *lp =3D netdev_priv(dev); + + if (!(lp->features & XAE_FEATURE_STATS)) + return; + + if (lp->axienet_config->get_eth_ctrl_stats) + lp->axienet_config->get_eth_ctrl_stats(lp, ctrl_stats); +} + const struct ethtool_rmon_hist_range axienet_rmon_ranges[] =3D { { 64, 64 }, { 65, 127 }, @@ -2510,16 +2567,12 @@ const struct ethtool_rmon_hist_range axienet_rmon_r= anges[] =3D { }; =20 static void -axienet_ethtool_get_rmon_stats(struct net_device *dev, - struct ethtool_rmon_stats *rmon_stats, - const struct ethtool_rmon_hist_range **ranges) +axienet_1g_get_rmon_stats(struct axienet_local *lp, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges) { - struct axienet_local *lp =3D netdev_priv(dev); unsigned int start; =20 - if (!(lp->features & XAE_FEATURE_STATS)) - return; - do { start =3D read_seqcount_begin(&lp->hw_stats_seqcount); rmon_stats->undersize_pkts =3D @@ -2563,6 +2616,20 @@ axienet_ethtool_get_rmon_stats(struct net_device *de= v, *ranges =3D axienet_rmon_ranges; } =20 +static void +axienet_ethtool_get_rmon_stats(struct net_device *dev, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges) +{ + struct axienet_local *lp =3D netdev_priv(dev); + + if (!(lp->features & XAE_FEATURE_STATS)) + return; + + if (lp->axienet_config->get_rmon_stats) + lp->axienet_config->get_rmon_stats(lp, rmon_stats, ranges); +} + static const struct ethtool_ops axienet_ethtool_ops =3D { .supported_coalesce_params =3D ETHTOOL_COALESCE_MAX_FRAMES | ETHTOOL_COALESCE_USECS | @@ -2914,6 +2981,14 @@ static const struct axienet_config axienet_1g_config= =3D { .phylink_set_caps =3D axienet_1g_phylink_set_caps, .pcs_ops =3D &axienet_pcs_ops, .stats_update =3D axienet_1g_stats_update, + .get_stats64 =3D axienet_1g_get_stats64, + .get_ethtool_stats =3D axienet_1g_get_ethtool_stats, + .get_strings =3D axienet_1g_get_strings, + .get_sset_count =3D axienet_1g_get_sset_count, + .get_pause_stats =3D axienet_1g_get_pause_stats, + .get_eth_mac_stats =3D axienet_1g_get_eth_mac_stats, + .get_eth_ctrl_stats =3D axienet_1g_get_eth_ctrl_stats, + .get_rmon_stats =3D axienet_1g_get_rmon_stats, }; =20 /* Match table for of_platform binding */ --=20 2.25.1 From nobody Tue Sep 29 14:54:54 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011051.outbound.protection.outlook.com [52.101.62.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0627C48C3F2; Thu, 6 Aug 2026 18:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039988; cv=fail; b=A8B8nIsK5artSIyEuVavDCd88Oxnarwm7hfmsH+X4bkRmRkGrZ21veQqqO9tyDvwWDhBUMo4RRQhU+75Z/hjaWSss91oX+pM0IKTWUJs4KjFBCnKTiWo7Z3KbTxfdIUn88sONfxdNFdAiMc7yNfyrAVaXp4PrljgHB3BAHiReZ8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786039988; c=relaxed/simple; bh=9HQbGCzqCEH8zZJwsZjRiVlgQl4G1ILPceUZ6TkfOSo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OcSQal3N/fLj8ibix5yHSphzTEPx/yLYlOwAer9pamPkDoUiiFtItk/9tA02BDVoyPiy32O4Eeovgba5bhqVMYmHEqDGVm+/pIMc7rjaDoDd13qQBfsoNOZr3sxvqeQpS4tugwW0TX0tOR/sIork4lGJ+uiApv428IcmBdiGWJM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=Tn2keIoN; arc=fail smtp.client-ip=52.101.62.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="Tn2keIoN" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=kOKWYWdnbDf8rBq2+CUnDcbrmim5BdJm83LMuWr+Pttzx1fp+OqGnQBviQDep/yX9+HGrjjbYw4uQ2iYExCny1euXWf8XJNlfyLpe9GZ+f7muRXy811EuB4lSc6NV3hlfdTOxrEHgrOEw/cwiWmgDmayfeigpK4xMdj9b+jSMbgJYwks1+4dVgddLfdYeCWJkncEKwmkhpDGjng0mhWpyJ71M2628iDkHRM2a9uBEMjHmxnuzNqayr78sbU7S2w+dL9JxTFl47/NGhH9ktwbXVAGgDXV61ruajvQa9R08Jf3AAdahSLCQJzBwrxbmgORUAvOUaHNCpzG7Qtl1u12BQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=47qshhibRdpFrge1emmnrmtk1pk2XpWdHCDeUMxCOdo=; b=pAT5l0H/dl8PsCVvtbGoQYuO8gGcUteKw5q4WLNEXzU+brLzjVIsgb81kEKITcS4+aCpl6ahU8P/N022AIX2vdbReUIzoeEf3lm39LlXue2WWa0jr4GoFVAtN06Z+yRh1/O6HNGeGLirr8sq/GmnAWiT/O2h8XhmE46GUaXYFllNLGZcJcqucrWlT+f/dUPbhRTtA3npcYyE3W+zx7eLOzZpuEMqwevaL8PwQO0rDhxX4BTeIPfG9zqnxu1r8ZHyN/VZgmM3pgpk6QQczbgfYhq5lzK5oeB6BkW+RfmufuL2aibQaVUAbDfueiDZEaw8q1u0dw8UQEbfN+5VhHYG7A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lunn.ch smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=47qshhibRdpFrge1emmnrmtk1pk2XpWdHCDeUMxCOdo=; b=Tn2keIoNrkEP2KwS7rkRi72gF4O2ACYEE8YSg3zIr9hhlklxFt/C2bcH39TnV0tCc2BijWwQVm1lekEZlHk8Kgfokr7NpVvt7fflKVi26o6/nfS1LN40oeWxYGPzOKhk0gTBehnTQgQoJJlqYew35fQ/fAi79Px14rYTziH4+M4= Received: from BN0PR07CA0016.namprd07.prod.outlook.com (2603:10b6:408:141::21) by CY8PR12MB7146.namprd12.prod.outlook.com (2603:10b6:930:5e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.16; Thu, 6 Aug 2026 18:12:54 +0000 Received: from BN1PEPF0000467F.namprd03.prod.outlook.com (2603:10b6:408:141:cafe::2) by BN0PR07CA0016.outlook.office365.com (2603:10b6:408:141::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.20 via Frontend Transport; Thu, 6 Aug 2026 18:12:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN1PEPF0000467F.mail.protection.outlook.com (10.167.243.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Thu, 6 Aug 2026 18:12:54 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 6 Aug 2026 13:12:53 -0500 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 6 Aug 2026 13:12:47 -0500 From: Suraj Gupta To: Radhey Shyam Pandey , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Michal Simek , Rob Herring , Brian Masney , Stephen Boyd , Greg Kroah-Hartman , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Danilo Krummrich , "Michael Turquette" , "Rafael J . Wysocki" , Russell King , Shuah Khan , Jonathan Corbet Subject: [PATCH net-next v2 7/7] net: xilinx: axienet: Add statistics support for XXV ethernet Date: Thu, 6 Aug 2026 23:41:53 +0530 Message-ID: <20260806181153.1213996-8-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260806181153.1213996-1-suraj.gupta2@amd.com> References: <20260723123838.125145-1-suraj.gupta2@amd.com> <20260806181153.1213996-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|CY8PR12MB7146:EE_ X-MS-Office365-Filtering-Correlation-Id: bad58ba8-80ed-4f04-8118-08def3e655dd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|23010399003|376014|7416014|22082099003|18002099003|11063799006|4143699003|3023799007|6133799003|10067099003|10063799003|56012099006|921020; X-Microsoft-Antispam-Message-Info: 5cuTeRaL9EkxCy7O/Az/cYM47cKZycyCkvBWhuRjcvJyFrJANu0N/CcREA7hYafht0oaYywsoaF6GABnEna2eh9+Khp1eOUJmz4RJehhBf9Tccyf4Ax7UZydQv06YBPc2fgp00QcmrxQrzPY6rtDxiyiCYRQonk9D3JQLfonc0+4cpdorvKgRGS/a7o4PFZEI053UaAUpJL4oAiQ8r9YeSRC5BWKAWu72pgL6hPuCyf9pPFCkfoOSJl2keMfrTQUDD9emrIpXrvEJZg5ANqxtNUx7rd+hHJPEIYXCDLh1epbLgP46OMp2PAy71l3GltKPRq+fft0AMj/woau6M2VD9GDOae5P58Y9BDgxJy0q87YLks2lW8mHbnL3XancZI9ZI5ZwB9HOFXIrzs3Z35xpN2AOpq4xgtfYpy6DnnHNHgAFZDg88BE6kzO5ZDBcTnfSlfbQpmcdGX83GRaDxeZliyB3k7U79cldWqx+bJvDg2p2aDYHsmJA1lFHs5T4xKGeKLiwmKgUx0gcn1s1pC2RUJ2ANfTmAMRReB0ZvC0va/XosXWZ8gclovjWX9ImETPn9K/AOBabIw/otkCYife5kEKNUmxObCDoz9GpC/j2TpVZQ69s9kfa9+IEqf/02Ak03EE6ZlNueKIac/KuVxqB1asiMThWjvDkjkXnEgSiDEpzvP69C5GqjRs4q5ICmbevJogcOnoAl1ENi9aEqJvQhSnGorBZed/cUaEWnRskGTB+VFI3Z/ErfKZvvYxY23G X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(23010399003)(376014)(7416014)(22082099003)(18002099003)(11063799006)(4143699003)(3023799007)(6133799003)(10067099003)(10063799003)(56012099006)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dZas51XTc3H0pJXTnm9eJ/hycuzgrLbc+Sj6s2id9Y0kooLwfYkFPdxQZo+KaCge0FP558GHs/HtTqqz1QcqwI1PHKNBfUTozF+pQOtuLRfod62mNC1rBoD1axxJUmQplZTycb1yZ/MVSSV5w4bCog9DlmDB4vKyi1IYnCefa36UihKSfc+KxCQEysIx7bERvNpIXUTOL16jiyMK3TfbqsTm5+uSqNta80SmYwekJ3al+Em+5zQR1m/Wn1pZRMoiRxT+NREPNLuALqsRNNZHsfkZKhhP6AVvJFNTJa3KGuQugnT8nMvICIXVuULRGhEZMhuWDwxL7qCeQ5+43+QKaKDwGrCwEMKlk4Ov1mpKccnyiYQ73CWsdY1V1BSQXTP7H4BbNhquWUOiNUkr2F7n94lt3OpbgwlR+nha7iFCfSZMjHtfrvv3V+5QV86qvo7T X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 18:12:54.1285 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bad58ba8-80ed-4f04-8118-08def3e655dd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7146 Content-Type: text/plain; charset="utf-8" The XXV ethernet exposes a dedicated statistics block whose counters are clear-on-tick (PG210): writing TICK_REG latches the internal accumulators into the readable registers and clears them, so each post-TICK read yields the count for the interval since the previous TICK. Software accumulates those intervals, so no last-counter delta (as used by the 1G MAC) is needed. Feed both ndo_get_stats64() and the ethtool statistics (-S, pause, MAC and RMON) from this accumulator path through the axienet_config statistics ops. MAC control statistics stay unsupported as the hardware exposes no matching counters. Signed-off-by: Suraj Gupta --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 + .../net/ethernet/xilinx/xilinx_axienet_main.c | 22 +- .../net/ethernet/xilinx/xilinx_axienet_xxv.c | 266 ++++++++++++++++++ .../net/ethernet/xilinx/xilinx_axienet_xxv.h | 55 ++++ 4 files changed, 343 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index f286c428343f..2ea086fc4dc3 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -549,6 +549,7 @@ struct skbuf_dma_descriptor { * @rx_ring_head: RX skb ring buffer head index. * @rx_ring_tail: RX skb ring buffer tail index. * @xxv_ip_version: XXV IP version. + * @xxv_stat_base: Software accumulators for the XXV clear-on-tick counter= s. * @axienet_config: MAC-type specific configuration and operations. */ struct axienet_local { @@ -603,6 +604,7 @@ struct axienet_local { =20 u64 hw_stat_base[STAT_COUNT]; u32 hw_last_counter[STAT_COUNT]; + u64 xxv_stat_base[XXV_STAT_COUNT]; seqcount_mutex_t hw_stats_seqcount; struct mutex stats_lock; struct delayed_work stats_work; diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 198de353372a..e693f4a49f20 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -592,7 +592,11 @@ static void axienet_refresh_stats(struct work_struct *= work) mutex_unlock(&lp->stats_lock); } =20 - /* Just less than 2^32 bytes at 2.5 GBit/s */ + /* Re-arm the poll before any counter can overflow between updates: the + * 1G byte counter reaches just under 2^32 in this interval at 2.5 Gbit/s, + * and the XXV internal accumulators must be latched (via TICK in + * axienet_xxv_stats_update()) before they saturate at line rate. + */ schedule_delayed_work(&lp->stats_work, 13 * HZ); } =20 @@ -601,7 +605,16 @@ static int __axienet_device_reset(struct axienet_local= *lp) u32 value; int ret; =20 - /* Save statistics counters in case they will be reset */ + /* Save statistics counters in case they will be reset. + * + * The XAE_FEATURE_STATS blocks in this function read the TEMAC + * statistics registers at XAE_STATS_OFFSET, i.e. they assume the 1G + * counter layout. This is safe because __axienet_device_reset() is + * only reached on the legacy (non-dmaengine) DMA path, which the + * legacy_dma capability restricts to the 1G MAC. MACs that use their + * own statistics mechanism (e.g. XXV, which is dmaengine-only) never + * execute this path. + */ mutex_lock(&lp->stats_lock); if (lp->features & XAE_FEATURE_STATS) axienet_stats_update(lp, true); @@ -1777,6 +1790,11 @@ static int axienet_stop(struct net_device *ndev) =20 cancel_work_sync(&lp->rx_dim.work); cancel_delayed_work_sync(&lp->stats_work); + if (lp->axienet_config->stats_update) { + mutex_lock(&lp->stats_lock); + lp->axienet_config->stats_update(lp); + mutex_unlock(&lp->stats_lock); + } =20 phylink_stop(lp->phylink); phylink_disconnect_phy(lp->phylink); diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.c b/drivers/net= /ethernet/xilinx/xilinx_axienet_xxv.c index 46b48a773c15..dbc9c21b104a 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.c @@ -8,9 +8,11 @@ #include #include #include +#include #include #include #include +#include =20 #include "xilinx_axienet.h" #include "xilinx_axienet_xxv.h" @@ -95,6 +97,69 @@ static struct axienet_option xxvenet_options[] =3D { {} }; =20 +/* PG210 statistics-block offsets indexed by enum xxv_stat. Each entry is + * the 32-bit LSB register address; the corresponding MSB is at +4. + */ +static const u32 axienet_xxv_stat_offsets[XXV_STAT_COUNT] =3D { + [XXV_STAT_RX_TOTAL_PACKETS] =3D XXV_STAT_RX_TOTAL_PACKETS_OFFSET, + [XXV_STAT_RX_TOTAL_GOOD_PACKETS] =3D XXV_STAT_RX_TOTAL_GOOD_PACKETS_OFFSE= T, + [XXV_STAT_RX_TOTAL_BYTES] =3D XXV_STAT_RX_TOTAL_BYTES_OFFSET, + [XXV_STAT_RX_TOTAL_GOOD_BYTES] =3D XXV_STAT_RX_TOTAL_GOOD_BYTES_OFFSET, + [XXV_STAT_RX_BAD_FCS] =3D XXV_STAT_RX_BAD_FCS_OFFSET, + [XXV_STAT_RX_INRANGEERR] =3D XXV_STAT_RX_INRANGEERR_OFFSET, + [XXV_STAT_RX_MULTICAST] =3D XXV_STAT_RX_MULTICAST_OFFSET, + [XXV_STAT_RX_BROADCAST] =3D XXV_STAT_RX_BROADCAST_OFFSET, + [XXV_STAT_RX_UNDERSIZE] =3D XXV_STAT_RX_UNDERSIZE_OFFSET, + [XXV_STAT_RX_FRAGMENT] =3D XXV_STAT_RX_FRAGMENT_OFFSET, + [XXV_STAT_RX_JABBER] =3D XXV_STAT_RX_JABBER_OFFSET, + [XXV_STAT_RX_OVERSIZE] =3D XXV_STAT_RX_OVERSIZE_OFFSET, + [XXV_STAT_RX_PAUSE] =3D XXV_STAT_RX_PAUSE_OFFSET, + [XXV_STAT_TX_TOTAL_PACKETS] =3D XXV_STAT_TX_TOTAL_PACKETS_OFFSET, + [XXV_STAT_TX_TOTAL_GOOD_PACKETS] =3D XXV_STAT_TX_TOTAL_GOOD_PACKETS_OFFSE= T, + [XXV_STAT_TX_TOTAL_BYTES] =3D XXV_STAT_TX_TOTAL_BYTES_OFFSET, + [XXV_STAT_TX_TOTAL_GOOD_BYTES] =3D XXV_STAT_TX_TOTAL_GOOD_BYTES_OFFSET, + [XXV_STAT_TX_BAD_FCS] =3D XXV_STAT_TX_BAD_FCS_OFFSET, + [XXV_STAT_TX_FRAME_ERROR] =3D XXV_STAT_TX_FRAME_ERROR_OFFSET, + [XXV_STAT_TX_MULTICAST] =3D XXV_STAT_TX_MULTICAST_OFFSET, + [XXV_STAT_TX_BROADCAST] =3D XXV_STAT_TX_BROADCAST_OFFSET, + [XXV_STAT_TX_PAUSE] =3D XXV_STAT_TX_PAUSE_OFFSET, +}; + +/* XXV (PG210) counters exposed via ethtool -S. Only counters that have no + * standard uAPI are listed here; the totals include errored frames, so th= ey + * are distinct from the good-frame counts in rtnl_link_stats64 and the + * IEEE MAC statistics. Every other XXV counter is reported through the + * dedicated stats64, pause, MAC and RMON callbacks instead. + */ +static const enum xxv_stat axienet_xxv_priv_stats[] =3D { + XXV_STAT_RX_TOTAL_PACKETS, + XXV_STAT_RX_TOTAL_BYTES, + XXV_STAT_TX_TOTAL_PACKETS, + XXV_STAT_TX_TOTAL_BYTES, + XXV_STAT_TX_BAD_FCS, + XXV_STAT_TX_FRAME_ERROR, +}; + +static const char axienet_xxv_ethtool_stats_strings[][ETH_GSTRING_LEN] =3D= { + "RX Total Packets", + "RX Total Bytes", + "TX Total Packets", + "TX Total Bytes", + "TX Bad FCS", + "TX Frame Error", +}; + +static u64 axienet_xxv_read_counter(struct axienet_local *lp, enum xxv_sta= t stat) +{ + u32 off =3D axienet_xxv_stat_offsets[stat]; + u32 lsb, msb; + + lsb =3D axienet_ior(lp, off); + msb =3D axienet_ior(lp, off + XXV_STAT_MSB_OFFSET); + + return ((u64)msb << 32) | lsb; +} + static bool axienet_xxv_ip_has_gtwiz_status(u32 ip_version) { u8 minor =3D FIELD_GET(XXV_MIN_MASK, ip_version); @@ -134,6 +199,7 @@ static void axienet_xxv_setoptions(struct net_device *n= dev, u32 options) static void axienet_xxv_probe_init(struct axienet_local *lp) { lp->xxv_ip_version =3D axienet_ior(lp, XXV_CONFIG_REVISION); + lp->features |=3D XAE_FEATURE_STATS; } =20 /** @@ -314,6 +380,198 @@ static int axienet_10g25g_clk_init(struct axienet_loc= al *lp) return 0; } =20 +/** + * axienet_xxv_stats_update - Latch and accumulate XXV hardware counters + * @lp: Pointer to the axienet_local structure + * + * The XXV statistics counters are clear-on-tick (PG210): writing TICK_REG + * latches the internal accumulators into the readable STAT_*_LSB/MSB regi= sters + * and clears the internal accumulators. Each post-TICK read therefore ret= urns + * the count for the interval since the previous TICK, so software accumul= ates + * those intervals into lp->xxv_stat_base. A last-counter delta (as used b= y the + * free-running 1G MAC path) is not needed. + */ +static void axienet_xxv_stats_update(struct axienet_local *lp) +{ + u64 counter[XXV_STAT_COUNT]; + enum xxv_stat stat; + + /* Latch the clear-on-tick snapshot and read the counters outside the + * seqcount write section, so only the accumulator updates run inside it + * and the reader retry window stays short. + */ + axienet_iow(lp, XXV_TICKREG_OFFSET, XXV_TICKREG_STATEN_MASK); + for (stat =3D 0; stat < XXV_STAT_COUNT; stat++) + counter[stat] =3D axienet_xxv_read_counter(lp, stat); + + write_seqcount_begin(&lp->hw_stats_seqcount); + for (stat =3D 0; stat < XXV_STAT_COUNT; stat++) + lp->xxv_stat_base[stat] +=3D counter[stat]; + write_seqcount_end(&lp->hw_stats_seqcount); +} + +/** + * axienet_xxv_get_stats64 - Fill rtnl_link_stats64 from XXV counters + * @lp: Pointer to the axienet_local structure + * @stats: Output rtnl_link_stats64 structure to populate + */ +static void axienet_xxv_get_stats64(struct axienet_local *lp, + struct rtnl_link_stats64 *stats) +{ + unsigned int start; + u64 tx_hw_errors; + + do { + start =3D read_seqcount_begin(&lp->hw_stats_seqcount); + stats->rx_crc_errors =3D lp->xxv_stat_base[XXV_STAT_RX_BAD_FCS]; + /* Both in-range length errors and frame-too-long (oversize) + * frames are IEEE 802.3 length errors, so fold them together + * into rx_length_errors; rx_over_errors is reserved for receiver + * FIFO/ring overflow, which the XXV MAC does not expose. + */ + stats->rx_length_errors =3D + lp->xxv_stat_base[XXV_STAT_RX_INRANGEERR] + + lp->xxv_stat_base[XXV_STAT_RX_OVERSIZE]; + stats->rx_errors =3D lp->xxv_stat_base[XXV_STAT_RX_UNDERSIZE] + + lp->xxv_stat_base[XXV_STAT_RX_FRAGMENT] + + lp->xxv_stat_base[XXV_STAT_RX_JABBER] + + stats->rx_crc_errors + + stats->rx_length_errors; + stats->multicast =3D lp->xxv_stat_base[XXV_STAT_RX_MULTICAST]; + tx_hw_errors =3D lp->xxv_stat_base[XXV_STAT_TX_BAD_FCS] + + lp->xxv_stat_base[XXV_STAT_TX_FRAME_ERROR]; + } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); + + /* Fold the HW TX error count into the software tx_errors seeded from + * dev->stats by the caller. The XXV xmit path bumps dev->stats.tx_errors + * for frames dropped on pad failure before they reach the MAC, while the + * HW counters only cover frames the MAC actually transmitted; the two are + * disjoint. This runs once, outside the seqcount retry loop, so a racing + * stats update cannot make the accumulation re-add on retry. + */ + stats->tx_errors +=3D tx_hw_errors; +} + +/** + * axienet_xxv_get_ethtool_stats - Copy XXV counters for ethtool -S + * @lp: Pointer to the axienet_local structure + * @data: Output buffer sized for ARRAY_SIZE(axienet_xxv_priv_stats) u64 v= alues + */ +static void axienet_xxv_get_ethtool_stats(struct axienet_local *lp, u64 *d= ata) +{ + unsigned int i, start; + + do { + start =3D read_seqcount_begin(&lp->hw_stats_seqcount); + for (i =3D 0; i < ARRAY_SIZE(axienet_xxv_priv_stats); i++) + data[i] =3D lp->xxv_stat_base[axienet_xxv_priv_stats[i]]; + } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); +} + +/** + * axienet_xxv_get_strings - Copy XXV ethtool statistics name strings + * @data: Output buffer for the statistics name strings + */ +static void axienet_xxv_get_strings(u8 *data) +{ + memcpy(data, axienet_xxv_ethtool_stats_strings, + sizeof(axienet_xxv_ethtool_stats_strings)); +} + +/** + * axienet_xxv_get_sset_count - Number of XXV ethtool statistics + * + * Return: Count of XXV hardware statistics reported via ethtool -S. + */ +static int axienet_xxv_get_sset_count(void) +{ + return ARRAY_SIZE(axienet_xxv_ethtool_stats_strings); +} + +/** + * axienet_xxv_get_pause_stats - Fill ethtool pause frame statistics + * @lp: Pointer to the axienet_local structure + * @pause_stats: Output ethtool_pause_stats structure to populate + */ +static void axienet_xxv_get_pause_stats(struct axienet_local *lp, + struct ethtool_pause_stats *pause_stats) +{ + unsigned int start; + + do { + start =3D read_seqcount_begin(&lp->hw_stats_seqcount); + pause_stats->tx_pause_frames =3D + lp->xxv_stat_base[XXV_STAT_TX_PAUSE]; + pause_stats->rx_pause_frames =3D + lp->xxv_stat_base[XXV_STAT_RX_PAUSE]; + } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); +} + +/** + * axienet_xxv_get_eth_mac_stats - Fill IEEE 802.3 MAC statistics + * @lp: Pointer to the axienet_local structure + * @mac_stats: Output ethtool_eth_mac_stats structure to populate + */ +static void axienet_xxv_get_eth_mac_stats(struct axienet_local *lp, + struct ethtool_eth_mac_stats *mac_stats) +{ + unsigned int start; + + do { + start =3D read_seqcount_begin(&lp->hw_stats_seqcount); + mac_stats->FramesTransmittedOK =3D + lp->xxv_stat_base[XXV_STAT_TX_TOTAL_GOOD_PACKETS]; + mac_stats->FramesReceivedOK =3D + lp->xxv_stat_base[XXV_STAT_RX_TOTAL_GOOD_PACKETS]; + mac_stats->OctetsTransmittedOK =3D + lp->xxv_stat_base[XXV_STAT_TX_TOTAL_GOOD_BYTES]; + mac_stats->OctetsReceivedOK =3D + lp->xxv_stat_base[XXV_STAT_RX_TOTAL_GOOD_BYTES]; + mac_stats->FrameCheckSequenceErrors =3D + lp->xxv_stat_base[XXV_STAT_RX_BAD_FCS]; + mac_stats->MulticastFramesXmittedOK =3D + lp->xxv_stat_base[XXV_STAT_TX_MULTICAST]; + mac_stats->BroadcastFramesXmittedOK =3D + lp->xxv_stat_base[XXV_STAT_TX_BROADCAST]; + mac_stats->MulticastFramesReceivedOK =3D + lp->xxv_stat_base[XXV_STAT_RX_MULTICAST]; + mac_stats->BroadcastFramesReceivedOK =3D + lp->xxv_stat_base[XXV_STAT_RX_BROADCAST]; + mac_stats->InRangeLengthErrors =3D + lp->xxv_stat_base[XXV_STAT_RX_INRANGEERR]; + } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); +} + +/** + * axienet_xxv_get_rmon_stats - Fill RMON statistics and histogram ranges + * @lp: Pointer to the axienet_local structure + * @rmon_stats: Output ethtool_rmon_stats structure to populate + * @ranges: Set to the RMON histogram range table + */ +static void axienet_xxv_get_rmon_stats(struct axienet_local *lp, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges) +{ + unsigned int start; + + do { + start =3D read_seqcount_begin(&lp->hw_stats_seqcount); + rmon_stats->undersize_pkts =3D + lp->xxv_stat_base[XXV_STAT_RX_UNDERSIZE]; + rmon_stats->oversize_pkts =3D + lp->xxv_stat_base[XXV_STAT_RX_OVERSIZE]; + rmon_stats->fragments =3D + lp->xxv_stat_base[XXV_STAT_RX_FRAGMENT]; + rmon_stats->jabbers =3D + lp->xxv_stat_base[XXV_STAT_RX_JABBER]; + } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); + + /* XXV currently exposes only aggregate RMON counters, not per-bin + * histogram buckets. Keep ranges NULL until histogram bins are wired. + */ + *ranges =3D NULL; +} + const struct axienet_config axienet_10g25g_config =3D { .sw_padding =3D true, .internal_pcs =3D true, @@ -326,4 +584,12 @@ const struct axienet_config axienet_10g25g_config =3D { .get_regs =3D axienet_xxv_get_regs, .phylink_set_caps =3D axienet_xxv_phylink_set_capabilities, .pcs_ops =3D &axienet_xxv_pcs_ops, + .stats_update =3D axienet_xxv_stats_update, + .get_stats64 =3D axienet_xxv_get_stats64, + .get_ethtool_stats =3D axienet_xxv_get_ethtool_stats, + .get_strings =3D axienet_xxv_get_strings, + .get_sset_count =3D axienet_xxv_get_sset_count, + .get_pause_stats =3D axienet_xxv_get_pause_stats, + .get_eth_mac_stats =3D axienet_xxv_get_eth_mac_stats, + .get_rmon_stats =3D axienet_xxv_get_rmon_stats, }; diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.h b/drivers/net= /ethernet/xilinx/xilinx_axienet_xxv.h index 15a323ee05b2..ebfa7d57a859 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_xxv.h @@ -63,6 +63,33 @@ struct axienet_config; #define XXV_STAT_GTWIZ_OFFSET 0x000004A0 #define XXV_STAT_AN_LINK_CTL2_OFFSET 0x000009F0 =20 +/* XXV statistics counter registers (PG210). Each counter is a pair of 32-= bit + * registers; the MSB register is XXV_STAT_MSB_OFFSET bytes above the LSB. + */ +#define XXV_STAT_MSB_OFFSET 4 +#define XXV_STAT_TX_FRAME_ERROR_OFFSET 0x000006A0 +#define XXV_STAT_TX_TOTAL_PACKETS_OFFSET 0x00000700 +#define XXV_STAT_TX_TOTAL_GOOD_PACKETS_OFFSET 0x00000708 +#define XXV_STAT_TX_TOTAL_BYTES_OFFSET 0x00000710 +#define XXV_STAT_TX_TOTAL_GOOD_BYTES_OFFSET 0x00000718 +#define XXV_STAT_TX_BAD_FCS_OFFSET 0x000007B8 +#define XXV_STAT_TX_MULTICAST_OFFSET 0x000007D8 +#define XXV_STAT_TX_BROADCAST_OFFSET 0x000007E0 +#define XXV_STAT_TX_PAUSE_OFFSET 0x000007F0 +#define XXV_STAT_RX_TOTAL_PACKETS_OFFSET 0x00000808 +#define XXV_STAT_RX_TOTAL_GOOD_PACKETS_OFFSET 0x00000810 +#define XXV_STAT_RX_TOTAL_BYTES_OFFSET 0x00000818 +#define XXV_STAT_RX_TOTAL_GOOD_BYTES_OFFSET 0x00000820 +#define XXV_STAT_RX_UNDERSIZE_OFFSET 0x00000898 +#define XXV_STAT_RX_FRAGMENT_OFFSET 0x000008A0 +#define XXV_STAT_RX_OVERSIZE_OFFSET 0x000008A8 +#define XXV_STAT_RX_JABBER_OFFSET 0x000008B8 +#define XXV_STAT_RX_BAD_FCS_OFFSET 0x000008C0 +#define XXV_STAT_RX_MULTICAST_OFFSET 0x000008E0 +#define XXV_STAT_RX_BROADCAST_OFFSET 0x000008E8 +#define XXV_STAT_RX_PAUSE_OFFSET 0x000008F8 +#define XXV_STAT_RX_INRANGEERR_OFFSET 0x00000908 + /* XXV MAC Register Mask Definitions */ #define XXV_GT_RESET_MASK BIT(0) #define XXV_TC_TX_MASK BIT(0) @@ -70,6 +97,7 @@ struct axienet_config; #define XXV_RCW1_FCS_MASK BIT(1) #define XXV_TC_FCS_MASK BIT(1) #define XXV_RX_BLKLCK_MASK BIT(0) +#define XXV_TICKREG_STATEN_MASK BIT(0) #define XXV_GTWIZ_RESET_DONE (BIT(0) | BIT(1)) #define XXV_MAJ_MASK GENMASK(7, 0) #define XXV_MIN_MASK GENMASK(15, 8) @@ -81,6 +109,33 @@ struct axienet_config; #define XXV_STAT_CORE_SPEED_10G_MASK BIT(0) #define XXV_RX_STATUS_MASK BIT(0) =20 +/* XXV (10G/25G) MAC statistics counters, used to index xxv_stat_base[]. */ +enum xxv_stat { + XXV_STAT_RX_TOTAL_PACKETS =3D 0, + XXV_STAT_RX_TOTAL_GOOD_PACKETS, + XXV_STAT_RX_TOTAL_BYTES, + XXV_STAT_RX_TOTAL_GOOD_BYTES, + XXV_STAT_RX_BAD_FCS, + XXV_STAT_RX_INRANGEERR, + XXV_STAT_RX_MULTICAST, + XXV_STAT_RX_BROADCAST, + XXV_STAT_RX_UNDERSIZE, + XXV_STAT_RX_FRAGMENT, + XXV_STAT_RX_JABBER, + XXV_STAT_RX_OVERSIZE, + XXV_STAT_RX_PAUSE, + XXV_STAT_TX_TOTAL_PACKETS, + XXV_STAT_TX_TOTAL_GOOD_PACKETS, + XXV_STAT_TX_TOTAL_BYTES, + XXV_STAT_TX_TOTAL_GOOD_BYTES, + XXV_STAT_TX_BAD_FCS, + XXV_STAT_TX_FRAME_ERROR, + XXV_STAT_TX_MULTICAST, + XXV_STAT_TX_BROADCAST, + XXV_STAT_TX_PAUSE, + XXV_STAT_COUNT, +}; + extern const struct axienet_config axienet_10g25g_config; =20 #endif /* XILINX_AXIENET_XXV_H */ --=20 2.25.1