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[79.42.255.151]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-47ff79a7f07sm8070586f8f.8.2026.08.06.09.53.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 09:53:44 -0700 (PDT) From: Christian Marangi To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 1/2] dt-bindings: PCI: mediatek-gen3: Split Airoha schema and document 2-lanes Date: Thu, 6 Aug 2026 18:53:31 +0200 Message-ID: <20260806165334.7328-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260806165334.7328-1-ansuelsmth@gmail.com> References: <20260806165334.7328-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To permit proper documentation of required property to support PCIe configured for 2-lanes mode, split the Airoha schema part from the mediatek-gen3 schema to a dedicated schema. A PCIe configured for 2-lanes mode require an additional reg for the secondary PCIe to be configured and the airoha,scu phandle to correctly configure the PCIe MUX. Rework the mediatek-gen3 schema to drop any redundant constraint previsouly introduced for Airoha PCIe properties. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/airoha,en7581-pcie.yaml | 244 ++++++++++++++++++ .../bindings/pci/mediatek-pcie-gen3.yaml | 77 +----- 2 files changed, 249 insertions(+), 72 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/airoha,en7581-pci= e.yaml diff --git a/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml = b/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml new file mode 100644 index 000000000000..78a181a3b599 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml @@ -0,0 +1,244 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/airoha,en7581-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gen3 PCIe controller on Airoha SoCs + +maintainers: + - Christian Marangi + +description: |+ + PCIe Gen3 MAC controller for Airoha SoCs, it supports Gen3 speed + and compatible with Gen2, Gen1 speed. + + This PCIe controller supports up to 256 MSI vectors, the MSI hardware + block diagram is as follows: + + +-----+ + | GIC | + +-----+ + ^ + | + port->irq + | + +-+-+-+-+-+-+-+-+ + |0|1|2|3|4|5|6|7| (PCIe intc) + +-+-+-+-+-+-+-+-+ + ^ ^ ^ + | | ... | + +-------+ +------+ +-----------+ + | | | + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ + | | | | | | | | | | | | (MSI vectors) + | | | | | | | | | | | | + + (MSI SET0) (MSI SET1) ... (MSI SET7) + + With 256 MSI vectors supported, the MSI vectors are composed of 8 sets, + each set has its own address for MSI message, and supports 32 MSI vectors + to generate interrupt. + +properties: + compatible: + const: airoha,en7581-pcie + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + ranges: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: sys-ck + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie-phy + + num-lanes: + enum: [1, 2] + + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + + airoha,scu: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to airoha SCU syscon + description: + Phandle to SCU syscon to configure PCIe MUX for 2 lines support. + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling INTx PCI interrupt= s. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + num-lanes: + const: 2 + then: + properties: + reg: + minItems: 2 + + reg-names: + items: + - const: pcie-mac + - const: sec-pcie-mac + + resets: + minItems: 4 + + reset-names: + items: + - const: phy-lane0 + - const: phy-lane1 + - const: perstout + - const: sec-perstout + + required: + - airoha,scu + + else: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - const: pcie-mac + + resets: + minItems: 2 + maxItems: 3 + + reset-names: + minItems: 2 + items: + - enum: [ phy-lane0, phy-lane1, phy-lane2 ] + - enum: [ phy-lane1, perstout ] + - const: phy-lane2 + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1fc00000 { + compatible =3D "airoha,en7581-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + + reg =3D <0x0 0x1fc00000 0x0 0x1670>, + <0x0 0x1fc20000 0x0 0x1670>; + reg-names =3D "pcie-mac", "sec-pcie-mac"; + + clocks =3D <&scuclk 7>; + clock-names =3D "sys-ck"; + + phys =3D <&pciephy>; + phy-names =3D "pcie-phy"; + + ranges =3D <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000= >; + + resets =3D <&scuclk 48>, + <&scuclk 49>, + <&scuclk 53>, + <&scuclk 54>; + reset-names =3D "phy-lane0", "phy-lane1", + "perstout", "sec-perstout"; + + num-lanes =3D <2>; + + mediatek,pbus-csr =3D <&pbus_csr 0x0 0x4>; + + airoha,scu =3D <&scuclk>; + + interrupts =3D ; + bus-range =3D <0x00 0xff>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml = b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 4db700fc36ba..510f1f2b1c5a 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -59,7 +59,6 @@ properties: - const: mediatek,mt8196-pcie - const: mediatek,mt8192-pcie - const: mediatek,mt8196-pcie - - const: airoha,en7581-pcie =20 reg: maxItems: 1 @@ -83,20 +82,20 @@ properties: =20 resets: minItems: 1 - maxItems: 3 + maxItems: 2 =20 reset-names: minItems: 1 - maxItems: 3 + maxItems: 2 items: - enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ] + enum: [ phy, mac ] =20 clocks: - minItems: 1 + minItems: 4 maxItems: 6 =20 clock-names: - minItems: 1 + minItems: 4 maxItems: 6 =20 assigned-clocks: @@ -115,17 +114,6 @@ properties: power-domains: maxItems: 1 =20 - mediatek,pbus-csr: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: phandle to pbus-csr syscon - - description: offset of pbus-csr base address register - - description: offset of pbus-csr base address mask register - description: - Phandle with two arguments to the syscon node used to detect if - a given address is accessible on PCIe controller. - '#interrupt-cells': const: 1 =20 @@ -177,16 +165,6 @@ allOf: - const: peri_26m - const: top_133m =20 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - if: properties: compatible: @@ -208,16 +186,6 @@ allOf: - const: peri_26m - const: peri_mem =20 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - if: properties: compatible: @@ -246,8 +214,6 @@ allOf: - const: phy - const: mac =20 - mediatek,pbus-csr: false - - if: properties: compatible: @@ -257,7 +223,6 @@ allOf: then: properties: clocks: - minItems: 4 maxItems: 4 =20 clock-names: @@ -267,38 +232,6 @@ allOf: - const: peri_26m - const: top_133m =20 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - - if: - properties: - compatible: - const: airoha,en7581-pcie - then: - properties: - clocks: - maxItems: 1 - - clock-names: - items: - - const: sys-ck - - resets: - minItems: 3 - - reset-names: - items: - - const: phy-lane0 - - const: phy-lane1 - - const: phy-lane2 - unevaluatedProperties: false =20 examples: --=20 2.53.0 From nobody Fri Oct 2 01:12:19 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDF10381EB7 for ; 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[79.42.255.151]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-47ff79a7f07sm8070586f8f.8.2026.08.06.09.53.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 09:53:46 -0700 (PDT) From: Christian Marangi To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 2/2] PCI: mediatek-gen3: Add 2-lanes mode support for Airoha AN7581 Date: Thu, 6 Aug 2026 18:53:32 +0200 Message-ID: <20260806165334.7328-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260806165334.7328-1-ansuelsmth@gmail.com> References: <20260806165334.7328-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Airoha AN7581 SoC supports configuring the first PCIe0 lane to 2-lanes mode (x2 link) by bonding it with the second PCIe lane (PCIe1). This is done by configuring the PCIe MUX in the SCU register. To correctly configure PCIe0 in x2 link, define in DT the following additional properties: - additional reg, 'sec-pcie-mac' for the secondary PCIe. - PERSTOUT reset for both main and secondary PCIE0, called 'perstout' and 'sec-perstout' - 'airoha,scu' property to correctly configure the SCU register for the PCIe MUX - 'num-lanes' set to '2' to enable PCIe0 in x2 link In such configuration the EQ preset are configured to the same values. To permit correct configuration of the PCIe link, additional logic is added to assert and deassert the PERSTOUT resets. Support of these additional reset was introduced in Airoha clk driver with commit 6712f48eb3a1 ("clk: en7523: add support for dedicated PCIe PERSTOUT reset") and on backporting of this commit also the clk driver change will be needed. Signed-off-by: Christian Marangi --- drivers/pci/controller/pcie-mediatek-gen3.c | 106 ++++++++++++++++---- 1 file changed, 89 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index b0accd828589..c8300c47374b 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -32,6 +32,11 @@ =20 #include "../pci.h" =20 +/* AN7581 SCU register */ +#define SCU_PCIC 0x88 +#define SCU_PCIC_PCIE_CTRL GENMASK(7, 0) + +/* PCIe register */ #define PCIE_BASE_CFG_REG 0x14 #define PCIE_BASE_CFG_SPEED GENMASK(15, 8) =20 @@ -131,6 +136,7 @@ #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) =20 #define MAX_NUM_PHY_RESETS 3 +#define MAX_NUM_PERSTOUT_RESETS 2 =20 #define PCIE_MTK_RESET_TIME_US 10 =20 @@ -203,9 +209,11 @@ struct mtk_msi_set { struct mtk_gen3_pcie { struct device *dev; void __iomem *base; + void __iomem *sec_base; phys_addr_t reg_base; struct reset_control *mac_reset; struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS]; + struct reset_control_bulk_data perstout_resets[MAX_NUM_PERSTOUT_RESETS]; struct phy *phy; struct clk_bulk_data *clks; int num_clks; @@ -928,6 +936,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *p= cie) if (ret) return dev_err_probe(dev, ret, "failed to get PHY bulk reset\n"); =20 + pcie->perstout_resets[0].id =3D "perstout"; + pcie->perstout_resets[1].id =3D "sec-perstout"; + + ret =3D devm_reset_control_bulk_get_optional_exclusive(dev, MAX_NUM_PERST= OUT_RESETS, + pcie->perstout_resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get PERSTOUT bulk reset\n"); + pcie->mac_reset =3D devm_reset_control_get_optional_exclusive(dev, "mac"); if (IS_ERR(pcie->mac_reset)) return dev_err_probe(dev, PTR_ERR(pcie->mac_reset), "failed to get MAC r= eset\n"); @@ -949,18 +965,38 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *= pcie) pcie->num_lanes =3D num_lanes; } =20 + /* Map secondary PCIe for 2-lanes mode for EN7581 */ + if (pcie->num_lanes =3D=3D 2 && device_is_compatible(dev, "airoha,en7581-= pcie")) { + regs =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec-pcie-ma= c"); + if (!regs) + return -EINVAL; + pcie->sec_base =3D devm_ioremap_resource(dev, regs); + if (IS_ERR(pcie->sec_base)) + return dev_err_probe(dev, PTR_ERR(pcie->sec_base), "failed to map secon= dary register base\n"); + } + return 0; } =20 static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) { struct pci_host_bridge *host =3D pci_host_bridge_from_priv(pcie); + unsigned int num_lanes =3D max(1, pcie->num_lanes); + struct regmap *pbus_regmap, *scu; struct device *dev =3D pcie->dev; struct resource_entry *entry; - struct regmap *pbus_regmap; u32 val, args[2], size; resource_size_t addr; - int err; + int i, err; + + if (num_lanes > 2) + return dev_err_probe(dev, -EINVAL, "unsupported num-lanes, maximum 2 lan= es supported\n"); + + if (num_lanes =3D=3D 2) { + scu =3D syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,scu"); + if (IS_ERR(scu)) + return dev_err_probe(dev, PTR_ERR(scu), "failed to map SCU regmap\n"); + } =20 /* * The controller may have been left out of reset by the bootloader @@ -992,6 +1028,19 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_p= cie *pcie) size =3D lower_32_bits(resource_size(entry->res)); regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); =20 + /* Assert PERSTOUT for all relevant lanes */ + err =3D reset_control_bulk_assert(MAX_NUM_PERSTOUT_RESETS, + pcie->perstout_resets); + if (err) { + dev_err(dev, "failed to assert PERSTOUTs\n"); + return err; + } + + /* Configure SCU MUX to disable PCIE1 for x2 lanes mode */ + if (num_lanes =3D=3D 2) + regmap_update_bits(scu, SCU_PCIC, SCU_PCIC_PCIE_CTRL, + FIELD_PREP(SCU_PCIC_PCIE_CTRL, BIT(1))); + /* * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 * requires PHY initialization and power-on before PHY reset deassert. @@ -1024,18 +1073,6 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_= pcie *pcie) pm_runtime_enable(dev); pm_runtime_get_sync(dev); =20 - val =3D FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | - FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | - FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | - FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41); - writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG); - - val =3D PCIE_K_PHYPARAM_QUERY | PCIE_K_QUERY_TIMEOUT | - FIELD_PREP(PCIE_K_PRESET_TO_USE_16G, 0x80) | - FIELD_PREP(PCIE_K_PRESET_TO_USE, 0x2) | - FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); - writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); - err =3D clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to prepare clock\n"); @@ -1043,14 +1080,47 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3= _pcie *pcie) } =20 /* - * Airoha EN7581 performs PCIe reset via clk callbacks since it has a - * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to - * complete the PCIe reset. + * Old Airoha EN7581 clock driver performed PCIe reset via + * clk callbacks since it has a hw issue with PCIE_PE_RSTB signal. + * This is now handled by dedicated PERSTOUT resets with clk + * driver only enabling the refclk. + * + * Wait is still needed for refclk to stabilize */ msleep(PCIE_T_PVPERL_MS); =20 + /* Configure all the lanes to the same EQ config */ + for (i =3D 0; i < num_lanes; i++) { + void __iomem *base =3D pcie->base; + + if (i =3D=3D 1) + base =3D pcie->sec_base; + + val =3D FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | + FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | + FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | + FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41); + writel_relaxed(val, base + PCIE_EQ_PRESET_01_REG); + + val =3D PCIE_K_PHYPARAM_QUERY | PCIE_K_QUERY_TIMEOUT | + FIELD_PREP(PCIE_K_PRESET_TO_USE_16G, 0x80) | + FIELD_PREP(PCIE_K_PRESET_TO_USE, 0x2) | + FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); + writel_relaxed(val, base + PCIE_PIPE4_PIE8_REG); + } + + /* Deassert PERSTOUT for all relevant lanes */ + err =3D reset_control_bulk_deassert(MAX_NUM_PERSTOUT_RESETS, + pcie->perstout_resets); + if (err) { + dev_err(dev, "failed to deassert PERSTOUTs\n"); + goto err_perstout_deassert; + } + return 0; =20 +err_perstout_deassert: + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); err_clk_prepare_enable: pm_runtime_put_sync(dev); pm_runtime_disable(dev); @@ -1136,6 +1206,8 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie = *pcie) =20 phy_power_off(pcie->phy); phy_exit(pcie->phy); + reset_control_bulk_assert(MAX_NUM_PERSTOUT_RESETS, + pcie->perstout_resets); reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); } --=20 2.53.0