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charset="utf-8" From: Palash Kambar Document QMP UFS PHY compatible for Hawi SoC. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Palash Kambar --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-ph= y.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.ya= ml index b2c5c9a375a3..4efe40c0dc97 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -38,6 +38,7 @@ properties: - qcom,kaanapali-qmp-ufs-phy - const: qcom,sm8750-qmp-ufs-phy - enum: + - qcom,hawi-qmp-ufs-phy - qcom,milos-qmp-ufs-phy - qcom,msm8996-qmp-ufs-phy - qcom,msm8998-qmp-ufs-phy @@ -108,6 +109,7 @@ allOf: compatible: contains: enum: + - qcom,hawi-qmp-ufs-phy - qcom,milos-qmp-ufs-phy - qcom,msm8998-qmp-ufs-phy - qcom,sa8775p-qmp-ufs-phy --=20 2.34.1 From nobody Fri Oct 2 01:10:38 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78A4B480320 for ; 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charset="utf-8" From: Palash Kambar Add the init sequence tables and config for the UFS QMP phy found in the Hawi SoC. Reviewed-by: Abel Vesa Reviewed-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Signed-off-by: Palash Kambar --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h | 24 +++ .../qualcomm/phy-qcom-qmp-qserdes-com-v8.h | 13 +- .../phy-qcom-qmp-qserdes-txrx-ufs-v8.h | 37 +++++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 139 ++++++++++++++++++ 4 files changed, 212 insertions(+), 1 deletion(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h b/drivers/phy/q= ualcomm/phy-qcom-qmp-pcs-ufs-v7.h new file mode 100644 index 000000000000..e0e73ac88e8a --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V7_H_ +#define QCOM_PHY_QMP_PCS_UFS_V7_H_ + +/* Only for QMP V7 PHY - UFS PCS registers */ +#define QPHY_V7_PCS_UFS_PHY_START 0x000 +#define QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V7_PCS_UFS_SW_RESET 0x008 +#define QPHY_V7_PCS_UFS_PCS_CTRL1 0x01c +#define QPHY_V7_PCS_UFS_PLL_CNTL 0x028 +#define QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c +#define QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY 0x060 +#define QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY 0x094 +#define QPHY_V7_PCS_UFS_LINECFG_DISABLE 0x140 +#define QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2 0x150 +#define QPHY_V7_PCS_UFS_READY_STATUS 0x16c +#define QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1 0x1b8 +#define QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1 0x1c0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h index d8ac4c4a2c31..a3432fa6e38e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2026, The Linux Foundation. All rights reserved. */ =20 #ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_ @@ -71,5 +71,16 @@ #define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4 #define QSERDES_V8_COM_CMN_STATUS 0x2c8 #define QSERDES_V8_COM_C_READY_STATUS 0x2f0 +#define QSERDES_V8_COM_PLL_IVCO_MODE1 0xf8 +#define QSERDES_V8_COM_CMN_IETRIM 0xfc +#define QSERDES_V8_COM_CMN_IPTRIM 0x100 +#define QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c +#define QSERDES_V8_COM_ADAPTIVE_ANALOG_CONFIG 0x268 +#define QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c +#define QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270 +#define QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274 +#define QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE1 0x278 +#define QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c +#define QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280 =20 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h b/driv= ers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h new file mode 100644 index 000000000000..1adc6dbc68a0 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_ + +#define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX (0x34) +#define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX (0x38) +#define QSERDES_UFS_V8_TX_LANE_MODE_1 (0x80) +#define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2 (0x1bc) +#define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4 (0x1c4) +#define QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4 (0x1dc) +#define QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x2c8) +#define QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS (0x1e4) +#define QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3 (0x2d0) +#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 (0x120) +#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 (0xd4) +#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 (0xec) +#define QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL (0x288) +#define QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4 (0x2b0) +#define QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4 (0x324) +#define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7 (0x3b4) +#define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9 (0x3bc) +#define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7 (0x3e0) +#define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9 (0x3e8) +#define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7 (0x40c) +#define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9 (0x414) +#define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7 (0x438) +#define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9 (0x440) +#define QSERDES_UFS_V8_RX_UCDR_SO_SATURATION (0xf4) +#define QSERDES_UFS_V8_RX_TERM_BW_CTRL0 (0x1ac) +#define QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL (0x498) +#define QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM (0x4d0) + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 0f4ad24aa405..d4aca22c181e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -29,9 +29,11 @@ #include "phy-qcom-qmp-pcs-ufs-v4.h" #include "phy-qcom-qmp-pcs-ufs-v5.h" #include "phy-qcom-qmp-pcs-ufs-v6.h" +#include "phy-qcom-qmp-pcs-ufs-v7.h" =20 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h" +#include "phy-qcom-qmp-qserdes-txrx-ufs-v8.h" =20 /* QPHY_PCS_READY_STATUS bit */ #define PCS_READY BIT(0) @@ -84,6 +86,13 @@ static const unsigned int ufsphy_v6_regs_layout[QPHY_LAY= OUT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, }; =20 +static const unsigned int ufsphy_v7_regs_layout[QPHY_LAYOUT_SIZE] =3D { + [QPHY_START_CTRL] =3D QPHY_V7_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] =3D QPHY_V7_PCS_UFS_READY_STATUS, + [QPHY_SW_RESET] =3D QPHY_V7_PCS_UFS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), @@ -1307,6 +1316,11 @@ static const struct regulator_bulk_data sm8750_ufsph= y_vreg_l[] =3D { { .supply =3D "vdda-pll", .init_load_uA =3D 18300 }, }; =20 +static const struct regulator_bulk_data hawi_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 324000 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 27000 }, +}; + static const struct qmp_ufs_offsets qmp_ufs_offsets =3D { .serdes =3D 0, .pcs =3D 0xc00, @@ -1325,6 +1339,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_= v6 =3D { .rx2 =3D 0x1a00, }; =20 +static const struct qmp_ufs_offsets qmp_ufs_offsets_v7 =3D { + .serdes =3D 0, + .pcs =3D 0x0400, + .tx =3D 0x2000, + .rx =3D 0x2000, + .tx2 =3D 0x3000, + .rx2 =3D 0x3000, +}; + static const struct qmp_phy_cfg milos_ufsphy_cfg =3D { .lanes =3D 2, =20 @@ -1845,6 +1868,119 @@ static const struct qmp_phy_cfg sm8750_ufsphy_cfg = =3D { =20 }; =20 +static const struct qmp_phy_init_tbl hawi_ufsphy_serdes[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO_MODE1, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IETRIM, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IPTRIM, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_CTRL, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADAPTIVE_ANALOG_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; + +static const struct qmp_phy_init_tbl hawi_ufsphy_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_LANE_MODE_1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x07), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x17), +}; + +static const struct qmp_phy_init_tbl hawi_ufsphy_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4, 0x04), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS, 0x07), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL, 0x8e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4, 0xb8), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7, 0x66), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7, 0x66), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7, 0x66), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7, 0x66), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_SATURATION, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_TERM_BW_CTRL0, 0xfa), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL, 0x30), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM, 0x77), +}; + +static const struct qmp_phy_init_tbl hawi_ufsphy_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PCS_CTRL1, 0x42), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2, 0x68), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + +static const struct qmp_phy_init_tbl hawi_ufsphy_g5_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PLL_CNTL, 0x3b), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05), +}; + +static const struct qmp_phy_cfg hawi_ufsphy_cfg =3D { + .lanes =3D 2, + + .offsets =3D &qmp_ufs_offsets_v7, + .max_supported_gear =3D UFS_HS_G5, + + .tbls =3D { + .serdes =3D hawi_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(hawi_ufsphy_serdes), + .tx =3D hawi_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(hawi_ufsphy_tx), + .rx =3D hawi_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(hawi_ufsphy_rx), + .pcs =3D hawi_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(hawi_ufsphy_pcs), + }, + + .tbls_hs_overlay[0] =3D { + .pcs =3D hawi_ufsphy_g5_pcs, + .pcs_num =3D ARRAY_SIZE(hawi_ufsphy_g5_pcs), + .max_gear =3D UFS_HS_G5, + }, + + .vreg_list =3D hawi_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(hawi_ufsphy_vreg_l), + .regs =3D ufsphy_v7_regs_layout, +}; + static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_= cfg_tbls *tbls) { void __iomem *serdes =3D qmp->serdes; @@ -2259,6 +2395,9 @@ static int qmp_ufs_probe(struct platform_device *pdev) =20 static const struct of_device_id qmp_ufs_of_match_table[] =3D { { + .compatible =3D "qcom,hawi-qmp-ufs-phy", + .data =3D &hawi_ufsphy_cfg, + }, { .compatible =3D "qcom,milos-qmp-ufs-phy", .data =3D &milos_ufsphy_cfg, }, { --=20 2.34.1