From nobody Fri Oct 2 01:12:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7139D38F935; Thu, 6 Aug 2026 13:53:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786024400; cv=none; b=CbEv6lXUXX4g6oR9MTUnSIll8nBRBHvO4aj9ONm4+n4e+zc++4C6LTqaTCsj8cpjmNsfypaV5IN0m2QkFYKtyvw5LOtWsUJJkIhAj4wM94MTQNWfw0ETlmreuUYIyconTazFqEfb0f8KaKoLu8uDxu/jDOVEDgS+KM7LCvPiO3k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786024400; c=relaxed/simple; bh=8j14VJKbz6zpjtn780yxQBSwgJqKRSzQK4DB7rajsE8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cDzUpLmwDYzNXVr1244rfR5FIoieuVhVWZ7okpcwRfGqTFQj41hqwo3pKxvm7LJpgzk4v5xEYn7Ci5iDQe7UVlVuMDPDmsMG2AZp6ixPzUiT2DT+5tqFIn7pHNoDB9C49PHRrktmdAe44sawSAE4FN6/dvd3OFlJCwlNggG3q6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dNi74+4p; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dNi74+4p" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 347CB1F000E9; Thu, 6 Aug 2026 13:53:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786024399; bh=CNFDGBasAzdtMYMXr/QlbpUhNB9kt+XhO0QxWK3ASd8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dNi74+4psZcWvuyypQ6jT4auh3Kr9dB0kfp8MHGrNCRMh4o/O7lwSaSoLkHHzdGzK gDm1LX8DUtLnGKzq4JEnFQ5U648Hrj0zzQNEDayOU2Er0E5hfyanaBpX7sJd85RBtP 5dxGQqLJVCykmwLMNLyEcBtu4NXOu5YyA8sePqMKRnpbPsVwilm2zl1IeUqap1NPdL V+WNX8tHbeM3iLUF+iZN8Si6b/y7ejToEiEoIN0qwuh1PmZM3wSnGUkfaWgAdN8MHF EXJEaSVaV46HagYmueFLHrjlk740OTb6HSR5QAzRw1efmMg3boy/m/p3O/WlPtjjrY ST5oIHhRfD1CA== From: Puranjay Mohan To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim Cc: Puranjay Mohan , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Usama Arif , Will Deacon , Anshuman Khandual , Ravi Bangoria , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v6 1/3] perf/core: Fix NULL pmu_ctx passed to pmu->sched_task() Date: Thu, 6 Aug 2026 06:52:21 -0700 Message-ID: <20260806135224.3267890-2-puranjay@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260806135224.3267890-1-puranjay@kernel.org> References: <20260806135224.3267890-1-puranjay@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" perf_pmu_sched_task() returns early when cpuctx->task_ctx is set, and cpc->task_epc is only non-NULL while a task context is scheduled in on this CPU. __perf_pmu_sched_task() therefore always passes NULL: Unable to handle kernel NULL pointer dereference at virtual address 00 pc : armv8pmu_sched_task+0x14/0x50 Call trace: armv8pmu_sched_task+0x14/0x50 (P) perf_pmu_sched_task+0xac/0x108 __perf_event_task_sched_out+0x6c/0xe0 Pass &cpc->epc instead. __perf_init_event_pmu_context() sets its ->pmu when the PMU is registered; ->ctx stays NULL until a CPU-wide event attaches. That is enough here because armv8pmu_sched_task() is the only in-tree implementation that dereferences the argument at all, and it only reads ->pmu. The oops therefore needs BRBE, which arrived in v6.17. Fixes: bd2756811766 ("perf: Rewrite core context handling") Cc: stable@vger.kernel.org Acked-by: Usama Arif Signed-off-by: Puranjay Mohan Reviewed-by: James Clark --- kernel/events/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index b282de3e7d7ca..9815894b67e77 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -3907,7 +3907,8 @@ static void __perf_pmu_sched_task(struct perf_cpu_pmu= _context *cpc, perf_ctx_lock(cpuctx, cpuctx->task_ctx); perf_pmu_disable(pmu); =20 - pmu->sched_task(cpc->task_epc, task, sched_in); + pmu->sched_task(cpc->task_epc ? cpc->task_epc : &cpc->epc, + task, sched_in); =20 perf_pmu_enable(pmu); perf_ctx_unlock(cpuctx, cpuctx->task_ctx); --=20 2.53.0-Meta From nobody Fri Oct 2 01:12:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E29138F935; Thu, 6 Aug 2026 13:53:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786024404; cv=none; b=QUV5TchacwTiWuwY/ED2CDfCSeetw1nj5vYN46dlxr0ZhxScIkaZmPym6TsCgfUoOOncL1C33nxur85MOytqG1gKhhKemsyFbdNqOEC3MbyTnCdzIXCMUi8okUqLhh2cQVrH6rGzTWbQjrbJVhkdOeNyz/KPqRYMkVrniMOmd5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786024404; c=relaxed/simple; bh=CO1nekQ96Zo5yBUy9L+L/CcDmHipw3KUTjZ/59r0Ymc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SkbULHPjrAWaveNr2+gzeyoTJ84F4/6loxPyONebU/c6PvlilN5kRtwcKAts77NILAiNhcNvQm/y7wLzVr2unFLbFAO3slyIMG/I/YI3XryGIwV8pt3xuBxicwcJL0j6cUTaP2Eoe1ZtU4+pTA6Mt9AHOQHO9IGHD+DjZWaVoJo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e+BWU4WI; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e+BWU4WI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB3E11F000E9; Thu, 6 Aug 2026 13:53:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786024402; bh=7DTQ07GJKnfbpZQI4eZNwIceuMVDGsiSmnyh13hn3T4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=e+BWU4WIQSW3J6P4C5TRKyo/AXNNQHs35lrkU1rCrq12MFCQqUAJcnTiEAfwgaA0K QGpIWb/krRM7CI3msRzsZATYaZVO6J6jwU3uVBzd5atQj8NQnB4TrtZW2RnaYIl/X0 h9H+f7VOsjjpg5yQLjx1OHOhoDb/HWkPWnN9W3WbAv5WTrb5lNa04cljWr/zdgBWDn 795UkbpZDwZubWpMnseP/14Fn24rJ6H6nUzSmB7OVGPMRYoDOhLbwM7wIIrnSleikD zlF4xMB6eMteV9aDqgoJ3lE94Ja/GJfwMQRSXr/WOq8orxYhvIcQlRTWDcdHmvunSA S/VSKMKP43H6w== From: Puranjay Mohan To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim Cc: Puranjay Mohan , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Usama Arif , Will Deacon , Anshuman Khandual , Ravi Bangoria , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v6 2/3] perf/core: Run sched_task() for PMUs with only CPU-wide events Date: Thu, 6 Aug 2026 06:52:22 -0700 Message-ID: <20260806135224.3267890-3-puranjay@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260806135224.3267890-1-puranjay@kernel.org> References: <20260806135224.3267890-1-puranjay@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" perf_pmu_sched_task() returns early when cpuctx->task_ctx is set and leaves the work to perf_ctx_sched_task_cb(). That one only walks ctx->pmu_ctx_list, so a PMU whose events are all CPU-wide is never visited and its sched_task() callback does not run. With perf record -b -e cycles -a -- ls armv8pmu_sched_task() is skipped on every switch to a task that has a perf event of its own, and BRBE records leak across the task boundary. intel_pmu_lbr_add() calls perf_sched_cb_inc() unconditionally as well, so LBR records leak the same way on x86. Drop the early return and instead skip the individual CPCs that perf_ctx_sched_task_cb() already handles. That requires the two to agree on which CPC belongs to which path, and they do not. perf_ctx_sched_task_cb() gates on cpc->sched_cb_usage, which perf_sched_cb_inc() sets per CPU for every branch stack user, while the new gate uses cpc->task_epc, which __link_epc() sets only on the CPU the task context is scheduled in on. A task with an event for that PMU pinned to another CPU has an epc on ctx->pmu_ctx_list while cpc->task_epc is NULL, so both paths would run and sched_task() would be called twice per context switch. On x86 the second __intel_pmu_lbr_restore() finds lbr_stack_state =3D=3D LBR_NONE and calls intel_pmu_lbr_reset(), throwing away the callstack the first one restored. So gate perf_ctx_sched_task_cb() on cpc->task_epc too. For the CPCs that perf_pmu_sched_task() now handles, the callback no longer runs inside the perf_ctx_disable() and perf_ctx_enable() pair in perf_event_context_sched_in(). __perf_pmu_sched_task() disables the PMU around the call itself, so the callback still runs with it disabled. Fixes: bd2756811766 ("perf: Rewrite core context handling") Cc: stable@vger.kernel.org Acked-by: Usama Arif Signed-off-by: Puranjay Mohan Reviewed-by: James Clark --- kernel/events/core.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index 9815894b67e77..675dd05935f35 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -3757,6 +3757,9 @@ static void perf_ctx_sched_task_cb(struct perf_event_= context *ctx, list_for_each_entry(pmu_ctx, &ctx->pmu_ctx_list, pmu_ctx_entry) { cpc =3D this_cpc(pmu_ctx->pmu); =20 + if (cpc->task_epc !=3D pmu_ctx) + continue; + if (cpc->sched_cb_usage && pmu_ctx->pmu->sched_task) pmu_ctx->pmu->sched_task(pmu_ctx, task, sched_in); } @@ -3921,12 +3924,15 @@ static void perf_pmu_sched_task(struct task_struct = *prev, struct perf_cpu_context *cpuctx =3D this_cpu_ptr(&perf_cpu_context); struct perf_cpu_pmu_context *cpc; =20 - /* cpuctx->task_ctx will be handled in perf_event_context_sched_in/out */ - if (prev =3D=3D next || cpuctx->task_ctx) + if (prev =3D=3D next) return; =20 - list_for_each_entry(cpc, this_cpu_ptr(&sched_cb_list), sched_cb_entry) + list_for_each_entry(cpc, this_cpu_ptr(&sched_cb_list), sched_cb_entry) { + if (cpuctx->task_ctx && cpc->task_epc) + continue; + __perf_pmu_sched_task(cpc, sched_in ? next : prev, sched_in); + } } =20 static void perf_event_switch(struct task_struct *task, --=20 2.53.0-Meta From nobody Fri Oct 2 01:12:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E54E53B47D0; Thu, 6 Aug 2026 13:53:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786024408; cv=none; b=b6nEvVysqXrJQ9HE44SV7sZzFqkXq3/YUKdidt1LWtwWX13WWty3rDQyFIql48C0NNYRSDpmVBP3zyFp/2d5/+oZ5vbpaSg105icxLeKypJ147xjkYX6AEd7aKhSb4MNMMjz7SVbnwLiwGsgxMSgVUwbDEnhpX6lTXHdSEa8pQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786024408; c=relaxed/simple; bh=/gUygZqG5iJqfrYiScFK1MMpZ5HE7PLQv++ImHqVe8c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DyUAIQG2/pPmJxpMTldP/3s791PdxfIVdwIqjwcpCNrM2tHEZcQnkDg2xR7Xz38SHyOZadGqjaNksbaCLV8ZjQxX7Tqr3y7ZJGCLUftvacY0knk5POteEmrPMXGJgNpeGQ9AcjlyZPDigg8gw1bKaOfCMHAIPH0MW72Jrlyv/BE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vp2tN+o3; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vp2tN+o3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 556B71F000E9; Thu, 6 Aug 2026 13:53:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786024406; bh=9MvHu1Pl2ssBHzhmhTZmBr2JBtolR+FQT5i70MkMUxQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Vp2tN+o31EsdMyor7sYZoPaRvifAaVI0ng6axlV+D3HQZ87rBtnUL8FxPgESR/eDI 9fdM4SQ9ACgkezeHcW04FMFaql9Kc9HS9j98nmY02HT4aq4BjB+azty6HJ0TC8viGH OHTurSNVGbLVxdOrIS0VEo/JvBDtm0nkMTyC0shIJqgDSgYYJaIm25iiVUAINwwHhL 8/3ZF10KVCp7Yp1PtMbSSe2DjxVAh69HMDlAyvLHou2ejEHUOA0nZju/1D6F8G8ZMp Yfwt98mBfhcbk0xLoPkLu79bZhedv0iXd+GbPj0i1ykSn9dMI065p8MR7Nh2NWn0n+ dXYvxhXgj8iZw== From: Puranjay Mohan To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim Cc: Puranjay Mohan , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Usama Arif , Will Deacon , Anshuman Khandual , Ravi Bangoria , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/3] perf/core: Clear the whole branch entry in perf_clear_branch_entry() Date: Thu, 6 Aug 2026 06:52:23 -0700 Message-ID: <20260806135224.3267890-4-puranjay@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260806135224.3267890-1-puranjay@kernel.org> References: <20260806135224.3267890-1-puranjay@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" perf_clear_branch_entry_bitfields() clears the bitfields of struct perf_branch_entry one by one and leaves from/to alone, since callers overwrite those straight away. The list has to be kept in sync with the struct by hand and has already fallen behind: new_type and priv were added to perf_branch_entry and never added here. Only BRBE writes those two, and neither is written for every record. brbe_set_perf_entry_type() leaves new_type alone for a branch type it does not recognise, and priv is not set for source-only records. arm_pmuv3.c allocates the per-CPU branch stack with kmalloc(), so such a record carries whatever the slot held: uninitialised kmalloc() data on the first pass over the buffer, the previous record's values after that. Both reach userspace through the branch stack. Nothing under arch/x86/events/ writes either field, so x86 is unaffected. Clear the entry with a single struct assignment instead: *br =3D (struct perf_branch_entry){ }; The bitfields add up to exactly 64 bits, so there is no padding, and every caller assigns from/to immediately afterwards, so zeroing those as well changes nothing. PERF_BR_SPEC_NA is 0, so dropping the explicit spec assignment leaves the behaviour unchanged. Nothing needs keeping in sync when a field is added. The helper no longer touches only bitfields, so rename it to perf_clear_branch_entry(). Fixes: b190bc4ac9e6 ("perf: Extend branch type classification") Fixes: 5402d25aa571 ("perf: Capture branch privilege information") Suggested-by: James Clark Reviewed-by: James Clark Acked-by: Usama Arif Signed-off-by: Puranjay Mohan --- arch/x86/events/amd/brs.c | 2 +- arch/x86/events/amd/lbr.c | 2 +- arch/x86/events/intel/lbr.c | 6 +++--- drivers/perf/arm_brbe.c | 2 +- include/linux/perf_event.h | 16 ++-------------- 5 files changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/x86/events/amd/brs.c b/arch/x86/events/amd/brs.c index 06f35a6b58a5b..68c5f42965e91 100644 --- a/arch/x86/events/amd/brs.c +++ b/arch/x86/events/amd/brs.c @@ -343,7 +343,7 @@ void amd_brs_drain(void) =20 rdmsrq(brs_from(brs_idx), from); =20 - perf_clear_branch_entry_bitfields(br+nr); + perf_clear_branch_entry(br + nr); =20 br[nr].from =3D from; br[nr].to =3D to; diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c index 5b437dc8e4ce2..3639817456119 100644 --- a/arch/x86/events/amd/lbr.c +++ b/arch/x86/events/amd/lbr.c @@ -183,7 +183,7 @@ void amd_pmu_lbr_read(void) entry.to.split.reserved) continue; =20 - perf_clear_branch_entry_bitfields(br + out); + perf_clear_branch_entry(br + out); =20 br[out].from =3D sign_ext_branch_ip(entry.from.split.ip); br[out].to =3D sign_ext_branch_ip(entry.to.split.ip); diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index f8fadb0b16a45..6541c7046c2b3 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -756,7 +756,7 @@ void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc) =20 rdmsrq(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); =20 - perf_clear_branch_entry_bitfields(br); + perf_clear_branch_entry(br); =20 br->from =3D msr_lastbranch.from; br->to =3D msr_lastbranch.to; @@ -847,7 +847,7 @@ void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) if (abort && x86_pmu.lbr_double_abort && out > 0) out--; =20 - perf_clear_branch_entry_bitfields(br+out); + perf_clear_branch_entry(br + out); br[out].from =3D from; br[out].to =3D to; br[out].mispred =3D mis; @@ -921,7 +921,7 @@ static void intel_pmu_store_lbr(struct cpu_hw_events *c= puc, to =3D rdlbr_to(i, lbr); info =3D rdlbr_info(i, lbr); =20 - perf_clear_branch_entry_bitfields(e); + perf_clear_branch_entry(e); =20 e->from =3D from; e->to =3D to; diff --git a/drivers/perf/arm_brbe.c b/drivers/perf/arm_brbe.c index ba554e0c846c4..effbdeacfcbb3 100644 --- a/drivers/perf/arm_brbe.c +++ b/drivers/perf/arm_brbe.c @@ -604,7 +604,7 @@ static bool perf_entry_from_brbe_regset(int index, stru= ct perf_branch_entry *ent return false; =20 brbinf =3D bregs.brbinf; - perf_clear_branch_entry_bitfields(entry); + perf_clear_branch_entry(entry); if (brbe_record_is_complete(brbinf)) { entry->from =3D bregs.brbsrc; entry->to =3D bregs.brbtgt; diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 48d851fbd8ea5..e034be4a473a8 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1467,21 +1467,9 @@ static inline u32 perf_sample_data_size(struct perf_= sample_data *data, return size; } =20 -/* - * Clear all bitfields in the perf_branch_entry. - * The to and from fields are not cleared because they are - * systematically modified by caller. - */ -static inline void perf_clear_branch_entry_bitfields(struct perf_branch_en= try *br) +static inline void perf_clear_branch_entry(struct perf_branch_entry *br) { - br->mispred =3D 0; - br->predicted =3D 0; - br->in_tx =3D 0; - br->abort =3D 0; - br->cycles =3D 0; - br->type =3D 0; - br->spec =3D PERF_BR_SPEC_NA; - br->reserved =3D 0; + *br =3D (struct perf_branch_entry){ }; } =20 extern void perf_output_sample(struct perf_output_handle *handle, --=20 2.53.0-Meta