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charset="utf-8" From: Ji Sheng Teoh Add new compatible string for Dubhe-70. Dubhe-70 is a low power RISC-V cpu core from StarFive Technology. Signed-off-by: Ji Sheng Teoh Signed-off-by: Ley Foon Tan Signed-off-by: Changhuang Liang Reviewed-by: Hal Feng Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 5feeb2203050..e7eda7a9c345 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -63,6 +63,7 @@ properties: - sifive,u74-mc - spacemit,x100 - spacemit,x60 + - starfive,dubhe-70 - thead,c906 - thead,c908 - thead,c910 --=20 2.25.1 From nobody Fri Oct 2 01:14:45 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2124.outbound.protection.partner.outlook.cn [139.219.17.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA03147987B; 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charset="utf-8" From: Ley Foon Tan Add compatible string for StarFive JHB100 plic. Signed-off-by: Ley Foon Tan Signed-off-by: Changhuang Liang Acked-by: Conor Dooley Reviewed-by: Hal Feng --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 78d8cd77b4ec..cde4bb691897 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -66,6 +66,7 @@ properties: - spacemit,k1-plic - starfive,jh7100-plic - starfive,jh7110-plic + - starfive,jhb100-plic - tenstorrent,blackhole-plic - const: sifive,plic-1.0.0 - items: --=20 2.25.1 From nobody Fri Oct 2 01:14:45 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2124.outbound.protection.partner.outlook.cn [139.219.17.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7DC447A86C; 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charset="utf-8" From: Ley Foon Tan Add device tree bindings for the StarFive JHB100 RISC-V SoC. Signed-off-by: Ley Foon Tan Signed-off-by: Changhuang Liang Reviewed-by: Hal Feng Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Docume= ntation/devicetree/bindings/riscv/starfive.yaml index 8ba0e10b529a..277618efff6e 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -43,6 +43,11 @@ properties: - const: starfive,jh7110s - const: starfive,jh7110 =20 + - items: + - enum: + - starfive,jhb100-evb1 + - const: starfive,jhb100 + additionalProperties: true =20 ... --=20 2.25.1 From nobody Fri Oct 2 01:14:45 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2116.outbound.protection.partner.outlook.cn [139.219.146.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5279247A88E; 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charset="utf-8" Add "starfive,jhb100-uart" compatible string, with "snps,dw-apb-uart" as the fallback. Signed-off-by: Changhuang Liang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index c0d0524458c1..f90ba8f3d4f6 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -79,6 +79,7 @@ properties: - starfive,jh7100-hsuart - starfive,jh7100-uart - starfive,jh7110-uart + - starfive,jhb100-uart - ultrarisc,dp1000-uart - const: snps,dw-apb-uart - const: snps,dw-apb-uart --=20 2.25.1 From nobody Fri Oct 2 01:14:45 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2124.outbound.protection.partner.outlook.cn [139.219.17.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7107947ACE1; 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charset="utf-8" From: Ley Foon Tan Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC, PMU, UART, INTC and 1GB DDR. Signed-off-by: Ley Foon Tan Signed-off-by: Changhuang Liang --- MAINTAINERS | 6 + arch/riscv/boot/dts/starfive/Makefile | 2 + arch/riscv/boot/dts/starfive/jhb100-evb1.dts | 32 ++ arch/riscv/boot/dts/starfive/jhb100.dtsi | 331 +++++++++++++++++++ 4 files changed, 371 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dts create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 56b337a06447..ce97de46e610 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26069,6 +26069,12 @@ F: Documentation/devicetree/bindings/phy/starfive,= jh7110-usb-phy.yaml F: drivers/phy/starfive/phy-jh7110-pcie.c F: drivers/phy/starfive/phy-jh7110-usb.c =20 +STARFIVE JHB100 DEVICETREES +M: Changhuang Liang +L: linux-riscv@lists.infradead.org +S: Supported +F: arch/riscv/boot/dts/starfive/jhb100* + STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER M: Changhuang Liang S: Supported diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/st= arfive/Makefile index 3dd1f05283f7..42841942fe54 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfi= ve-2-lite.dtb dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-lite-emmc.dtb dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-v1.2a.dtb dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-v1.3b.dtb + +dtb-$(CONFIG_ARCH_STARFIVE) +=3D jhb100-evb1.dtb diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts b/arch/riscv/boot= /dts/starfive/jhb100-evb1.dts new file mode 100644 index 000000000000..462b6fb7953b --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd. + */ + +#include "jhb100.dtsi" + +/ { + model =3D "StarFive JHB100 EVB-1"; + compatible =3D "starfive,jhb100-evb1", "starfive,jhb100"; + + aliases { + serial6 =3D &uart6; + }; + + chosen { + stdout-path =3D "serial6:115200n8"; + }; + + cpus { + timebase-frequency =3D <5000000>; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0x0 0x40000000 0x0 0x40000000>; /* 1GB */ + }; +}; + +&uart6 { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts= /starfive/jhb100.dtsi new file mode 100644 index 000000000000..14ab83ed4482 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd. + */ + +/dts-v1/; + +/ { + compatible =3D "starfive,jhb100"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "starfive,dubhe-70", "riscv"; + reg =3D <0x0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", "zba",= "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "sscofpmf"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <16>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <512>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <24>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c0>; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu1: cpu@1 { + compatible =3D "starfive,dubhe-70", "riscv"; + reg =3D <0x1>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", "zba",= "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "sscofpmf"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <16>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <512>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <24>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c1>; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu2: cpu@2 { + compatible =3D "starfive,dubhe-70", "riscv"; + reg =3D <0x2>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", "zba",= "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "sscofpmf"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <16>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <512>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <24>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c2>; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu3: cpu@3 { + compatible =3D "starfive,dubhe-70", "riscv"; + reg =3D <0x3>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", "zba",= "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "sscofpmf"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <16>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <512>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <24>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c3>; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu1>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu2>; + }; + }; + + cluster3 { + core0 { + cpu =3D <&cpu3>; + }; + }; + }; + + l2c0: cache-controller-0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2c1: cache-controller-1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2c2: cache-controller-2 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2c3: cache-controller-3 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l3_cache: cache-controller-4 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-sets =3D <1024>; + cache-size =3D <0x20000>; + cache-unified; + }; + }; + + pmu { + compatible =3D "riscv,pmu"; + + riscv,event-to-mhpmevent =3D <0x00005 0x0000 0xA>, + <0x00006 0x0000 0xB>, + <0x00008 0x0000 0x10>, + <0x00009 0x0000 0xF>, + <0x10000 0x0000 0x19>, + <0x10001 0x0000 0x1A>, + <0x10002 0x0000 0x1B>, + <0x10003 0x0000 0x1C>, + <0x10008 0x0000 0x8>, + <0x10009 0x0000 0x9>, + <0x1000C 0x0000 0x9E>, + <0x1000D 0x0000 0x9F>, + <0x10010 0x0000 0x1D>, + <0x10011 0x0000 0x1E>, + <0x10012 0x0000 0x1F>, + <0x10013 0x0000 0x20>, + <0x10014 0x0000 0x21>, + <0x10018 0x0000 0x17>, + <0x10019 0x0000 0x18>, + <0x10020 0x0000 0x8>, + <0x10021 0x0000 0x7>; + + riscv,event-to-mhpmcounters =3D <0x00005 0x00006 0x00007FF8>, + <0x00008 0x00009 0x00007FF8>, + <0x10000 0x10003 0x00007FF8>, + <0x10008 0x10009 0x00007FF8>, + <0x1000C 0x1000D 0x00007FF8>, + <0x10010 0x10014 0x00007FF8>, + <0x10018 0x10019 0x00007FF8>, + <0x10020 0x10021 0x00007FF8>; + + riscv,raw-event-to-mhpmcounters =3D + <0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>, /* Event ID 1-31 */ + <0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>, /* Event ID 32-33 */ + <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */ + }; + + clk_uart: clock-uart { + compatible =3D "fixed-clock"; /* Initial clock handler for UART */ + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges; + ranges; + + clint: timer@2000000 { + compatible =3D "starfive,jhb100-clint", "sifive,clint0"; + reg =3D <0x0 0x02000000 0x0 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + plic: interrupt-controller@c000000 { + compatible =3D "starfive,jhb100-plic", "sifive,plic-1.0.0"; + reg =3D <0x0 0x0c000000 0x0 0x4000000>; + riscv,ndev =3D <400>; + interrupt-controller; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + }; + + bus_nioc: bus { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-noncoherent; + dma-ranges =3D <0x4 0x00000000 0x0 0x40000000 0x2 0x0>, + <0x4 0x00000000 0x4 0x00000000 0x2 0x0>; + ranges; + + uart6: serial@11982000 { + compatible =3D "starfive,jhb100-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0x11982000 0x0 0x400>; + clocks =3D <&clk_uart>, <&clk_uart>; + clock-names =3D "baudclk", "apb_pclk"; + interrupt-parent =3D <&intc>; + interrupts =3D <26>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + intc: interrupt-controller@13220000 { + compatible =3D "starfive,jhb100-intc"; + reg =3D <0x0 0x13220000 0x0 0x80>; + interrupts =3D <1>; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + }; +}; --=20 2.25.1