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Thu, 06 Aug 2026 02:11:22 -0700 (PDT) From: David Oberhollenzer To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, johan@kernel.org, rogerq@ti.com Cc: Julian.FRIEDRICH@frequentis.com, upstream+omap@sigma-star.at, David Oberhollenzer Subject: [PATCH v2 1/2] dt-bindings: phy: ti,phy-usb3: Add aspcie reference clock setting Date: Thu, 6 Aug 2026 11:11:11 +0200 Message-ID: <20260806091112.164695-2-david.oberhollenzer@sigma-star.at> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260806091112.164695-1-david.oberhollenzer@sigma-star.at> References: <20260806091112.164695-1-david.oberhollenzer@sigma-star.at> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PHY control logic in the OMAP PCIe PHY subsystem has a configurable reference clock selection. It can either use the ljcb_clkp/ljcb_clkn pin as inputs, recovering the clock from the bus (RX mode), or generate the reference clock internally, driving the bus pins as outputs (TX mode). The setting is exposed through a register in a system controller. A device tree property is added to specify the syscon node, register offset and mode value. Signed-off-by: David Oberhollenzer --- .../devicetree/bindings/phy/ti,phy-usb3.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Docum= entation/devicetree/bindings/phy/ti,phy-usb3.yaml index 84f538aa587c..11787b042345 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml @@ -52,6 +52,20 @@ properties: enum: [wkupclk, sysclk, refclk, dpll_ref, dpll_ref_m2, phy-div, div-clk] =20 + ti,syscon-acspcie-tx-rx: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Syscon register and setting to configure the clock buffer to run + in RX mode (clock pins are inputs, the clock is recovered from + the bus), or in TX mode (pins are outputs, internal reference + clock drives the bus). + maxItems: 1 + items: + items: + - description: Phandle to the system control module + - description: Register offset of CTRL_CORE_SMA_SW_6 + - description: Setting for PCIE_TX_RX_CONTROL + syscon-phy-power: $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1 @@ -94,6 +107,17 @@ allOf: else: properties: syscon-pllreset: false + - if: + properties: + compatible: + contains: + const: ti,phy-pipe3-pcie + then: + properties: + ti,syscon-acspcie-tx-rx: true + else: + properties: + ti,syscon-acspcie-tx-rx: false =20 required: - reg @@ -135,4 +159,19 @@ examples: syscon-pllreset =3D <&scm_conf 0x3fc>; #phy-cells =3D <0>; }; + + - | + /* TI PIPE3 PCIE PHY */ + pcie-phy@4a0a4000 { + compatible =3D "ti,phy-pipe3-pcie"; + reg =3D <0x4a0a4000 0x80>, /* phy_rx */ + <0x4a0a4400 0x64>; /* phy_tx */ + reg-names =3D "phy_rx", "phy_tx"; + clocks =3D <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>; + clock-names =3D "dpll_ref", "dpll_ref_m2"; + #phy-cells =3D <0>; + syscon-phy-power =3D <&scm_conf_pcie 0x1c>; + syscon-pcs =3D <&scm_conf_pcie 0x10>; + ti,syscon-acspcie-tx-rx =3D <&scm_conf1 0x10 0x2>; + }; ... --=20 2.55.0 From nobody Fri Oct 2 01:56:29 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D80853DB630 for ; Thu, 6 Aug 2026 09:11:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Thu, 06 Aug 2026 02:11:23 -0700 (PDT) Received: from localtoast.corp.sigma-star.at ([82.150.214.1]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47ff7b31975sm4035213f8f.33.2026.08.06.02.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 02:11:23 -0700 (PDT) From: David Oberhollenzer To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, johan@kernel.org, rogerq@ti.com Cc: Julian.FRIEDRICH@frequentis.com, upstream+omap@sigma-star.at, David Oberhollenzer Subject: [PATCH v2 2/2] phy: ti: ti-pipe3: allow configuring ACSPCIe TX/RX mode Date: Thu, 6 Aug 2026 11:11:12 +0200 Message-ID: <20260806091112.164695-3-david.oberhollenzer@sigma-star.at> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260806091112.164695-1-david.oberhollenzer@sigma-star.at> References: <20260806091112.164695-1-david.oberhollenzer@sigma-star.at> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the PCIe PHYs, read the property from the device tree and update the RX/TX mode selection bits in the specified syscon register. Signed-off-by: David Oberhollenzer --- drivers/phy/ti/phy-ti-pipe3.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index b5543b5c674c..bc02010dadb7 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -115,6 +115,9 @@ #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9) #define MEM_CDR_LOS_SOURCE_SHIFT 9 =20 +#define PCIE_TX_RX_CTRL_MASK GENMASK(17, 16) +#define PCIE_TX_RX_CTRL_SHIFT 16 + /* * This is an Empirical value that works, need to confirm the actual * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status @@ -785,6 +788,24 @@ static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) return PTR_ERR_OR_ZERO(phy->pll_ctrl_base); } =20 +static int ti_pipe3_acspcie_tx_rx_mode(struct ti_pipe3 *phy) +{ + struct device_node *np =3D phy->dev->of_node; + struct regmap *regmap; + unsigned int args[2]; + + regmap =3D syscon_regmap_lookup_by_phandle_args(np, + "ti,syscon-acspcie-tx-rx", + 2, args); + if (IS_ERR(regmap)) { + dev_warn(phy->dev, "can't get ti,syscon-acspcie-tx-rx\n"); + return -EINVAL; + } + + return regmap_update_bits(regmap, args[0], PCIE_TX_RX_CTRL_MASK, + args[1] << PCIE_TX_RX_CTRL_SHIFT); +} + static int ti_pipe3_probe(struct platform_device *pdev) { struct ti_pipe3 *phy; @@ -807,6 +828,12 @@ static int ti_pipe3_probe(struct platform_device *pdev) phy->dpll_map =3D data->dpll_map; phy->settings =3D data->settings; =20 + if (phy->mode =3D=3D PIPE3_MODE_PCIE) { + ret =3D ti_pipe3_acspcie_tx_rx_mode(phy); + if (ret) + dev_warn(dev, "failed to set ACSPCIe TX/RX mode\n"); + } + ret =3D ti_pipe3_get_pll_base(phy); if (ret) return ret; --=20 2.55.0