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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f4538bc9bsm921225b3a.11.2026.08.06.01.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 01:16:52 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , Mukesh Savaliya , Yadu M G , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Bartosz Golaszewski , Konrad Dybcio Subject: [PATCH v9 1/6] arm64: dts: qcom: Add device tree for Nord SoC series Date: Thu, 6 Aug 2026 16:15:49 +0800 Message-ID: <20260806081554.448531-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> References: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: LCJsDatEo4OOfW_952ybdzEObMXyX_Ib X-Proofpoint-ORIG-GUID: LCJsDatEo4OOfW_952ybdzEObMXyX_Ib X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX6/YNJaCCDYDF QdXF76U0tG7izaDuzgSOiANXiRwDbKfLBnGDg9nj3jIw/kRzQ5kblDnZizuz0gYU/mLQQhKMWVv 05CsiaLDLCf2TfXkPWJVTJcRC1ur+S4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX7kcbtVLmXkhx 1W9fgVhIGGHZjcWzp+TXjW0jR1L/T+BQyT/oVmFquT596plUtCio3G8Yarsp/8GWciclsk94BjP /1sLgaFA452iiWdcmXoaL1sOfEiM4CH5R1qRyvtN8iO1WeNl96dIj/i3sNRBzr/FterAaEFQQRw hcFYsNc6QpSdUWkDhf2oFWkBKPPNSV8Y2xDNOTgt7JV/i88mgpmUOTpmNa3/P0LysOkJWRIPSoS URQFA/C2c9hME3Nf3Ox/JPJnyigm6z5/M6ljeh4/7fAEFuRwyp9KuVjPNYInXqwXUt4CQgGyBDp Ovp5oNPuArxiNHV8kUwYbMifh3q620c8FugVOKUxWCN4dPANiG4/u7+vjtLF17u4neK3TL27MjZ 6Cf0yha69imXqfreHAdlF7PACwZxTQMq1fbIfxkqCXHOmovvQx/9VkVZbHUoBJbMxrug2r5FY/J GyhnZdOe0GE75QiDf6g== X-Authority-Analysis: v=2.4 cv=d4bFDxjE c=1 sm=1 tr=0 ts=6a7442f7 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=8CEx8uHD1C-9Ad5L0JgA:9 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-05_06,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 impostorscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060063 Content-Type: text/plain; charset="utf-8" Add base device tree include (nord.dtsi) for the Nord SoC series describing the core hardware components: - 18 Oryon (qcom,oryon-1-5) cores in three clusters, with PSCI-based power management and CPU/cluster idle states - ARM GICv3 interrupt controller with ITS - TLMM GPIO/pinctrl controller - 8 TSENS thermal sensors with thermal zones - 3 APPS SMMU-500 instances - 3 QUPv3 GENI SE QUP blocks - PDP SCMI channel and mailbox - Watchdog, Crypto, TRNG and TCSR - Reserved memory, CMD-DB and firmware SCM - PSCI and architected timers Co-developed-by: Deepti Jaggi Signed-off-by: Deepti Jaggi Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord.dtsi | 4623 ++++++++++++++++++++++++++++ 1 file changed, 4623 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/nord.dtsi diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/= nord.dtsi new file mode 100644 index 000000000000..6373d2e65f24 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord.dtsi @@ -0,0 +1,4623 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + power-domains =3D <&cpu0_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + power-domains =3D <&cpu1_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + power-domains =3D <&cpu2_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + power-domains =3D <&cpu3_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + power-domains =3D <&cpu4_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + #cooling-cells =3D <2>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + power-domains =3D <&cpu5_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + clocks =3D <&cpu_perf 0>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10000>; + power-domains =3D <&cpu6_pd>; + power-domain-names =3D "psci"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + #cooling-cells =3D <2>; + + l2_10000: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10100>; + enable-method =3D "psci"; + power-domains =3D <&cpu7_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + #cooling-cells =3D <2>; + }; + + cpu8: cpu@10200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10200>; + enable-method =3D "psci"; + power-domains =3D <&cpu8_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + #cooling-cells =3D <2>; + }; + + cpu9: cpu@10300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10300>; + enable-method =3D "psci"; + power-domains =3D <&cpu9_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + #cooling-cells =3D <2>; + }; + + cpu10: cpu@10400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10400>; + enable-method =3D "psci"; + power-domains =3D <&cpu10_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + #cooling-cells =3D <2>; + }; + + cpu11: cpu@10500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x10500>; + enable-method =3D "psci"; + power-domains =3D <&cpu11_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_10000>; + clocks =3D <&cpu_perf 1>; + #cooling-cells =3D <2>; + }; + + cpu12: cpu@20000 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20000>; + enable-method =3D "psci"; + power-domains =3D <&cpu12_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + #cooling-cells =3D <2>; + + l2_20000: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu13: cpu@20100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20100>; + enable-method =3D "psci"; + power-domains =3D <&cpu13_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + #cooling-cells =3D <2>; + }; + + cpu14: cpu@20200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20200>; + enable-method =3D "psci"; + power-domains =3D <&cpu14_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + #cooling-cells =3D <2>; + }; + + cpu15: cpu@20300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20300>; + enable-method =3D "psci"; + power-domains =3D <&cpu15_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + #cooling-cells =3D <2>; + }; + + cpu16: cpu@20400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20400>; + enable-method =3D "psci"; + power-domains =3D <&cpu16_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + #cooling-cells =3D <2>; + }; + + cpu17: cpu@20500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon-1-5"; + reg =3D <0x0 0x20500>; + enable-method =3D "psci"; + power-domains =3D <&cpu17_pd>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_20000>; + clocks =3D <&cpu_perf 2>; + #cooling-cells =3D <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu6>; + }; + + core1 { + cpu =3D <&cpu7>; + }; + + core2 { + cpu =3D <&cpu8>; + }; + + core3 { + cpu =3D <&cpu9>; + }; + + core4 { + cpu =3D <&cpu10>; + }; + + core5 { + cpu =3D <&cpu11>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu12>; + }; + + core1 { + cpu =3D <&cpu13>; + }; + + core2 { + cpu =3D <&cpu14>; + }; + + core3 { + cpu =3D <&cpu15>; + }; + + core4 { + cpu =3D <&cpu16>; + }; + + core5 { + cpu =3D <&cpu17>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + core_off_c4: cluster-c4 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "retention"; + entry-latency-us =3D <93>; + exit-latency-us =3D <129>; + min-residency-us =3D <560>; + arm,psci-suspend-param =3D <0x00000003>; + }; + }; + + domain-idle-states { + cluster_pwr_dn: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x01000053>; + entry-latency-us =3D <2150>; + exit-latency-us =3D <1983>; + min-residency-us =3D <9144>; + }; + + domain_ss3: domain-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x02000153>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <10150>; + }; + }; + }; + + firmware: firmware { + scm { + compatible =3D "qcom,scm-nord", + "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x79000>; + }; + + pdp_scmi: scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&pdp0_mbox 0>, + <&pdp0_mbox 11>, + <&pdp0_mbox 1>; + mbox-names =3D "tx", + "tx_reply", + "rx"; + shmem =3D <&pdp0_a2p>, + <&pdp0_p2a>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu_perf: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* Size will be updated by bootloader */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu0_pd: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu1_pd: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu2_pd: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu3_pd: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu4_pd: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu5_pd: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu6_pd: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu7_pd: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu8_pd: power-domain-cpu8 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu9_pd: power-domain-cpu9 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu10_pd: power-domain-cpu10 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu11_pd: power-domain-cpu11 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu12_pd: power-domain-cpu12 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu13_pd: power-domain-cpu13 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu14_pd: power-domain-cpu14 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu15_pd: power-domain-cpu15 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu16_pd: power-domain-cpu16 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cpu17_pd: power-domain-cpu17 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + domain-idle-states =3D <&core_off_c4>; + }; + + cluster0_pd: power-domain-cluster0 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&cluster_pwr_dn>; + }; + + cluster1_pd: power-domain-cluster1 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&cluster_pwr_dn>; + }; + + cluster2_pd: power-domain-cluster2 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&cluster_pwr_dn>; + }; + + system_pd: power-domain-system { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&domain_ss3>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + cpucp_scandump_mem: cpucp-scandump-region@80000000 { + reg =3D <0x0 0x80000000 0x0 0x800000>; + no-map; + }; + + tme_sail_mem: tme-sail-region@81ff0000 { + reg =3D <0x0 0x81ff0000 0x0 0x10000>; + no-map; + }; + + tz_sail_mailbox_mem: tz-sail-mailbox-region@82000000 { + reg =3D <0x0 0x82000000 0x0 0x8000>; + no-map; + }; + + sail_mailbox_mem: sail-mailbox-region@82008000 { + reg =3D <0x0 0x82008000 0x0 0x1f8000>; + no-map; + }; + + sail_ota_mem: sail-ota-region@82200000 { + reg =3D <0x0 0x82200000 0x0 0x5ff000>; + no-map; + }; + + sail_vdt_mem: sail-vdt-region@827ff000 { + reg =3D <0x0 0x827ff000 0x0 0x1000>; + no-map; + }; + + hyp_mem: hyp-region@82800000 { + reg =3D <0x0 0x82800000 0x0 0x2400000>; + no-map; + }; + + deepsleep_mem: deepsleep-region@84c00000 { + reg =3D <0x0 0x84c00000 0x0 0x800000>; + no-map; + }; + + deepsleep_backup_mem: deepsleep-backup-region@86a00000 { + reg =3D <0x0 0x86a00000 0x0 0x200000>; + no-map; + }; + + soccp_fe_vm_0: soccp-fe-vm-0-region@86c00000 { + reg =3D <0x0 0x86c00000 0x0 0xac000>; + no-map; + }; + + soccp_fe_vm_1: soccp-fe-vm-1-region@86cac000 { + reg =3D <0x0 0x86cac000 0x0 0x18d000>; + no-map; + }; + + soccp_fe_vm_2: soccp-fe-vm-2-region@86e39000 { + reg =3D <0x0 0x86e39000 0x0 0x1c7000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump-region@87000000 { + reg =3D <0x0 0x87000000 0x0 0xa0000>; + no-map; + }; + + tme_log_mem: tme-log-region@87140000 { + reg =3D <0x0 0x87140000 0x0 0x4000>; + no-map; + }; + + aop_cmd_db_p_mem: aop-cmd-db-p-region@87148000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x87148000 0x0 0x20000>; + no-map; + }; + + nsp_sync_buffer_mem: nsp-sync-buffer-region@871ff000 { + reg =3D <0x0 0x871ff000 0x0 0x1000>; + no-map; + }; + + ddr_training_checksum_data_mem: ddr-training-checksum-data-region@872000= 00 { + reg =3D <0x0 0x87200000 0x0 0x2000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog-region@87202000 { + reg =3D <0x0 0x87202000 0x0 0x60000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump-region@87262000 { + reg =3D <0x0 0x87262000 0x0 0x1c0000>; + no-map; + }; + + uefi_log: uefi-log@87442000 { + reg =3D <0x0 0x87442000 0x0 0x10000>; + no-map; + }; + + secdata_apss_mem: secdata-apss-region@87452000 { + reg =3D <0x0 0x87452000 0x0 0x1000>; + no-map; + }; + + antireplay_emulation_mem: antireplay-emulation-region@87453000 { + reg =3D <0x0 0x87453000 0x0 0x1000>; + no-map; + }; + + soccp_sdi_mem: soccp-sdi-region@87454000 { + reg =3D <0x0 0x87454000 0x0 0x40000>; + no-map; + }; + + hyp_mem_database_mem: hyp-mem-database-region@87494000 { + reg =3D <0x0 0x87494000 0x0 0x60000>; + no-map; + }; + + pmic_mini_dump_mem: pmic-mini-dump-region@874f4000 { + reg =3D <0x0 0x874f4000 0x0 0x80000>; + no-map; + }; + + qup_fw_mem: qup-fw-region@87574000 { + reg =3D <0x0 0x87574000 0x0 0x20000>; + no-map; + }; + + softsku_mem: softsku-region@87594000 { + reg =3D <0x0 0x87594000 0x0 0x9000>; + no-map; + }; + + resource_scheduler_mem: resource-scheduler-region@8759d000 { + reg =3D <0x0 0x8759d000 0x0 0x20000>; + no-map; + }; + + pdp_ns_mem: pdp-ns-mem-region@87600000 { + reg =3D <0x0 0x87600000 0x0 0x8000>, + <0x0 0x87609000 0x0 0x1f7000>; + no-map; + }; + + pdp0_p2a: scmi-shmem@87608000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x87608000 0x0 0x80>; + no-map; + }; + + pdp0_a2p: scmi-shmem@87608180 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x87608180 0x0 0x80>; + no-map; + }; + + tz_stat_mem: tz-stat-region@87a00000 { + reg =3D <0x0 0x87a00000 0x0 0x100000>; + no-map; + }; + + qdss_apps_mem: qdss-apps-region@87b00000 { + reg =3D <0x0 0x87b00000 0x0 0x2000000>; + no-map; + }; + + global_sync_mem: global-sync-region@89f00000 { + reg =3D <0x0 0x89f00000 0x0 0x400000>; + no-map; + }; + + tzffi_mem: tzffi-region@8a300000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x8a300000 0x0 0x1400000>; + no-map; + }; + + gunyah_md_mem: gunyah-md-region@8b700000 { + reg =3D <0x0 0x8b700000 0x0 0x80000>; + no-map; + }; + + flashless_qntm_tool_mem: flashless-qntm-tool-region@8b780000 { + reg =3D <0x0 0x8b780000 0x0 0x182000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@8bb00000 { + reg =3D <0x0 0x8bb00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@8bb10000 { + reg =3D <0x0 0x8bb10000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@8bb1a000 { + reg =3D <0x0 0x8bb1a000 0x0 0x2000>; + no-map; + }; + + gpu_microcode_2_mem: gpu-microcode-2-region@8bb1c000 { + reg =3D <0x0 0x8bb1c000 0x0 0x2000>; + no-map; + }; + + soccp_mem: soccp-region@8bc00000 { + reg =3D <0x0 0x8bc00000 0x0 0x300000>; + no-map; + }; + + cvp_mem: cvp-region@8d100000 { + reg =3D <0x0 0x8d100000 0x0 0x800000>; + no-map; + }; + + cdsp0_mem: cdsp0-region@8d900000 { + reg =3D <0x0 0x8d900000 0x0 0x2300000>; + no-map; + }; + + cdsp1_mem: cdsp1-region@8fc00000 { + reg =3D <0x0 0x8fc00000 0x0 0x2300000>; + no-map; + }; + + cdsp2_mem: cdsp2-region@91f00000 { + reg =3D <0x0 0x91f00000 0x0 0x2300000>; + no-map; + }; + + cdsp3_mem: cdsp3-region@94200000 { + reg =3D <0x0 0x94200000 0x0 0x2300000>; + no-map; + }; + + hpass_dsp0_mem: hpass-dsp0-region@96500000 { + reg =3D <0x0 0x96500000 0x0 0x2800000>; + no-map; + }; + + hpass_dsp1_mem: hpass-dsp1-region@98d00000 { + reg =3D <0x0 0x98d00000 0x0 0x2800000>; + no-map; + }; + + hpass_dsp2_mem: hpass-dsp2-region@9b500000 { + reg =3D <0x0 0x9b500000 0x0 0x2800000>; + no-map; + }; + + q6_cdsp0_dtb_mem: q6-cdsp0-dtb-region@9dd00000 { + reg =3D <0x0 0x9dd00000 0x0 0x80000>; + no-map; + }; + + q6_cdsp1_dtb_mem: q6-cdsp1-dtb-region@9dd80000 { + reg =3D <0x0 0x9dd80000 0x0 0x80000>; + no-map; + }; + + q6_cdsp2_dtb_mem: q6-cdsp2-dtb-region@9de00000 { + reg =3D <0x0 0x9de00000 0x0 0x80000>; + no-map; + }; + + q6_cdsp3_dtb_mem: q6-cdsp3-dtb-region@9de80000 { + reg =3D <0x0 0x9de80000 0x0 0x80000>; + no-map; + }; + + hpass_dsp0_dtb_mem: hpass-dsp0-dtb-region@9df00000 { + reg =3D <0x0 0x9df00000 0x0 0x80000>; + no-map; + }; + + hpass_dsp1_dtb_mem: hpass-dsp1-dtb-region@9df80000 { + reg =3D <0x0 0x9df80000 0x0 0x80000>; + no-map; + }; + + hpass_dsp2_dtb_mem: hpass-dsp2-dtb-region@9e000000 { + reg =3D <0x0 0x9e000000 0x0 0x100000>; + no-map; + }; + + camera_icp_1_mem: camera-icp-1-region@9e100000 { + reg =3D <0x0 0x9e100000 0x0 0x800000>; + no-map; + }; + + camera_icp_2_mem: camera-icp-2-region@9e900000 { + reg =3D <0x0 0x9e900000 0x0 0x800000>; + no-map; + }; + + camera_qup_1_mem: camera-qup-1-region@9f100000 { + reg =3D <0x0 0x9f100000 0x0 0x200000>; + no-map; + }; + + camera_qup_2_mem: camera-qup-2-region@9f300000 { + reg =3D <0x0 0x9f300000 0x0 0x200000>; + no-map; + }; + + video_mem: video-region@9f500000 { + reg =3D <0x0 0x9f500000 0x0 0xc00000>; + no-map; + }; + + pil_umd_reserved: mdt-load-region@a0100000 { + reg =3D <0x0 0xa0100000 0x0 0x100000>; + no-map; + }; + + mm_dspq: mm-dspq-region@ba200000 { + reg =3D <0x0 0xba200000 0x0 0x200000>; + no-map; + }; + + display_config_reserved: display-config-region@ba400000 { + reg =3D <0x0 0xba400000 0x0 0xa00000>; + no-map; + }; + + mm_calibration_data_mem: mm-calibration-data-region@bae00000 { + reg =3D <0x0 0xbae00000 0x0 0x800000>; + no-map; + }; + + audio_config_mem: audio-config-region@bb600000 { + reg =3D <0x0 0xbb600000 0x0 0xa00000>; + no-map; + }; + + dare_tz_mem: dare-tz-region@bc000000 { + reg =3D <0x0 0xbc000000 0x0 0xa300000>; + no-map; + }; + + hpass_rpc_remote_heap_mem: hpass-rpc-remote-heap-region@d4600000 { + reg =3D <0x0 0xd4600000 0x0 0x800000>; + no-map; + }; + + mdf_mem: mdf-region@d4e00000 { + reg =3D <0x0 0xd4e00000 0x0 0x2000000>; + no-map; + }; + + firmware_mem: firmware-region@d6e00000 { + reg =3D <0x0 0xd6e00000 0x0 0x800000>; + no-map; + }; + + firmware_shared_mem: firmware-shared-region@d7650000 { + reg =3D <0x0 0xd7650000 0x0 0x180000>; + no-map; + }; + + firmware_logs_mem: firmware-logs-region@d77d0000 { + reg =3D <0x0 0xd77d0000 0x0 0x20000>; + no-map; + }; + + sail_p_mem: sail-p-region@8c0000000 { + reg =3D <0x8 0xc0000000 0x0 0x8000000>; + no-map; + }; + + reserved_mem2: reserved-region@8c8000000 { + reg =3D <0x8 0xc8000000 0x0 0x18000000>; + no-map; + }; + + dump_mem: mem-dump-region { + alloc-ranges =3D <0x0 0x00000000 0x0 0xffffffff>; + size =3D <0x0 0x79b0000>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0 0 0 0 0x10 0>; + ranges =3D <0 0 0 0 0x10 0>; + + qupv3_2: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x2000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu_0 0x15a3 0x0>; + ranges; + + i2c14: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi14: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart14: serial@880000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c15: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi15: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart15: serial@884000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c16: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi16: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart16: serial@888000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c17: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi17: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart17: serial@88c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c18: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi18: spi@890000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart18: serial@890000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c19: i2c@894000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi19: spi@894000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart19: serial@894000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c20: i2c@898000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi20: spi@898000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart20: serial@898000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + }; + + qupv3_0: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x009c0000 0x0 0x2000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu_2 0x1003 0x0>; + ranges; + + i2c0: i2c@980000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00980000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi0: spi@980000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00980000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart0: serial@980000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00980000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c1: i2c@984000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00984000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi1: spi@984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00984000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart1: serial@984000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00984000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c2: i2c@988000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00988000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi2: spi@988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00988000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart2: serial@988000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00988000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c3: i2c@98c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi3: spi@98c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart3: serial@98c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c4: i2c@990000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00990000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi4: spi@990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00990000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart4: serial@990000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00990000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c5: i2c@994000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00994000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi5: spi@994000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00994000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart5: serial@994000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00994000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + }; + + qupv3_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu_2 0x1043 0x0>; + ranges; + + i2c7: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi7: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart7: serial@a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c8: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi8: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart8: serial@a84000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c9: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart9: serial@a88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c10: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart10: serial@a8c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c11: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi11: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart11: serial@a90000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c12: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi12: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart12: serial@a94000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + i2c13: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + interrupts =3D ; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi13: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + + uart13: serial@a98000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + interrupts =3D ; + + status =3D "disabled"; + }; + }; + + rng: rng@10c3000 { + compatible =3D "qcom,nord-trng", + "qcom,trng"; + reg =3D <0x0 0x010c3000 0x0 0x1000>; + }; + + ufs_mem_hc: ufshc@1d44000 { + compatible =3D "qcom,nord-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0x0 0x01d44000 0x0 0x3000>, + <0x0 0x01d60000 0x0 0x15000>; + reg-names =3D "std", + "mcq"; + interrupts =3D ; + lanes-per-direction =3D <2>; + iommus =3D <&apps_smmu_0 0x14c0 0x0>; + dma-coherent; + msi-parent =3D <&gic_its 0x14c0>; + + status =3D "disabled"; + }; + + cryptobam: dma-controller@1dc4000 { + compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg =3D <0x0 0x01dc4000 0x0 0x28000>; + interrupts =3D ; + #dma-cells =3D <1>; + iommus =3D <&apps_smmu_0 0x1689 0>; + qcom,ee =3D <0>; + qcom,num-ees =3D <4>; + num-channels =3D <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible =3D "qcom,nord-qce", "qcom,sm8150-qce", "qcom,qce"; + reg =3D <0x0 0x01dfa000 0x0 0x6000>; + dmas =3D <&cryptobam 4>, <&cryptobam 5>; + dma-names =3D "rx", "tx"; + iommus =3D <&apps_smmu_0 0x1689 0>; + + /* It stops nord-gearvm variant from booting to console */ + status =3D "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1f60000 { + compatible =3D "qcom,nord-tcsr", + "syscon"; + reg =3D <0x0 0x01f60000 0x0 0xa0000>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,nord-pdc", + "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x10000>; + qcom,pdc-ranges =3D <0 745 43>, + <67 543 31>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c22c000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c22d000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens2: thermal-sensor@c22e000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens3: thermal-sensor@c22f000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens4: thermal-sensor@c230000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c230000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens5: thermal-sensor@c231000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c231000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens6: thermal-sensor@c232000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c232000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tsens7: thermal-sensor@c233000 { + compatible =3D "qcom,nord-tsens", + "qcom,tsens-v2"; + reg =3D <0x0 0x0c233000 0x0 0x1000>, + <0x0 0x0c229000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <16>; + #thermal-sensor-cells =3D <1>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,nord-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0xc0000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 181>; + wakeup-parent =3D <&pdc>; + }; + + apps_smmu_0: iommu@15a00000 { + compatible =3D "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg =3D <0x0 0x15a00000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + dma-coherent; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apps_smmu_1: iommu@15c00000 { + compatible =3D "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg =3D <0x0 0x15c00000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + dma-coherent; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apps_smmu_2: iommu@15e00000 { + compatible =3D "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg =3D <0x0 0x15e00000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + dma-coherent; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x480000>; + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x40000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17040000 0x0 0x40000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + pdp0_mbox: mailbox@17610000 { + compatible =3D "qcom,nord-cpucp-mbox", + "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x0 0x17610000 0x0 0x4c08>, + <0x0 0x19980000 0x0 0x300>; + #mbox-cells =3D <1>; + interrupts =3D ; + }; + + memtimer: timer@17810000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17810000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17811000 { + reg =3D <0x17811000 0x1000>, + <0x17812000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@17813000 { + reg =3D <0x17813000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@17815000 { + reg =3D <0x17815000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@17817000 { + reg =3D <0x17817000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@17819000 { + reg =3D <0x17819000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@1781b000 { + reg =3D <0x1781b000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@1781d000 { + reg =3D <0x1781d000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + watchdog@17826000 { + compatible =3D "qcom,apss-wdt-nord", + "qcom,kpss-wdt"; + reg =3D <0x0 0x17826000 0x0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + }; + + arch_timer: timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + thermal_zones: thermal-zones { + ddr-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-4-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-5-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-4-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-5-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens0 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-4-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-5-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-4-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-5-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens1 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + amux-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-4-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-5-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + pcie-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens2 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + amux-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-4-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-2-5-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <125000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpullc-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhvx-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audhmx-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + pcie-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens3 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-0-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-1-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-2-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-2-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-2-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-3-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-3-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-3-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens4 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-0-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-1-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-2-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-2-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-2-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsphvx-3-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-3-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-3-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens5 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + amux-6-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpu-0-0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cv-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + video-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + camera-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-3-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpu-0-1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens6 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + amux-7-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpu-0-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpu-1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cv-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + video-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + camera-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddr-3-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 13>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 14>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpu-0-0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens7 15>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f4538bc9bsm921225b3a.11.2026.08.06.01.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 01:16:56 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , Mukesh Savaliya , Yadu M G , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski , Shawn Guo Subject: [PATCH v9 2/6] arm64: dts: qcom: Add device tree for Nord GearVM variant Date: Thu, 6 Aug 2026 16:15:50 +0800 Message-ID: <20260806081554.448531-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> References: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: bqCtiNB68H68_odevZsZ6S_iBqixtF6E X-Authority-Analysis: v=2.4 cv=Or9/DS/t c=1 sm=1 tr=0 ts=6a7442fb cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=C7SS7-jxath9lZw70LYA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX8im/QtYNAgvR 2E5CMSUAtoEkt35KHLym3J5jsBbMGy+rh/fNdo5zPwMMlLpEgRnKZ8tBv4K+FBFUNgRvw6baouv 21FP91XBH3l51fUdBMwRoSpfcPAtbF7WwwN8bDaJskvdCBTcTAsuJ2SQugeVursAZmY+jla8+5A lNv6I8SwetDW0ydmH+T3EaQmzSpj9D8nz7k2RncbSvL05nrAzyQxraX5NapVoID6tX3FilSavPB B2AmkVPcYc4jBSv9bHItDfEOzZZ/2GmOSzAEKwl5gwalu7CHWppA+Mn2eyqnXoGxRFVegDHe8Nb HbN5f4JW5kPwkzKGG4QNiEd62YjhpO3D8lpXmWSdrnUAvqWOcB/4G0S4izpTXmW8ywTRVMi6wzD H+tza397MEvGuuF3yRqZ3SXmFzQmWciD6iTKSR911kOxJ44uR7MSRfQUQuNKmphncEf8Ta30XAI ASZxXZ43XN6+q4lnqXA== X-Proofpoint-GUID: bqCtiNB68H68_odevZsZ6S_iBqixtF6E X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX/8xr6iTI0NxV cLDBBWv/rGZKBR/NflakkJyuOWvpSYyUzBH5q2GZt6dXPORPftujsNMKGaZDLbOfUl3vmVvtx8v 50ccBxAaiqIw5HFZVkisZZlgYV2CKIo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-05_06,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 priorityscore=1501 spamscore=0 bulkscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060063 Content-Type: text/plain; charset="utf-8" From: Deepti Jaggi Add SoC-level device tree include for Nord GearVM variant, where a VM controls platform resources (clocks, regulators, powerdomains, etc.) as SCMI server. It currently covers: - 64 SCMI shared memory regions reserved at 0xd7600000-0xd763f000 for SMC-based firmware communication channels - Three QUPV3 GENI SE QUP blocks (qupv3_0/1/2) with I2C/SPI/UART controllers using SCMI power and performance domains via scmi11 - UFS host controller with SCMI power domain via scmi3 Signed-off-by: Deepti Jaggi Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-gearvm.dtsi | 2848 +++++++++++++++++++++ 1 file changed, 2848 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/nord-gearvm.dtsi diff --git a/arch/arm64/boot/dts/qcom/nord-gearvm.dtsi b/arch/arm64/boot/dt= s/qcom/nord-gearvm.dtsi new file mode 100644 index 000000000000..cd20acb89c1b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-gearvm.dtsi @@ -0,0 +1,2848 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "nord.dtsi" + +&firmware { + scmi0: scmi-0 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem0>; + /* We expect the bootloader to update the IRQ number */ + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi0_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi0_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi0_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi1: scmi-1 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem1>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi1_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi1_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi1_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi2: scmi-2 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem2>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi2_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi2_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi2_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi3: scmi-3 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem3>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi3_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi3_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi3_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi4: scmi-4 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem4>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi4_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi4_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi4_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi5: scmi-5 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem5>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi5_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi5_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi5_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi6: scmi-6 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem6>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi6_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi6_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi6_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi7: scmi-7 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem7>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi7_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi7_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi7_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi8: scmi-8 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem8>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi8_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi8_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi8_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi9: scmi-9 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem9>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi9_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi9_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi9_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi10: scmi-10 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem10>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi10_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi10_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi10_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi11: scmi-11 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem11>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi11_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi11_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi11_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi12: scmi-12 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem12>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi12_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi12_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi12_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi13: scmi-13 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem13>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi13_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi13_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi13_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi14: scmi-14 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem14>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi14_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi14_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi14_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi15: scmi-15 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem15>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi15_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi15_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi15_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi16: scmi-16 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem16>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi16_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi16_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi16_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi17: scmi-17 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem17>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi17_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi17_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi17_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi18: scmi-18 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem18>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi18_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi18_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi18_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi19: scmi-19 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem19>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi19_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi19_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi19_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi20: scmi-20 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem20>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi20_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi20_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi20_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi21: scmi-21 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem21>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi21_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi21_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi21_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi22: scmi-22 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem22>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi22_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi22_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi22_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi23: scmi-23 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem23>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi23_sensor: protocol@15 { + reg =3D <0x15>; + #thermal-sensor-cells =3D <1>; + }; + }; + + scmi24: scmi-24 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem24>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi24_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi24_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi24_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi25: scmi-25 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem25>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi25_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi25_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi25_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi26: scmi-26 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem26>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi26_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi26_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi26_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi27: scmi-27 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem27>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi27_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi27_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi27_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi28: scmi-28 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem28>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi28_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi28_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi28_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi29: scmi-29 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem29>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi29_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi29_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi29_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi30: scmi-30 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem30>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi30_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi30_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi30_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi31: scmi-31 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem31>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi31_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi31_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi31_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi32: scmi-32 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem32>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi32_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi32_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi32_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi33: scmi-33 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem33>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi33_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi33_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi33_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi34: scmi-34 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem34>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi34_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi34_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi34_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi35: scmi-35 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem35>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi35_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi35_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi35_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi36: scmi-36 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem36>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi36_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi36_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi36_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi37: scmi-37 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem37>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi37_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi37_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi37_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi38: scmi-38 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem38>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi38_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi38_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi38_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi39: scmi-39 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem39>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi39_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi39_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi39_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi40: scmi-40 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem40>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi40_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi40_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi40_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi41: scmi-41 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem41>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi41_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi41_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi41_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi42: scmi-42 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem42>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi42_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi42_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi42_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi43: scmi-43 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem43>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi43_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi43_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi43_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi44: scmi-44 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem44>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi44_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi44_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi44_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi45: scmi-45 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem45>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi45_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi45_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi45_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi46: scmi-46 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem46>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi46_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi46_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi46_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi47: scmi-47 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem47>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi47_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi47_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi47_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi48: scmi-48 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem48>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi48_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi48_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi48_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi49: scmi-49 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem49>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi49_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi49_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi49_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi50: scmi-50 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem50>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi50_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi50_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi50_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi51: scmi-51 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem51>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi51_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi51_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi51_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi52: scmi-52 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem52>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi52_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi52_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi52_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi53: scmi-53 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem53>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi53_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi53_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi53_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi54: scmi-54 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem54>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi54_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi54_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi54_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi55: scmi-55 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem55>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi55_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi55_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi55_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi56: scmi-56 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem56>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi56_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi56_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi56_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi57: scmi-57 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem57>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi57_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi57_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi57_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi58: scmi-58 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem58>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi58_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi58_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi58_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi59: scmi-59 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem59>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi59_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi59_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi59_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi60: scmi-60 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem60>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi60_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi60_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi60_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi61: scmi-61 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem61>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi61_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi61_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi61_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi62: scmi-62 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem62>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi62_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi62_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi62_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi63: scmi-63 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem63>; + interrupts =3D ; + interrupt-names =3D "a2p"; + #address-cells =3D <1>; + #size-cells =3D <0>; + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi63_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi63_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi63_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; +}; + +&i2c0 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c1 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c2 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c3 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c4 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c5 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c7 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c8 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c9 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 9>, + <&scmi11_dvfs 9>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c10 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 10>, + <&scmi11_dvfs 10>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c11 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c12 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c13 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c14 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c15 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c16 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c17 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c18 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c19 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names =3D "power", + "perf"; +}; + +&i2c20 { + compatible =3D "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains =3D <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names =3D "power", + "perf"; +}; + +&qupv3_0 { + compatible =3D "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&qupv3_1 { + compatible =3D "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&qupv3_2 { + compatible =3D "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&reserved_memory { + shmem0: scmi-shmem@d7600000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7600000 0x0 0x1000>; + no-map; + }; + + shmem1: scmi-shmem@d7601000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7601000 0x0 0x1000>; + no-map; + }; + + shmem2: scmi-shmem@d7602000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7602000 0x0 0x1000>; + no-map; + }; + + shmem3: scmi-shmem@d7603000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7603000 0x0 0x1000>; + no-map; + }; + + shmem4: scmi-shmem@d7604000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7604000 0x0 0x1000>; + no-map; + }; + + shmem5: scmi-shmem@d7605000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7605000 0x0 0x1000>; + no-map; + }; + + shmem6: scmi-shmem@d7606000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7606000 0x0 0x1000>; + no-map; + }; + + shmem7: scmi-shmem@d7607000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7607000 0x0 0x1000>; + no-map; + }; + + shmem8: scmi-shmem@d7608000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7608000 0x0 0x1000>; + no-map; + }; + + shmem9: scmi-shmem@d7609000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7609000 0x0 0x1000>; + no-map; + }; + + shmem10: scmi-shmem@d760a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760a000 0x0 0x1000>; + no-map; + }; + + shmem11: scmi-shmem@d760b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760b000 0x0 0x1000>; + no-map; + }; + + shmem12: scmi-shmem@d760c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760c000 0x0 0x1000>; + no-map; + }; + + shmem13: scmi-shmem@d760d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760d000 0x0 0x1000>; + no-map; + }; + + shmem14: scmi-shmem@d760e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760e000 0x0 0x1000>; + no-map; + }; + + shmem15: scmi-shmem@d760f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd760f000 0x0 0x1000>; + no-map; + }; + + shmem16: scmi-shmem@d7610000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7610000 0x0 0x1000>; + no-map; + }; + + shmem17: scmi-shmem@d7611000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7611000 0x0 0x1000>; + no-map; + }; + + shmem18: scmi-shmem@d7612000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7612000 0x0 0x1000>; + no-map; + }; + + shmem19: scmi-shmem@d7613000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7613000 0x0 0x1000>; + no-map; + }; + + shmem20: scmi-shmem@d7614000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7614000 0x0 0x1000>; + no-map; + }; + + shmem21: scmi-shmem@d7615000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7615000 0x0 0x1000>; + no-map; + }; + + shmem22: scmi-shmem@d7616000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7616000 0x0 0x1000>; + no-map; + }; + + shmem23: scmi-shmem@d7617000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7617000 0x0 0x1000>; + no-map; + }; + + shmem24: scmi-shmem@d7618000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7618000 0x0 0x1000>; + no-map; + }; + + shmem25: scmi-shmem@d7619000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7619000 0x0 0x1000>; + no-map; + }; + + shmem26: scmi-shmem@d761a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761a000 0x0 0x1000>; + no-map; + }; + + shmem27: scmi-shmem@d761b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761b000 0x0 0x1000>; + no-map; + }; + + shmem28: scmi-shmem@d761c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761c000 0x0 0x1000>; + no-map; + }; + + shmem29: scmi-shmem@d761d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761d000 0x0 0x1000>; + no-map; + }; + + shmem30: scmi-shmem@d761e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761e000 0x0 0x1000>; + no-map; + }; + + shmem31: scmi-shmem@d761f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd761f000 0x0 0x1000>; + no-map; + }; + + shmem32: scmi-shmem@d7620000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7620000 0x0 0x1000>; + no-map; + }; + + shmem33: scmi-shmem@d7621000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7621000 0x0 0x1000>; + no-map; + }; + + shmem34: scmi-shmem@d7622000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7622000 0x0 0x1000>; + no-map; + }; + + shmem35: scmi-shmem@d7623000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7623000 0x0 0x1000>; + no-map; + }; + + shmem36: scmi-shmem@d7624000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7624000 0x0 0x1000>; + no-map; + }; + + shmem37: scmi-shmem@d7625000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7625000 0x0 0x1000>; + no-map; + }; + + shmem38: scmi-shmem@d7626000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7626000 0x0 0x1000>; + no-map; + }; + + shmem39: scmi-shmem@d7627000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7627000 0x0 0x1000>; + no-map; + }; + + shmem40: scmi-shmem@d7628000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7628000 0x0 0x1000>; + no-map; + }; + + shmem41: scmi-shmem@d7629000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7629000 0x0 0x1000>; + no-map; + }; + + shmem42: scmi-shmem@d762a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762a000 0x0 0x1000>; + no-map; + }; + + shmem43: scmi-shmem@d762b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762b000 0x0 0x1000>; + no-map; + }; + + shmem44: scmi-shmem@d762c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762c000 0x0 0x1000>; + no-map; + }; + + shmem45: scmi-shmem@d762d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762d000 0x0 0x1000>; + no-map; + }; + + shmem46: scmi-shmem@d762e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762e000 0x0 0x1000>; + no-map; + }; + + shmem47: scmi-shmem@d762f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd762f000 0x0 0x1000>; + no-map; + }; + + shmem48: scmi-shmem@d7630000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7630000 0x0 0x1000>; + no-map; + }; + + shmem49: scmi-shmem@d7631000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7631000 0x0 0x1000>; + no-map; + }; + + shmem50: scmi-shmem@d7632000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7632000 0x0 0x1000>; + no-map; + }; + + shmem51: scmi-shmem@d7633000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7633000 0x0 0x1000>; + no-map; + }; + + shmem52: scmi-shmem@d7634000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7634000 0x0 0x1000>; + no-map; + }; + + shmem53: scmi-shmem@d7635000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7635000 0x0 0x1000>; + no-map; + }; + + shmem54: scmi-shmem@d7636000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7636000 0x0 0x1000>; + no-map; + }; + + shmem55: scmi-shmem@d7637000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7637000 0x0 0x1000>; + no-map; + }; + + shmem56: scmi-shmem@d7638000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7638000 0x0 0x1000>; + no-map; + }; + + shmem57: scmi-shmem@d7639000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd7639000 0x0 0x1000>; + no-map; + }; + + shmem58: scmi-shmem@d763a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763a000 0x0 0x1000>; + no-map; + }; + + shmem59: scmi-shmem@d763b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763b000 0x0 0x1000>; + no-map; + }; + + shmem60: scmi-shmem@d763c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763c000 0x0 0x1000>; + no-map; + }; + + shmem61: scmi-shmem@d763d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763d000 0x0 0x1000>; + no-map; + }; + + shmem62: scmi-shmem@d763e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763e000 0x0 0x1000>; + no-map; + }; + + shmem63: scmi-shmem@d763f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd763f000 0x0 0x1000>; + no-map; + }; +}; + +&spi0 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names =3D "power", + "perf"; +}; + +&spi1 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names =3D "power", + "perf"; +}; + +&spi2 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names =3D "power", + "perf"; +}; + +&spi3 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names =3D "power", + "perf"; +}; + +&spi4 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names =3D "power", + "perf"; +}; + +&spi5 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names =3D "power", + "perf"; +}; + +&spi7 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names =3D "power", + "perf"; +}; + +&spi8 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names =3D "power", + "perf"; +}; + +&spi11 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names =3D "power", + "perf"; +}; + +&spi12 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names =3D "power", + "perf"; +}; + +&spi13 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names =3D "power", + "perf"; +}; + +&spi14 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names =3D "power", + "perf"; +}; + +&spi15 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names =3D "power", + "perf"; +}; + +&spi16 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names =3D "power", + "perf"; +}; + +&spi17 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names =3D "power", + "perf"; +}; + +&spi18 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names =3D "power", + "perf"; +}; + +&spi19 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names =3D "power", + "perf"; +}; + +&spi20 { + compatible =3D "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains =3D <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names =3D "power", + "perf"; +}; + +&uart0 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names =3D "power", + "perf"; +}; + +&uart1 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names =3D "power", + "perf"; +}; + +&uart2 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names =3D "power", + "perf"; +}; + +&uart3 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names =3D "power", + "perf"; +}; + +&uart4 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names =3D "power", + "perf"; +}; + +&uart5 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names =3D "power", + "perf"; +}; + +&uart7 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names =3D "power", + "perf"; +}; + +&uart8 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names =3D "power", + "perf"; +}; + +&uart9 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 9>, + <&scmi11_dvfs 9>; + power-domain-names =3D "power", + "perf"; +}; + +&uart10 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 10>, + <&scmi11_dvfs 10>; + power-domain-names =3D "power", + "perf"; +}; + +&uart11 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names =3D "power", + "perf"; +}; + +&uart12 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names =3D "power", + "perf"; +}; + +&uart13 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names =3D "power", + "perf"; +}; + +&uart14 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names =3D "power", + "perf"; +}; + +&uart15 { + compatible =3D "qcom,sa8797p-geni-debug-uart", + "qcom,sa8255p-geni-debug-uart"; + power-domains =3D <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names =3D "power", + "perf"; +}; + +&uart16 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names =3D "power", + "perf"; +}; + +&uart17 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names =3D "power", + "perf"; +}; + +&uart18 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names =3D "power", + "perf"; +}; + +&uart19 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names =3D "power", + "perf"; +}; + +&uart20 { + compatible =3D "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains =3D <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names =3D "power", + "perf"; +}; + +&ufs_mem_hc { + compatible =3D "qcom,sa8797p-ufshc", + "qcom,sa8255p-ufshc"; + power-domains =3D <&scmi3_pd 0>; +}; --=20 2.43.0 From nobody Fri Oct 2 01:56:13 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B04D23DDB13 for ; Thu, 6 Aug 2026 08:17:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f4538bc9bsm921225b3a.11.2026.08.06.01.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 01:17:01 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , Mukesh Savaliya , Yadu M G , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Bartosz Golaszewski , Konrad Dybcio Subject: [PATCH v9 3/6] arm64: dts: qcom: Add device tree for Nord Embedded variant Date: Thu, 6 Aug 2026 16:15:51 +0800 Message-ID: <20260806081554.448531-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> References: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=aNzAb79m c=1 sm=1 tr=0 ts=6a7442ff cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=M_pxE5vcLJVX-WqgpTUA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: HWtqf83yO0wsPBttu_JRpN_hgYXI0REB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX8E2iA7+9AvYS wiwHQHKRRvpr4gVHK+vOiqH0HNKi4s5GYIfaRS+P0iyKlsDUxtROCWC6sP2SSO9SEKGXsjWbpTj TQwTAa+aXdKSw0ATd7lI45wsoUJ5PAfxmkVhaZQV0LJjRsGwL3jOgxz3i7AuM658NrGXvWPCwjc 7skQdB8Kjxi52F8SxeGYpLGTSRsDeMhJRpci1bH7LfNRVSVhhj+UM9HDw7EzwaXswXlrQEqozKy OcZQInQGASBXY2tqxUfRnk6m/nGNL/HxmB978QIdmuNaNsqjuB5LHQWcwkDl8QnLDnmEp5CI+b+ mtLMmOgKy4ssfP1pxPXxk0N91LKjgrWydAK5ftiN0ZE9UGakZHpJ3e5DM4O66AT+cIiVXUJMlLn 1O2Ru0+TOU6+1GKyFwyPofitCDvIr+wpJMMYEZw4I4zl+JiIpPIC57Gc96dlWbRr+vQy+C/OgNh 1eyaR0qk79FB4ZdXZEg== X-Proofpoint-ORIG-GUID: HWtqf83yO0wsPBttu_JRpN_hgYXI0REB X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX6Ezk5TkSgIl4 h9xIYMoz5i8F5u12jtgNyyv6wMiiVQO6IjEEBSTMjGBwF6Ge1h3l3eaYLlD0lZRDx1k1yo27ZEB clDlm6SrDJA9IhZWO0FSllB0f4hE2ic= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-05_06,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 suspectscore=0 adultscore=0 clxscore=1015 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060063 Content-Type: text/plain; charset="utf-8" Unlike the GearVM variant, Nord Embedded variant has platform resources (clocks, regulators, powerdomains, pins, etc.) directly controlled by the operating system. Add a separate dtsi file extending the existing top-level nord.dtsi with nodes representing these peripherals as well as describing how they are wired up with the already defined components. Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 1726 +++++++++++++++++++ 1 file changed, 1726 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/nord-embedded.dtsi diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/= dts/qcom/nord-embedded.dtsi new file mode 100644 index 000000000000..3276dc5069e7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -0,0 +1,1726 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "nord.dtsi" + +/ { + clk_virt: interconnect-clk-virt { + compatible =3D "qcom,nord-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible =3D "qcom,nord-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; +}; + +&crypto { + interconnects =3D <&aggre1_noc_tile MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWA= YS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "memory"; + + status =3D "okay"; +}; + +&i2c0 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c0_default>; + pinctrl-names =3D "default"; +}; + +&i2c1 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c1_default>; + pinctrl-names =3D "default"; +}; + +&i2c2 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c2_default>; + pinctrl-names =3D "default"; +}; + +&i2c3 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c3_default>; + pinctrl-names =3D "default"; +}; + +&i2c4 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c4_default>; + pinctrl-names =3D "default"; +}; + +&i2c5 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c5_default>; + pinctrl-names =3D "default"; +}; + +&i2c7 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c7_default>; + pinctrl-names =3D "default"; +}; + +&i2c8 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c8_default>; + pinctrl-names =3D "default"; +}; + +&i2c9 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c9_default>; + pinctrl-names =3D "default"; +}; + +&i2c10 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c10_default>; + pinctrl-names =3D "default"; +}; + +&i2c11 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c11_default>; + pinctrl-names =3D "default"; +}; + +&i2c12 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c12_default>; + pinctrl-names =3D "default"; +}; + +&i2c13 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c13_default>; + pinctrl-names =3D "default"; +}; + +&i2c14 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c14_default>; + pinctrl-names =3D "default"; +}; + +&i2c16 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c16_default>; + pinctrl-names =3D "default"; +}; + +&i2c17 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c17_default>; + pinctrl-names =3D "default"; +}; + +&i2c18 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c18_default>; + pinctrl-names =3D "default"; +}; + +&i2c19 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c19_default>; + pinctrl-names =3D "default"; +}; + +&i2c20 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_i2c20_default>; + pinctrl-names =3D "default"; +}; + +&qupv3_0 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_M_AHB_CLK>, + <&segcc SE_GCC_QUPV3_WRAP0_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; +}; + +&qupv3_1 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_M_AHB_CLK>, + <&segcc SE_GCC_QUPV3_WRAP1_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; +}; + +&qupv3_2 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_M_AHB_CLK>, + <&negcc NE_GCC_QUPV3_WRAP2_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; +}; + +&spi0 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi0_default>; + pinctrl-names =3D "default"; +}; + +&spi1 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi1_default>; + pinctrl-names =3D "default"; +}; + +&spi2 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi2_default>; + pinctrl-names =3D "default"; +}; + +&spi3 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi3_default>; + pinctrl-names =3D "default"; +}; + +&spi4 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi4_default>; + pinctrl-names =3D "default"; +}; + +&spi5 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi5_default>; + pinctrl-names =3D "default"; +}; + +&spi7 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi7_default>; + pinctrl-names =3D "default"; +}; + +&spi8 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi8_default>; + pinctrl-names =3D "default"; +}; + +&spi11 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi11_default>; + pinctrl-names =3D "default"; +}; + +&spi12 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi12_default>; + pinctrl-names =3D "default"; +}; + +&spi13 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi13_default>; + pinctrl-names =3D "default"; +}; + +&spi14 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi14_default>; + pinctrl-names =3D "default"; +}; + +&spi16 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi16_default>; + pinctrl-names =3D "default"; +}; + +&spi17 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi17_default>; + pinctrl-names =3D "default"; +}; + +&spi18 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi18_default>; + pinctrl-names =3D "default"; +}; + +&spi19 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi19_default>; + pinctrl-names =3D "default"; +}; + +&spi20 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + pinctrl-0 =3D <&qup_spi20_default>; + pinctrl-names =3D "default"; +}; + +&soc { + gcc: clock-controller@100000 { + compatible =3D "qcom,nord-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f4200>; + clocks =3D <&bi_tcxo_div2>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,nord-cnoc-main"; + reg =3D <0x0 0x01500000 0x0 0x1d200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible =3D "qcom,nord-cnoc-cfg"; + reg =3D <0x0 0x01600000 0x0 0xd200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,nord-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x1c080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc_tile: interconnect@16c0000 { + compatible =3D "qcom,nord-aggre2-noc-tile"; + reg =3D <0x0 0x016c0000 0x0 0x1b400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,nord-aggre1-noc"; + reg =3D <0x0 0x016e0000 0x0 0x1c400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,nord-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1b400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&rpmhcc RPMH_IPA_CLK>; + }; + + aggre1_noc_tile: interconnect@1720000 { + compatible =3D "qcom,nord-aggre1-noc-tile"; + reg =3D <0x0 0x01720000 0x0 0x23400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&negcc NE_GCC_AGGRE_NOC_USB2_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible =3D "qcom,nord-mmss-noc"; + reg =3D <0x0 0x01780000 0x0 0x72800>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_cfg: interconnect@1ba0000 { + compatible =3D "qcom,nord-pcie-cfg"; + reg =3D <0x0 0x01ba0000 0x0 0x7200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_data_outbound: interconnect@1bc0000 { + compatible =3D "qcom,nord-pcie-data-outbound"; + reg =3D <0x0 0x01bc0000 0x0 0x17000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_data_inbound: interconnect@1c00000 { + compatible =3D "qcom,nord-pcie-data-inbound"; + reg =3D <0x0 0x01c00000 0x0 0x4b080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + ufs_mem_phy: phy@1d40000 { + compatible =3D "qcom,nord-qmp-ufs-phy", + "qcom,sm8650-qmp-ufs-phy"; + reg =3D <0x0 0x01d40000 0x0 0x2000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&negcc NE_GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>; + clock-names =3D "ref", + "ref_aux", + "qref"; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + power-domains =3D <&negcc NE_GCC_UFS_MEM_PHY_GDSC>; + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ice: crypto@1d48000 { + compatible =3D "qcom,nord-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x01d48000 0x0 0x10000>; + clocks =3D <&negcc NE_GCC_UFS_PHY_ICE_CORE_CLK>, + <&negcc NE_GCC_UFS_PHY_AHB_CLK>; + clock-names =3D "core", + "iface"; + power-domains =3D <&negcc NE_GCC_UFS_PHY_GDSC>; + }; + + hscnoc: interconnect@2000000 { + compatible =3D "qcom,nord-hscnoc"; + reg =3D <0x0 0x02000000 0x0 0xb22000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + hpass_ag_noc: interconnect@5fc0000 { + compatible =3D "qcom,nord-hpass-ag-noc"; + reg =3D <0x0 0x05fc0000 0x0 0x37080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + negcc: clock-controller@8900000 { + compatible =3D "qcom,nord-negcc"; + reg =3D <0x0 0x08900000 0x0 0xf4200>; + clocks =3D <&bi_tcxo_div2>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + segcc: clock-controller@8a00000 { + compatible =3D "qcom,nord-segcc"; + reg =3D <0x0 0x08a00000 0x0 0xf4200>; + clocks =3D <&bi_tcxo_div2>, + <&sleep_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + nwgcc: clock-controller@8b00000 { + compatible =3D "qcom,nord-nwgcc"; + reg =3D <0x0 0x08b00000 0x0 0xf4200>; + clocks =3D <&bi_tcxo_div2>, + <&sleep_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + tcsrcc: clock-controller@f1d9000 { + compatible =3D "qcom,nord-tcsrcc", + "syscon"; + reg =3D <0x0 0x0f1d9000 0x0 0xf00c>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + apps_rsc: rsc@18900000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + interrupts =3D , + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + label =3D "apps_rsc"; + power-domains =3D <&system_pd>; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,nord-rpmh-clk"; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,nord-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level =3D ; + }; + }; + }; + }; + + nsp_data_noc_0: interconnect@1f200000 { + compatible =3D "qcom,nord-nsp-data-noc-0"; + reg =3D <0x0 0x1f200000 0x0 0x2a200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nsp_data_noc_1: interconnect@1f600000 { + compatible =3D "qcom,nord-nsp-data-noc-1"; + reg =3D <0x0 0x1f600000 0x0 0x2a200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nsp_data_noc_2: interconnect@1fa00000 { + compatible =3D "qcom,nord-nsp-data-noc-2"; + reg =3D <0x0 0x1fa00000 0x0 0x2a200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nsp_data_noc_3: interconnect@1fe00000 { + compatible =3D "qcom,nord-nsp-data-noc-3"; + reg =3D <0x0 0x1fe00000 0x0 0x2a200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; +}; + +&tlmm { + qup_i2c0_default: qup-i2c0-default-state { + pins =3D "gpio111", "gpio112"; + function =3D "qup0_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins =3D "gpio111", "gpio112"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins =3D "gpio113", "gpio114"; + function =3D "qup0_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins =3D "gpio115", "gpio116"; + function =3D "qup0_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins =3D "gpio117", "gpio118"; + function =3D "qup0_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins =3D "gpio121", "gpio122"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins =3D "gpio123", "gpio124"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins =3D "gpio125", "gpio126"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins =3D "gpio127", "gpio128"; + function =3D "qup1_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins =3D "gpio129", "gpio130"; + function =3D "qup1_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c11_default: qup-i2c11-default-state { + pins =3D "gpio131", "gpio132"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c12_default: qup-i2c12-default-state { + pins =3D "gpio133", "gpio134"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c13_default: qup-i2c13-default-state { + pins =3D "gpio137", "gpio138"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c14_default: qup-i2c14-default-state { + pins =3D "gpio139", "gpio140"; + function =3D "qup2_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c16_default: qup-i2c16-default-state { + pins =3D "gpio145", "gpio146"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c17_default: qup-i2c17-default-state { + pins =3D "gpio150", "gpio151"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c18_default: qup-i2c18-default-state { + pins =3D "gpio154", "gpio155"; + function =3D "qup2_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c19_default: qup-i2c19-default-state { + pins =3D "gpio156", "gpio157"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c20_default: qup-i2c20-default-state { + pins =3D "gpio158", "gpio159"; + function =3D "qup2_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + data-pins { + pins =3D "gpio109", "gpio111", "gpio112"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio110"; + function =3D "qup0_se0"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi1_default: qup-spi1-default-state { + data-pins { + pins =3D "gpio109", "gpio111", "gpio112"; + function =3D "qup0_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio110"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi2_default: qup-spi2-default-state { + data-pins { + pins =3D "gpio113", "gpio114", "gpio115"; + function =3D "qup0_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio116"; + function =3D "qup0_se2"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi3_default: qup-spi3-default-state { + data-pins { + pins =3D "gpio113", "gpio115", "gpio116"; + function =3D "qup0_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio114"; + function =3D "qup0_se3"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi4_default: qup-spi4-default-state { + data-pins { + pins =3D "gpio117", "gpio118", "gpio119"; + function =3D "qup0_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio120"; + function =3D "qup0_se4"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi5_default: qup-spi5-default-state { + data-pins { + pins =3D "gpio109", "gpio121", "gpio122"; + function =3D "qup0_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio110"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi7_default: qup-spi7-default-state { + data-pins { + pins =3D "gpio123", "gpio124", "gpio125"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio126"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi8_default: qup-spi8-default-state { + data-pins { + pins =3D "gpio123", "gpio125", "gpio126"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio124"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi11_default: qup-spi11-default-state { + data-pins { + pins =3D "gpio131", "gpio132", "gpio137"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio138"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi12_default: qup-spi12-default-state { + data-pins { + pins =3D "gpio133", "gpio134", "gpio135"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio136"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi13_default: qup-spi13-default-state { + data-pins { + pins =3D "gpio131", "gpio137", "gpio138"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio132"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi14_default: qup-spi14-default-state { + data-pins { + pins =3D "gpio139", "gpio140", "gpio141"; + function =3D "qup2_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio142"; + function =3D "qup2_se0"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi16_default: qup-spi16-default-state { + data-pins { + pins =3D "gpio145", "gpio146", "gpio147"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio148"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi17_default: qup-spi17-default-state { + data-pins { + pins =3D "gpio150", "gpio151", "gpio152"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio153"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi18_default: qup-spi18-default-state { + data-pins { + pins =3D "gpio143", "gpio154", "gpio155"; + function =3D "qup2_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio144"; + function =3D "qup2_se4"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi19_default: qup-spi19-default-state { + data-pins { + pins =3D "gpio156", "gpio157", "gpio158"; + function =3D "qup2_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio159"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_spi20_default: qup-spi20-default-state { + data-pins { + pins =3D "gpio156", "gpio158", "gpio159"; + function =3D "qup2_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio157"; + function =3D "qup2_se6"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_uart0_default: qup-uart0-default-state { + pins =3D "gpio109", "gpio110"; + function =3D "qup0_se0"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart1_default: qup-uart1-default-state { + pins =3D "gpio109", "gpio110"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + pins =3D "gpio115", "gpio116"; + function =3D "qup0_se2"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart3_default: qup-uart3-default-state { + pins =3D "gpio113", "gpio114"; + function =3D "qup0_se3"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins =3D "gpio119", "gpio120"; + function =3D "qup0_se4"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + pins =3D "gpio109", "gpio110"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart7_default: qup-uart7-default-state { + pins =3D "gpio125", "gpio126"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart8_default: qup-uart8-default-state { + pins =3D "gpio123", "gpio124"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart9_default: qup-uart9-default-state { + pins =3D "gpio127", "gpio128"; + function =3D "qup1_se2"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart10_default: qup-uart10-default-state { + pins =3D "gpio129", "gpio130"; + function =3D "qup1_se3"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart11_default: qup-uart11-default-state { + pins =3D "gpio137", "gpio138"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart12_default: qup-uart12-default-state { + pins =3D "gpio135", "gpio136"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart13_default: qup-uart13-default-state { + pins =3D "gpio131", "gpio132"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart14_default: qup-uart14-default-state { + pins =3D "gpio141", "gpio142"; + function =3D "qup2_se0"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart15_default: qup-uart15-default-state { + pins =3D "gpio143", "gpio144"; + function =3D "qup2_se1"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart16_default: qup-uart16-default-state { + pins =3D "gpio147", "gpio148"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart17_default: qup-uart17-default-state { + pins =3D "gpio150", "gpio151", "gpio152", "gpio153"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart18_default: qup-uart18-default-state { + pins =3D "gpio143", "gpio144"; + function =3D "qup2_se4"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart19_default: qup-uart19-default-state { + pins =3D "gpio158", "gpio159"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart20_default: qup-uart20-default-state { + pins =3D "gpio156", "gpio157"; + function =3D "qup2_se6"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart0 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart0_default>; + pinctrl-names =3D "default"; +}; + +&uart1 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart1_default>; + pinctrl-names =3D "default"; +}; + +&uart2 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart2_default>; + pinctrl-names =3D "default"; +}; + +&uart3 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart3_default>; + pinctrl-names =3D "default"; +}; + +&uart4 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart4_default>; + pinctrl-names =3D "default"; +}; + +&uart5 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart5_default>; + pinctrl-names =3D "default"; +}; + +&uart7 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart7_default>; + pinctrl-names =3D "default"; +}; + +&uart8 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart8_default>; + pinctrl-names =3D "default"; +}; + +&uart9 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart9_default>; + pinctrl-names =3D "default"; +}; + +&uart10 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart10_default>; + pinctrl-names =3D "default"; +}; + +&uart11 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart11_default>; + pinctrl-names =3D "default"; +}; + +&uart12 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart12_default>; + pinctrl-names =3D "default"; +}; + +&uart13 { + clocks =3D <&segcc SE_GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart13_default>; + pinctrl-names =3D "default"; +}; + +&uart14 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart14_default>; + pinctrl-names =3D "default"; +}; + +&uart15 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart15_default>; + pinctrl-names =3D "default"; +}; + +&uart16 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart16_default>; + pinctrl-names =3D "default"; +}; + +&uart17 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart17_default>; + pinctrl-names =3D "default"; +}; + +&uart18 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart18_default>; + pinctrl-names =3D "default"; +}; + +&uart19 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart19_default>; + pinctrl-names =3D "default"; +}; + +&uart20 { + clocks =3D <&negcc NE_GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + pinctrl-0 =3D <&qup_uart20_default>; + pinctrl-names =3D "default"; +}; + +&ufs_mem_hc { + clocks =3D <&negcc NE_GCC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_UFS_PHY_AHB_CLK>, + <&negcc NE_GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&negcc NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + resets =3D <&negcc NE_GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + interconnects =3D <&aggre1_noc_tile MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + power-domains =3D <&negcc NE_GCC_UFS_PHY_GDSC>; + operating-points-v2 =3D <&ufs_opp_table>; + required-opps =3D <&rpmhpd_opp_nom>; + qcom,ice =3D <&ice>; + #reset-cells =3D <1>; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz =3D /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-403000000 { + opp-hz =3D /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f4538bc9bsm921225b3a.11.2026.08.06.01.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 01:17:06 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , Mukesh Savaliya , Yadu M G , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Krzysztof Kozlowski , Bartosz Golaszewski Subject: [PATCH v9 4/6] dt-bindings: arm: qcom: Document Nord reference boards Date: Thu, 6 Aug 2026 16:15:52 +0800 Message-ID: <20260806081554.448531-5-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> References: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=aNzAb79m c=1 sm=1 tr=0 ts=6a744303 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=3mLb7b5QgQ_nS9KBAK4A:9 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: fKy8lq2u2if_9bBnLczNWj36sM7gPSpx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX6lOyr94V9GtF JSek3Mf2ijPbJzHNGVop1HiilzvSAW5hDkIZZOs1fB53Uy821UhkWLIzE6rrwH/6tEXRJWqLZws suZ7rT15r3N2tJdg9k+1WIsSzdyI3GDMbFZQHeBp7gDBO8v3XZTNt9M3rw5ZB0WZW2sJhRxYizm QXtVIudAsqMmf4h7MuNIwca2KPs5JbfnJ4+9gPH81fR4Swvpw7AMViiEQAnwyC9XGZzzQd6XkzP +u/fTEma8wcwgMOGtX1tEF8yz8z65VP0laHIDY2BLJo6u2tvZduXGHechpP2pQCSud3/nva/30i jZI6ffmgL5dt0mkb9k2HmSauHtf/VmhZ0GENiXbllYNszntU4Vcex0lvc6FYtVKKJVVvm7JSBHj pfLRf94IuKGugRz78X/k1SRBQAJZMxNjvV/MsXsW9KLZ/S4D3dNxdx9oV5NsLv/d0seaBod5qjg 28jVLklaxSd1KOEmmaQ== X-Proofpoint-ORIG-GUID: fKy8lq2u2if_9bBnLczNWj36sM7gPSpx X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX6IWTPHnMPH6p xlHasTZFxGk/ZgSBHd43Maw7J0nTsfN/fcrtpL9QcW7MCx6sB5xpXnENHYmLXND3B+MCiTT86xB 9ERDSt28iL+ga6Md5+SWD9FlQzySgSg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-05_06,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 suspectscore=0 adultscore=0 clxscore=1015 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060063 Content-Type: text/plain; charset="utf-8" Nord is a new generation of SoC series from Qualcomm which includes SA8797P (for Automotive) and Dragonwing IQ10 (for IOT/Robotics). Document SA8797P Ride and IQ10 Robotics Reference Design (RRD) boards. Acked-by: Krzysztof Kozlowski Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index ff8a35df7862..198314ddaa84 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -402,6 +402,12 @@ properties: - xiaomi,sagit - const: qcom,msm8998 =20 + - items: + - enum: + - qcom,iq10-rrd + - qcom,sa8797p-ride + - const: qcom,nord + - description: Qualcomm Technologies, Inc. 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f4538bc9bsm921225b3a.11.2026.08.06.01.17.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 01:17:11 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , Mukesh Savaliya , Yadu M G , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski , Shawn Guo Subject: [PATCH v9 5/6] arm64: dts: qcom: Add device tree for Nord Ride board Date: Thu, 6 Aug 2026 16:15:53 +0800 Message-ID: <20260806081554.448531-6-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> References: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: o_2O03fFT6KXF2x62pJiOkEZ7kzK8KbW X-Proofpoint-ORIG-GUID: o_2O03fFT6KXF2x62pJiOkEZ7kzK8KbW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX1wYB4NfHYJY2 j2mKOhPaGKrpUcVxb1yBnq/mNI3niitjiKnzO7TXvXzY40oikPAfXvL3kOznqhklmJbcwGoEtIV QOT2S5+dGxAvMyGX/1F5EoSgtb2HuIryuquZLeXFx3r8K7jXZqUQchhcoXhZB6iTQ+MyiaEuI+R w92pH0+Kwtd0VRTvquUAh0e2roLkQA4zOoby9L160PLHCwPOYKb4mfo0V+O2LcUEClRB0ZTcbaV j7tm137i13KMTDZibbjzl/tLBX51kOb3uahMoQZJZHD2B9NRmTFq4lzOxtAy/2pJIdTXwJIHAhM fK0jP7sHoVA/srlKZ15lrt+vp5GSaq16O/tn8n955Y7rNi5ZX/cToqu2cfRBDcjBr3bhsdoS9Br d1LZFbppv+iIItTXweeDUFiJGnvEAurBCGswFd0pijUDE/0TlRXIPKGekNPXnmJIajKdHvr+B2Y GwzrsYKj26KnGt4acrg== X-Authority-Analysis: v=2.4 cv=K5cS2SWI c=1 sm=1 tr=0 ts=6a744308 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=2Hjw6vQzkyH4OD-tzjAA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX3YbpOzLH9tzM LE6cTtUNWC4BaQeEDb+dhoc8kmMVac2RArVY3VPH+skvdQQ0vCEpdKZpipxGXiGnDYMkRWJnulm yR/bq1im3odqxs5L7JAK1KnvILGROUU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-05_06,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060063 Content-Type: text/plain; charset="utf-8" From: Deepti Jaggi Add initial device tree for the Qualcomm SA8797P Ride reference board, which is built on Nord GearVM variant. - Configure UART15 as the primary console and UART4 as the secondary serial port - Enable UFS storage support - Define thermal zones for PMIC dies, UFS, and two SDRAM sensors, all sourced from SCMI sensor protocol on channel 23 Signed-off-by: Deepti Jaggi Reviewed-by: Bartosz Golaszewski Tested-by: Yadu M G Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/nord-ride.dts | 236 +++++++++++++++++++++++++ 2 files changed, 237 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/nord-ride.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 1c86e7e98f55..d05920a0d5eb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -160,6 +160,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-sony-xperia-yoshin= o-lilac.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-xiaomi-sagit.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D nord-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D purwa-iot-evk.dtb =20 purwa-iot-evk-el2-dtbs :=3D purwa-iot-evk.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/nord-ride.dts b/arch/arm64/boot/dts/q= com/nord-ride.dts new file mode 100644 index 000000000000..4a762e4ce62a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-ride.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "nord-gearvm.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. SA8797P Ride"; + compatible =3D "qcom,sa8797p-ride", "qcom,nord"; + + aliases { + serial0 =3D &uart15; + serial1 =3D &uart4; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + }; +}; + +&scmi3 { + status =3D "okay"; +}; + +&scmi11 { + status =3D "okay"; +}; + +&scmi23 { + status =3D "okay"; +}; + +&thermal_zones { + pmic_kobra_thermal: pmic-a-die-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 3>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmic_kai_0_thermal: pmic-e-die-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 4>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmic_kai_1_thermal: pmic-f-die-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 5>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmic_kai_2_thermal: pmic-g-die-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 6>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmic_kai_3_thermal: pmic-h-die-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 7>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmic_kai_4_thermal: pmic-i-die-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 8>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmic_kai_5_thermal: pmic-j-die-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 9>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmic_kai_6_thermal: pmic-k-die-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 10>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmic_kai_7_thermal: pmic-l-die-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 11>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmic_kai_ufs_thermal: ufs-thermal { + polling-delay-passive =3D <0>; + thermal-sensors =3D <&scmi23_sensor 0>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "critical"; + }; + }; + }; + + pmic_kai_sdram0_thermal: sdram0-thermal { + polling-delay-passive =3D <0>; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f4538bc9bsm921225b3a.11.2026.08.06.01.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 01:17:16 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , Mukesh Savaliya , Yadu M G , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Bartosz Golaszewski , Konrad Dybcio Subject: [PATCH v9 6/6] arm64: dts: qcom: Add device tree for Nord RRD board Date: Thu, 6 Aug 2026 16:15:54 +0800 Message-ID: <20260806081554.448531-7-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> References: <20260806081554.448531-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: vcYG88I8PjNRsGaquZETtLJtl0JTymxK X-Authority-Analysis: v=2.4 cv=Or9/DS/t c=1 sm=1 tr=0 ts=6a74430d cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=7kUQgkP5GImsC5sEelMA:9 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfXw00/yz+Zaz+V zEUcj0iE9qK5NfYjoSyf11o3CIcpDo8wH+U+r0cm6QD4QCA1xJBWI+/spWjVtAPHvY2LqeSzmJs YNH8RQoYjjgHwz9E3e58TdffPJ1Q2mA6EPZpS6vfUclWibAra50f1fpgunDZlQjsBQ6Ka5dtAdo OEmFTNdgqPLSBnsbWGs6JHOmk4xbIQJFw6fXTQMo7DYYgMVAaSjM9APBSg76YqLx05gqXgWRM9X Ntju/sAAhOtGchsLzQk13KNpx1zFgChrFJWHGfjyy6aZsqkZXkh0t1KMakbJzp2nqMuibfWV2aZ rZjRurb8EatXlwOXu27Fa4P/UtJ/voEQadiZL6LBn/y11/yEkRSsSEEYja6ZP3PdIn2xDKeoiqn auI9tPJ1qjjnpU1qCqDR1I9HgObbA2B7yL+6KYZvYYdurktaRJ+M3X5nnxeLdNV98JVPy/5mVsT xjzJJwE+vsThMS6jKJw== X-Proofpoint-GUID: vcYG88I8PjNRsGaquZETtLJtl0JTymxK X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDA2MyBTYWx0ZWRfX+sz+jQDAoA/x BJbbKrGTLqkr5tC+uOpJFrXF436Sz8N6UTb9ZOZiOvXYYni0ZuP7C7LL/eoR28I/CIm9+GBnLK7 6twSptuF4bKA2B94ETsWcJB1RnjhCeI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-05_06,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 priorityscore=1501 spamscore=0 bulkscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060063 Content-Type: text/plain; charset="utf-8" Add initial device tree for the Qualcomm Dragonwing IQ10 RRD (Robotics Reference Design) board, which is built on Nord Embedded variant. Enable the debug UART, UFS storage, PMICs, I2C and SPI. Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/nord-rrd.dts | 548 ++++++++++++++++++++++++++ 2 files changed, 549 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/nord-rrd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index d05920a0d5eb..38d326644146 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -161,6 +161,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-sony-xperia-yoshin= o-maple.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D nord-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D nord-rrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D purwa-iot-evk.dtb =20 purwa-iot-evk-el2-dtbs :=3D purwa-iot-evk.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qc= om/nord-rrd.dts new file mode 100644 index 000000000000..a2a19f2304fa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include + +#include "nord-embedded.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IQ10 RRD"; + compatible =3D "qcom,iq10-rrd", "qcom,nord"; + + aliases { + serial0 =3D &uart15; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + }; +}; + +&apps_rsc { + /* PMIC A - Kobra_MM (PMM8650AU) - SID 0x0, Bus E0 */ + regulators-0 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "A_E0"; + + vreg_l4a_1p2: ldo4 { + regulator-name =3D "vreg_l4a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name =3D "vreg_l6a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a_1p2: ldo7 { + regulator-name =3D "vreg_l7a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a_1p8: ldo8 { + regulator-name =3D "vreg_l8a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s1a_vdd2h_l: smps1 { + regulator-name =3D "vreg_s1a_vdd2h_l"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s3a_1p8: smps3 { + regulator-name =3D "vreg_s3a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s5a_mv: smps5 { + regulator-name =3D "vreg_s5a_mv"; + regulator-min-microvolt =3D <1328000>; + regulator-max-microvolt =3D <1370000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s6a_vddq_l: smps6 { + regulator-name =3D "vreg_s6a_vddq_l"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s8a_vdda_ebi: smps8 { + regulator-name =3D "vreg_s8a_vdda_ebi"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + }; + + /* PMIC E - Kai_MV - SID 0x4, Bus E0 */ + regulators-1 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "E_E0"; + + vreg_l1e_0p9: ldo1 { + regulator-name =3D "vreg_l1e_0p9"; + regulator-min-microvolt =3D <936000>; + regulator-max-microvolt =3D <936000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name =3D "vreg_l2e_0p9"; + regulator-min-microvolt =3D <936000>; + regulator-max-microvolt =3D <936000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3e_1p8: ldo3 { + regulator-name =3D "vreg_l3e_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s1e_nsp3: smps1 { + regulator-name =3D "vreg_s1e_nsp3"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s7e_mxa: smps7 { + regulator-name =3D "vreg_s7e_mxa"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + }; + + /* PMIC F - Kai_MV - SID 0x5, Bus E0 */ + regulators-2 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "F_E0"; + + vreg_l1f_vdd2l: ldo1 { + regulator-name =3D "vreg_l1f_vdd2l"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_vdd1: ldo3 { + regulator-name =3D "vreg_l3f_vdd1"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s1f_nsp1: smps1 { + regulator-name =3D "vreg_s1f_nsp1"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s7f_lv_sub: smps7 { + regulator-name =3D "vreg_s7f_lv_sub"; + regulator-min-microvolt =3D <1036000>; + regulator-max-microvolt =3D <1136000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s8f_vddq_h: smps8 { + regulator-name =3D "vreg_s8f_vddq_h"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC G - Kai_MV - SID 0x6, Bus E0 */ + regulators-3 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "G_E0"; + + vreg_l2g_0p7: ldo2 { + regulator-name =3D "vreg_l2g_0p7"; + regulator-min-microvolt =3D <752000>; + regulator-max-microvolt =3D <752000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s1g_nsp0: smps1 { + regulator-name =3D "vreg_s1g_nsp0"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s5g_vdd2h_h: smps5 { + regulator-name =3D "vreg_s5g_vdd2h_h"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1150000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + }; + + /* PMIC H - Kai_MV - SID 0x7, Bus E0 */ + regulators-4 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "H_E0"; + + vreg_l1h_0p9: ldo1 { + regulator-name =3D "vreg_l1h_0p9"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2h_1p2: ldo2 { + regulator-name =3D "vreg_l2h_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_s1h_nsp2: smps1 { + regulator-name =3D "vreg_s1h_nsp2"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s5h_mxc: smps5 { + regulator-name =3D "vreg_s5h_mxc"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC I - Kai_MV - SID 0x8, Bus E0 */ + regulators-5 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "I_E0"; + + vreg_l1i_0p9: ldo1 { + regulator-name =3D "vreg_l1i_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name =3D "vreg_l2i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3i_2p5: ldo3 { + regulator-name =3D "vreg_l3i_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s2i_gfx0: smps2 { + regulator-name =3D "vreg_s2i_gfx0"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s7i_mm: smps7 { + regulator-name =3D "vreg_s7i_mm"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC J - Kai_MV - SID 0x9, Bus E0 */ + regulators-6 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "J_E0"; + + vreg_s7j_gfx1: smps7 { + regulator-name =3D "vreg_s7j_gfx1"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC K - Kai_MV - SID 0xA, Bus E0 */ + regulators-7 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "K_E0"; + + vreg_l1k_vdd2l: ldo1 { + regulator-name =3D "vreg_l1k_vdd2l"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2k_0p9: ldo2 { + regulator-name =3D "vreg_l2k_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3k_vdd1: ldo3 { + regulator-name =3D "vreg_l3k_vdd1"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC L - Kai_MV - SID 0xB, Bus E0 */ + regulators-8 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "L_E0"; + + vreg_l3l_1p8: ldo3 { + regulator-name =3D "vreg_l3l_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s1l_nsp_mxc: smps1 { + regulator-name =3D "vreg_s1l_nsp_mxc"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s2l_cx: smps2 { + regulator-name =3D "vreg_s2l_cx"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&i2c7 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + rtc@32 { + compatible =3D "epson,rx8900"; + reg =3D <0x32>; + }; +}; + +&qupv3_0 { + firmware-name =3D "qcom/nord/qupv3fw.elf"; + + status =3D "okay"; +}; + +&qupv3_1 { + firmware-name =3D "qcom/nord/qupv3fw.elf"; + + status =3D "okay"; +}; + +&qupv3_2 { + firmware-name =3D "qcom/nord/qupv3fw.elf"; + + status =3D "okay"; +}; + +&spi16 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +&uart15 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 181 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l3i_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l2i_1p2>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1i_0p9>; + vdda-pll-supply =3D <&vreg_l2h_1p2>; + + status =3D "okay"; +}; --=20 2.43.0