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Thu, 6 Aug 2026 00:31:06 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Aleksandr Loktionov , Alexander Lobakin , Arthur Kiyanovski , Daniel Zahka , David Ahern , "Gal Pressman" , Jiri Pirko , Jiri Pirko , Jonathan Corbet , Leon Romanovsky , , , , Mark Bloch , Nikolay Aleksandrov , "Nikolay Aleksandrov" , Petr Machata , "Przemek Kitszel" , Ratheesh Kannoth , Saeed Mahameed , Shuah Khan , Simon Horman , Tariq Toukan , Vlad Dumitrescu Subject: [PATCH net-next V5 1/2] devlink: add generic device max_sfs parameter Date: Thu, 6 Aug 2026 10:30:36 +0300 Message-ID: <20260806073037.3001886-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260806073037.3001886-1-tariqt@nvidia.com> References: <20260806073037.3001886-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F67:EE_|DM4PR12MB5771:EE_ X-MS-Office365-Filtering-Correlation-Id: 4a002d63-8c24-480e-0ae9-08def38cbd7e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|1800799024|36860700016|376014|7416014|18002099003|22082099003|11063799006|6133799003|10067099003|56012099006; X-Microsoft-Antispam-Message-Info: bPE3r9mMAm7Z+X1bpzNACEeZlRHF5sRtn8d4YUnb1K3l0LmpZAPhIzCrTTKHmzJLnvNo8/YuG4Y6EXp927/rAD7z52EMW8jmJkV/Ps1j+Ydn/XDhaPw+1JZTOdNasEyQ9l2MXxrqDGqE9CajRTEsJgmX1HuJ5L9s/gN20lj5NHCDnq6tzVOotCWn+zo1fmMYimK8ElX67bRXEiF8uVd94BlAKSrdK8XEAjMwlhcPKOpQh7iaPaymtyFckAePyMLYQTW2mcIAyf0j+Yx98NDikO0e1kR0+R+hqJwcpF+8/ecZF2lDK2Cg2SXWx9tgOnMSCy69sNCcYAjWAauojgSPH+JVlrMqXxiMZHT7uI57xBWJN2s+KPky6x8l+BjWeKYHgBoZ4pS3SLvrtdbznxZOkeBZPNq5EqzdORRV9RkuuvBex30hzgf7iAA5O1Uq3n5FoOixdR/bz3ZH4dS9YuKqQdhkgd9u9HhfEwrsOMdier37812flH3DiAPp79YyuGLcdf2BIb65du0ALirRdV2WZYRpYGD8ySFJXuSZbO2rdnaIrIWFWo8TU+0Zr6PJIuksD67M2q/zBj4aE3TZ2dZfvO4oJ4xAhUFAGVrM1NVbRBMVwgMkWT8JwVQCunNB1+1vdI5Qf92Ma+fM2sPFNSf3JKUKgNY/0VsG4JLaILruOmC4QEr32RQu/U0zsPQKjuwML0mXoqLbzQXSm6nJvarfmw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(82310400026)(1800799024)(36860700016)(376014)(7416014)(18002099003)(22082099003)(11063799006)(6133799003)(10067099003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vItmtIluCpyk55KXo+kBbedz2N3By4LUVM59jmEwuSm2wmkT+zzDLlgnDqKlqNgWol6SMAMdtPaE5YxREHuqqmOG6HDCkLE5n/DJpIZeGp19thy6o3085ehgPR3zUnstJqEXS0cU351hT/aWuYXHJqK42Dn9H7oOdB7/KgIFyvCv/6p5hz7x2ccWP9fYAOQ1qdkKOIBomqFMKK6la9/zpHoh45I6NZ7Pe/LaoT4cQGefPWNRcyv28NKLCvQbyLZNmR879rG1XG6i9UQFr1z/0EenukxHXoUbbXar12Mav5zGt/hGNMEwPlycHFQn/WIPb7+P0BSA9qB1kE8VSiyvlxyLWIcwtvoY323zUlFmmB9LSnV1gG20VHF7jhsV7+SxeE4yeYGJ5rl6694Y3wcpBwhFqZwymXN+HriTQGKonSgR3PK9KAK9tKjL3lRV6C5Z X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 07:31:33.2499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4a002d63-8c24-480e-0ae9-08def38cbd7e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F67.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5771 Content-Type: text/plain; charset="utf-8" From: Nikolay Aleksandrov Add a new generic devlink device parameter (max_sfs) to control if and how many light-weight NIC subfunctions can be created. Subfunctions are a light-weight network functions backed by an underlying PCI function. Their lifecycle can already be managed by devlink, but currently users cannot enable them in the device. They can be enabled/disabled only via external vendor tools. This parameter allows subfunctions to be enabled (>0) or disabled (0) via devlink. A subsequent patch will add support for max_sfs to the mlx5 driver. Signed-off-by: Nikolay Aleksandrov Reviewed-by: David Ahern Reviewed-by: Jiri Pirko Reviewed-by: Aleksandr Loktionov Reviewed-by: Alexander Lobakin Signed-off-by: Tariq Toukan --- Documentation/networking/devlink/devlink-params.rst | 6 ++++++ include/net/devlink.h | 4 ++++ net/devlink/param.c | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/Documentation/networking/devlink/devlink-params.rst b/Document= ation/networking/devlink/devlink-params.rst index ca19ee3e63c8..13eb8aa84c38 100644 --- a/Documentation/networking/devlink/devlink-params.rst +++ b/Documentation/networking/devlink/devlink-params.rst @@ -165,3 +165,9 @@ own name. - u32 - Controls the maximum number of MAC address filters that can be assi= gned to a Virtual Function (VF). + * - ``max_sfs`` + - u32 + - The maximum number of subfunctions which can be created on the devi= ce. + Modifying this parameter may require a device restart and PCI bus + rescanning because the BAR layout may change. A value of 0 disables + subfunction creation. diff --git a/include/net/devlink.h b/include/net/devlink.h index 4830aba4087a..7abd23376319 100644 --- a/include/net/devlink.h +++ b/include/net/devlink.h @@ -554,6 +554,7 @@ enum devlink_param_generic_id { DEVLINK_PARAM_GENERIC_ID_TOTAL_VFS, DEVLINK_PARAM_GENERIC_ID_NUM_DOORBELLS, DEVLINK_PARAM_GENERIC_ID_MAX_MAC_PER_VF, + DEVLINK_PARAM_GENERIC_ID_MAX_SFS, =20 /* add new param generic ids above here*/ __DEVLINK_PARAM_GENERIC_ID_MAX, @@ -627,6 +628,9 @@ enum devlink_param_generic_id { #define DEVLINK_PARAM_GENERIC_MAX_MAC_PER_VF_NAME "max_mac_per_vf" #define DEVLINK_PARAM_GENERIC_MAX_MAC_PER_VF_TYPE DEVLINK_PARAM_TYPE_U32 =20 +#define DEVLINK_PARAM_GENERIC_MAX_SFS_NAME "max_sfs" +#define DEVLINK_PARAM_GENERIC_MAX_SFS_TYPE DEVLINK_PARAM_TYPE_U32 + #define DEVLINK_PARAM_GENERIC(_id, _cmodes, _get, _set, _validate) \ { \ .id =3D DEVLINK_PARAM_GENERIC_ID_##_id, \ diff --git a/net/devlink/param.c b/net/devlink/param.c index 1cc562a6ebfd..8ca0f3ed646c 100644 --- a/net/devlink/param.c +++ b/net/devlink/param.c @@ -117,6 +117,11 @@ static const struct devlink_param devlink_param_generi= c[] =3D { .name =3D DEVLINK_PARAM_GENERIC_MAX_MAC_PER_VF_NAME, .type =3D DEVLINK_PARAM_GENERIC_MAX_MAC_PER_VF_TYPE, }, + { + .id =3D DEVLINK_PARAM_GENERIC_ID_MAX_SFS, + .name =3D DEVLINK_PARAM_GENERIC_MAX_SFS_NAME, + .type =3D DEVLINK_PARAM_GENERIC_MAX_SFS_TYPE, + }, }; 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Thu, 6 Aug 2026 00:31:12 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Aleksandr Loktionov , Alexander Lobakin , Arthur Kiyanovski , Daniel Zahka , David Ahern , "Gal Pressman" , Jiri Pirko , Jiri Pirko , Jonathan Corbet , Leon Romanovsky , , , , Mark Bloch , Nikolay Aleksandrov , "Nikolay Aleksandrov" , Petr Machata , "Przemek Kitszel" , Ratheesh Kannoth , Saeed Mahameed , Shuah Khan , Simon Horman , Tariq Toukan , Vlad Dumitrescu Subject: [PATCH net-next V5 2/2] net/mlx5: implement max_sfs parameter Date: Thu, 6 Aug 2026 10:30:37 +0300 Message-ID: <20260806073037.3001886-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260806073037.3001886-1-tariqt@nvidia.com> References: <20260806073037.3001886-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F65:EE_|SA1PR12MB7245:EE_ X-MS-Office365-Filtering-Correlation-Id: 43ad870a-0ff5-40b1-15eb-08def38cc0ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|7416014|376014|23010399003|18002099003|22082099003|11063799006|56012099006|3023799007|6133799003|10067099003; X-Microsoft-Antispam-Message-Info: zp3Z5HRsOyzFEkb4lZ4ryUbsXxnsJ/3PNzUglUtx0AKVaC0MqaKcVmm1zmEjsoEjxkTreqw/2haxCE/4sIfJkSUsrtXvzw+IRhrzTsJeG68kSTUJYZcPwXNmoYX3cFzPLKjQUp+Wy47GPD+lavWO10Qrp9AuVXFc0pi/CNBJkDnRX8WgMx63pnG2Ah50w7garODuchUSki1LKfa9/cv7lsgYwtArriXqBPJKqG6NnGLsA6AQF7pRd9DMZnY1anZlNZTkqzQP/mIRwciKKo1/5s64BORPYYp9qX8J5+uFrdHrm//6hBdR40sWhVR1Ha1hhBexrcdVqa9eubd5Tfx269XWwz4koT76Z/XvOg4GzDDNq72DjOpWH95P3+uLwIPEUi8XWofSF0xcCAu8ndiVd0quY54RGDDzSdNpVBNUVVI9lZvuMHiPRrrcGl+gO1il8l66z8ibTqWwJbSRw4BgysjwOeMbe7ZJOGUGz78nCqynX9KONv/3ce4vsEmk5XgH8Ie5Tx5sKhwYC3L+qIw8dPRtlm2qnPuiPLBaJbiFz0rmpg2uuS+RV/kglKS/NYLSfHOj7Xkqkx7QNC0UXihokWewRI/ncHiXbYeAe/FhayS0mB7s4sBCTyVDmWPQKELI/su9bK/9UAOKoIRBPatca9vPGnOPXsLT60EqxArsp0wCD/4GdeVh4OsiEcwJMEmm5zJVbmOrzuTXQ36YdVzTyQ== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(7416014)(376014)(23010399003)(18002099003)(22082099003)(11063799006)(56012099006)(3023799007)(6133799003)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5bKTvz2+tiMb3rS8eQICgfmkWgkmvn1ZpXJlOwkAAcuc4GN+ZxPzCPuPBcCBdZByrYSyDjK5vCtc7J5t58Pj+RAWpbAdIgzBCRIlUiGzEOdG5EI6KHocnI0EjwjIGYkigCLpF54MOidOt1mRsiC7DFQcw/xIXIshlo6udkhvjvBfeFUhoZfTfRz2v9pA8thVx78BDDJ/DY0esf0j5hG2QsWMbW83CvrlUvktfdFDr/2UopeJOTgUy0myma8/Toa1vp/y4Wiv6h9eX4glpQ/TaMGMTxrWwryk4aAOOk32leH37hx5Y51JrP5l5JGGQPH8hbGO5Z3wM+ClTe0iXmlsJz0TJqBB6yRiStwA8D+MZr3z0Rb8GBLptQUflSjFQ+rn5GLoQ3qv9gf+bsTwBfJWmWZLjAuLMMvOU6IlLaIWzY7D9Dnt3sw7gsPxevDgQAaH X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2026 07:31:38.6231 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43ad870a-0ff5-40b1-15eb-08def38cc0ba X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F65.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7245 Content-Type: text/plain; charset="utf-8" From: Nikolay Aleksandrov Implement max_sfs generic parameter to allow users to control the total light-weight NIC subfunctions that can be created using devlink instead of external vendor tools. A value of 0 will effectively disable creation of new subfunction devices. A warning is sent to user-space via extack (returning extack without error code is interpreted as a warning by user-space tools). The maximum value is capped at U16_MAX. Signed-off-by: Nikolay Aleksandrov Reviewed-by: David Ahern Reviewed-by: Alexander Lobakin Signed-off-by: Tariq Toukan --- Documentation/networking/devlink/mlx5.rst | 7 +- .../mellanox/mlx5/core/lib/nv_param.c | 125 +++++++++++++++++- 2 files changed, 128 insertions(+), 4 deletions(-) diff --git a/Documentation/networking/devlink/mlx5.rst b/Documentation/netw= orking/devlink/mlx5.rst index cf1dffa67669..9421c89951a0 100644 --- a/Documentation/networking/devlink/mlx5.rst +++ b/Documentation/networking/devlink/mlx5.rst @@ -45,8 +45,13 @@ Parameters - The range is between 1 and a device-specific max. - Applies to each physical function (PF) independently, if the device supports it. Otherwise, it applies symmetrically to all PFs. + * - ``max_sfs`` + - permanent + - The range is between 0 and a device-specific max. + - Applies to each physical function (PF) independently. =20 -Note: permanent parameters such as ``enable_sriov`` and ``total_vfs`` requ= ire FW reset to take effect +Note: permanent parameters such as ``enable_sriov``, ``total_vfs`` and ``m= ax_sfs`` + require FW reset to take effect =20 .. code-block:: bash =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c b/drive= rs/net/ethernet/mellanox/mlx5/core/lib/nv_param.c index 4a7275e8b62e..72cc8da5f119 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c @@ -68,7 +68,9 @@ struct mlx5_ifc_mnvda_reg_bits { =20 struct mlx5_ifc_nv_global_pci_conf_bits { u8 sriov_valid[0x1]; - u8 reserved_at_1[0x10]; + u8 reserved_at_1[0xa]; + u8 per_pf_num_sf[0x1]; + u8 reserved_at_c[0x5]; u8 per_pf_total_vf[0x1]; u8 reserved_at_12[0xe]; =20 @@ -93,9 +95,11 @@ struct mlx5_ifc_nv_global_pci_cap_bits { }; =20 struct mlx5_ifc_nv_pf_pci_conf_bits { - u8 reserved_at_0[0x9]; + u8 log_sf_bar_size[0x8]; + u8 pf_total_sf_en[0x1]; u8 pf_total_vf_en[0x1]; - u8 reserved_at_a[0x16]; + u8 reserved_at_a[0x6]; + u8 total_sf[0x10]; =20 u8 reserved_at_20[0x20]; =20 @@ -158,6 +162,8 @@ struct mlx5_ifc_nv_sw_accelerate_conf_bits { #define MLX5_GET_CFG_HDR_LEN(_mnvda_ptr) \ MLX5_GET(mnvda_reg, _mnvda_ptr, configuration_item_header.length) =20 +#define MLX5_DEFAULT_LOG_SF_BAR_SIZE 12 + static int mlx5_nv_param_read(struct mlx5_core_dev *dev, void *mnvda, size_t len) { @@ -755,6 +761,115 @@ static int mlx5_devlink_total_vfs_validate(struct dev= link *devlink, u32 id, return 0; } =20 +static int mlx5_devlink_max_sfs_get(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct mlx5_core_dev *dev =3D devlink_priv(devlink); + u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] =3D {}; + void *data; + int err; + + err =3D mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to read global PCI configuration"); + return err; + } + + data =3D MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + if (!MLX5_GET(nv_global_pci_conf, data, per_pf_num_sf)) { + ctx->val.vu32 =3D 0; + return 0; + } + + memset(mnvda, 0, sizeof(mnvda)); + err =3D mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "Failed to read PF configuration"); + return err; + } + + data =3D MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + if (MLX5_GET(nv_pf_pci_conf, data, pf_total_sf_en)) + ctx->val.vu32 =3D MLX5_GET(nv_pf_pci_conf, data, total_sf); + else + ctx->val.vu32 =3D 0; + + return 0; +} + +static int mlx5_devlink_max_sfs_validate(struct devlink *devlink, u32 id, + union devlink_param_value *val, + struct netlink_ext_ack *extack) +{ + if (val->vu32 > U16_MAX) { + NL_SET_ERR_MSG_FMT_MOD(extack, + "Max SFs allowed value is %u", U16_MAX); + return -EINVAL; + } + + return 0; +} + +static int mlx5_devlink_max_sfs_set(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct mlx5_core_dev *dev =3D devlink_priv(devlink); + u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] =3D {}; + void *data; + int err; + + /* we don't explicitly disable per_pf_num_sf when max_sfs is 0 because + * another PF may be using SFs + */ + if (ctx->val.vu32) { + err =3D mlx5_nv_param_read_global_pci_conf(dev, mnvda, + sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to read global PCI configuration"); + return err; + } + + data =3D MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + /* always enable per_pf_num_sf because another PF may use SFs */ + MLX5_SET(nv_global_pci_conf, data, per_pf_num_sf, 1); + + err =3D mlx5_nv_param_write(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to change per_pf_num_sf global PCI configuration"); + return err; + } + memset(mnvda, 0, sizeof(mnvda)); + } + + err =3D mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "Failed to read PF configuration"); + return err; + } + + data =3D MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + MLX5_SET(nv_pf_pci_conf, data, log_sf_bar_size, + ctx->val.vu32 ? MLX5_DEFAULT_LOG_SF_BAR_SIZE : 0); + MLX5_SET(nv_pf_pci_conf, data, pf_total_sf_en, !!ctx->val.vu32); + MLX5_SET(nv_pf_pci_conf, data, total_sf, ctx->val.vu32); + + err =3D mlx5_nv_param_write(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to change PF PCI configuration"); + return err; + } + NL_SET_ERR_MSG_MOD(extack, + "Modifying max_sfs requires a FW reset and PCI bus rescan"); + + return 0; +} + static const struct devlink_param mlx5_nv_param_devlink_params[] =3D { DEVLINK_PARAM_GENERIC(ENABLE_SRIOV, BIT(DEVLINK_PARAM_CMODE_PERMANENT), mlx5_devlink_enable_sriov_get, @@ -763,6 +878,10 @@ static const struct devlink_param mlx5_nv_param_devlin= k_params[] =3D { mlx5_devlink_total_vfs_get, mlx5_devlink_total_vfs_set, mlx5_devlink_total_vfs_validate), + DEVLINK_PARAM_GENERIC(MAX_SFS, BIT(DEVLINK_PARAM_CMODE_PERMANENT), + mlx5_devlink_max_sfs_get, + mlx5_devlink_max_sfs_set, + mlx5_devlink_max_sfs_validate), DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_CQE_COMPRESSION_TYPE, "cqe_compress_type", DEVLINK_PARAM_TYPE_STRING, BIT(DEVLINK_PARAM_CMODE_PERMANENT), --=20 2.44.0