From nobody Fri Oct 2 02:32:14 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1C5343B5843; Thu, 6 Aug 2026 02:14:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982499; cv=none; b=abAHTmo9j1Ci6Gb+3NFsrLrha0wuoAzShssSwumje94nrJR1dL65lBBxv9QvqSILj/KiFNsI2G667HKD8vH08CFdjdjRK/EGQwK5D+8fMnPlBh1MzGX/sPbjn5j3e0iJL4NqeIVAGGld4XZxmrrr1Kzl0FKGM1/kkklToiUaANg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982499; c=relaxed/simple; bh=odb8gyvTrWJ1VPtBH6EFBmPze/YZHWTjZGsZosBDE70=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HUSa4J/He7vLypW6NrLk6P7QRnDoXAebQnZhEpZl+HUjuhYlHQO1iUqNrTno0eM1fZmgGoE+KvhRWJosYDRLE4UnzDpVPCXKo+gZzbMtjUP9WAWFJrz5Kxl1RvZZ58qTUgNBUQW/O4YgsiedXrHazjNVKYSceswT3c7VAf/ujmM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxyvAf7nNqItsKAA--.35006S3; Thu, 06 Aug 2026 10:14:55 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBx3wce7nNqB1QlAA--.7102S3; Thu, 06 Aug 2026 10:14:54 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: Sean Christopherson , Paolo Bonzini , WANG Xuerui , Arnd Bergmann , Xi Ruoyao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] LoongArch: KVM: Add vmid support for stage2 MMU Date: Thu, 6 Aug 2026 10:07:35 +0800 Message-Id: <20260806020739.2149268-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260806020739.2149268-1-maobibo@loongson.cn> References: <20260806020739.2149268-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBx3wce7nNqB1QlAA--.7102S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" LoongArch KVM hypervisor supports two-level MMU, vpid index is used for stage1 MMU and vmid index is used for stage2 MMU. On 3A5000, vmid must be the same with vpid. On 3A6000 platform vmid may separate from vpid. If vCPU migrate to different physical CPUs, vpid need change however vmid can keep unchanged, so that TLB entries for stage2 MMU is valid still. Also vmid index of the whole VM machine is the same on one physical CPU, all vCPUs on the VM can share the same vmid index on one physical CPU. Here hw vmid index is added and it keeps the same with hw vpid still. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_host.h | 3 +++ arch/loongarch/kernel/asm-offsets.c | 1 + arch/loongarch/kvm/main.c | 1 + arch/loongarch/kvm/switch.S | 5 ++--- arch/loongarch/kvm/tlb.c | 5 ++++- 5 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include= /asm/kvm_host.h index 23cfbecebbd7..78f97dea124d 100644 --- a/arch/loongarch/include/asm/kvm_host.h +++ b/arch/loongarch/include/asm/kvm_host.h @@ -232,6 +232,9 @@ struct kvm_vcpu_arch { /* Cache for pages needed inside spinlock regions */ struct kvm_mmu_memory_cache mmu_page_cache; =20 + /* hw vmid info for guest VM */ + unsigned long hw_vmid; + /* vcpu's vpid */ u64 vpid; gpa_t flush_gpa; diff --git a/arch/loongarch/kernel/asm-offsets.c b/arch/loongarch/kernel/as= m-offsets.c index 1b861cbc5e10..065ced1f3c1f 100644 --- a/arch/loongarch/kernel/asm-offsets.c +++ b/arch/loongarch/kernel/asm-offsets.c @@ -300,6 +300,7 @@ static void __used output_kvm_defines(void) OFFSET(KVM_ARCH_HSP, kvm_vcpu_arch, host_sp); OFFSET(KVM_ARCH_HTP, kvm_vcpu_arch, host_tp); OFFSET(KVM_ARCH_HPGD, kvm_vcpu_arch, host_pgd); + OFFSET(KVM_ARCH_VMID, kvm_vcpu_arch, hw_vmid); OFFSET(KVM_ARCH_KVMPGD, kvm_vcpu_arch, kvm_pgd); OFFSET(KVM_ARCH_HANDLE_EXIT, kvm_vcpu_arch, handle_exit); OFFSET(KVM_ARCH_HEENTRY, kvm_vcpu_arch, host_eentry); diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index 3e1005526f4b..401c84f38e8c 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -223,6 +223,7 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int = cpu) =20 context->vpid_cache =3D vpid; vcpu->arch.vpid =3D vpid; + vcpu->arch.hw_vmid =3D vcpu->arch.vpid & vpid_mask; } =20 void kvm_check_vpid(struct kvm_vcpu *vcpu) diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S index 936e4ae3e408..af972394fd55 100644 --- a/arch/loongarch/kvm/switch.S +++ b/arch/loongarch/kvm/switch.S @@ -66,9 +66,8 @@ ld.d t0, a2, KVM_ARCH_KVMPGD csrwr t0, LOONGARCH_CSR_PGDL =20 - /* Mix GID and RID */ - csrrd t1, LOONGARCH_CSR_GSTAT - bstrpick.w t1, t1, CSR_GSTAT_GID_SHIFT_END, CSR_GSTAT_GID_SHIFT + /* Set VMID for gpa --> hpa mapping */ + ld.d t1, a2, KVM_ARCH_VMID csrrd t0, LOONGARCH_CSR_GTLBC bstrins.w t0, t1, CSR_GTLBC_TGID_SHIFT_END, CSR_GTLBC_TGID_SHIFT csrwr t0, LOONGARCH_CSR_GTLBC diff --git a/arch/loongarch/kvm/tlb.c b/arch/loongarch/kvm/tlb.c index ebdbe9264e9c..b25847aab968 100644 --- a/arch/loongarch/kvm/tlb.c +++ b/arch/loongarch/kvm/tlb.c @@ -23,7 +23,10 @@ void kvm_flush_tlb_all(void) =20 void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa) { + unsigned int vmid; + lockdep_assert_irqs_disabled(); gpa &=3D (PAGE_MASK << 1); - invtlb(INVTLB_GID_ADDR, read_csr_gstat() & CSR_GSTAT_GID, gpa); + vmid =3D (vcpu->arch.hw_vmid << CSR_GSTAT_GID_SHIFT) & CSR_GSTAT_GID; + invtlb(INVTLB_GID_ADDR, vmid, gpa); } --=20 2.39.3 From nobody Fri Oct 2 02:32:14 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8A1DC3B6C12; Thu, 6 Aug 2026 02:14:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982500; cv=none; b=UzGvfpBQw+Gm2kTbS4Gql/mjqbP/l8KRJ5oD5T9CiwC4X0QXOHzGJ+0bfcPTWAgKCfsjnyXqgTvpXRigD36InaH7khLOAqxp1JZTUkPXHuP4jdxvs8KuEWNENpZkgL7SPG9a2CcbSctjo+DNJPzA+gZmeyIpbg40WZExHCnqqEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982500; c=relaxed/simple; bh=9K7em9CH/pE8OuUB+llqO/Oynnahu2JvHPf10AVk95A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nONSZynl/Xms13aDmjH/+aVZv4aBnhN2SKjuKJCEUCY9Dp2aviP8DEJioT2u2rZNsDqJJ7Xnvub1kYEmIeWnDvmptEjOZVn/fzhjLnVOMChauL4yH1y5cdoscxVNUJkz2nnUl+cjQVf5c3jTxeNI0Y6bEz/5ahYtYDjrHrCUQy0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxWqEf7nNqLtsKAA--.11960S3; Thu, 06 Aug 2026 10:14:55 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBx3wce7nNqB1QlAA--.7102S4; Thu, 06 Aug 2026 10:14:55 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: Sean Christopherson , Paolo Bonzini , WANG Xuerui , Arnd Bergmann , Xi Ruoyao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] LoongArch: KVM: Add separate vCPU and VM id update function Date: Thu, 6 Aug 2026 10:07:36 +0800 Message-Id: <20260806020739.2149268-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260806020739.2149268-1-maobibo@loongson.cn> References: <20260806020739.2149268-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBx3wce7nNqB1QlAA--.7102S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" There are two-level MMU on LoongArch KVM system, the first level (stage1) MMU is mapping for GVA --> GPA, the second level (stage2) is mapping for GPA --> HPA. Similar with ASID, there is different ID management to support multiple VMs and vCPUs. The stage1 MMU is called VPID, and the second MMU is called VMID, the corresponding ID management function is __kvm_check_vpid() and __kvm_check_vmid(). Signed-off-by: Bibo Mao --- arch/loongarch/kvm/main.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index 401c84f38e8c..ac804e77e844 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -223,10 +223,9 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int= cpu) =20 context->vpid_cache =3D vpid; vcpu->arch.vpid =3D vpid; - vcpu->arch.hw_vmid =3D vcpu->arch.vpid & vpid_mask; } =20 -void kvm_check_vpid(struct kvm_vcpu *vcpu) +static void __kvm_check_vpid(struct kvm_vcpu *vcpu) { int cpu; bool migrated; @@ -254,7 +253,6 @@ void kvm_check_vpid(struct kvm_vcpu *vcpu) kvm_update_vpid(vcpu, cpu); trace_kvm_vpid_change(vcpu, vcpu->arch.vpid); vcpu->cpu =3D cpu; - kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); =20 /* * LLBCTL is a separated guest CSR register from host, a general @@ -280,6 +278,23 @@ void kvm_check_vpid(struct kvm_vcpu *vcpu) } } =20 +static void __kvm_check_vmid(struct kvm_vcpu *vcpu) +{ + unsigned long vmid; + + vmid =3D vcpu->arch.vpid & vpid_mask; + if (vcpu->arch.hw_vmid !=3D vmid) { + vcpu->arch.hw_vmid =3D vcpu->arch.vpid & vpid_mask; + kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); + } +} + +void kvm_check_vpid(struct kvm_vcpu *vcpu) +{ + __kvm_check_vpid(vcpu); + __kvm_check_vmid(vcpu); +} + void kvm_init_vmcs(struct kvm *kvm) { kvm->arch.vmcs =3D vmcs; --=20 2.39.3 From nobody Fri Oct 2 02:32:14 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D07433B71AD; Thu, 6 Aug 2026 02:14:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982499; cv=none; b=nOmX6hMY5AASL+5bsqu9dVBr5xLk31xSKBifJYDX4ycBdkiyc/A8Q9nKEh7rI60c2eKiKCfIv/9nuYtX01RLOJgSUxO+rqLQYAdCHu+7gwWgRYyuVWI4ackVdcX9x77VCApJZTgba8kG1adbcud+c87dVwraQ0LoAVOQhJ/pWJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982499; c=relaxed/simple; bh=mq0+r5Y3TSjSaid7n9JBYBQEiS+qH7k4yc7FfrOG6NQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=h/JWOp3H0B/KVp6Fh1WSLEpjDMaHNof3cIw6gH4Tjvx3VELDFV5GimDa/9j0EOhg1hI03r3szBhfczWIN0B1VAdMDBwOvYMmh5q3xFwdWCVLZjrQ4ocQhKxugKvzu4lw9cGP1mM75fG9ZOT7BQ5Fz4fuQSEv0AptBvQyxPO72Mg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxvKEg7nNqM9sKAA--.11711S3; Thu, 06 Aug 2026 10:14:56 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBx3wce7nNqB1QlAA--.7102S5; Thu, 06 Aug 2026 10:14:55 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: Sean Christopherson , Paolo Bonzini , WANG Xuerui , Arnd Bergmann , Xi Ruoyao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] LoongArch: KVM: Add separate vmid feature support Date: Thu, 6 Aug 2026 10:07:37 +0800 Message-Id: <20260806020739.2149268-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260806020739.2149268-1-maobibo@loongson.cn> References: <20260806020739.2149268-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBx3wce7nNqB1QlAA--.7102S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Feature cpu_has_guestid is used to check whether separate vmid/vpid is supported or not. It is disabled by default, add this feature checking, there is no function change. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/main.c | 14 +++++++++----- arch/loongarch/kvm/mmu.c | 6 ++++-- arch/loongarch/kvm/vcpu.c | 3 ++- 3 files changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index ac804e77e844..c36e62ab0d91 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -218,7 +218,8 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int = cpu) ++vpid; /* vpid 0 reserved for root */ =20 /* start new vpid cycle */ - kvm_flush_tlb_all(); + if (!cpu_has_guestid) + kvm_flush_tlb_all(); } =20 context->vpid_cache =3D vpid; @@ -282,10 +283,13 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu) { unsigned long vmid; =20 - vmid =3D vcpu->arch.vpid & vpid_mask; - if (vcpu->arch.hw_vmid !=3D vmid) { - vcpu->arch.hw_vmid =3D vcpu->arch.vpid & vpid_mask; - kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); + /* On some machines like 3A5000, vmid needs the same with vpid */ + if (!cpu_has_guestid) { + vmid =3D vcpu->arch.vpid & vpid_mask; + if (vcpu->arch.hw_vmid !=3D vmid) { + vcpu->arch.hw_vmid =3D vcpu->arch.vpid & vpid_mask; + kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); + } } } =20 diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c index e104897aa532..714640a2e614 100644 --- a/arch/loongarch/kvm/mmu.c +++ b/arch/loongarch/kvm/mmu.c @@ -929,8 +929,10 @@ int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigne= d long gpa, bool write, in * * With SW PTW, invalid TLB is added in TLB refill exception. */ - vcpu->arch.flush_gpa =3D gpa; - kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); + if (!cpu_has_guestid) { + vcpu->arch.flush_gpa =3D gpa; + kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); + } } =20 return 0; diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index 20c207d80e31..0b2355aec932 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -210,7 +210,8 @@ static int kvm_check_requests(struct kvm_vcpu *vcpu) return RESUME_GUEST; =20 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) - vcpu->arch.vpid =3D 0; /* Drop vpid for this vCPU */ + if (!cpu_has_guestid) + vcpu->arch.vpid =3D 0; /* Drop vpid for this vCPU */ =20 if (kvm_dirty_ring_check_request(vcpu)) return RESUME_HOST; --=20 2.39.3 From nobody Fri Oct 2 02:32:14 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CA57B3BB13B; Thu, 6 Aug 2026 02:15:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982504; cv=none; b=gYXXERs2q5n6Z6o9BwxgkA99xKpgqDXglBK3lS4GHpTojpQVZwti2cqvtqMZ6J/lFD9Jt9229B0xhzHW7OWxv5IpqQh5W4O/yuOQYsBxW4vF94XSnZ6lSwToowlWLCBNdUuzqx8ZKviCsYnbyOoPqkVpOB77rF1uCxaOB9/Oy/w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982504; c=relaxed/simple; bh=vLqje1R0wmw0hkuEkX2+EcU/OagBhQaMLcK5D1Yeg8w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dUr3vrbtr1DhW7T4CDRgsvogr8K4PagB9pS+iD3/mPndS/XwGUuvv5U7C4r1w3+aOSue0YfTayTVLPIbKG+fmd/Jvj3l+kbb7yWiBb25tRAPxe+DOCj3N4/oddY0PG92Xzs1q41NQRpFsIJs4lgnpt37p/cMiQtZiUm989wihtk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxyvAj7nNqQNsKAA--.35008S3; Thu, 06 Aug 2026 10:14:59 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxzMYi7nNqCFQlAA--.58013S2; Thu, 06 Aug 2026 10:14:58 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: Sean Christopherson , Paolo Bonzini , WANG Xuerui , Arnd Bergmann , Xi Ruoyao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] LoongArch: KVM: Implement vmid updating logic Date: Thu, 6 Aug 2026 10:07:38 +0800 Message-Id: <20260806020739.2149268-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260806020739.2149268-1-maobibo@loongson.cn> References: <20260806020739.2149268-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxzMYi7nNqCFQlAA--.58013S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" VMID calculation method is the same with ASID on LoongArch, it is percpu vmid calculation method. For every physical CPU, VMID of different VM is different, and it is the same for different vCPUs of the same VM. When vCPU is scheduled on the physical CPU, it checked vmid of this VM and the global cached vmid, and judge whether it is valid or not. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_host.h | 7 +++++ arch/loongarch/kvm/main.c | 42 ++++++++++++++++++++++++++- arch/loongarch/kvm/mmu.c | 19 +++++++++++- arch/loongarch/kvm/tlb.c | 14 +++++++++ 4 files changed, 80 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include= /asm/kvm_host.h index 78f97dea124d..e623f781e2a5 100644 --- a/arch/loongarch/include/asm/kvm_host.h +++ b/arch/loongarch/include/asm/kvm_host.h @@ -79,6 +79,7 @@ struct kvm_arch_memory_slot { #define HOST_MAX_PMNUM 16 struct kvm_context { unsigned long vpid_cache; + unsigned long vmid_cache; struct kvm_vcpu *last_vcpu; /* Host PMU CSR */ u64 perf_ctrl[HOST_MAX_PMNUM]; @@ -132,6 +133,8 @@ struct kvm_arch { unsigned long kvm_features; =20 s64 time_offset; + cpumask_t tlb_flush_pending; + unsigned long vmid[NR_CPUS]; struct kvm_context __percpu *vmcs; struct loongarch_ipi *ipi; struct loongarch_dmsintc *dmsintc; @@ -319,6 +322,8 @@ bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu); int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); =20 /* MMU handling */ +void kvm_flush_tlb_all_stage1(void); +void kvm_flush_tlb_all_stage2(void); void kvm_flush_tlb_all(void); void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa); int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned long badv, bool wr= ite, int ecode); @@ -353,6 +358,8 @@ static inline void kvm_arch_vcpu_block_finish(struct kv= m_vcpu *vcpu) {} static inline void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memor= y_slot *slot) {} void kvm_check_vpid(struct kvm_vcpu *vcpu); enum hrtimer_restart kvm_swtimer_wakeup(struct hrtimer *timer); +#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS +int kvm_arch_flush_remote_tlbs(struct kvm *kvm); void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, const struct kvm_= memory_slot *memslot); void kvm_init_vmcs(struct kvm *kvm); void kvm_exc_entry(void); diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index c36e62ab0d91..72c1d23156e5 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -220,6 +220,8 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int = cpu) /* start new vpid cycle */ if (!cpu_has_guestid) kvm_flush_tlb_all(); + else + kvm_flush_tlb_all_stage1(); } =20 context->vpid_cache =3D vpid; @@ -279,9 +281,32 @@ static void __kvm_check_vpid(struct kvm_vcpu *vcpu) } } =20 -static void __kvm_check_vmid(struct kvm_vcpu *vcpu) +static void kvm_update_vmid(struct kvm_vcpu *vcpu, int cpu) { unsigned long vmid; + struct kvm_context *context; + + context =3D per_cpu_ptr(vcpu->kvm->arch.vmcs, cpu); + vmid =3D context->vmid_cache + 1; + if (!(vmid & vpid_mask)) { + /* finish round of vmid loop */ + if (unlikely(!vmid)) + vmid =3D vpid_mask + 1; + + ++vmid; /* vmid 0 reserved for root */ + + /* start new vmid cycle */ + kvm_flush_tlb_all_stage2(); + } + + context->vmid_cache =3D vmid; + vcpu->kvm->arch.vmid[cpu] =3D vmid; +} + +static void __kvm_check_vmid(struct kvm_vcpu *vcpu) +{ + int cpu; + unsigned long ver, old, vmid; =20 /* On some machines like 3A5000, vmid needs the same with vpid */ if (!cpu_has_guestid) { @@ -291,6 +316,20 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu) kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); } } + + cpu =3D smp_processor_id(); + if (cpumask_test_and_clear_cpu(cpu, &vcpu->kvm->arch.tlb_flush_pending)) + vcpu->kvm->arch.vmid[cpu] =3D 0; + + /* + * Check if our vmid is of an older version + */ + ver =3D vcpu->kvm->arch.vmid[cpu] & ~vpid_mask; + old =3D this_cpu_ptr(vcpu->kvm->arch.vmcs)->vmid_cache & ~vpid_mask; + if (ver !=3D old) + kvm_update_vmid(vcpu, cpu); + + vcpu->arch.hw_vmid =3D vcpu->kvm->arch.vmid[cpu] & vpid_mask; } =20 void kvm_check_vpid(struct kvm_vcpu *vcpu) @@ -396,6 +435,7 @@ static int kvm_loongarch_env_init(void) for_each_possible_cpu(cpu) { context =3D per_cpu_ptr(vmcs, cpu); context->vpid_cache =3D vpid_mask + 1; + context->vmid_cache =3D vpid_mask + 1; context->last_vcpu =3D NULL; } =20 diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c index 714640a2e614..80e7a8bdc344 100644 --- a/arch/loongarch/kvm/mmu.c +++ b/arch/loongarch/kvm/mmu.c @@ -932,7 +932,8 @@ int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned= long gpa, bool write, in if (!cpu_has_guestid) { vcpu->arch.flush_gpa =3D gpa; kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu); - } + } else + cpumask_set_cpu(vcpu->cpu, &vcpu->kvm->arch.tlb_flush_pending); } =20 return 0; @@ -942,6 +943,22 @@ void kvm_arch_sync_dirty_log(struct kvm *kvm, struct k= vm_memory_slot *memslot) { } =20 +int kvm_arch_flush_remote_tlbs(struct kvm *kvm) +{ + /* + * Queue a TLB invalidation for each CPU to perform on next + * vcpu loading + */ + if (cpu_has_guestid) { + cpumask_setall(&kvm->arch.tlb_flush_pending); + /* Be sure that other CPUS can watch the changes */ + smp_wmb(); + } + + /* Return 1 continue to send ipi to running vCPUs */ + return 1; +} + void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, const struct kvm_memory_slot *memslot) { diff --git a/arch/loongarch/kvm/tlb.c b/arch/loongarch/kvm/tlb.c index b25847aab968..a573db026e01 100644 --- a/arch/loongarch/kvm/tlb.c +++ b/arch/loongarch/kvm/tlb.c @@ -21,6 +21,20 @@ void kvm_flush_tlb_all(void) local_irq_restore(flags); } =20 +/* Invalidate all stage1 TLB entries including GVA-->GPA mappings */ +void kvm_flush_tlb_all_stage1(void) +{ + lockdep_assert_irqs_disabled(); + invtlb_all(INVGTLB_ALLGID_GVA_TO_GPA, 0, 0); +} + +/* Invalidate all stage2 TLB entries including GPA-->HPA mappings */ +void kvm_flush_tlb_all_stage2(void) +{ + lockdep_assert_irqs_disabled(); + invtlb_all(INVTLB_ALLGID_GPA_TO_HPA, 0, 0); +} + void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa) { unsigned int vmid; --=20 2.39.3 From nobody Fri Oct 2 02:32:14 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 873603B9DA6; Thu, 6 Aug 2026 02:15:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982503; cv=none; b=hgMvDNYbn7SUuOYajm3Y5QnoIbsqXx0nCrRVC0OSpBazOKcA22Mt1GeikdWwW1lu5BhLw1lz21ucKDNcr3YkgtxelPvgpcRwFBtFra48UfF4bH/7mGFk5t8GwURsKjE8J33QnknCOHG6EE+rBn+Qn1Wuu0zpuqtw0kmn4PC/d0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785982503; c=relaxed/simple; bh=SrwofF6fkmtOFWRnvfCn/7l/BmUSaJg3/yEnOArDwjU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QnQn8F/+Do8VmkdugphK/3cNux1DZovANfT75kZNrbOmj2+ROscJpePBOptuLDt24Q3NSvPycr1zH7baDXnJj5V0NEWopB/DCiKRF41WLUH2wxQT4cGhEOcIfESDaSv6KQt4+AfP3oJA541lmXBXrQ1/Sq7ua0F5Ect/7wuCfE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx2KAj7nNqRNsKAA--.11729S3; Thu, 06 Aug 2026 10:14:59 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxzMYi7nNqCFQlAA--.58013S3; Thu, 06 Aug 2026 10:14:58 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: Sean Christopherson , Paolo Bonzini , WANG Xuerui , Arnd Bergmann , Xi Ruoyao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] LoongArch: KVM: Enable separate vmid feature Date: Thu, 6 Aug 2026 10:07:39 +0800 Message-Id: <20260806020739.2149268-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260806020739.2149268-1-maobibo@loongson.cn> References: <20260806020739.2149268-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxzMYi7nNqCFQlAA--.58013S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With CSR GTLBC shortname for Guest TLB Control Register, separate vmid feature will be enabled if bit 14 CSR_GTLBC_USEVMID is set. Enable this feature if cpu_has_guestid is true when LVZ is enabled and the LVZ version is 2. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/loongarch.h | 5 +++++ arch/loongarch/kernel/cpu-probe.c | 6 ++++++ arch/loongarch/kvm/main.c | 4 +++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index 2a6bc99177d8..a20fb68d8ac4 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -138,6 +138,9 @@ #define CPUCFG6_PMBITS_SHIFT 8 #define CPUCFG6_UPM BIT(14) =20 +#define LOONGARCH_CPUCFG8 0x8 +#define CPUCFG8_VMID BIT(8) + #define LOONGARCH_CPUCFG16 0x10 #define CPUCFG16_L1_IUPRE BIT(0) #define CPUCFG16_L1_IUUNIFY BIT(1) @@ -350,6 +353,8 @@ #define CSR_GTLBC_TGID_WIDTH 8 #define CSR_GTLBC_TGID_SHIFT_END (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_W= IDTH - 1) #define CSR_GTLBC_TGID (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT) +#define CSR_GTLBC_USEVMID_SHIFT 14 +#define CSR_GTLBC_USEVMID (_ULCAST_(0x1) << CSR_GTLBC_USEVMID_SHIFT) #define CSR_GTLBC_TOTI_SHIFT 13 #define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT) #define CSR_GTLBC_USETGID_SHIFT 12 diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index 74d31f260dfd..fc68f695d49c 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -241,6 +241,12 @@ static void cpu_probe_common(struct cpuinfo_loongarch = *c) if (config & CPUCFG6_PMP) c->options |=3D LOONGARCH_CPU_PMP; =20 + if (c->options & LOONGARCH_CPU_LVZ) { + config =3D read_cpucfg(LOONGARCH_CPUCFG8); + if (config & CPUCFG8_VMID) + c->options |=3D LOONGARCH_CPU_GUESTID; + } + config =3D csr_read32(LOONGARCH_CSR_ASID); config =3D (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT; asid_mask =3D GENMASK(config - 1, 0); diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index 72c1d23156e5..712b078db0d5 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -359,7 +359,7 @@ int kvm_arch_enable_virtualization_cpu(void) write_csr_gcfg(0); write_csr_gstat(0); write_csr_gintc(0); - clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI); + clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID); =20 /* * Enable virtualization features granting guest direct control of @@ -382,6 +382,8 @@ int kvm_arch_enable_virtualization_cpu(void) =20 /* Enable using TGID */ set_csr_gtlbc(CSR_GTLBC_USETGID); + if (cpu_has_guestid) + set_csr_gtlbc(CSR_GTLBC_USEVMID); kvm_debug("GCFG:%lx GSTAT:%lx GINTC:%lx GTLBC:%lx", read_csr_gcfg(), read_csr_gstat(), read_csr_gintc(), read_csr_gtlbc()); =20 --=20 2.39.3