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Thu, 06 Aug 2026 04:43:48 -0700 (PDT) X-Received: by 2002:a05:6a00:bd0e:b0:847:8b0f:2508 with SMTP id d2e1a72fcca58-84f2dfc8c37mr17374646b3a.13.1786016628446; Thu, 06 Aug 2026 04:43:48 -0700 (PDT) Received: from hu-nihalkum-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f456b75dcsm1234756b3a.34.2026.08.06.04.43.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 04:43:48 -0700 (PDT) From: Nihal Kumar Gupta Date: Thu, 06 Aug 2026 17:13:26 +0530 Subject: [PATCH v7 1/5] arm64: dts: qcom: shikra: Add CAMSS node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-shikra-camss-review-v7-1-c7360fd6a5ac@oss.qualcomm.com> References: <20260806-shikra-camss-review-v7-0-c7360fd6a5ac@oss.qualcomm.com> In-Reply-To: <20260806-shikra-camss-review-v7-0-c7360fd6a5ac@oss.qualcomm.com> To: Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Andi Shyti , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Suresh Vankadara , Vikram Sharma , Nihal Kumar Gupta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Shikra shares the same IP as QCM2290 with two CSIPHYs, two CSIDs and two VFEs, but does not include CDM and OPE blocks, so only a single IOMMU context bank is needed. Co-developed-by: Vikram Sharma Signed-off-by: Vikram Sharma Reviewed-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy Signed-off-by: Nihal Kumar Gupta --- arch/arm64/boot/dts/qcom/shikra.dtsi | 100 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index 92d22e3b6931cf49f213d1807f78fc1a261f290d..44e1a333e97f1c88a672c77579f= be987d4285693 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1828,6 +1828,106 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, }; }; =20 + camss: camss@5c11000 { + compatible =3D "qcom,shikra-camss", "qcom,qcm2290-camss"; + + reg =3D <0x0 0x05c11000 0x0 0x1000>, + <0x0 0x05c6e000 0x0 0x1000>, + <0x0 0x05c75000 0x0 0x1000>, + <0x0 0x05c52000 0x0 0x1000>, + <0x0 0x05c53000 0x0 0x1000>, + <0x0 0x05c66000 0x0 0x400>, + <0x0 0x05c68000 0x0 0x400>, + <0x0 0x05c6f000 0x0 0x4000>, + <0x0 0x05c76000 0x0 0x4000>; + reg-names =3D "top", + "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "vfe0", + "vfe1"; + + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>; + clock-names =3D "ahb", + "axi", + "camnoc_nrt_axi", + "camnoc_rt_axi", + "csi0", + "csi1", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "top_ahb", + "vfe0", + "vfe0_cphy_rx", + "vfe1", + "vfe1_cphy_rx"; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "vfe0", + "vfe1"; + + interconnects =3D <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, + <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_mnoc"; + + iommus =3D <&apps_smmu 0x400 0x0>; + + power-domains =3D <&gcc GCC_CAMSS_TOP_GDSC>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + }; + }; + remoteproc_mpss: remoteproc@6080000 { compatible =3D "qcom,shikra-mpss-pas"; reg =3D <0x0 0x06080000 0x0 0x100>; --=20 2.34.1 From nobody Fri Oct 2 01:15:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F027472769 for ; Thu, 6 Aug 2026 11:43:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786016640; cv=none; b=f+AprVpndZNCB1EayAtHyOMFAxF0ENLtRc064xE6x735KplBk6lO/Zs0BCw/zHWEyNvOGAWnGrwum6EqwUUizCJc51YWDWcL35r7OqDExNQBwNx7NoGvDEG8261DXHlNBO8xI9ipKhi0eZM1xHpoo/BfCfosQ6FSM5Naj4Qx5P4= ARC-Message-Signature: i=1; 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Reviewed-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy Reviewed-by: Loic Poulain Signed-off-by: Nihal Kumar Gupta --- arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index 44e1a333e97f1c88a672c77579fbe987d4285693..ce5887b9b1d4a186fe967779b96= 15ab4e4727ff8 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -795,6 +795,38 @@ qup_uart9_default: qup-uart9-default-state { bias-disable; }; =20 + cci_i2c0_default: cci-i2c0-default-state { + /* SDA, SCL */ + pins =3D "gpio36", "gpio37"; + function =3D "cci_i2c0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci_i2c0_sleep: cci-i2c0-sleep-state { + /* SDA, SCL */ + pins =3D "gpio36", "gpio37"; + function =3D "cci_i2c0"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci_i2c1_default: cci-i2c1-default-state { + /* SDA, SCL */ + pins =3D "gpio41", "gpio42"; + function =3D "cci_i2c1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci_i2c1_sleep: cci-i2c1-sleep-state { + /* SDA, SCL */ + pins =3D "gpio41", "gpio42"; + function =3D "cci_i2c1"; + drive-strength =3D <2>; + bias-pull-down; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins =3D "sdc1_clk"; @@ -1928,6 +1960,43 @@ port@1 { }; }; =20 + cci: cci@5c1b000 { + compatible =3D "qcom,shikra-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x05c1b000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_0_CLK>; + clock-names =3D "ahb", + "cci"; + + power-domains =3D <&gcc GCC_CAMSS_TOP_GDSC>; + + pinctrl-0 =3D <&cci_i2c0_default &cci_i2c1_default>; + pinctrl-1 =3D <&cci_i2c0_sleep &cci_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <400000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg =3D <1>; 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Reviewed-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Signed-off-by: Nihal Kumar Gupta --- arch/arm64/boot/dts/qcom/shikra.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index ce5887b9b1d4a186fe967779b9615ab4e4727ff8..661eca4ba85eb83f776278a6750= cb969a409c974 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -827,6 +827,34 @@ cci_i2c1_sleep: cci-i2c1-sleep-state { bias-pull-down; }; =20 + cam_mclk0_default: cam-mclk0-default-state { + pins =3D "gpio34"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_mclk1_default: cam-mclk1-default-state { + pins =3D "gpio35"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_mclk2_default: cam-mclk2-default-state { + pins =3D "gpio96"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; 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The only difference between them is the integrated modem on CQM, which does not affect camera hardware. Add a shared overlay for optional IMX577 integration via CSIPHY1, used by both CQM and CQS EVK boards. Reviewed-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy Signed-off-by: Nihal Kumar Gupta --- arch/arm64/boot/dts/qcom/Makefile | 6 ++ .../dts/qcom/shikra-cqm-cqs-evk-imx577-camera.dtso | 79 ++++++++++++++++++= ++++ 2 files changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 1c86e7e98f55d539f5292816ce06c9a46bd4904c..03ed24afad5795b49848a2548c0= facdc9f3e7115 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -339,6 +339,12 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sdx75-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-cqm-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-cqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-iqs-evk.dtb + +shikra-cqm-evk-imx577-camera-dtbs :=3D shikra-cqm-evk.dtb shikra-cqm-cqs-e= vk-imx577-camera.dtbo +shikra-cqs-evk-imx577-camera-dtbs :=3D shikra-cqs-evk.dtb shikra-cqm-cqs-e= vk-imx577-camera.dtbo + +dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-cqm-evk-imx577-camera.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-cqs-evk-imx577-camera.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm6115-fxtec-pro1x.dtb diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-cqs-evk-imx577-camera.dtso= b/arch/arm64/boot/dts/qcom/shikra-cqm-cqs-evk-imx577-camera.dtso new file mode 100644 index 0000000000000000000000000000000000000000..3a481d972cd27a2a324d96d8f47= c161e11ea54f3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-cqs-evk-imx577-camera.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdd-csiphy-1p2-supply =3D <&pm4125_l5>; + vdd-csiphy-1p8-supply =3D <&pm4125_l13>; + + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + csiphy1_ep: endpoint { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&imx577_ep1>; + }; + }; + }; +}; + +&cci { + status =3D "okay"; +}; + +&cci_i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + camera@1a { + compatible =3D "sony,imx577"; + reg =3D <0x1a>; + + reset-gpios =3D <&tlmm 33 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&cam_mclk1_default &cam1_reset_default>; + pinctrl-names =3D "default"; + + clocks =3D <&gcc GCC_CAMSS_MCLK1_CLK>; + assigned-clocks =3D <&gcc GCC_CAMSS_MCLK1_CLK>; + assigned-clock-rates =3D <24000000>; + + /* + * avdd and dvdd are supplied by on-board regulators on the + * IMX577 module from the connector's 3.3 V rail; they are + * not SoC-controlled. dovdd (1.8 V) powers the carrier board + * level-shifter that translates CCI I2C and reset lines + * between the SoC and the connector. + */ + dovdd-supply =3D <&pm4125_l15>; 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Add a dedicated overlay for optional IMX577 integration via CSIPHY1. Reviewed-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy Signed-off-by: Nihal Kumar Gupta --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../dts/qcom/shikra-iqs-evk-imx577-camera.dtso | 79 ++++++++++++++++++= ++++ 2 files changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 03ed24afad5795b49848a2548c0facdc9f3e7115..5884ff14ad4552249b029d4aad5= 69ccde5768647 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -342,9 +342,11 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-iqs-evk.dtb =20 shikra-cqm-evk-imx577-camera-dtbs :=3D shikra-cqm-evk.dtb shikra-cqm-cqs-e= vk-imx577-camera.dtbo shikra-cqs-evk-imx577-camera-dtbs :=3D shikra-cqs-evk.dtb shikra-cqm-cqs-e= vk-imx577-camera.dtbo +shikra-iqs-evk-imx577-camera-dtbs :=3D shikra-iqs-evk.dtb shikra-iqs-evk-i= mx577-camera.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-cqm-evk-imx577-camera.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-cqs-evk-imx577-camera.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-iqs-evk-imx577-camera.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm6115-fxtec-pro1x.dtb diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk-imx577-camera.dtso b/a= rch/arm64/boot/dts/qcom/shikra-iqs-evk-imx577-camera.dtso new file mode 100644 index 0000000000000000000000000000000000000000..d8c968a918c67cdebc0e7c6fc14= ef820c97ecb75 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk-imx577-camera.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdd-csiphy-1p2-supply =3D <&pm8150_l11>; + vdd-csiphy-1p8-supply =3D <&pm8150_l12>; + + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + csiphy1_ep: endpoint { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&imx577_ep1>; + }; + }; + }; +}; + +&cci { + status =3D "okay"; +}; + +&cci_i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + camera@1a { + compatible =3D "sony,imx577"; + reg =3D <0x1a>; + + reset-gpios =3D <&tlmm 33 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&cam_mclk1_default &cam1_reset_default>; + pinctrl-names =3D "default"; + + clocks =3D <&gcc GCC_CAMSS_MCLK1_CLK>; + assigned-clocks =3D <&gcc GCC_CAMSS_MCLK1_CLK>; + assigned-clock-rates =3D <24000000>; + + /* + * avdd and dvdd are supplied by on-board regulators on the + * IMX577 module from the connector's 3.3 V rail; they are + * not SoC-controlled. dovdd (1.8 V) powers the carrier board + * level-shifter that translates CCI I2C and reset lines + * between the SoC and the connector. + */ + dovdd-supply =3D <&pm8150_l15>; + + port { + imx577_ep1: endpoint { + link-frequencies =3D /bits/ 64 <600000000>; + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&csiphy1_ep>; + }; + }; + }; +}; + +&tlmm { + cam1_reset_default: cam1-reset-default-state { + pins =3D "gpio33"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; --=20 2.34.1