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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19842bsm223493a12.4.2026.08.06.23.53.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 23:53:17 -0700 (PDT) From: Luo Jie Date: Thu, 06 Aug 2026 23:53:05 -0700 Subject: [PATCH v2 01/12] clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-qcom_ipq5210_cmnpll-v2-1-cce718b8ec17@oss.qualcomm.com> References: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> In-Reply-To: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Konrad Dybcio X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786085594; l=2916; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=aPfM9tsY6BErRqddiYvZSV7svFUbPepkOVp4lOV3/Uk=; b=HA9+LwQTz0ocNwWoyTCb6nKKjhhMtrw2rVjCnFzBD6dbzRH+vMWSc6bdqCBKmu2qf4jVIEE98 4Tvk01NrUQZCIK5+YUEaH/BLGvc1Hb8cfJ1SL3HM0z3AUQH2Dem7tCx X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX0FD1I5SnEQE2 4SQ9LEG7ji7wJVx2QydVAsLjnlMTTYHyrqcrdZuxNPPTx8f45lfnagopj2cDyoJgJT3rbD7G8gm XaFbFPhNKcTLTpLcqFto7HOLqMd0YozwMmqo+1MXV06cdSew4IR3STut8Ih89WDr7PXcSIjo598 qRWCCUu2WyM+B/HYefw4YL/2vAOr6lE30F/3oz2HkUSmBhshwtYO7OQwG56tTtvkcu2mGRRMS6c Ee4ttuAtYgvsL1LlMqLGevcwBxFaZnvWh5jg8kI+dDlTl9fU7fiC12xjwhKYaZo0bFsdwUnlzil KVa6ESKHPsmBaiBaZWuf57S13yckf97cevGQ1x+NYw/J7tA70nViGn4gG8N/6h47Ti3c1HMGAta 7V/SycQyCM8aXjCDrWMynszIOMFeHyvfpj88BY6T4CL2EFvyNIjMco2R2bs3Z48k/vCWIhBTiu/ RMwxZ2zrFFQg66OW0IA== X-Authority-Analysis: v=2.4 cv=DvhmPm/+ c=1 sm=1 tr=0 ts=6a7580e1 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=abD0O5-mJzoiGkpUKuEA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: BFNnUvaOtdSMi1hGGb5lkvcDVrrOm-1b X-Proofpoint-GUID: BFNnUvaOtdSMi1hGGb5lkvcDVrrOm-1b X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX83HGGTAGK2ZO AGU2YTTOsRyyqAOi/5pkgfVMqrqzE36CjGKsrGL+sSQhp7z48w5dY4N149CSiw5eZ3FfHsTYEQD CaOubP/HxTalsshJ3chZ+dHd1MU3KDE= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 clxscore=1015 spamscore=0 malwarescore=0 suspectscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070050 Replace clk_hw_register_fixed_rate_parent_hw() with the managed devm_clk_hw_register_fixed_rate_parent_data() so the fixed-rate output clocks are automatically unregistered when the device is unbound. Since all clocks in the driver are now registered via devm_ variants, the remove callback 'ipq_cmn_pll_clk_remove()' and the manual 'unregister_fixed_clk' error-path loop are no longer needed and are removed. Signed-off-by: Luo Jie Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/ipq-cmn-pll.c | 39 +++++++++------------------------------ 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index dafe8c1738df..4fdf78f6829e 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -390,13 +390,14 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 /* Register the fixed rate output clocks. */ for (i =3D 0; i < num_clks; i++) { - hw =3D clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, - cmn_pll_hw, 0, - fixed_clk[i].rate); - if (IS_ERR(hw)) { - ret =3D PTR_ERR(hw); - goto unregister_fixed_clk; - } + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + + hw =3D devm_clk_hw_register_fixed_rate_parent_data(dev, + fixed_clk[i].name, + &pdata, 0, + fixed_clk[i].rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); =20 hw_data->hws[fixed_clk[i].id] =3D hw; } @@ -410,17 +411,11 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); if (ret) - goto unregister_fixed_clk; + return ret; =20 platform_set_drvdata(pdev, hw_data); =20 return 0; - -unregister_fixed_clk: - while (i > 0) - clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); - - return ret; } =20 static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) @@ -462,21 +457,6 @@ static int ipq_cmn_pll_clk_probe(struct platform_devic= e *pdev) return 0; } =20 -static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *hw_data =3D platform_get_drvdata(pdev); - int i; - - /* - * The clock with index CMN_PLL_CLK is unregistered by - * device management. - */ - for (i =3D 0; i < hw_data->num; i++) { - if (i !=3D CMN_PLL_CLK) - clk_hw_unregister(hw_data->hws[i]); - } -} - static const struct dev_pm_ops ipq_cmn_pll_pm_ops =3D { SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) }; @@ -494,7 +474,6 @@ MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); =20 static struct platform_driver ipq_cmn_pll_clk_driver =3D { .probe =3D ipq_cmn_pll_clk_probe, - .remove =3D ipq_cmn_pll_clk_remove, .driver =3D { .name =3D "ipq_cmn_pll", .of_match_table =3D ipq_cmn_pll_clk_ids, --=20 2.43.0 From nobody Thu Oct 1 15:52:42 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28A5B44BCBE for ; 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The IPQ5210 CMN PLL supplies configurable clocks to the NSS (network subsystem), PPE (packet process engine), and PON (passive optical network) hardware blocks. It also supplies a raw EPHY output clock for the integrated Ethernet PHY and several gated fixed-rate outputs to Ethernet PHY and switch devices. Signed-off-by: Luo Jie Acked-by: Rob Herring (Arm) --- .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h | 30 ++++++++++++++++++= ++++ 2 files changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.y= aml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index a4f9af8fa187..91e17f126a9b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -25,6 +25,7 @@ properties: compatible: enum: - qcom,ipq5018-cmn-pll + - qcom,ipq5210-cmn-pll - qcom,ipq5332-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq6018-cmn-pll diff --git a/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h b/include/dt-= bindings/clock/qcom,ipq5210-cmn-pll.h new file mode 100644 index 000000000000..191589fd5311 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H + +/* Parent clock */ +#define IPQ5210_CMN_PLL_CLK 0 + +/* Fixed-rate clocks */ +#define IPQ5210_XO_24MHZ_CLK 1 +#define IPQ5210_SLEEP_32KHZ_CLK 2 + +/* Configurable divider clocks */ +#define IPQ5210_NSS_CLK 3 +#define IPQ5210_PPE_CLK 4 +#define IPQ5210_PON_REFCLK 5 +#define IPQ5210_EPHY_RAW_CLK 6 + +/* Gate clocks */ +#define IPQ5210_PCS_31P25MHZ_CLK 7 +#define IPQ5210_ETH0_50MHZ_CLK 8 +#define IPQ5210_ETH1_50MHZ_CLK 9 +#define IPQ5210_ETH2_50MHZ_CLK 10 +#define IPQ5210_EPHY_50MHZ_CLK 11 +#define IPQ5210_ETH_25MHZ_CLK 12 + +#endif --=20 2.43.0 From nobody Thu Oct 1 15:52:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37DD544E021 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19842bsm223493a12.4.2026.08.06.23.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 23:53:20 -0700 (PDT) From: Luo Jie Date: Thu, 06 Aug 2026 23:53:07 -0700 Subject: [PATCH v2 03/12] clk: divider: Introduce CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-qcom_ipq5210_cmnpll-v2-3-cce718b8ec17@oss.qualcomm.com> References: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> In-Reply-To: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786085594; l=5259; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=jNuWv+XGpMyALJIAtJj9yL61d7ZOIi8C4yCBzoV8Xqk=; b=x0n6y7n/nwQbD4vnCCEHQxz+2vroumwMI3r42ziSL9lWhw8OFIwCQM3ZcY1RSo4LQVZb9N3g8 u0MUJQ5QAe9C/UTktvoXT3K2OSMCrL16/eQbpRNTR739BwuSGvSTM4p X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: Xf86FQ_jPiyx6nQVeRFHD8_pqWhKe97O X-Authority-Analysis: v=2.4 cv=SYbHsPRu c=1 sm=1 tr=0 ts=6a7580e2 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=sASEB03DHn1-PaNBISUA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfXw0BBeXRrs1Sl IJ7vcHMhfHegIkKc5C6t618FiOhJt8Sempe12GF1bufnxplt35pNcKZnqhggR37pHDBrkMuNUUc hkX/n2DNkyWIJxzljzrhnMyMU6qdACg= X-Proofpoint-GUID: Xf86FQ_jPiyx6nQVeRFHD8_pqWhKe97O X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX52ameA0bFs/M tSLr6VoOU4WKM6D+Wkm3mDUizLjtcBsgRjhVdktHxLrvNyYhy/K8x9gVraY3MkV1KGgViD+PZLH z48K+l2QUKNk9cvojMpu9DzElW4vqT8zhS73NHBZIXph7rSY3HVOYUWJ9Iae0P+Ex8rppkeeKJ2 7Uu1HSzEAyNg2A652QcmAZvg3HLQXWS6yDtI/3GZqphl1HV69bpk7Fuk+ytQhag8wFzNlCIHUGF p160VYprzMm2I2PEI4TXbelq6k3+UpmGLOkKyNrjLfW6oSZiX94OMqY4P3wia93YTg0UKm9uayn 0ZX5w+4rDqopurhld3PDmdYqbSU/8H862jMfzXZmNXz7MRtHWBSrdSM+sZI8gs4UHTe78xD7r4F HSaKxfFRW8YUccVke7TEedom+siXrodM0x+6z0qoHr9I9bcti1CeEpf61ZRhjDIIE0LOqSMRTrv rmbZKKVUfV5hb2NgGBQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070050 Some hardware dividers derive an even divisor directly from the raw register value, i.e. divisor =3D 2 * val, with no +1 offset. This differs from CLK_DIVIDER_EVEN_INTEGERS, which is one-based (divisor =3D 2 * (val + 1)). Add CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET for this variant, updating _get_maxdiv()/_get_div()/_get_val() accordingly. _is_valid_div() is extended to also reject odd divisors, since _get_val()'s `div >> 1` would otherwise silently decode them to the wrong even value (e.g. 3 -> 1 -> 2). To avoid regressing rate requests that previously computed an odd divisor (which used to succeed with a silently wrong rate), round to the nearest even divisor in _div_round_up(), _div_round_closest(), and _next_div(), mirroring how CLK_DIVIDER_POWER_OF_TWO already rounds to the nearest power of two. Also guard divider_ro_determine_rate() against a zero divisor, which can occur from an unprogrammed/reset register, the same way divider_recalc_rate() already does: WARN unless CLK_DIVIDER_ALLOW_ZERO is set, and return -EINVAL. Signed-off-by: Luo Jie --- drivers/clk/clk-divider.c | 22 ++++++++++++++++++++++ include/linux/clk-provider.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index b3b485d23ea8..f062d77ee106 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -74,6 +74,8 @@ static unsigned int _get_maxdiv(const struct clk_div_tabl= e *table, u8 width, return 1 << clk_div_mask(width); if (flags & CLK_DIVIDER_EVEN_INTEGERS) return 2 * (clk_div_mask(width) + 1); + if (flags & CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET) + return 2 * clk_div_mask(width); if (table) return _get_table_maxdiv(table, width); return clk_div_mask(width) + 1; @@ -101,6 +103,8 @@ static unsigned int _get_div(const struct clk_div_table= *table, return val ? val : clk_div_mask(width) + 1; if (flags & CLK_DIVIDER_EVEN_INTEGERS) return 2 * (val + 1); + if (flags & CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET) + return 2 * val; if (table) return _get_table_div(table, val); return val + 1; @@ -128,6 +132,8 @@ static unsigned int _get_val(const struct clk_div_table= *table, return (div =3D=3D clk_div_mask(width) + 1) ? 0 : div; if (flags & CLK_DIVIDER_EVEN_INTEGERS) return (div >> 1) - 1; + if (flags & CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET) + return div >> 1; if (table) return _get_table_val(table, div); return div - 1; @@ -181,6 +187,8 @@ static bool _is_valid_div(const struct clk_div_table *t= able, unsigned int div, { if (flags & CLK_DIVIDER_POWER_OF_TWO) return is_power_of_2(div); + if (flags & CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET) + return div >=3D 2 && !(div & 1); if (table) return _is_valid_table_div(table, div); return true; @@ -230,6 +238,8 @@ static int _div_round_up(const struct clk_div_table *ta= ble, =20 if (flags & CLK_DIVIDER_POWER_OF_TWO) div =3D __roundup_pow_of_two(div); + else if (flags & CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET) + div =3D max(2, (div + 1) & ~1); if (table) div =3D _round_up_table(table, div); =20 @@ -249,6 +259,9 @@ static int _div_round_closest(const struct clk_div_tabl= e *table, if (flags & CLK_DIVIDER_POWER_OF_TWO) { up =3D __roundup_pow_of_two(up); down =3D __rounddown_pow_of_two(down); + } else if (flags & CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET) { + up =3D max(2, (up + 1) & ~1); + down =3D max(2, down & ~1); } else if (table) { up =3D _round_up_table(table, up); down =3D _round_down_table(table, down); @@ -286,6 +299,8 @@ static int _next_div(const struct clk_div_table *table,= int div, =20 if (flags & CLK_DIVIDER_POWER_OF_TWO) return __roundup_pow_of_two(div); + if (flags & CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET) + return div + (div & 1); if (table) return _round_up_table(table, div); =20 @@ -372,6 +387,13 @@ int divider_ro_determine_rate(struct clk_hw *hw, struc= t clk_rate_request *req, =20 div =3D _get_div(table, val, flags, width); =20 + if (!div) { + WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO), + "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", + clk_hw_get_name(hw)); + return -EINVAL; + } + /* Even a read-only clock can propagate a rate change */ if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { if (!req->best_parent_hw) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index b01a38fef8cf..368970d6a12a 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -703,6 +703,8 @@ struct clk_div_table { * big endian. * CLK_DIVIDER_EVEN_INTEGERS - clock divisor is 2, 4, 6, 8, 10, etc. * Formula is 2 * (value read from hardware + 1). + * CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET - clock divisor is 2, 4, 6, 8, etc. + * Formula is 2 * (value read from hardware). */ struct clk_divider { struct clk_hw hw; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19842bsm223493a12.4.2026.08.06.23.53.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 23:53:22 -0700 (PDT) From: Luo Jie Date: Thu, 06 Aug 2026 23:53:08 -0700 Subject: [PATCH v2 04/12] clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-qcom_ipq5210_cmnpll-v2-4-cce718b8ec17@oss.qualcomm.com> References: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> In-Reply-To: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786085594; l=3344; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=uxbVpH4XlgrAkvtkrxKBvgSlTb725f4BxWp2snEJzAE=; b=Tf1TSlNqRiNlCIfyTUuTF+aD6By4zFIY6GA5dcNX1SrDsUb1lt6LRwSLnumR183W0L61kLHOa 50Y6y8gkATXChgk4SAd+UI/15C4RlMxi7/YQJsuZN/38HGPfMYBz4kv X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Authority-Analysis: v=2.4 cv=frDsol4f c=1 sm=1 tr=0 ts=6a7580e4 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=vx7U0BMSOfWHh9VQJyQA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: WKjh8T9H6BYLe4ptrkaZQNf4tQDbETAe X-Proofpoint-ORIG-GUID: WKjh8T9H6BYLe4ptrkaZQNf4tQDbETAe X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfXxsrbz/j5Ss6Z vRb4pP+6AhbvTU7l8BtL9hZyjrHtcPGIynnnQNS1FXNhXkPpaOVRFUpnvNeIWjIhPH+Js4Y5n+B 13dIQa8CuCiCChWQVENcQgFXX7/2AbE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX1mG+c0TDlJ3D O0xqY4lIlk63Rkws3fRwoxVXv/xUlNyWnk33IvM/s3+WRmpT/XA3ENZaA+CMgMhqeMipi49vE7Z GeEI09ISGe3UtRPRF4bk0cN2rkltAQkprQv9KzeOEE8KoQM8k4EVCJBckORuqnfNki74L55dG1+ jieDQbtrtZ1ofPxeLboscxqOLSrfFOYOlxXB9pMpywZcV00Cq8QVDUBVNELJwlmsM2DDnU8c1cu OoKoNckRdeOEJRCuibtHiO5JmrVjtTsEGHhkdddS6bOMJATZQVSdxc9pbnaci8dVujYQVVpO/Nm CgEl4JPRVbvV8imGJr4QrwZbdUiUtulwuvkWsRpYmZP6s39F4oUErwAcG/niX5yR7d94g4r4PMI o4y0Keh43VlSYasE2A2BLFxEMJQL2dJuzk0C2sZSeIjOUXmHiPbzj1BOIzaf/bWfVDsHDyy1uBj l62qM+kD6wMABWvyNcQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070050 Add a flags field to struct clk_regmap_div and OR it into the CLK_DIVIDER_ROUND_CLOSEST flag passed to divider_determine_rate(), divider_ro_determine_rate(), divider_get_val(), and divider_recalc_rate(), so that qcom drivers can opt into CLK_DIVIDER_* behavior variants such as CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET. This is additive and backward compatible: existing clk_regmap_div users don't initialize .flags, so it defaults to 0, and CLK_DIVIDER_ROUND_CLOSEST | 0 is identical to current behavior. divider_get_val() can now return -EINVAL once a caller sets a divisor-constraining flag such as CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET (previously unreachable, since no flag passed here constrained _is_valid_div()). Check for this in div_set_rate() before using the result, mirroring clk_divider_set_rate()'s existing handling of the same return value. Signed-off-by: Luo Jie --- drivers/clk/qcom/clk-regmap-divider.c | 14 +++++++++----- drivers/clk/qcom/clk-regmap-divider.h | 1 + 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-r= egmap-divider.c index 672e82caf205..fe4542b5bd58 100644 --- a/drivers/clk/qcom/clk-regmap-divider.c +++ b/drivers/clk/qcom/clk-regmap-divider.c @@ -27,7 +27,8 @@ static int div_ro_determine_rate(struct clk_hw *hw, val &=3D BIT(divider->width) - 1; =20 return divider_ro_determine_rate(hw, req, NULL, divider->width, - CLK_DIVIDER_ROUND_CLOSEST, val); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags, + val); } =20 static int div_determine_rate(struct clk_hw *hw, struct clk_rate_request *= req) @@ -35,7 +36,7 @@ static int div_determine_rate(struct clk_hw *hw, struct c= lk_rate_request *req) struct clk_regmap_div *divider =3D to_clk_regmap_div(hw); =20 return divider_determine_rate(hw, req, NULL, divider->width, - CLK_DIVIDER_ROUND_CLOSEST); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags); } =20 static int div_set_rate(struct clk_hw *hw, unsigned long rate, @@ -43,10 +44,12 @@ static int div_set_rate(struct clk_hw *hw, unsigned lon= g rate, { struct clk_regmap_div *divider =3D to_clk_regmap_div(hw); struct clk_regmap *clkr =3D ÷r->clkr; - u32 div; + int div; =20 div =3D divider_get_val(rate, parent_rate, NULL, divider->width, - CLK_DIVIDER_ROUND_CLOSEST); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags); + if (div < 0) + return div; =20 return regmap_update_bits(clkr->regmap, divider->reg, (BIT(divider->width) - 1) << divider->shift, @@ -65,7 +68,8 @@ static unsigned long div_recalc_rate(struct clk_hw *hw, div &=3D BIT(divider->width) - 1; =20 return divider_recalc_rate(hw, parent_rate, div, NULL, - CLK_DIVIDER_ROUND_CLOSEST, divider->width); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags, + divider->width); } =20 const struct clk_ops clk_regmap_div_ops =3D { diff --git a/drivers/clk/qcom/clk-regmap-divider.h b/drivers/clk/qcom/clk-r= egmap-divider.h index e75a65c3839c..4fde766b2633 100644 --- a/drivers/clk/qcom/clk-regmap-divider.h +++ b/drivers/clk/qcom/clk-regmap-divider.h @@ -13,6 +13,7 @@ struct clk_regmap_div { u32 reg; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19842bsm223493a12.4.2026.08.06.23.53.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 23:53:23 -0700 (PDT) From: Luo Jie Date: Thu, 06 Aug 2026 23:53:09 -0700 Subject: [PATCH v2 05/12] clk: qcom: ipq-cmn-pll: Add NSS clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-qcom_ipq5210_cmnpll-v2-5-cce718b8ec17@oss.qualcomm.com> References: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> In-Reply-To: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786085595; l=5236; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=UsBpjqso7qwEzQ7kYDKho/dDU1/+mseogrEormQfYF4=; b=H9l39pKjv9hSE9VgBhsevPNsCU9f2/Dnhl9XiA/q5ZzUhSMl3LkL57WvLHmQYnF3cp6bm76l0 2mx0NKhJ21qDedtd8UCvJz4JhjAu3R8+5HvKWTlcVvHoV6im9Ept4Q1 X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX12C1AVDmInft w5YZM6oRixCJyzywQp6W75qSCXRi+LvEeLOaya3wcnblZueCFH0qMYyyRMhir7NRF0MscOEeg76 XCIsWL5TQLWm1/DKipTlD8NV7dQCUPU= X-Proofpoint-ORIG-GUID: CBmxcmVhnaRxRDCuhC7JcEkbpdX0UnmJ X-Proofpoint-GUID: CBmxcmVhnaRxRDCuhC7JcEkbpdX0UnmJ X-Authority-Analysis: v=2.4 cv=B+eJFutM c=1 sm=1 tr=0 ts=6a7580e5 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Z-rpqniIaXCS-UcZ7pQA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX12uBsvcVQH8D bB9p37jmBfH3yIGKBlE3DjFVySuje3k/gp7DyH/zrcHS89jD/pvUryO1ae9enesWLqBBReZPFte Vpme9VYyi1hIGnGhNUek9tbiPyWc0JA5y+sc+WDVzeopn1mWHAeMNKQLoSYohBzqHe05ljSfP3B SdJBt2TJb45TC7UdVQRcNHZ6K9uT39qz4FDsEuM/a0z8mhHDk4ttP5lE8r0yvpcoyQLi/3BMAZz JY+iUvSk1wzu7/ggJ1AIxBPdzy1CTFuYgNoxXax/Ni99yxhnVt2iqO+ZTNSFnZrTg34Q6s+JGLQ 4/Pix2wSfiWqHhKRyVzqaDeK9GZM92gbaHNXVIrwrk6E+OWX7b6kgebiaTtwm6zON9NsTEheqRz exU79/ijAzPuEYLEvlY/PXMS4B8GQxBATxMkNe8SnFgGYX44v5YvAy8xEixCLQ+n1ObDbld+01j Ey6gKRdpFQfWisId7gw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070050 The NSS (network subsystem) clock is derived from the CMN PLL output divided by 2 and then further divided by a configurable 6-bit divider. This is functionally identical to clk_regmap_div_ops, aside from the implicit divide-by-2, which the new CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET flag now expresses. Register the NSS clock through a new ipq_cmn_pll_regmap_div_register() helper, built as a plain struct clk_regmap_div instance instead of hand-rolling recalc_rate/set_rate, and drop the [8, 63] range clamp that the hand-rolled implementation enforced, since the full 6-bit register range is now allowed, matching clk_regmap_div_ops's own behavior. The helper takes the register field mask and clock name as parameters so that the upcoming PPE clock, which shares the same register with a different field, can reuse it. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 80 ++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 75 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 4fdf78f6829e..c1b00699eb72 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -60,12 +60,18 @@ #include #include =20 +#include "clk-regmap.h" +#include "clk-regmap-divider.h" + #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 #define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) =20 #define CMN_PLL_LOCKED 0x64 #define CMN_PLL_CLKS_LOCKED BIT(8) =20 +#define CMN_PLL_NSS_PPE_FREQ_CTRL 0x98 +#define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) + #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) =20 @@ -80,15 +86,27 @@ #define CMN_PLL_DIVIDER_CTRL 0x794 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) =20 +/** + * enum cmn_pll_clk_type - CMN PLL output clock registration type + * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock + * @CMN_PLL_CLK_NSS: NSS clock with configurable divider + */ +enum cmn_pll_clk_type { + CMN_PLL_CLK_FIXED_RATE, + CMN_PLL_CLK_NSS, +}; + /** * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information * @id: Clock specifier to be supplied * @name: Clock name to be registered + * @type: Clock registration type * @rate: Clock rate */ struct cmn_pll_fixed_output_clk { unsigned int id; const char *name; + enum cmn_pll_clk_type type; unsigned long rate; }; =20 @@ -105,6 +123,7 @@ struct clk_cmn_pll { #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ .id =3D _id, \ .name =3D _name, \ + .type =3D CMN_PLL_CLK_FIXED_RATE, \ .rate =3D _rate, \ } =20 @@ -357,11 +376,46 @@ static struct clk_hw *ipq_cmn_pll_clk_hw_register(str= uct platform_device *pdev) return &cmn_pll->hw; } =20 +static struct clk_hw *ipq_cmn_pll_regmap_div_register(struct platform_devi= ce *pdev, + struct regmap *regmap, + struct clk_hw *cmn_pll_hw, + const char *name, + u32 field_mask) +{ + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + struct device *dev =3D &pdev->dev; + struct clk_regmap_div *div_clk; + int ret; + + div_clk =3D devm_kzalloc(dev, sizeof(*div_clk), GFP_KERNEL); + if (!div_clk) + return ERR_PTR(-ENOMEM); + + div_clk->reg =3D CMN_PLL_NSS_PPE_FREQ_CTRL; + div_clk->shift =3D __ffs(field_mask); + div_clk->width =3D hweight32(field_mask); + div_clk->flags =3D CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET; + div_clk->clkr.regmap =3D regmap; + div_clk->clkr.hw.init =3D &(struct clk_init_data){ + .name =3D name, + .parent_data =3D &pdata, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ops, + }; + + ret =3D devm_clk_register_regmap(dev, &div_clk->clkr); + if (ret) + return ERR_PTR(ret); + + return &div_clk->clkr.hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; struct clk_hw_onecell_data *hw_data; struct device *dev =3D &pdev->dev; + struct clk_cmn_pll *cmn_pll; struct clk_hw *cmn_pll_hw; unsigned int num_clks; struct clk_hw *hw; @@ -388,14 +442,30 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) if (IS_ERR(cmn_pll_hw)) return PTR_ERR(cmn_pll_hw); =20 + cmn_pll =3D to_clk_cmn_pll(cmn_pll_hw); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19842bsm223493a12.4.2026.08.06.23.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 23:53:24 -0700 (PDT) From: Luo Jie Date: Thu, 06 Aug 2026 23:53:10 -0700 Subject: [PATCH v2 06/12] clk: qcom: ipq-cmn-pll: Add PPE clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-qcom_ipq5210_cmnpll-v2-6-cce718b8ec17@oss.qualcomm.com> References: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> In-Reply-To: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786085595; l=1768; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=qWuwbIrQ7RgJGuhrwovJePA4VGYgHtm8h3XVOSoUQ7c=; b=EESzC3jaa1DxBnT1Ykx8jPGSvZu5E4SBnVB8iZzBtY9PAwWBnPWf78FYVRThVFUXT7+L0V6/3 cd5BI3Up7LpAdDmlKNOSA1G18sCNe6GM93Br9/JwWKqGGXDUfA04JCj X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Authority-Analysis: v=2.4 cv=frDsol4f c=1 sm=1 tr=0 ts=6a7580e7 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=mAYwyletAeVdbrWGRpcA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: OEXLjC9xMnesOinAVVAEbRFh0eXVgy8d X-Proofpoint-ORIG-GUID: OEXLjC9xMnesOinAVVAEbRFh0eXVgy8d X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfXz8ykNb9KSEQk 7kJq4rpprSSKJfEVMh3zXjZ0622dyyHAiQEftAngHNnQzXvijXFMJ1+mHyyKIOZN02BXfPnKQkE +7YCUKvhYjIDUiSThnlD+g2g52fYxb4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX7AFrGSKw/g08 BToVgMRZUAMBOMA5+U48jfOCi8ypP9UgH+LVRmeQG+UUtc9LLd10ou3nWXYQMf7wn5LuFpTtPA7 zVTnxAbZCkTJNSkNsjlyzYewOeR1obyDlTEj6WUe9ENh5/ot9I7IFYYWt7IEINyXaZK6CNsCYch O+ilget4lWleBPzwvfJ2pkUzaLV5dCR5lNy1KDLBNvJRwPJk3iTQQWqzL2xLjpa3BNu1G8OdT4n XnUP3g6HcqYkcZuYDt7eq7bjm0GvyrNYY7nu0tK7ikOH4C/g6FHkZXNFeb7euM0KWYWyEBEhVCJ 8GkywgnzFWjlmzFXE1VM5y78CpaTYPGdIzALMcNeGCiVmzm+Tiqx+FSx1eJmGeccQB5FNsoWCAb aniMz74M/Kew/GUG2iGEMwAN7b7AorJijW6OBVFSuki4l1f2y7t98zrVE+Steis3v/pq5wCQxpf 2gB2njtcD8poAIAyDog== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070050 The PPE (packet process engine) clock is derived from the CMN PLL output divided by 2 and then further divided by a configurable 6-bit divider. It shares the CMN_PLL_NSS_PPE_FREQ_CTRL register with the NSS clock but uses a different field (bits [5:0]). Register the PPE clock through the ipq_cmn_pll_regmap_div_register() helper introduced for the NSS clock, passing the PPE-specific field mask. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index c1b00699eb72..a24e57b33c6b 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -71,6 +71,7 @@ =20 #define CMN_PLL_NSS_PPE_FREQ_CTRL 0x98 #define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) +#define CMN_PLL_PPE_CLK_SEL GENMASK(5, 0) =20 #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) @@ -90,10 +91,12 @@ * enum cmn_pll_clk_type - CMN PLL output clock registration type * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock * @CMN_PLL_CLK_NSS: NSS clock with configurable divider + * @CMN_PLL_CLK_PPE: PPE clock with configurable divider */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, CMN_PLL_CLK_NSS, + CMN_PLL_CLK_PPE, }; =20 /** @@ -464,6 +467,12 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) fixed_clk[i].name, CMN_PLL_NSS_CLK_SEL); break; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19842bsm223493a12.4.2026.08.06.23.53.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 23:53:26 -0700 (PDT) From: Luo Jie Date: Thu, 06 Aug 2026 23:53:11 -0700 Subject: [PATCH v2 07/12] clk: qcom: ipq-cmn-pll: Add PON reference clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-qcom_ipq5210_cmnpll-v2-7-cce718b8ec17@oss.qualcomm.com> References: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> In-Reply-To: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786085595; l=6945; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=AJC5Vy5cYaputpiPxiRR3kf3ciQhUvXNBdfghb/Toes=; b=agcKUv6CpQEUmZfNyGJ8XXjQfm7byhm7SSmjMV4Gkp780pB7mRTUhKbFyFmdGsiL3OAr2LTNg rIw8yiK619eAdJAVjhXyDZJQytC/0CEe1SaBcRyEiH5xnpdYkCLhFJw X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Authority-Analysis: v=2.4 cv=frDsol4f c=1 sm=1 tr=0 ts=6a7580e8 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=Vzc9HlkDlmRur2svsm8A:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: ZKEHHzjDaHXl2BgC5DS9TYJ00Mg0xHq4 X-Proofpoint-ORIG-GUID: ZKEHHzjDaHXl2BgC5DS9TYJ00Mg0xHq4 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX/O61tBwVivZ4 uDKYEkjCc6NNYtpoGUaOjkoqZEVkBNiq86pWA0FpbB9HCsS4UUhaDrl+z9Tp/rvLm6Nm+3bJWqP qGJ3vHWnKEOHzVQdQE+Chx2Fy0lzbLE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfXxO7yyQk1GYkn Qz3czds8G6EZ02ZF89LYnsuDt9VyuztemPPb+G7dgTZf1vO8ld7Yh08lzHt0OJmXE5ztpDhF9ha aGnVKDTPlCt3a+uaZD490Jpp02aoDvt1fB2W73Mg5pMPAcuGyCHIzSkAS5VHs8mbxKQyhkmaBN8 YojSmP/uHl0BEcJnvX5/V1sZmgWtQ07TASup7KpMg2rbWJT0bLer5XC6Bh1y2ffbgN+A/S6w2+q WqNPvostiReoApfFC/E7XByLQVXuwq5gR/X25rNywz71vNUc4W2ctfrL1fVU+J90TEDnvWqp/gO +6awH+FhvDgkeFgjYLE3EY+tf9sNZT/WEIriDhE4LrUqy2Oa1Fo6JJegOaQKH2W/89yz4B5RonV So3NAZeYStQB60WXGaNKF+k0mWunx5caxDX1GLWdy+a+rook/TfSyd5zkflbKOF4DI832VeqxJS jP7UlqV2+v5QG8y6Q/w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070050 The PON (Passive Optical Network) reference clock is derived from the CMN PLL output divided by 2 and then further divided by a configurable 8-bit divider (1-255). The clock supports two modes: - UNIPHY mode (CMN_PLL_PON_MODE_SEL =3D 0): fixed 31.25 MHz output - PON mode (CMN_PLL_PON_MODE_SEL =3D 1): pll_rate / (2 * divider) The clock output can be independently enabled and disabled via the CMN_PLL_PON_EN bit. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 171 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 171 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index a24e57b33c6b..356988c03a7a 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -73,6 +73,11 @@ #define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) #define CMN_PLL_PPE_CLK_SEL GENMASK(5, 0) =20 +#define CMN_PLL_PON_CONFIG 0x42c +#define CMN_PLL_PON_MODE_SEL BIT(9) +#define CMN_PLL_PON_EN BIT(8) +#define CMN_PLL_PON_DIV_CTRL GENMASK(7, 0) + #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) =20 @@ -92,11 +97,13 @@ * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock * @CMN_PLL_CLK_NSS: NSS clock with configurable divider * @CMN_PLL_CLK_PPE: PPE clock with configurable divider + * @CMN_PLL_CLK_PON: PON reference clock */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, CMN_PLL_CLK_NSS, CMN_PLL_CLK_PPE, + CMN_PLL_CLK_PON, }; =20 /** @@ -413,6 +420,164 @@ static struct clk_hw *ipq_cmn_pll_regmap_div_register= (struct platform_device *pd return &div_clk->clkr.hw; } =20 +/* + * PON (Passive Optical Network) reference clock operations. + * The PON refclk is derived from CMN PLL rate / 2, then divided by + * a configurable 8-bit divider (1-255). + */ +static int clk_pon_refclk_enable(struct clk_hw *hw) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + + return regmap_set_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_EN); +} + +static void clk_pon_refclk_disable(struct clk_hw *hw) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + + regmap_clear_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_EN); +} + +static int clk_pon_refclk_is_enabled(struct clk_hw *hw) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + + return regmap_test_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_EN); +} + +static unsigned long clk_pon_refclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + u32 val, div; + int ret; + + ret =3D regmap_read(pon_clk->regmap, CMN_PLL_PON_CONFIG, &val); + if (WARN_ON_ONCE(ret)) + return 0; + + /* Check if in UNIPHY mode (bit 9 =3D 0) - fixed 31.25 MHz */ + if (!(val & CMN_PLL_PON_MODE_SEL)) + return 31250000UL; + + /* PON mode: calculate from divider */ + div =3D FIELD_GET(CMN_PLL_PON_DIV_CTRL, val); + if (WARN_ON_ONCE(!div)) + return 0; + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, 2ULL * div); +} + +static int clk_pon_refclk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long div, pon_rate, uniphy_rate =3D 31250000UL; + + if (WARN_ON_ONCE(!req->rate)) + return -EINVAL; + + div =3D DIV64_U64_ROUND_CLOSEST((u64)req->best_parent_rate, 2ULL * req->r= ate); + + /* Clamp to valid range (1-255) */ + div =3D clamp_t(unsigned long, div, 1, 255); + + pon_rate =3D DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, 2ULL * div= ); + + /* Pick whichever mode gets closer to the requested rate */ + req->rate =3D abs_diff(req->rate, uniphy_rate) < abs_diff(req->rate, pon_= rate) ? + uniphy_rate : pon_rate; + + return 0; +} + +static int clk_pon_refclk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + unsigned long div; + int ret; + + if (rate =3D=3D 0) + return -EINVAL; + + /* + * An exact request for 31.25 MHz is always satisfiable by UNIPHY + * mode, even though PON mode with a suitable divider can produce + * the same frequency for some parent rates. Preferring UNIPHY here + * is safe: this function is only ever called with a rate produced + * by clk_pon_refclk_determine_rate() through the standard + * clk_set_rate() path, and either mode yields the identical output + * rate for this value. + */ + if (rate =3D=3D 31250000UL) + return regmap_clear_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_MODE_SEL); + + div =3D DIV64_U64_ROUND_CLOSEST((u64)parent_rate, 2ULL * rate); + if (div =3D=3D 0 || div > 255) + return -EINVAL; + + /* Switch to PON mode */ + ret =3D regmap_set_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_MODE_SEL); + if (ret) + return ret; + + return regmap_update_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_DIV_CTRL, + FIELD_PREP(CMN_PLL_PON_DIV_CTRL, div)); +} + +static const struct clk_ops clk_pon_refclk_ops =3D { + .enable =3D clk_pon_refclk_enable, + .disable =3D clk_pon_refclk_disable, + .is_enabled =3D clk_pon_refclk_is_enabled, + .recalc_rate =3D clk_pon_refclk_recalc_rate, + .determine_rate =3D clk_pon_refclk_determine_rate, + .set_rate =3D clk_pon_refclk_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_pon_refclk_register(struct platform_devi= ce *pdev, + struct regmap *regmap, + struct clk_hw *cmn_pll_hw, + const char *name) +{ + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; + struct clk_cmn_pll *pon_clk; + int ret; + + pon_clk =3D devm_kzalloc(dev, sizeof(*pon_clk), GFP_KERNEL); + if (!pon_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_pon_refclk_ops; + /* + * The PON reference clock may already be enabled by bootloader + * or consumed by hardware without an in-kernel client driver. + * Add CLK_IGNORE_UNUSED so the clock framework does not disable + * it when no consumer has claimed it. + */ + init.flags =3D CLK_IGNORE_UNUSED; + + pon_clk->hw.init =3D &init; + pon_clk->regmap =3D regmap; + + ret =3D devm_clk_hw_register(dev, &pon_clk->hw); + if (ret) + return ERR_PTR(ret); + + return &pon_clk->hw; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19842bsm223493a12.4.2026.08.06.23.53.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 23:53:28 -0700 (PDT) From: Luo Jie Date: Thu, 06 Aug 2026 23:53:12 -0700 Subject: [PATCH v2 08/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-qcom_ipq5210_cmnpll-v2-8-cce718b8ec17@oss.qualcomm.com> References: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> In-Reply-To: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786085595; l=4581; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=weKfows8FNPEjrNrqtloW4BpPR7xbWNzhhCb6c50wCM=; b=7z+++t57FkitF4QGy2RzXTIRHVwhiD8ZaUoZUxq+8m0bVIrKoQtJsP9AY1mNefun5RP479qlF 6xsrBMdEcHwAYFDppyiKpI+j4N39U1MUrPQrVokwIQPt51WY9vQIa8Q X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX6hTqnB6cfeoB xuNFoSpqcY/cEw5xZ1Hl4oN/fCV7DwsIVPwixkqlQuHMV4SHK4Tl/Lz0bWqsydUaicEhPmEfRSV lwLAbdrwJUU4/zcsJhgbTfVOpvyg+05sv61YZbQOqmfIfcXuicvfXoFLU57YD0u1NPud3qcPBH7 ZtwBa+1v83YDxSKeCdiB4O8Wu+F8JQOwOtEGii6rUWCDeF4M0rQgxjY1D9v9VgAD4uEERSnSkhU n6Pnoqm9lMknEwWeEzk6zrpyKtgLvRYDCO+kKz/lqWeWebGEaTT1JE0ukS4bctx9hk2jeM+X8O7 fWlwPabTn9J7JizWs6EEpsTVss1aaeQV+zJAxpoEo7APs7ekMQNpTDg6ZzxVJCopU3zHnnnkM1W 9atK+jzGhzLkZUTsezChac1wgMWvynKosocFBS3NxLb4JPxvzrb+mvePgX+pxoxOEkWk6iemvTL J4YLVmTGfU/MxsRr3Yg== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX6rL3uCu7p3eX yaqr6HRsTm/OB91/p3AMTnWg0QuR2VgrMiHk63YD2p8I8cLoaezplf9jHs+4uC0zWw6TLpggM/x fzPnAItK3sUw7AOoZW5UELdJVzHILts= X-Proofpoint-ORIG-GUID: guJzOTrmlRFwVD5sYSHZePvMbR3BsrnZ X-Proofpoint-GUID: guJzOTrmlRFwVD5sYSHZePvMbR3BsrnZ X-Authority-Analysis: v=2.4 cv=e5Y2j6p/ c=1 sm=1 tr=0 ts=6a7580e9 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=VFrLHRkP8_lOF4sqez4A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070050 The EPHY-RAW clock is an IPQ5210-specific output from the CMN PLL that provides the raw reference clock to the SoC-integrated Ethernet PHY (EPHY), which supports up to 2.5G link speed. The output frequency is selected via bit 10 (CMN_PLL_GEPHY_312P5M_125M_SEL) of the CMN_PLL_PON_CONFIG register: - 0: 125 MHz - for 1G/100M/10M link speed - 1: 312.5 MHz - for 2.5G link speed Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 98 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 98 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 356988c03a7a..586f9c620e7e 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -77,6 +77,7 @@ #define CMN_PLL_PON_MODE_SEL BIT(9) #define CMN_PLL_PON_EN BIT(8) #define CMN_PLL_PON_DIV_CTRL GENMASK(7, 0) +#define CMN_PLL_GEPHY_312P5M_125M_SEL BIT(10) =20 #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) @@ -98,12 +99,14 @@ * @CMN_PLL_CLK_NSS: NSS clock with configurable divider * @CMN_PLL_CLK_PPE: PPE clock with configurable divider * @CMN_PLL_CLK_PON: PON reference clock + * @CMN_PLL_CLK_EPHY_RAW: EPHY-RAW clock */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, CMN_PLL_CLK_NSS, CMN_PLL_CLK_PPE, CMN_PLL_CLK_PON, + CMN_PLL_CLK_EPHY_RAW, }; =20 /** @@ -578,6 +581,95 @@ static struct clk_hw *ipq_cmn_pll_pon_refclk_register(= struct platform_device *pd return &pon_clk->hw; } =20 +/* + * EPHY-RAW clock operations for IPQ5210. + * The output clock rate is selected via bit 10 of CMN_PLL_PON_CONFIG: + * 0: 125 MHz (for 1G link speed) + * 1: 312.5 MHz (for 2.5G link speed) + */ +static unsigned long clk_ephy_raw_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cmn_pll *ephy_raw_clk =3D to_clk_cmn_pll(hw); + u32 val; + int ret; + + ret =3D regmap_read(ephy_raw_clk->regmap, CMN_PLL_PON_CONFIG, &val); + if (WARN_ON_ONCE(ret)) + return 0; + + if (val & CMN_PLL_GEPHY_312P5M_125M_SEL) + return 312500000UL; + + return 125000000UL; +} + +static int clk_ephy_raw_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long rate_125m =3D 125000000UL, rate_312p5m =3D 312500000UL; + + /* Pick whichever of the two supported rates is closer to the request */ + req->rate =3D abs_diff(req->rate, rate_125m) < abs_diff(req->rate, rate_3= 12p5m) ? + rate_125m : rate_312p5m; + + return 0; +} + +static int clk_ephy_raw_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cmn_pll *ephy_raw_clk =3D to_clk_cmn_pll(hw); + + if (rate =3D=3D 125000000UL) + return regmap_clear_bits(ephy_raw_clk->regmap, + CMN_PLL_PON_CONFIG, + CMN_PLL_GEPHY_312P5M_125M_SEL); + + if (rate =3D=3D 312500000UL) + return regmap_set_bits(ephy_raw_clk->regmap, + CMN_PLL_PON_CONFIG, + CMN_PLL_GEPHY_312P5M_125M_SEL); + + return -EINVAL; +} + +static const struct clk_ops clk_ephy_raw_ops =3D { + .recalc_rate =3D clk_ephy_raw_recalc_rate, + .determine_rate =3D clk_ephy_raw_determine_rate, + .set_rate =3D clk_ephy_raw_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_ephy_raw_register(struct platform_device= *pdev, + struct regmap *regmap, + struct clk_hw *cmn_pll_hw, + const char *name) +{ + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + struct clk_cmn_pll *ephy_raw_clk; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19842bsm223493a12.4.2026.08.06.23.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 23:53:29 -0700 (PDT) From: Luo Jie Date: Thu, 06 Aug 2026 23:53:13 -0700 Subject: [PATCH v2 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-qcom_ipq5210_cmnpll-v2-9-cce718b8ec17@oss.qualcomm.com> References: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> In-Reply-To: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786085595; l=7262; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=3SshFUJAe2YCABf7vZhxKHsnDDjDnSisNVo3j+1z8NQ=; b=hK08ThqyO3RY9ir1gTDl9nHHgGCOoRV14/brbkyv5V35V5k25bLaEsKlm5KnpTeblLgDYEmb6 TGmRN3Yx9jFAYasJqu2pB5d1ZlZkInAqZiUQfUydrhiZFG+5/STnyTk X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX182OadTySJIj AH5Ms5EQJecjoaJ+VkGJNlSTYFy70tK+2IeI9pUI1OAGPRZK6mWylDO/93V8wcwzoWnCbn48so5 Q16oy1gMSIabKUyl1VQIWF6hMAjuvbc= X-Authority-Analysis: v=2.4 cv=PK0/P/qC c=1 sm=1 tr=0 ts=6a7580eb cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=iNkdjwxjGt8fguHhLfQA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX64L70DjCPrUT Ymgf13GzpuRGODiZUKVJl6x1ZB37hVq1RWSKpcg58ZvPHGNItxCdjK0liSnkl51q2SLRJpW4lOB HQVguBfpWTNK0+EnMsX6NlO8vt1V5FwKfAz/vn/fH1tpVo0fGGhJgmBevQLg7MX7IvXe0lw0Uhm +VBQh1aYNPZ+t1ifpMXLadtw4gYQZ7C540DJJ3J0Zw0ihw9aluQKf6bJwndJplBMZ2gSqI8skMo tMBIq5aBkfhlOrRcx4lTWbfCG70rBBIsyrOtIb2rtvEqBg0RDxDHNA3KHIWH+9tgMMEN8y/5Nfz 3q6YXxMipR2/DYlZA9/21yzqU6cRDZYBiXgigxQ/rb6+K9DbbdkhiUVxaXV9IQtupd2WYpkvCHo Y1gJOdvMRt6FSyf+D8HlYm5il4qXm9jIAKQ0tN21Pk2zFr94woB92lSVHfUB9pVePlqRGkv9iyO N/mwPspnNb/xOlvkLXw== X-Proofpoint-GUID: Qy9O-TADAMyhaKBMZxGh0xXIfXKBIWK1 X-Proofpoint-ORIG-GUID: Qy9O-TADAMyhaKBMZxGh0xXIfXKBIWK1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 impostorscore=0 spamscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070050 Some CMN PLL output clocks require a hardware gate in addition to a fixed rate. The gate control bits reside in the register CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered via a new struct clk_fixed_gate and clk_fixed_gate_ops, combining a fixed rate with enable/disable/is_enabled gate control through the shared regmap for CMN_PLL_OUTPUT_RELATED_1. The enable_bit field is added to struct cmn_pll_fixed_output_clk (set to -1 for non-gated clocks). The CLK_PLL_OUTPUT_RAW() and CLK_PLL_GATE() helper macros are introduced alongside the existing CLK_PLL_OUTPUT(). Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 141 +++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 136 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 586f9c620e7e..2b05896ff00f 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -93,9 +93,19 @@ #define CMN_PLL_DIVIDER_CTRL 0x794 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) =20 +/* Clock gate enable bits. */ +#define CMN_PLL_OUTPUT_RELATED_1 0x79c +#define CLK25M_EN_BIT 15 +#define CLK50M_EN_BIT3_BIT 14 +#define CLK250M_EN_BIT 13 +#define CLK31P25M_EN_BIT 12 +#define CLK50M_EN_BIT 11 +#define CLK50M_EN_BIT2_BIT 10 + /** * enum cmn_pll_clk_type - CMN PLL output clock registration type * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock + * @CMN_PLL_CLK_FIXED_GATE: fixed rate clock with a hardware gate * @CMN_PLL_CLK_NSS: NSS clock with configurable divider * @CMN_PLL_CLK_PPE: PPE clock with configurable divider * @CMN_PLL_CLK_PON: PON reference clock @@ -103,6 +113,7 @@ */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, + CMN_PLL_CLK_FIXED_GATE, CMN_PLL_CLK_NSS, CMN_PLL_CLK_PPE, CMN_PLL_CLK_PON, @@ -115,33 +126,66 @@ enum cmn_pll_clk_type { * @name: Clock name to be registered * @type: Clock registration type * @rate: Clock rate + * @enable_bit: Enable bit in CMN_PLL_OUTPUT_RELATED_1 for gate clock, + * -1 for non-gated clocks. */ struct cmn_pll_fixed_output_clk { unsigned int id; const char *name; enum cmn_pll_clk_type type; unsigned long rate; + int enable_bit; }; =20 /** * struct clk_cmn_pll - CMN PLL hardware specific data * @regmap: hardware regmap. * @hw: handle between common and hardware-specific interfaces + * + * This structure is used for all CMN PLL-derived clocks including + * the main PLL, NSS clock, PPE clock, PON reference clock, and + * EPHY-RAW clock. */ struct clk_cmn_pll { struct regmap *regmap; struct clk_hw hw; }; =20 -#define CLK_PLL_OUTPUT(_id, _name, _rate) { \ - .id =3D _id, \ - .name =3D _name, \ - .type =3D CMN_PLL_CLK_FIXED_RATE, \ - .rate =3D _rate, \ +/** + * struct clk_fixed_gate - fixed rate clock with a hardware gate + * @regmap: hardware regmap. + * @hw: handle between common and hardware-specific interfaces + * @rate: fixed clock rate. + * @enable_bit: enable bit in CMN_PLL_OUTPUT_RELATED_1, which is shared + * across multiple gate clocks, but regmap already serializes + * read-modify-write access to a given register, so no + * additional locking is needed here. + */ +struct clk_fixed_gate { + struct regmap *regmap; + struct clk_hw hw; + unsigned long rate; + int enable_bit; +}; + +#define CLK_PLL_OUTPUT_RAW(_id, _name, _type, _rate, _bit) { \ + .id =3D _id, \ + .name =3D _name, \ + .type =3D _type, \ + .rate =3D _rate, \ + .enable_bit =3D _bit, \ } =20 +#define CLK_PLL_OUTPUT(_id, _name, _rate) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_RATE, _rate, -1) + +#define CLK_PLL_GATE(_id, _name, _rate, _bit) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_GATE, _rate, _bit) + #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) =20 +#define to_clk_fixed_gate(_hw) container_of(_hw, struct clk_fixed_gate, hw) + static const struct regmap_config ipq_cmn_pll_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -670,6 +714,85 @@ static struct clk_hw *ipq_cmn_pll_ephy_raw_register(st= ruct platform_device *pdev return &ephy_raw_clk->hw; } =20 +static int clk_fixed_gate_enable(struct clk_hw *hw) +{ + struct clk_fixed_gate *gate_clk =3D to_clk_fixed_gate(hw); + + return regmap_set_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, + BIT(gate_clk->enable_bit)); +} + +static void clk_fixed_gate_disable(struct clk_hw *hw) +{ + struct clk_fixed_gate *gate_clk =3D to_clk_fixed_gate(hw); + + regmap_clear_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, + BIT(gate_clk->enable_bit)); +} + +static int clk_fixed_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_fixed_gate *gate_clk =3D to_clk_fixed_gate(hw); + + return regmap_test_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, + BIT(gate_clk->enable_bit)); +} + +static unsigned long clk_fixed_gate_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_fixed_gate *gate_clk =3D to_clk_fixed_gate(hw); + + return gate_clk->rate; +} + +static const struct clk_ops clk_fixed_gate_ops =3D { + .enable =3D clk_fixed_gate_enable, + .disable =3D clk_fixed_gate_disable, + .is_enabled =3D clk_fixed_gate_is_enabled, + .recalc_rate =3D clk_fixed_gate_recalc_rate, +}; + +static struct clk_hw *ipq_cmn_pll_register_fixed_gate(struct device *dev, + const char *name, + struct clk_hw *parent_hw, + struct regmap *regmap, + unsigned long rate, + int enable_bit) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct clk_fixed_gate *gate_clk; + struct clk_init_data init =3D {}; + int ret; + + gate_clk =3D devm_kzalloc(dev, sizeof(*gate_clk), GFP_KERNEL); + if (!gate_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_fixed_gate_ops; + /* + * These gated clocks may be relied on by external hardware or + * bootloader-enabled paths without an in-kernel client driver. + * Add CLK_IGNORE_UNUSED so the clock framework does not disable + * them when no consumer has claimed them. + */ + init.flags =3D CLK_IGNORE_UNUSED; + + gate_clk->hw.init =3D &init; + gate_clk->regmap =3D regmap; + gate_clk->rate =3D rate; + gate_clk->enable_bit =3D enable_bit; + + ret =3D devm_clk_hw_register(dev, &gate_clk->hw); + if (ret) + return ERR_PTR(ret); + + return &gate_clk->hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -709,6 +832,14 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) hw =3D ERR_PTR(-EINVAL); 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The IPQ5210 CMN PLL supplies 12 output clocks: Fixed-rate: XO 24 MHz, sleep 32 kHz Gated fixed-rate: PCS 31.25 MHz, ETH0/1/2 50 MHz, EPHY 50 MHz, ETH 25 MHz Configurable divider: NSS, PPE PON reference: PON (enable/disable + 8-bit divider) EPHY-RAW: 125/312.5 MHz select Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 2b05896ff00f..eeadc94a23df 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -55,6 +55,7 @@ =20 #include #include +#include #include #include #include @@ -182,6 +183,18 @@ struct clk_fixed_gate { #define CLK_PLL_GATE(_id, _name, _rate, _bit) \ CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_GATE, _rate, _bit) =20 +#define CLK_PLL_NSS(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_NSS, 0, -1) + +#define CLK_PLL_PPE(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_PPE, 0, -1) + +#define CLK_PLL_PON(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_PON, 0, -1) + +#define CLK_PLL_EPHY_RAW(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_EPHY_RAW, 0, -1) + #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) =20 #define to_clk_fixed_gate(_hw) container_of(_hw, struct clk_fixed_gate, hw) @@ -200,6 +213,22 @@ static const struct cmn_pll_fixed_output_clk ipq5018_o= utput_clks[] =3D { { /* Sentinel */ } }; =20 +static const struct cmn_pll_fixed_output_clk ipq5210_output_clks[] =3D { + CLK_PLL_OUTPUT(IPQ5210_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(IPQ5210_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_GATE(IPQ5210_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL, CLK31P= 25M_EN_BIT), + CLK_PLL_GATE(IPQ5210_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL, CLK50M_EN_= BIT), + CLK_PLL_GATE(IPQ5210_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL, CLK50M_EN_= BIT2_BIT), + CLK_PLL_GATE(IPQ5210_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL, CLK50M_EN_= BIT3_BIT), + CLK_PLL_GATE(IPQ5210_EPHY_50MHZ_CLK, "ephy-50mhz", 50000000UL, CLK250M_EN= _BIT), + CLK_PLL_GATE(IPQ5210_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL, CLK25M_EN_BI= T), + CLK_PLL_NSS(IPQ5210_NSS_CLK, "nss"), + CLK_PLL_PPE(IPQ5210_PPE_CLK, "ppe"), + CLK_PLL_PON(IPQ5210_PON_REFCLK, "pon"), + CLK_PLL_EPHY_RAW(IPQ5210_EPHY_RAW_CLK, "ephy-raw"), + { /* Sentinel */ } +}; + static const struct cmn_pll_fixed_output_clk ipq6018_output_clks[] =3D { CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL), CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 4165= 00000UL), @@ -942,6 +971,7 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops =3D { =20 static const struct of_device_id ipq_cmn_pll_clk_ids[] =3D { { .compatible =3D "qcom,ipq5018-cmn-pll", .data =3D &ipq5018_output_clks = }, + { .compatible =3D "qcom,ipq5210-cmn-pll", .data =3D &ipq5210_output_clks = }, { .compatible =3D "qcom,ipq5332-cmn-pll", .data =3D &ipq5332_output_clks = }, { .compatible =3D "qcom,ipq5424-cmn-pll", .data =3D &ipq5424_output_clks = }, { .compatible =3D "qcom,ipq6018-cmn-pll", .data =3D &ipq6018_output_clks = }, --=20 2.43.0 From nobody Thu Oct 1 15:52:42 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE4D14570FA for ; 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The reference clock of CMN PLL is routed from XO to the CMN PLL through the WiFi block. XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 15 +++++++++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 941f866ecfe9..7410d092814e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -74,6 +74,21 @@ &uart1 { status =3D "okay"; }; =20 +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically + * enables the right dividers, to ensure the reference clock output + * from WiFi to the CMN PLL is 48 MHZ. + */ +&ref_48mhz_clk { + clock-div =3D <1>; + clock-mult =3D <1>; +}; + &xo_board { clock-frequency =3D <24000000>; }; + +&xo_clk { + clock-frequency =3D <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 2cdc10529c48..7025bdd9036e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include =20 / { @@ -13,6 +14,12 @@ / { interrupt-parent =3D <&intc>; =20 clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -22,6 +29,11 @@ xo_board: xo-board-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; }; + + xo_clk: xo-clk { + compatible =3D "fixed-clock"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19842bsm223493a12.4.2026.08.06.23.53.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 23:53:35 -0700 (PDT) From: Luo Jie Date: Thu, 06 Aug 2026 23:53:16 -0700 Subject: [PATCH v2 12/12] arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-qcom_ipq5210_cmnpll-v2-12-cce718b8ec17@oss.qualcomm.com> References: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> In-Reply-To: <20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1786085595; l=1388; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=fCMrPmPUNafBvO10YWswU3IRQXLhDtGia0biGdyfMJ8=; b=zPJlTejwSlIiks/S9GRhED1Pg5YBRxh98sLwAUScXZ53SPlbxLbxUTMzkOZwvLodCgXwbG4G6 anQKjPEKjnBAlDnIFqihtVPf7C1hRVHjV5hWa31Mv84wgfUqvHvn8pA X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfXx24PU0K04CKV nhJWtAGVYYNcf0WICOvr3djszX41RgC7acNd3Teu/msIymV4HRekCy3147+qktL5t7G7LrmWVYF invzEo2D1kfVqDCGx5ZChRnU6Bvz1Lzjx22e78aGWRoRlsqIEIoCGclzWuJc+iaVGCAM4ZrQ2Cn oOQ3/P6XH23yKWhG/eJ2xQUw5FzgzXyK6z3Vjcak9J1EF2mfrm140zXm8uPg0HdKd9v2L6445nF kcluIBg21so5Mn7rZSf6hKNJqwISB3bjfcLCPZANEHBhUtKEGlNMXYS60Am+hi7CKSTWdZTgAJq HX+xyz8GFvo1Ib+MQz9Aobyl2t/1fGbhnywMBEtWN9+5N9VTogQYy8BfKFDlttxTud/3pPqs3tL 87zeF0elyF5OR2KGoEv4xSdIAcSzkoYDdK5DhIvUokV/aLSt9s3iDRs+bd0tPTE3rWDDLnHQxtg vvvae90o7YM6lp7gaLg== X-Authority-Analysis: v=2.4 cv=HPXz0Itv c=1 sm=1 tr=0 ts=6a7580f1 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=CPdYy-Otk887xBsD2wUA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: LenD1iShamnXczh2iCVFrS06ic8bCiPQ X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1MCBTYWx0ZWRfX/8xvVporBw9n H100K3hlgG5d/wH5npVBNiziAHdOnngAyWrg8kNcu3+k1qzi6cOFtLtIZqsLm2SR5jGgQNlUTFu +2O8zFvnIWdlyrOis5RMzr4QD3bOnwo= X-Proofpoint-GUID: LenD1iShamnXczh2iCVFrS06ic8bCiPQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 adultscore=0 spamscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070050 xo_board is fixed to 24 MHZ, which is routed from WiFi output clock 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 7 ++++++- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 7410d092814e..fa537633d5f5 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -85,8 +85,13 @@ &ref_48mhz_clk { clock-mult =3D <1>; }; =20 +/* + * The frequency of xo_board is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board { - clock-frequency =3D <24000000>; + clock-div =3D <2>; + clock-mult =3D <1>; }; =20 &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 7025bdd9036e..8f6b37041132 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -26,7 +26,8 @@ sleep_clk: sleep-clk { }; =20 xo_board: xo-board-clk { - compatible =3D "fixed-clock"; + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; #clock-cells =3D <0>; }; =20 --=20 2.43.0