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X1E80100 compatible forces the software workaround. Add PDC compatible for purwa as "qcom,x1p42100-pdc" to remove the workaround from Purwa. Reviewed-by: Krzysztof Kozlowski Acked-by: Konrad Dybcio Signed-off-by: Maulik Shah --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index 8162a49d49a6..b3d19c86a240 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -58,6 +58,7 @@ properties: - qcom,sm8650-pdc - qcom,sm8750-pdc - qcom,x1e80100-pdc + - qcom,x1p42100-pdc - const: qcom,pdc =20 reg: --=20 2.43.0 From nobody Fri Oct 2 01:55:51 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB9E542048F for ; Thu, 6 Aug 2026 08:56:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Add support to reset the PDC to pass through mode using qcom_scm_io_writel() similar to X1E80100. Make sure x1e_quirk to workaround a hardware bug is set only for X1E80100 as X1P42100 have this fixed in silicon. Signed-off-by: Maulik Shah Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/irqchip/qcom-pdc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index ce6d80c7f17a..29025a212ece 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -715,7 +715,10 @@ static int qcom_pdc_probe(struct platform_device *pdev= , struct device_node *pare } =20 pdc->x1e_quirk =3D true; + } =20 + if (of_device_is_compatible(node, "qcom,x1e80100-pdc") || + of_device_is_compatible(node, "qcom,x1p42100-pdc")) { if (!qcom_scm_is_available()) return -EPROBE_DEFER; =20 --=20 2.43.0 From nobody Fri Oct 2 01:55:51 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CE93420478 for ; Thu, 6 Aug 2026 08:56:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=ed25519-sha256; t=1786006595; l=1193; i=maulik.shah@oss.qualcomm.com; s=20240109; h=from:subject:message-id; bh=4ZppwTlfz6Ivjj4MWFvZ2LiBEjnO14YAj/9Y226N4TU=; b=5mG8Aa+uU4xTPGAY1nMtGuNS/JdMZBrC0S7pP/NQjP0zTCkAhYrX6vhPaLHOrZ8mZM9nMu/ik q4by26z5529Akz6LRRj3bOr+5U+yjW+qvp36MDIfmxpIyZCuOLzUsnp X-Developer-Key: i=maulik.shah@oss.qualcomm.com; a=ed25519; pk=bd9h5FIIliUddIk8p3BlQWBlzKEQ/YW5V+fe759hTWQ= X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDA2OSBTYWx0ZWRfX7MSd8GpE9+tC bSoQB8xEJwyyejDwTndZKp/1DIjRqwqR6HLBjtPvkzY5hGJu7P0698qZG19PAUbo/wuuyxaRkqW VbwuJedKAd5Qq1HtxD/ZYih6Qri3bM8= X-Proofpoint-GUID: RxgKqOW0Hd9rNz7ycKF7LCSk0LhW0GvU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDA2OSBTYWx0ZWRfX2tIr3zOPUf43 527tZj1reZ/wTBZLse0dPtyATwJKz1Fel46ZkRf/1DEDAaoLumsntBpgg6Iqt+coZ0lEnUvTtpM Iea9HodzSIl0nscS4W3tLuYe+OsFzQVxBsy3heSC8GgQYcXghsjGmNuReWtlL9IFD/BTa+paOk0 lb1RHFOUr+FK9gKKtQTjxxUqVNqtqer77Zf881m/c13yDn1NF+Phn5vrFL8QdTxrZyv6lCcICYK 0kdb1tXOKkmW5+2eFD6Eevq6Zgx9y/8WIEO43DrR7uRa1flTQs8LXOg/10Of4hU5NQTPFIpZLBc gz449Y9s0odhMvQp+29MItqoW03X16yt01Kei1i6fDWh1JLK2BEvvb1HxLXnsP6uc84LUARo2cT 0W6SamJnUZYVNg5Wzv5Dvs4VXt763T+B6UgePY2TzUTZ70I7/UxMX7Xam2uwxBkGKrmW7l0Zp2u Ezjsf+MAjGkFYAVPGMA== X-Authority-Analysis: v=2.4 cv=Mo1iLWae c=1 sm=1 tr=0 ts=6a744c55 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=vCmKDeXsP24Y5dEMWNIA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: RxgKqOW0Hd9rNz7ycKF7LCSk0LhW0GvU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-05_06,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060069 X1P42100 (Purwa) shares the X1E80100 (Hamoa) PDC device, but the hardware register bug addressed in commit e9a48ea4d90b ("irqchip/qcom-pdc: Workaround hardware register bug on X1E80100") is already fixed in X1P42100 silicon. X1E80100 compatible forces the software workaround. Use the X1P42100 specific compatible string for the PDC node to remove the workaround. Fixes: f08edb529916 ("arm64: dts: qcom: Add X1P42100 SoC and CRD") Reviewed-by: Konrad Dybcio Signed-off-by: Maulik Shah Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/purwa.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom= /purwa.dtsi index c698e6cb2543..4348dd3d1dc5 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -224,6 +224,11 @@ &pcie6a_phy { compatible =3D "qcom,x1p42100-qmp-gen4x4-pcie-phy"; }; =20 +/* X1P42100 PDC is same as X1E80100, but without hardware register bug */ +&pdc { + compatible =3D "qcom,x1p42100-pdc", "qcom,pdc"; +}; + &qfprom { gpu_speed_bin: gpu-speed-bin@119 { reg =3D <0x119 0x2>; --=20 2.43.0