From nobody Fri Oct 2 01:10:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEDC144213A; Thu, 6 Aug 2026 14:51:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786027909; cv=none; b=lQClSbnUx1uALzvDGuEIutBxQnK8Ukzk9GkdW+WZvuSfEtU9sw3K4wBW3YNO+RhDILZoWgxzxGFKJxkcnGooYB6TqDEIyx0suNkNnMMbgkR7MGP/RSZGnFBnRZcRFlkH688fr7cUlHMhK/DayyUYHNOeCTXJ/5KTPzPxuJmRtn8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786027909; c=relaxed/simple; bh=oEa1rZ7jhjgKUm5sxpeN55GPhpoxQuvfkNNHnl/9FHQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KoSsJe6WoqB4+O82CqTThTxIdYh2poXl5BIzx+Xek0ft3AP6Bc08E8G3QllceBy/X57waUthwDJwH4GvOhTHm0lD6b7ZvwDhBgp/EIP2dvHSFvBgn4Mt1rjJUFReH/t/7RVsLhoxE09/l910bBV2HwV1MT4ikSYOyd9aysLSnXQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DTS5vp83; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DTS5vp83" Received: by smtp.kernel.org (Postfix) with ESMTPS id 63F6EC2BCB9; Thu, 6 Aug 2026 14:51:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786027909; bh=oEa1rZ7jhjgKUm5sxpeN55GPhpoxQuvfkNNHnl/9FHQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DTS5vp83U09PG6xNL5uVi0RDzn3f7BfuokZyraDKEgnMWQGtaxkm6E2Ntwen8iod7 B5MbAcWtiCu4XPD48fue8TIBUCDuDCl3d+vkWUvzGopGGojP6PCmb6Nu/ZQADUa5a+ pmQEwHqMUyZ4I8eCsffGiLwapgXVS1qlwKk7evXFpjW292XoSNwVzG4SrGgqT5/389 0FfWp+kUB+fNRFXFPiSPiTymgPnj00n7S+xgUU/N3KaaWX+O8ArJwUZqbZlg0T6uPY KzQ9RO6w7nglUQubawnvyDXw6l8z/XkLL5l155mcNLie7XwwrLKoXvjN7shMbw6Kgx AUG61BVLmWhWQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40F7CC56207; Thu, 6 Aug 2026 14:51:49 +0000 (UTC) From: Sarath Ganapathiraju via B4 Relay Date: Thu, 06 Aug 2026 20:21:36 +0530 Subject: [PATCH v5 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-master-20260805-sync-v5-1-0ff42e9b6431@oss.qualcomm.com> References: <20260806-master-20260805-sync-v5-0-0ff42e9b6431@oss.qualcomm.com> In-Reply-To: <20260806-master-20260805-sync-v5-0-0ff42e9b6431@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prasad.kumpatla@oss.qualcomm.com, Sarath Ganapathiraju , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786027907; l=2278; i=sarath.ganapathiraju@oss.qualcomm.com; s=default; h=from:subject:message-id; bh=qxVOLK3Yva6vAmZ6Xln4mzA/Miy1La7zeDTze4nIz90=; b=87HM7BtBsxxGw2O5gXizH1O4GgWMqqzSmrvoovkXlvDd5KvAQHQCY9+PNew5ooQAXBH4DvikZ dGQsisWptNVATfEoynSAlarQnXWnfUGvDYKn0FNWKQ3cXJ9Zmo4I3WZ X-Developer-Key: i=sarath.ganapathiraju@oss.qualcomm.com; a=ed25519; pk=4p2FWGXM+F2sir13Lu5stw5aKX5trUymK/ttESvgxQg= X-Endpoint-Received: by B4 Relay for sarath.ganapathiraju@oss.qualcomm.com/default with auth_id=870 X-Original-From: Sarath Ganapathiraju Reply-To: sarath.ganapathiraju@oss.qualcomm.com From: Sarath Ganapathiraju Add a binding for the Qualcomm LPASS VA CSR rate generator node that exposes the lpass_heartbeat_pulse clock on hawi. The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the start of the DMAs and Codec Interfaces for the audio usecase and can serve as a periodic wakeup source for the DSP. Signed-off-by: Sarath Ganapathiraju Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 51 ++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr= .yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml new file mode 100644 index 000000000000..9935173d8bee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,hawi-lpass-va-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS VA CSR heartbeat pulse clock provider + +maintainers: + - Srinivas Kandagatla + - Sarath Ganapathiraju + +description: + The LPASS (Low Power Audio Subsystem) VA CSR block contains a rate + generator that produces a periodic HeartBeat Pulse, also known as + the RateGen Pulse. This pulse synchronizes the start of DMAs and + Codec Interfaces for audio usecases and can serve as a periodic + wakeup source for the DSP. + +properties: + compatible: + enum: + - qcom,hawi-lpass-va-csr + + reg: + maxItems: 1 + description: Address and size of the rate generator registers within + the VA CSR block. + + "#clock-cells": + const: 0 + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@7eed000 { + compatible =3D "qcom,hawi-lpass-va-csr"; + reg =3D <0x0 0x07eed000 0x0 0x14>; + #clock-cells =3D <0>; + }; + }; --=20 2.34.1 From nobody Fri Oct 2 01:10:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEC403A83B1; Thu, 6 Aug 2026 14:51:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786027909; cv=none; b=tAux11n2N3143zHpn3oIAiokdlyM9HfW5Dki+1y0PzSkZR4w9YdOaEMKF5TdYmU5XCVCzN7oOcruS/j1oft1Ix/11a5leJoUK8h0DVxJ0vJ2UxIgFEEvWXPK4YHwngolGMg5Np2DNL8l8B3SHMyrjh6hmrULF/6ZwHbmQFzonrU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786027909; c=relaxed/simple; bh=soxRym6RY3RfM53rerMfeBGkcyCA5XDKnD5/Hsi4xLM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qyHmXkPuRCXrXTE/ibOn+3QjbT/sbrI0ifu0qfmTo01whAQX0V/qR408N84pY9VPOyVY9cBQeF2Zifgu/XP7UmUPG27XDbOrXOKgb6w2ibrKZX2FxE0c5Sf322il62eSYBir4IjuPcvqP9AQtXe1wUEWyv46yDN4cpV19WPa7T8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oi1xGXzP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oi1xGXzP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 70FFEC2BCFB; Thu, 6 Aug 2026 14:51:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786027909; bh=soxRym6RY3RfM53rerMfeBGkcyCA5XDKnD5/Hsi4xLM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oi1xGXzP4M6ua5KBcjtxymCs4V5pQtOp5rYAjKUw+FSKa+1vd5qdwTxumMPmr+8Ne 3HtByVEb5oK0S7box4p418nEOTkvnbumBbsbtRjAbcA6whp0jAhbU+A8KNZx4a7X02 NK8waTkHi3MKaxH+KGtS0C9UCvYTq7VTKZ67yUvXIvT4uhoX92dDt88nDSjz+MJmNt ylYor4v/P8g0V82FbgeDsqAEbf+p+SnuzwKC9JEMFNtxFJiWSa4brkDPNI/wczWJod H8FpJk/HbZtrIy21cwKQ2xAGtlg3sL3mPnYSe+cH5xGAYkGF6rgYjzYkQFd/HhF/+T Q2PiuUoiolYeg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51D3CC5AC7C; Thu, 6 Aug 2026 14:51:49 +0000 (UTC) From: Sarath Ganapathiraju via B4 Relay Date: Thu, 06 Aug 2026 20:21:37 +0530 Subject: [PATCH v5 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260806-master-20260805-sync-v5-2-0ff42e9b6431@oss.qualcomm.com> References: <20260806-master-20260805-sync-v5-0-0ff42e9b6431@oss.qualcomm.com> In-Reply-To: <20260806-master-20260805-sync-v5-0-0ff42e9b6431@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prasad.kumpatla@oss.qualcomm.com, Sarath Ganapathiraju X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786027907; l=6661; i=sarath.ganapathiraju@oss.qualcomm.com; s=default; h=from:subject:message-id; bh=QCZX+fDXiHb3ToEAJRmgWv5daRhV3Xx1Tckmhg/5yfY=; b=NNtJmRDse4DTlxPlb0X+zf53FAcSDL0pkv1wSeV+EF4q5m1PlOAeK0sWBzhWdEyEYl1qplow+ 076wDW88awNCEfjZio1WA9IPuF4lnCd3h6FCMVN9UGl1+7gF/ruplk9 X-Developer-Key: i=sarath.ganapathiraju@oss.qualcomm.com; a=ed25519; pk=4p2FWGXM+F2sir13Lu5stw5aKX5trUymK/ttESvgxQg= X-Endpoint-Received: by B4 Relay for sarath.ganapathiraju@oss.qualcomm.com/default with auth_id=870 X-Original-From: Sarath Ganapathiraju Reply-To: sarath.ganapathiraju@oss.qualcomm.com From: Sarath Ganapathiraju The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the start of the DMAs and Codec Interfaces for the audio usecases and can serve as a periodic wakeup source for the DSP. Add the LPASS VA CSR driver that models the rate generator as a clock provider so it is enabled and disabled automatically alongside the other clocks during runtime PM resume and suspend. Signed-off-by: Sarath Ganapathiraju --- drivers/clk/qcom/Kconfig | 14 ++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpass-va-csr.c | 148 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 163 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d1fc9bf87126..756f6ed727d0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -2040,6 +2040,20 @@ config CLK_GFM_LPASS_SM8250 Support for the Glitch Free Mux (GFM) Low power audio subsystem (LPASS) clocks found on SM8250 SoCs. =20 +config QCOM_CLK_LPASS_HEARTBEAT_PULSE + tristate "Qualcomm LPASS VA CSR heartbeat pulse clock provider" + depends on COMMON_CLK + depends on ARM64 || COMPILE_TEST + select REGMAP_MMIO + default m if ARCH_QCOM + help + Qualcomm LPASS VA CSR block contains the rate generator hardware + that produces the HeartBeat Pulse (also known as RateGen Pulse). + This driver models the rate generator as a clock provider so + that consumers can enable or disable it via the common clock + framework, and it can be used to synchronize the start of DMAs + and Codec Interfaces or as a periodic wakeup source for the DSP. + config SM_VIDEOCC_8450 tristate "SM8450 Video Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index daf25d583be2..8d3e3381bc29 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_CLK_ELIZA_DISPCC) +=3D dispcc-eliza.o obj-$(CONFIG_CLK_ELIZA_GCC) +=3D gcc-eliza.o obj-$(CONFIG_CLK_ELIZA_TCSRCC) +=3D tcsrcc-eliza.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o +obj-$(CONFIG_QCOM_CLK_LPASS_HEARTBEAT_PULSE) +=3D lpass-va-csr.o obj-$(CONFIG_CLK_GLYMUR_CAMCC) +=3D camcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_EVACC) +=3D evacc-glymur.o diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-cs= r.c new file mode 100644 index 000000000000..2e692407a966 --- /dev/null +++ b/drivers/clk/qcom/lpass-va-csr.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define LPASS_RATE_GEN_CTRL 0xd000 +#define LPASS_RATE_GEN_COUNTER_0 0xd004 +#define LPASS_RATE_GEN_DELAY 0xd010 + +#define LPASS_RATE_GEN_MAX_REG LPASS_RATE_GEN_DELAY + +#define LPASS_RG_CTRL_EN BIT(0) + +struct lpass_va_csr_data { + u32 counter_0; + u32 delay; +}; + +static const struct lpass_va_csr_data hawi_csr_data =3D { + .counter_0 =3D 0x960, + .delay =3D 0x16, +}; + +static const struct regmap_config lpass_rate_gen_regmap_config =3D { + .name =3D "lpass_rate_gen", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D LPASS_RATE_GEN_MAX_REG, + .cache_type =3D REGCACHE_MAPLE, +}; + +struct lpass_va_csr { + struct regmap *regmap; + const struct lpass_va_csr_data *data; + struct clk_hw hb_hw; +}; + +#define to_lpass_va_csr(_hw) container_of(_hw, struct lpass_va_csr, hb_hw) + +static int heartbeat_pulse_prepare(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + int ret; + + ret =3D regmap_write(csr->regmap, LPASS_RATE_GEN_COUNTER_0, csr->data->co= unter_0); + if (ret) + return ret; + + ret =3D regmap_write(csr->regmap, LPASS_RATE_GEN_DELAY, csr->data->delay); + if (ret) + return ret; + + return regmap_set_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN= ); +} + +static void heartbeat_pulse_unprepare(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + + regmap_clear_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN); +} + +static int heartbeat_pulse_is_prepared(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + + return regmap_test_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_E= N); +} + +static const struct clk_ops heartbeat_pulse_ops =3D { + .prepare =3D heartbeat_pulse_prepare, + .unprepare =3D heartbeat_pulse_unprepare, + .is_prepared =3D heartbeat_pulse_is_prepared, +}; + +static int lpass_va_csr_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct lpass_va_csr *csr; + struct clk_init_data init =3D { + .name =3D "lpass_heartbeat_pulse", + .ops =3D &heartbeat_pulse_ops, + }; + void __iomem *base; + int ret; + + csr =3D devm_kzalloc(dev, sizeof(*csr), GFP_KERNEL); + if (!csr) + return -ENOMEM; + + csr->data =3D of_device_get_match_data(dev); + if (!csr->data) + return dev_err_probe(dev, -EINVAL, "no variant data for compatible\n"); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + csr->regmap =3D devm_regmap_init_mmio(dev, base, + &lpass_rate_gen_regmap_config); + if (IS_ERR(csr->regmap)) + return dev_err_probe(dev, PTR_ERR(csr->regmap), + "failed to init regmap\n"); + + csr->hb_hw.init =3D &init; + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "failed to enable PM runtime\n"); + + ret =3D devm_clk_hw_register(dev, &csr->hb_hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register heartbeat clock\n"); + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &csr->hb_h= w); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + return 0; +} + +static const struct of_device_id lpass_va_csr_dt_match[] =3D { + { .compatible =3D "qcom,hawi-lpass-va-csr", .data =3D &hawi_csr_data }, + {} +}; +MODULE_DEVICE_TABLE(of, lpass_va_csr_dt_match); + +static struct platform_driver lpass_va_csr_driver =3D { + .driver =3D { + .name =3D "qcom-lpass-va-csr", + .of_match_table =3D lpass_va_csr_dt_match, + }, + .probe =3D lpass_va_csr_probe, +}; + +module_platform_driver(lpass_va_csr_driver); + +MODULE_DESCRIPTION("Qualcomm LPASS VA CSR heartbeat pulse clock provider"); +MODULE_LICENSE("GPL"); --=20 2.34.1