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Wed, 5 Aug 2026 02:38:41 -0400 (EDT) From: Jiaxing Hu To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, alchark@flipper.net, chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [RFC PATCH v5 v5 1/8] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Date: Wed, 5 Aug 2026 18:38:19 +1200 Message-ID: <20260805063826.95682-2-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805063826.95682-1-gahing@gahingwoo.com> References: <20260805063826.95682-1-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RK3576 NPU has two cores of the same RKNN block the RK3588 binding already describes, but it wires them up differently: two extra CBUF clocks, two power domains per core, and a single reset instead of two. It also has no NPU SRAM supply. Widen the property ranges to cover both, then pin each SoC back to its own shape in allOf so nothing loosens for RK3588, and keep sram-supply required for rockchip,rk3588-rknn-core only. Signed-off-by: Jiaxing Hu --- .../npu/rockchip,rk3588-rknn-core.yaml | 47 +++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-cor= e.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.ya= ml index caca2a490..3b611b64c 100644 --- a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml @@ -21,6 +21,7 @@ properties: =20 compatible: enum: + - rockchip,rk3576-rknn-core - rockchip,rk3588-rknn-core =20 reg: @@ -33,14 +34,18 @@ properties: - const: core # Main NPU core processing unit registers =20 clocks: - maxItems: 4 + minItems: 4 + maxItems: 6 =20 clock-names: + minItems: 4 items: - const: aclk - const: hclk - const: npu - const: pclk + - const: aclk_cbuf + - const: hclk_cbuf =20 interrupts: maxItems: 1 @@ -51,12 +56,15 @@ properties: npu-supply: true =20 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 resets: + minItems: 1 maxItems: 2 =20 reset-names: + minItems: 1 items: - const: srst_a - const: srst_h @@ -75,7 +83,40 @@ required: - resets - reset-names - npu-supply - - sram-supply + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3588-rknn-core + then: + properties: + clocks: + maxItems: 4 + clock-names: + maxItems: 4 + power-domains: + maxItems: 1 + resets: + minItems: 2 + reset-names: + minItems: 2 + required: + - sram-supply + else: + properties: + clocks: + minItems: 6 + clock-names: + minItems: 6 + power-domains: + minItems: 2 + resets: + maxItems: 1 + reset-names: + maxItems: 1 + sram-supply: false =20 additionalProperties: false =20 --=20 2.43.0 From nobody Sat Oct 3 04:23:47 2026 Received: from flow-a7-smtp.messagingengine.com (flow-a7-smtp.messagingengine.com [103.168.172.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33C013DB309; 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Wed, 5 Aug 2026 02:38:50 -0400 (EDT) From: Jiaxing Hu To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, alchark@flipper.net, chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [RFC PATCH v5 v5 2/8] dt-bindings: power: rockchip: allow resets in a power domain node Date: Wed, 5 Aug 2026 18:38:20 +1200 Message-ID: <20260805063826.95682-3-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805063826.95682-1-gahing@gahingwoo.com> References: <20260805063826.95682-1-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some domains do not come up in a usable state on their own and need their resets cycled once power is on. The RK3576 NPU domains are one case: without it the first access after power-on takes an async SError. pd-node has no resets property and every nesting level is unevaluatedProperties: false, so describing that in DT is rejected today. Add it alongside clocks. Signed-off-by: Jiaxing Hu --- .../bindings/power/rockchip,power-controller.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-control= ler.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controlle= r.yaml index b41db576f..f23c1a118 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -136,6 +136,14 @@ $defs: A number of phandles to clocks that need to be enabled while power domain switches state. =20 + resets: + minItems: 1 + maxItems: 30 + description: | + A number of phandles to resets that need to be cycled once the p= ower + domain has been switched on, for domains whose logic does not co= me up + in a usable state by itself. + domain-supply: description: domain regulator supply. =20 --=20 2.43.0 From nobody Sat Oct 3 04:23:47 2026 Received: from flow-a7-smtp.messagingengine.com (flow-a7-smtp.messagingengine.com [103.168.172.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 620533DAAAF; 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Wed, 5 Aug 2026 02:39:00 -0400 (EDT) From: Jiaxing Hu To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, alchark@flipper.net, chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [RFC PATCH v5 v5 3/8] dt-bindings: iommu: rockchip: allow the RK3576 NPU MMU clock set Date: Wed, 5 Aug 2026 18:38:21 +1200 Message-ID: <20260805063826.95682-4-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805063826.95682-1-gahing@gahingwoo.com> References: <20260805063826.95682-1-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RK3576 NPU MMUs need more than aclk and iface. With only those two enabled the MMU accepts reads but silently drops register writes: a DTE_ADDR value written from the power domain, while the domain clocks are still on, reads back correctly, and the write rk_iommu_resume() does microseconds later does not land at all. The vendor DT names the CBUF clocks as that MMU's interface clocks and its driver keeps every NPU clock on for as long as the device is powered. The driver side of this is already upstream, commit 841363ebb508 ("iommu/rockchip: Take all DT clocks"), which switched rk_iommu to devm_clk_bulk_get_all(). Widen the schema to match so those nodes can be described. minItems stays at 2, so every existing devicetree, which all carry exactly aclk and iface, is unaffected. Signed-off-by: Jiaxing Hu --- .../devicetree/bindings/iommu/rockchip,iommu.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml b/= Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml index 6ce41d11f..a3cedcaaa 100644 --- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml @@ -42,14 +42,22 @@ properties: minItems: 1 =20 clocks: + minItems: 2 items: - description: Core clock - description: Interface clock + - description: Compute clock, RK3576 NPU MMUs only + - description: Convolution buffer core clock, RK3576 NPU MMUs only + - description: Convolution buffer interface clock, RK3576 NPU MMUs o= nly =20 clock-names: + minItems: 2 items: - const: aclk - const: iface + - const: npu + - const: aclk_cbuf + - const: hclk_cbuf =20 "#iommu-cells": const: 0 --=20 2.43.0 From nobody Sat Oct 3 04:23:47 2026 Received: from flow-a7-smtp.messagingengine.com (flow-a7-smtp.messagingengine.com [103.168.172.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3AE93DB309; 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Wed, 5 Aug 2026 02:39:08 -0400 (EDT) From: Jiaxing Hu To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, alchark@flipper.net, chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [RFC PATCH v5 v5 4/8] pmdomain/rockchip: add optional per-domain power-on settle delay Date: Wed, 5 Aug 2026 18:38:22 +1200 Message-ID: <20260805063826.95682-5-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805063826.95682-1-gahing@gahingwoo.com> References: <20260805063826.95682-1-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RK3576 NPU domains need a short settle time after the idle request is released before the QoS registers behind the domain answer. Without it rockchip_pmu_restore_qos() reads back zeroes, and the NPU throws an async SError on the first cold power-on. Give rockchip_domain_info an optional delay_us and wait for it between releasing idle and restoring QoS. Rename DOMAIN_M_O_R_G to DOMAIN_M_O_R_G_W, since the suffixes name the fields the macro sets and this one now also carries a wakeup delay; RK3576 is its only user, so the old spelling is not kept around. Signed-off-by: Jiaxing Hu --- drivers/pmdomain/rockchip/pm-domains.c | 52 +++++++++++++++----------- 1 file changed, 30 insertions(+), 22 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index ba66ae719..e1857f878 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -59,6 +60,7 @@ struct rockchip_domain_info { u32 pwr_offset; u32 mem_offset; u32 req_offset; + u32 delay_us; }; =20 struct rockchip_pmu_info { @@ -185,7 +187,7 @@ struct rockchip_pmu { .need_regulator =3D regulator, \ } =20 -#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r= _status, r_offset, req, idle, ack, g_mask, wakeup) \ +#define DOMAIN_M_O_R_G_W(_name, p_offset, pwr, status, m_offset, m_status,= r_status, r_offset, req, idle, ack, g_mask, delay, wakeup) \ { \ .name =3D _name, \ .pwr_offset =3D p_offset, \ @@ -200,6 +202,7 @@ struct rockchip_pmu { .req_mask =3D (req), \ .idle_mask =3D (idle), \ .clk_ungate_mask =3D (g_mask), \ + .delay_us =3D (delay), \ .ack_mask =3D (ack), \ .active_wakeup =3D wakeup, \ } @@ -258,8 +261,8 @@ struct rockchip_pmu { #define DOMAIN_RK3568(name, pwr, req, wakeup, regulator) \ DOMAIN_M_R(name, pwr, pwr, req, req, req, wakeup, regulator) =20 -#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req= , idle, g_mask, wakeup) \ - DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offs= et, req, idle, idle, g_mask, wakeup) +#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req= , idle, g_mask, delay, wakeup) \ + DOMAIN_M_O_R_G_W(name, p_offset, pwr, status, 0, r_status, r_status, r_of= fset, req, idle, idle, g_mask, delay, wakeup) =20 /* * Dynamic Memory Controller may need to coordinate with us -- see @@ -681,6 +684,10 @@ static int rockchip_pd_power(struct rockchip_pm_domain= *pd, bool power_on) if (ret < 0) goto out; =20 + /* Some domains need to settle before the QoS registers answer. */ + if (pd->info->delay_us) + udelay(pd->info->delay_us); + rockchip_pmu_restore_qos(pd); } =20 @@ -1300,25 +1307,26 @@ static const struct rockchip_domain_info rk3568_pm_= domains[] =3D { }; =20 static const struct rockchip_domain_info rk3576_pm_domains[] =3D { - [RK3576_PD_NPU] =3D DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, = 0x0, 0, 0, 0, false), - [RK3576_PD_NVM] =3D DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6)= , 0x4, BIT(2), BIT(18), BIT(2), false), - [RK3576_PD_SDGMAC] =3D DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(= 7), 0x4, BIT(1), BIT(17), 0x6, false), - [RK3576_PD_AUDIO] =3D DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8= ), 0x4, BIT(0), BIT(16), BIT(0), false), - [RK3576_PD_PHP] =3D DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9)= , 0x0, BIT(15), BIT(15), BIT(15), false), - [RK3576_PD_SUBPHP] =3D DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(= 10), 0x0, 0, 0, 0, false), - [RK3576_PD_VOP] =3D DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11= ), 0x0, 0x6000, 0x6000, 0x6000, false), - [RK3576_PD_VO1] =3D DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14= ), 0x0, BIT(12), BIT(12), 0x7000, false), - [RK3576_PD_VO0] =3D DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15= ), 0x0, BIT(11), BIT(11), 0x6800, false), - [RK3576_PD_USB] =3D DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16= ), 0x0, BIT(10), BIT(10), 0x6400, true), - [RK3576_PD_VI] =3D DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17)= , 0x0, BIT(9), BIT(9), BIT(9), false), - [RK3576_PD_VEPU0] =3D DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(1= 8), 0x0, BIT(7), BIT(7), 0x280, false), - [RK3576_PD_VEPU1] =3D DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(1= 9), 0x0, BIT(8), BIT(8), BIT(8), false), - [RK3576_PD_VDEC] =3D DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20= ), 0x0, BIT(6), BIT(6), BIT(6), false), - [RK3576_PD_VPU] =3D DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21= ), 0x0, BIT(5), BIT(5), BIT(5), false), - [RK3576_PD_NPUTOP] =3D DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(= 22), 0x0, 0x18, 0x18, 0x18, false), - [RK3576_PD_NPU0] =3D DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23= ), 0x0, BIT(1), BIT(1), 0x1a, false), - [RK3576_PD_NPU1] =3D DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24= ), 0x0, BIT(2), BIT(2), 0x1c, false), - [RK3576_PD_GPU] =3D DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25= ), 0x0, BIT(0), BIT(0), BIT(0), false), + /* name p_offset pwr s= tatus r_status r_offset req idle g_mask delay wakeup */ + [RK3576_PD_NPU] =3D DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, = 0x0, 0, 0, 0, 0, false), + [RK3576_PD_NVM] =3D DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6)= , 0x4, BIT(2), BIT(18), BIT(2), 0, false), + [RK3576_PD_SDGMAC] =3D DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(= 7), 0x4, BIT(1), BIT(17), 0x6, 0, false), + [RK3576_PD_AUDIO] =3D DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8= ), 0x4, BIT(0), BIT(16), BIT(0), 0, false), + [RK3576_PD_PHP] =3D DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9)= , 0x0, BIT(15), BIT(15), BIT(15), 0, false), + [RK3576_PD_SUBPHP] =3D DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(= 10), 0x0, 0, 0, 0, 0, false), + [RK3576_PD_VOP] =3D DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11= ), 0x0, 0x6000, 0x6000, 0x6000, 0, false), + [RK3576_PD_VO1] =3D DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14= ), 0x0, BIT(12), BIT(12), 0x7000, 0, false), + [RK3576_PD_VO0] =3D DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15= ), 0x0, BIT(11), BIT(11), 0x6800, 0, false), + [RK3576_PD_USB] =3D DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16= ), 0x0, BIT(10), BIT(10), 0x6400, 0, true), + [RK3576_PD_VI] =3D DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17)= , 0x0, BIT(9), BIT(9), BIT(9), 0, false), + [RK3576_PD_VEPU0] =3D DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(1= 8), 0x0, BIT(7), BIT(7), 0x280, 0, false), + [RK3576_PD_VEPU1] =3D DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(1= 9), 0x0, BIT(8), BIT(8), BIT(8), 0, false), + [RK3576_PD_VDEC] =3D DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20= ), 0x0, BIT(6), BIT(6), BIT(6), 0, false), + [RK3576_PD_VPU] =3D DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21= ), 0x0, BIT(5), BIT(5), BIT(5), 0, false), + [RK3576_PD_NPUTOP] =3D DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(= 22), 0x0, 0x18, 0x18, 0x18, 15, false), + [RK3576_PD_NPU0] =3D DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23= ), 0x0, BIT(1), BIT(1), 0x1a, 15, false), + [RK3576_PD_NPU1] =3D DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24= ), 0x0, BIT(2), BIT(2), 0x1c, 15, false), + [RK3576_PD_GPU] =3D DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25= ), 0x0, BIT(0), BIT(0), BIT(0), 0, false), }; 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Wed, 5 Aug 2026 02:39:18 -0400 (EDT) From: Jiaxing Hu To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, alchark@flipper.net, chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [RFC PATCH v5 v5 5/8] pmdomain/rockchip: cycle optional power-domain resets on power-on Date: Wed, 5 Aug 2026 18:38:23 +1200 Message-ID: <20260805063826.95682-6-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805063826.95682-1-gahing@gahingwoo.com> References: <20260805063826.95682-1-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Rockchip domains come out of power-on with their bus interface in an undefined state. On the RK3576 NPU this shows up as a hang on the first access after a cold power-on; the vendor kernel cycles the domain's resets at this point and that clears it. Take the domain node's resets if it has any, and pulse them between releasing idle and restoring QoS. The resets are optional, so domains that do not declare any behave exactly as before. Signed-off-by: Jiaxing Hu --- drivers/pmdomain/rockchip/pm-domains.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index e1857f878..82051f600 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -103,6 +104,7 @@ struct rockchip_pm_domain { struct clk_bulk_data *clks; struct device_node *node; struct regulator *supply; + struct reset_control *resets; }; =20 struct rockchip_pmu { @@ -688,6 +690,13 @@ static int rockchip_pd_power(struct rockchip_pm_domain= *pd, bool power_on) if (pd->info->delay_us) udelay(pd->info->delay_us); =20 + /* Optional: some domains need their resets cycled after power-on. */ + if (pd->resets) { + reset_control_assert(pd->resets); + udelay(10); + reset_control_deassert(pd->resets); + } + rockchip_pmu_restore_qos(pd); } =20 @@ -857,6 +866,14 @@ static int rockchip_pm_add_one_domain(struct rockchip_= pmu *pmu, if (error) goto err_put_clocks; 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Wed, 5 Aug 2026 02:39:26 -0400 (EDT) From: Jiaxing Hu To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, alchark@flipper.net, chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [RFC PATCH v5 v5 6/8] accel/rocket: add RK3576 NPU (RKNN) support Date: Wed, 5 Aug 2026 18:38:24 +1200 Message-ID: <20260805063826.95682-7-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805063826.95682-1-gahing@gahingwoo.com> References: <20260805063826.95682-1-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RK3576 carries the same RKNN block as the RK3588, with two cores instead of three and a few platform differences: - the CBUF (convolution buffer) has its own clock domain, so the core needs six clocks rather than four; - the BIU reset moved into the power domain, leaving one reset here; - the NPU spans two power domains, and a device with more than one is skipped by the driver-core single-domain auto-attach, so the list has to be attached explicitly; - the DPU completion interrupt is armed exactly as on RK3588 but never reaches the GIC. The completion is visible in INTERRUPT_RAW_STATUS, so sample that from an hrtimer rather than wait for an interrupt that does not come. The interrupt stays armed, so if it ever does arrive the normal handler finalises the job first. Select all of that from of_device_id match data so the RK3588 path keeps its existing counts and behaviour unchanged. Signed-off-by: Jiaxing Hu Tested-by: Igor Paunovic # RK3588, Orange Pi 5 Plus --- drivers/accel/rocket/rocket_core.c | 26 +++++- drivers/accel/rocket/rocket_core.h | 20 ++++- drivers/accel/rocket/rocket_device.c | 4 + drivers/accel/rocket/rocket_drv.c | 22 ++++- drivers/accel/rocket/rocket_job.c | 121 ++++++++++++++++++++++++--- 5 files changed, 176 insertions(+), 17 deletions(-) diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rock= et_core.c index b3b2fa9ba..e08288c8c 100644 --- a/drivers/accel/rocket/rocket_core.c +++ b/drivers/accel/rocket/rocket_core.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include =20 @@ -21,14 +22,22 @@ int rocket_core_init(struct rocket_core *core) u32 version; int err =3D 0; =20 + /* RK3576 moves the BIU reset into its power domain and takes only srst_a= . */ core->resets[0].id =3D "srst_a"; core->resets[1].id =3D "srst_h"; - err =3D devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core= ->resets), + err =3D devm_reset_control_bulk_get_exclusive(&pdev->dev, core->soc->num_= resets, core->resets); if (err) return dev_err_probe(dev, err, "failed to get resets for core %d\n", cor= e->index); =20 - err =3D devm_clk_bulk_get(dev, ARRAY_SIZE(core->clks), core->clks); + core->clks[0].id =3D "aclk"; + core->clks[1].id =3D "hclk"; + core->clks[2].id =3D "npu"; + core->clks[3].id =3D "pclk"; + /* RK3576 clocks the CBUF separately; the compute path stalls without the= se. */ + core->clks[4].id =3D "aclk_cbuf"; + core->clks[5].id =3D "hclk_cbuf"; + err =3D devm_clk_bulk_get(dev, core->soc->num_clks, core->clks); if (err) return dev_err_probe(dev, err, "failed to get clocks for core %d\n", cor= e->index); =20 @@ -65,6 +74,19 @@ int rocket_core_init(struct rocket_core *core) return err; } =20 + /* + * RK3576 spans two power domains, and a multi-domain device is skipped + * by the driver-core single-domain auto-attach, so attach the list here. + */ + if (core->soc->multi_power_domain) { + struct dev_pm_domain_list *pd_list; + + err =3D devm_pm_domain_attach_list(dev, NULL, &pd_list); + if (err < 0) + return dev_err_probe(dev, err, + "failed to attach NPU power domains\n"); + } + pm_runtime_use_autosuspend(dev); =20 /* diff --git a/drivers/accel/rocket/rocket_core.h b/drivers/accel/rocket/rock= et_core.h index f6d738285..205ff070d 100644 --- a/drivers/accel/rocket/rocket_core.h +++ b/drivers/accel/rocket/rocket_core.h @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -27,16 +28,25 @@ #define rocket_core_writel(core, reg, value) \ writel(value, (core)->core_iomem + (REG_CORE_##reg) - REG_CORE_S_STATUS) =20 +/* Per-SoC differences, selected by the of_device_id match data. */ +struct rocket_soc_data { + unsigned int num_clks; /* clk_bulk count: 4 base, 6 with CBUF */ + unsigned int num_resets; /* reset_bulk count: 2 base, 1 on RK3576 */ + bool multi_power_domain; /* device spans more than one PM domain */ + bool poll_completion; /* completion IRQ never reaches the GIC */ +}; + struct rocket_core { struct device *dev; struct rocket_device *rdev; + const struct rocket_soc_data *soc; unsigned int index; =20 int irq; void __iomem *pc_iomem; void __iomem *cna_iomem; void __iomem *core_iomem; - struct clk_bulk_data clks[4]; + struct clk_bulk_data clks[6]; struct reset_control_bulk_data resets[2]; =20 struct iommu_group *iommu_group; @@ -52,6 +62,14 @@ struct rocket_core { atomic_t pending; } reset; =20 + struct hrtimer poll_timer; + struct work_struct poll_work; + atomic_t poll_active; + unsigned int poll_ticks; + unsigned int poll_seq; + unsigned int poll_work_seq; + bool poll_dying; + struct drm_gpu_scheduler sched; u64 fence_context; u64 emit_seqno; diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/ro= cket_device.c index 46e6ee1e7..bfb00f967 100644 --- a/drivers/accel/rocket/rocket_device.c +++ b/drivers/accel/rocket/rocket_device.c @@ -31,6 +31,10 @@ struct rocket_device *rocket_device_init(struct platform= _device *pdev, if (of_device_is_available(core_node)) num_cores++; =20 + for_each_compatible_node(core_node, NULL, "rockchip,rk3576-rknn-core") + if (of_device_is_available(core_node)) + num_cores++; + rdev->cores =3D devm_kcalloc(dev, num_cores, sizeof(*rdev->cores), GFP_KE= RNEL); if (!rdev->cores) return ERR_PTR(-ENOMEM); diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocke= t_drv.c index 8bbbce594..7f7dfa374 100644 --- a/drivers/accel/rocket/rocket_drv.c +++ b/drivers/accel/rocket/rocket_drv.c @@ -176,6 +176,7 @@ static int rocket_probe(struct platform_device *pdev) =20 rdev->cores[core].rdev =3D rdev; rdev->cores[core].dev =3D &pdev->dev; + rdev->cores[core].soc =3D of_device_get_match_data(&pdev->dev); rdev->cores[core].index =3D core; =20 rdev->num_cores++; @@ -213,8 +214,23 @@ static void rocket_remove(struct platform_device *pdev) } } =20 +static const struct rocket_soc_data rk3588_soc_data =3D { + .num_clks =3D 4, + .num_resets =3D 2, + .multi_power_domain =3D false, + .poll_completion =3D false, +}; + +static const struct rocket_soc_data rk3576_soc_data =3D { + .num_clks =3D 6, + .num_resets =3D 1, + .multi_power_domain =3D true, + .poll_completion =3D true, +}; + static const struct of_device_id dt_match[] =3D { - { .compatible =3D "rockchip,rk3588-rknn-core" }, + { .compatible =3D "rockchip,rk3588-rknn-core", .data =3D &rk3588_soc_data= }, + { .compatible =3D "rockchip,rk3576-rknn-core", .data =3D &rk3576_soc_data= }, {} }; MODULE_DEVICE_TABLE(of, dt_match); @@ -240,7 +256,7 @@ static int rocket_device_runtime_resume(struct device *= dev) if (core < 0) return -ENODEV; =20 - err =3D clk_bulk_prepare_enable(ARRAY_SIZE(rdev->cores[core].clks), rdev-= >cores[core].clks); + err =3D clk_bulk_prepare_enable(rdev->cores[core].soc->num_clks, rdev->co= res[core].clks); if (err) { dev_err(dev, "failed to enable (%d) clocks for core %d\n", err, core); return err; @@ -260,7 +276,7 @@ static int rocket_device_runtime_suspend(struct device = *dev) if (!rocket_job_is_idle(&rdev->cores[core])) return -EBUSY; =20 - clk_bulk_disable_unprepare(ARRAY_SIZE(rdev->cores[core].clks), rdev->core= s[core].clks); + clk_bulk_disable_unprepare(rdev->cores[core].soc->num_clks, rdev->cores[c= ore].clks); =20 return 0; } diff --git a/drivers/accel/rocket/rocket_job.c b/drivers/accel/rocket/rocke= t_job.c index bb77b6bf0..28845ac4e 100644 --- a/drivers/accel/rocket/rocket_job.c +++ b/drivers/accel/rocket/rocket_job.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -21,6 +22,15 @@ =20 #define JOB_TIMEOUT_MS 500 =20 +/* + * RK3576 arms the same DPU completion as RK3588, but the interrupt never + * reaches the GIC. The completion itself is visible in INTERRUPT_RAW_STAT= US, + * so sample that instead. The tick cap bounds jobs that never raise it at= all, + * which is the same open problem as the wrong inference results. + */ +#define RK3576_POLL_INTERVAL_NS 1000000LL /* 1 ms */ +#define RK3576_POLL_MAX_TICKS 8 + static struct rocket_job * to_rocket_job(struct drm_sched_job *sched_job) { @@ -151,6 +161,14 @@ static void rocket_job_hw_submit(struct rocket_core *c= ore, struct rocket_job *jo =20 rocket_pc_writel(core, OPERATION_ENABLE, PC_OPERATION_ENABLE_OP_EN(1)); =20 + if (core->soc->poll_completion) { + core->poll_ticks =3D 0; + core->poll_seq++; + atomic_set(&core->poll_active, 1); + hrtimer_start(&core->poll_timer, ns_to_ktime(RK3576_POLL_INTERVAL_NS), + HRTIMER_MODE_REL); + } + dev_dbg(core->dev, "Submitted regcmd at 0x%llx to core %d", task->regcmd,= core->index); } =20 @@ -341,25 +359,87 @@ static struct dma_fence *rocket_job_run(struct drm_sc= hed_job *sched_job) return ERR_PTR(ret); } =20 +static void rocket_job_handle_irq(struct rocket_core *core); + +static enum hrtimer_restart rocket_poll_timer_fn(struct hrtimer *timer) +{ + struct rocket_core *core =3D container_of(timer, struct rocket_core, poll= _timer); + u32 raw; + + if (!atomic_read(&core->poll_active)) + return HRTIMER_NORESTART; + + core->poll_work_seq =3D core->poll_seq; + + raw =3D rocket_pc_readl(core, INTERRUPT_RAW_STATUS); + if ((raw & (PC_INTERRUPT_RAW_STATUS_DPU_0 | PC_INTERRUPT_RAW_STATUS_DPU_1= )) || + ++core->poll_ticks >=3D RK3576_POLL_MAX_TICKS) { + atomic_set(&core->poll_active, 0); + schedule_work(&core->poll_work); + return HRTIMER_NORESTART; + } + + hrtimer_forward_now(timer, ns_to_ktime(RK3576_POLL_INTERVAL_NS)); + return HRTIMER_RESTART; +} + +/* Start the job's next task, or retire it. Caller holds job_lock. */ +static void rocket_job_next_locked(struct rocket_core *core) +{ + lockdep_assert_held(&core->job_lock); + + if (!core->in_flight_job) + return; + + if (core->in_flight_job->next_task_idx < core->in_flight_job->task_count)= { + rocket_job_hw_submit(core, core->in_flight_job); + return; + } + + iommu_detach_group(NULL, iommu_group_get(core->dev)); + dma_fence_signal(core->in_flight_job->done_fence); + pm_runtime_put_autosuspend(core->dev); + core->in_flight_job =3D NULL; +} + +static void rocket_poll_work_fn(struct work_struct *work) +{ + struct rocket_core *core =3D container_of(work, struct rocket_core, poll_= work); + + pm_runtime_mark_last_busy(core->dev); + + scoped_guard(mutex, &core->job_lock) { + /* + * The interrupt can land while this work is queued, retire the job + * and start the next task. poll_seq only moves under job_lock, in + * hw_submit, so comparing it here says whether that happened. Doing + * it outside the lock would leave the window open rather than close + * it, and this work would then submit a task on top of a live one. + */ + if (READ_ONCE(core->poll_dying) || core->poll_work_seq !=3D core->poll_s= eq) + return; + + rocket_pc_writel(core, OPERATION_ENABLE, 0x0); + rocket_pc_writel(core, INTERRUPT_CLEAR, 0x1ffff); + + rocket_job_next_locked(core); + } +} + static void rocket_job_handle_irq(struct rocket_core *core) { + if (core->soc->poll_completion) { + atomic_set(&core->poll_active, 0); + hrtimer_cancel(&core->poll_timer); + } + pm_runtime_mark_last_busy(core->dev); =20 rocket_pc_writel(core, OPERATION_ENABLE, 0x0); rocket_pc_writel(core, INTERRUPT_CLEAR, 0x1ffff); =20 scoped_guard(mutex, &core->job_lock) - if (core->in_flight_job) { - if (core->in_flight_job->next_task_idx < core->in_flight_job->task_coun= t) { - rocket_job_hw_submit(core, core->in_flight_job); - return; - } - - iommu_detach_group(NULL, iommu_group_get(core->dev)); - dma_fence_signal(core->in_flight_job->done_fence); - pm_runtime_put_autosuspend(core->dev); - core->in_flight_job =3D NULL; - } + rocket_job_next_locked(core); } =20 static void @@ -460,6 +540,10 @@ int rocket_job_init(struct rocket_core *core) int ret; =20 INIT_WORK(&core->reset.work, rocket_reset_work); + INIT_WORK(&core->poll_work, rocket_poll_work_fn); + hrtimer_setup(&core->poll_timer, rocket_poll_timer_fn, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + atomic_set(&core->poll_active, 0); spin_lock_init(&core->fence_lock); mutex_init(&core->job_lock); =20 @@ -501,8 +585,23 @@ int rocket_job_init(struct rocket_core *core) =20 void rocket_job_fini(struct rocket_core *core) { + /* + * Stop the poll from starting hardware work before tearing anything + * down: it submits the next task, and drm_sched_fini() does not wait + * for work already queued. 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Wed, 5 Aug 2026 02:39:34 -0400 (EDT) From: Jiaxing Hu To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, alchark@flipper.net, chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [RFC PATCH v5 v5 7/8] arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes Date: Wed, 5 Aug 2026 18:38:25 +1200 Message-ID: <20260805063826.95682-8-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805063826.95682-1-gahing@gahingwoo.com> References: <20260805063826.95682-1-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the two RKNN cores and their IOMMUs, plus the NPU power-domain resets the pmdomain driver now cycles on power-on. Both cores are disabled by default; boards enable what they wire up. Each core lists both NPU power domains, its own first. The compute path needs NPU1 powered even when only core 0 runs, and a node with a single domain would be auto-attached by the driver core before the driver can attach the list itself. The IOMMUs keep one domain each, since they rely on that same auto-attach. Signed-off-by: Jiaxing Hu --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 80 +++++++++++++++++++++++- 1 file changed, 78 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index b0c0d3c8b..1e6dd039f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1070,14 +1070,22 @@ power-domain@RK3576_PD_NPUTOP { power-domain@RK3576_PD_NPU0 { reg =3D ; clocks =3D <&cru HCLK_RKNN_ROOT>, - <&cru ACLK_RKNN0>; + <&cru ACLK_RKNN0>, + <&cru CLK_RKNN_DSU0>, + <&cru ACLK_RKNN_CBUF>, + <&cru HCLK_RKNN_CBUF>; + resets =3D <&cru SRST_A_RKNN0_BIU>; pm_qos =3D <&qos_npu_m0>; #power-domain-cells =3D <0>; }; power-domain@RK3576_PD_NPU1 { reg =3D ; clocks =3D <&cru HCLK_RKNN_ROOT>, - <&cru ACLK_RKNN1>; + <&cru ACLK_RKNN1>, + <&cru CLK_RKNN_DSU0>, + <&cru ACLK_RKNN_CBUF>, + <&cru HCLK_RKNN_CBUF>; + resets =3D <&cru SRST_A_RKNN1_BIU>; pm_qos =3D <&qos_npu_m1>; #power-domain-cells =3D <0>; }; @@ -1832,6 +1840,74 @@ qos_npu_m1ro: qos@27f22100 { reg =3D <0x0 0x27f22100 0x0 0x20>; }; =20 + rknn_core_0: npu@27700000 { + compatible =3D "rockchip,rk3576-rknn-core"; + reg =3D <0x0 0x27700000 0x0 0x1000>, + <0x0 0x27701000 0x0 0x1000>, + <0x0 0x27703000 0x0 0x1000>; + reg-names =3D "pc", "cna", "core"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKNN0>, <&cru HCLK_RKNN_ROOT>, + <&cru CLK_RKNN_DSU0>, <&cru PCLK_NPUTOP_ROOT>, + <&cru ACLK_RKNN_CBUF>, <&cru HCLK_RKNN_CBUF>; + clock-names =3D "aclk", "hclk", "npu", "pclk", + "aclk_cbuf", "hclk_cbuf"; + resets =3D <&cru SRST_A_RKNN0>; + reset-names =3D "srst_a"; + power-domains =3D <&power RK3576_PD_NPU0>, <&power RK3576_PD_NPU1>; + iommus =3D <&rknn_mmu_0>; + status =3D "disabled"; + }; + + rknn_mmu_0: iommu@27702000 { + compatible =3D "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0x27702000 0x0 0x100>, + <0x0 0x27702100 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru ACLK_RKNN0>, <&cru HCLK_RKNN_ROOT>, + <&cru CLK_RKNN_DSU0>, <&cru ACLK_RKNN_CBUF>, + <&cru HCLK_RKNN_CBUF>; + clock-names =3D "aclk", "iface", "npu", + "aclk_cbuf", "hclk_cbuf"; + #iommu-cells =3D <0>; + power-domains =3D <&power RK3576_PD_NPU0>; + status =3D "disabled"; + }; + + rknn_core_1: npu@27708000 { + compatible =3D "rockchip,rk3576-rknn-core"; + reg =3D <0x0 0x27708000 0x0 0x1000>, + <0x0 0x27709000 0x0 0x1000>, + <0x0 0x2770b000 0x0 0x1000>; + reg-names =3D "pc", "cna", "core"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKNN1>, <&cru HCLK_RKNN_ROOT>, + <&cru CLK_RKNN_DSU0>, <&cru PCLK_NPUTOP_ROOT>, + <&cru ACLK_RKNN_CBUF>, <&cru HCLK_RKNN_CBUF>; + clock-names =3D "aclk", "hclk", "npu", "pclk", + "aclk_cbuf", "hclk_cbuf"; + resets =3D <&cru SRST_A_RKNN1>; + reset-names =3D "srst_a"; + power-domains =3D <&power RK3576_PD_NPU1>, <&power RK3576_PD_NPU0>; + iommus =3D <&rknn_mmu_1>; + status =3D "disabled"; + }; + + rknn_mmu_1: iommu@2770a000 { + compatible =3D "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0x2770a000 0x0 0x100>, + <0x0 0x2770a100 0x0 0x100>; + interrupts =3D ; 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Wed, 5 Aug 2026 02:39:43 -0400 (EDT) From: Jiaxing Hu To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, alchark@flipper.net, chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [RFC PATCH v5 v5 8/8] arm64: dts: rockchip: rk3576-rock-4d: enable NPU Date: Wed, 5 Aug 2026 18:38:26 +1200 Message-ID: <20260805063826.95682-9-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805063826.95682-1-gahing@gahingwoo.com> References: <20260805063826.95682-1-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable rknn_core_0 and its IOMMU on the Radxa ROCK 4D and supply the core from vdd_npu_s0. The supply is marked always-on because the NPU power domains are what gate the block here, and dropping the rail underneath them takes an async SError on the next power-on rather than a clean retry. Only rknn_core_0 is enabled: the driver binds one core per node and the second core is left to whoever can test it. Signed-off-by: Jiaxing Hu --- arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/b= oot/dts/rockchip/rk3576-rock-4d.dts index 272af1012..965e0906b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -442,6 +442,7 @@ regulator-state-mem { }; =20 vdd_npu_s0: dcdc-reg2 { + regulator-always-on; regulator-boot-on; regulator-enable-ramp-delay =3D <400>; regulator-min-microvolt =3D <550000>; @@ -869,3 +870,12 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint =3D <&hdmi_in_vp0>; }; }; + +&rknn_core_0 { + npu-supply =3D <&vdd_npu_s0>; + status =3D "okay"; +}; + +&rknn_mmu_0 { + status =3D "okay"; +}; --=20 2.43.0