From nobody Fri Oct 2 05:30:26 2026 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F7203932C6 for ; Wed, 5 Aug 2026 05:35:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785908131; cv=none; b=MSIJ5GZneHsDogYI234wTfCdSlFdp4Rmq/hB9FwZ3ajBJ/grURHvyOjWGzGSH7oMFP9OQZM4F2pF6D8ETrrQ9Sxr7FjduGldunaPyPKaKKS6xQJKNGwuVCcLzLshbtyjYj1JLTyoDMhsvEq50nPyOitiG46XN3QIN+ZhaWWEZms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785908131; c=relaxed/simple; bh=j33YZ6CfweNN6iiskAYLb8a1L781jvQcgyuM6dGuVh0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jjfe5f/A0+Sum2nof9WKfOz27VXOcFypdoK55Wxs8gysJULPrxWCXrrvsTXc2QvcOGtpDwl3oJjuPV10+gZkRQb+BwJT2uu6aIzkXmQCH7+ufpbD9VpXdPQDL30jDyFYgDqD/3gmpqr/0J8/w2HjAzI6Z2IZOeTPyO9zvXhVQm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NNfvtXeA; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NNfvtXeA" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-2ceb096e675so7941355ad.0 for ; Tue, 04 Aug 2026 22:35:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785908130; x=1786512930; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=SNE+4b0/cY6qO/wMLz1H6Q1CQk2R0SO7Rau9LTG2NX4=; b=NNfvtXeABZlbWjhLmRR28slZesuXNf1sRyoUTGpt65NQodyNo2Vk7GI+b0ZUPaML0a leQiCAeY8ryvIgFn5HJ5HNp7oK8RjTg10xqBCbZg6arQ16wgIch8Uj0zgpN+gIyQc6DW 4UAhzfzHUVroZKtSPvCFeNzsUGMZ8YxktnNUER5AudEQfkCVEKeNGAvmVfCO3zE611qF TgfSegrWv9xUv9gwGE9HcIK5FpQxa6owR5n7i5CR0SzQaQnjP85u1T+5wWJr+/7fPU0p KUXgvIDEc/MDuLYcp0DdwW56Res0EnPbbuhxl56tV2HtDSwaNtlWfdhKnxKld20Ouqt/ KdOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785908130; x=1786512930; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=SNE+4b0/cY6qO/wMLz1H6Q1CQk2R0SO7Rau9LTG2NX4=; b=jIYoTWlYLrWCilyVm8nQF8XGF48zIijTxNrlSNALA/WIOcx2vXCBYrS1zEtRnebC31 xRcWNsUA+9m4Aun06/nlWS1zSdh3xm/GnM+8r4tV0hgsE5RDnu7ozDxy4ZZBxDbK7AUA byVGn9WnFFFvQLdk+F/tX++ToT+IB+L9xiw94WeGDnz1Pges8ytdhcketgBu96uLzjGl IDWCZxh94g22zLk4Md3/4jd2hjQEIQwzyfotAf8Kb59xzNZCZ8h5QjQfwf3lJhYiBQI6 GWYF0c0dcHcR14wlc2EtmqFICDEJ0HbTjSXssh7TgpgUjJ5k/RJf+jP8AuUXXJyYvu0w S8bQ== X-Forwarded-Encrypted: i=1; AHgh+RomiYGnLa3/xFpQxL/GsigcBlKRgW4rL8uhmz+H6N0UV7UmrGy3kvh4KKDRJBPgTx/3DdfbLPX8hya9v24=@vger.kernel.org X-Gm-Message-State: AOJu0Yxse4zhsb0eIfsmJGLS6nzgE3kdVJrlR5jzZz8LpCS74ntF6VZt s4grRtoX7WOWMbju5IS7mxv5VvxZg0Dr/XkeisIrhyGkv8WrzwR2oukk X-Gm-Gg: AR+sD11ZyNGg8U9CZaZp79lqeIB4gsaBtLooEJrd824S5tQBrT/wDzQUJgM/hKNoSUT IM1W4KBN22FdK37Ut53pU6hlx0xVW1grO2z5M1D0y+Cd6Ryjqq6X/A4jvuVf1cRGRgg+/pdFbws BOfCGP5jYSfU59Ayv/eGM7aRbvxL8gYn/i5+mAxxwlVLhkHPGNEdgDTnurUaOmwArl25A2PTcib GApFEOPrhC0BTj3MJgxMPI6s5E8Mf5KPvd4veKWxL5ASQJBGnMocleMPnp+BCYRwlA6ZxiTQ51M gJggLrG0akBIvB6jenKs6xn/mw2W2iPTP75KIHEeqLVOUl5mKM+1iCg3wVZg/rhg4e3s+dRx+20 8T/Ps2XGHlJpqK+vdLV1TALmh2s/JBsXhZl0whpbV0SHTyFawaARUfYMgnwbnTrjeQHLT3pIoFy m14aVsmNi/h/lBXRBLAqt1W2tpBDzhvBf5z5EafPGBh/KN/zDOwWERvXA4/L2w11RijoaFhhz6a GG5J3vUsC4JKrRH1928pA3zrIxx X-Received: by 2002:a17:903:245:b0:2c6:90ec:f601 with SMTP id d9443c01a7336-2d0ca7aea8cmr41389385ad.8.1785908129743; Tue, 04 Aug 2026 22:35:29 -0700 (PDT) Received: from [127.0.1.1] (61-220-246-151.hinet-ip.hinet.net. [61.220.246.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d0aa4c0b1fsm14307245ad.64.2026.08.04.22.35.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Aug 2026 22:35:29 -0700 (PDT) From: Kyle Hsieh Date: Wed, 05 Aug 2026 13:38:20 +0800 Subject: [PATCH v3 1/2] dt-bindings: iio: adc: ti,ads112c04: Add binding for ADS112C04 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-ti-ads112c04-driver-v3-1-49f436829e01@gmail.com> References: <20260805-ti-ads112c04-driver-v3-0-49f436829e01@gmail.com> In-Reply-To: <20260805-ti-ads112c04-driver-v3-0-49f436829e01@gmail.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kyle Hsieh X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4388; i=kylehsieh1995@gmail.com; h=from:subject:message-id; bh=j33YZ6CfweNN6iiskAYLb8a1L781jvQcgyuM6dGuVh0=; b=owEBbQGS/pANAwAKAaWDQrcJVsSBAcsmYgBqcsxNtFIVsPYwl01+sisYtA9hsX6zcsHULxjdP tAVoxJTnw2JATMEAAEKAB0WIQTJHsaNZOdY+THGqJelg0K3CVbEgQUCanLMTQAKCRClg0K3CVbE gTSgB/9zrSTVPQrZRhQcdxl3WpBFrlJatlJYeeHWVcq3u49ZhHJayV3cfuK0y//zvq8b6RdXIy1 ZHtIp/4HklBEk+PzOB5JjfNpJ/EvKEqjyOVL0ykmB4M8UhxXYeIifSMl7V5e7Bt0MNbMK4vghS0 QVKXGW7ckeki+9Eu9HubbLiqj4RubSOGsFDjoymW7h4JWSssbiekVIKjLWn27NDaT0OtxNCmqg3 i6OeblihpoTT17YrEKakFiwNKD2liM7Z473S5HT6FRi6Nvmwet6xt3kDWJkWnuWNF4iABzmU0Ic Naq0SpVeNmw9BpbaWWsIp3sS/9yuXZWmp2AITYAPj+gFBAnt X-Developer-Key: i=kylehsieh1995@gmail.com; a=openpgp; fpr=C91EC68D64E758F931C6A897A58342B70956C481 Add device tree binding documentation for Texas Instruments ADS112C04 I2C Analog-to-Digital Converters. These devices provide 4-channel, 16-bit delta-sigma ADCs with an I2C interface, programmable gain amplifier (PGA), and data-ready (DRDY) interrupt output. The binding uses child nodes to dynamically define the connected single-ended or differential channels. Signed-off-by: Kyle Hsieh --- .../devicetree/bindings/iio/adc/ti,ads112c04.yaml | 146 +++++++++++++++++= ++++ 1 file changed, 146 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads112c04.yaml b/= Documentation/devicetree/bindings/iio/adc/ti,ads112c04.yaml new file mode 100644 index 000000000000..ff079bb5b3dd --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads112c04.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,ads112c04.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments ADS112C04 ADC + +maintainers: + - Kyle Hsieh + +description: + The ADS112C04 (16-bit) are precision analog-to-digital converters (ADCs) + with an I2C interface. They feature a flexible input multiplexer, a + low-noise programmable gain amplifier (PGA), two programmable excitation + current sources, a voltage reference, and a precision temperature sensor. + +properties: + compatible: + enum: + - ti,ads112c04 + + reg: + maxItems: 1 + description: I2C address of the device. + + interrupts: + maxItems: 1 + description: Data ready (DRDY) interrupt output. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reset-gpios: + maxItems: 1 + description: GPIO connected to the RESET pin. Active low. + + avdd-supply: true + dvdd-supply: true + + refp-supply: true + refn-supply: true + + ti,refp-refn-resistor-ohms: + description: Resistance of the external resistor between REFP and REFN. + +patternProperties: + "^channel@[0-9a-b]$": + $ref: adc.yaml + unevaluatedProperties: false + properties: + reg: + items: + - maximum: 11 + + single-channel: + maximum: 3 + + diff-channels: + items: + maximum: 3 + + excitation-channels: + maxItems: 2 + items: + maximum: 3 + + excitation-current-nanoamp: + maxItems: 2 + items: + enum: [10000, 50000, 100000, 250000, 500000, 1000000, 1500000] + + burn-out-current-nanoamp: + items: + - enum: [10000] + + reference-sources: + items: + - enum: [internal-2.048v, external, avdd] + default: internal-2.048v + + dependencies: + excitation-channels: [ excitation-current-nanoamp ] + excitation-current-nanoamp: [ excitation-channels ] + + oneOf: + - required: [ single-channel ] + - required: [ diff-channels ] + +required: + - compatible + - reg + - avdd-supply + - dvdd-supply + +dependencies: + refn-supply: [ refp-supply ] + +oneOf: + - required: + - refp-supply + - required: + - ti,refp-refn-resistor-ohms + - properties: + refp-supply: false + refn-supply: false + ti,refp-refn-resistor-ohms: false + +unevaluatedProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@40 { + compatible =3D "ti,ads112c04"; + reg =3D <0x40>; + interrupt-parent =3D <&gpio>; + interrupts =3D <12 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios =3D <&gpio 13 GPIO_ACTIVE_LOW>; + avdd-supply =3D <&vdd_3v3_reg>; + dvdd-supply =3D <&vdd_3v3_reg>; + refp-supply =3D <&vref_reg>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + diff-channels =3D <0>, <1>; + }; + + channel@1 { + reg =3D <1>; + single-channel =3D <2>; + }; + }; + }; --=20 2.34.1 From nobody Fri Oct 2 05:30:26 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BD833AE1BD for ; Wed, 5 Aug 2026 05:35:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785908136; cv=none; b=TKQQTMH5vmYcO/5cKn3vgmGx02EPduPE3veEgH5L5/ioG/kOjXh05HLSrNM5HSCSrGwMD5Ze7xcWEu286ApH0T41FKn+BpWFhhVV+q0dhwYnRAHyCu5TlctJPnN44G0Po7MLU0+kIjT+mEeaoG0U4anBk4OJxzf8lf78E/s7sMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785908136; c=relaxed/simple; bh=mh9Vc4GD7cjIRTzPZeqOurJ6XGAGOWFO88DhFXJJq1M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XcVSnQ9wNW0ZKXJ5e5w1k0V/ZcPFqhxVL+gj36UYA/rzvUJf4opY/om71u9mBmpQZClTniImhMrDmyoZRfd0ixiH9S8FGkcckQlycNbstR5f2sb/lVCqVQeAeX2p9sxKSI3gfzt+KPESKldil1dQS/Uc6byFdcCdfchOjg0SrzQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hJIvmDQf; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hJIvmDQf" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-2caea3f742bso9261355ad.0 for ; Tue, 04 Aug 2026 22:35:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785908133; x=1786512933; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Zu/v7gJ1LYt5IfuF9GnMxPtWyVEdaTkgDZLaiUaUYMI=; b=hJIvmDQfYjtjNGjMnKVHgUpb/lUbqlAndnUPF2ODBuY3JBF2HsSxozx+uiHF6FWQKZ gFylNAAIpUmEwK70o6SYX+zYN6lulLMxoG+xmLolgUtLfUDtrBZvQgtT49kBjYbqhkbt GLUhHuGLW1FZNib0S2CkDoce5Psx5VFdLrsIu+mWru3hBb0e5bWwUiONIhQcqTomierN +ISPxPj+enkuiCt0BlrIb+6JXdr9/SmaFwbElDl6r/e5UXfyyTlBy6+Ox+obV6dO7o7n fwh+jamIeZDzxoyPqMsq8iGt2kJ/+CjfDcG6y/RypmSS1rO9ls5s0UshRj9E6FSqvk9g T3Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785908133; x=1786512933; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=Zu/v7gJ1LYt5IfuF9GnMxPtWyVEdaTkgDZLaiUaUYMI=; b=jb8rQOJGgrQe6lWGfLcz1vb/8oggxbSQbn6HnIa12d7dhzSF8M9tu0wiI+o0CiIxkO NJJ5UXKCQrKpt3iTNMtCzpQ96/Z+cKA37ZOfF+kqBoImJlggQNM/oIVo5lo3gHnrOSr0 wsvUfZ9kPWfcoVl5jKLGb+0nBG42Jbh34ZLehPuPVZpbp1Oz5SshfMbH8P4FvZlUmfsw ejIYqLGhumlxyd5jJLi8dBtpW2ckvJgFkNqZ0PMg7ChF+7ajqhsCmPkZlmwxImvFfiMx gDAgkBze909/hZUhrGHe70oEhDJ5BOZkLYeiDWxsOjRgHzDMdN0XEyyHuQAbckDNm7hD UzkQ== X-Forwarded-Encrypted: i=1; AHgh+RpCM/GvCtfycOuAhdKeB3uv55kuIjz/ku1qAi9CXJb2aR0/7LGnDyXQ9EMEMjykMquU4uJ2PLw7kvMOLlU=@vger.kernel.org X-Gm-Message-State: AOJu0YyEBcK/eBpYrp6ET0UO2/xnQyyGmBqMv7AVdX9Qf/n7si5HSAxj S0PyxbBB2SfVuiJYLp7Tk4PlsWWcuwPfctXD64CxyujJELZqw3mKvFRg X-Gm-Gg: AR+sD11watzzPwIn4iHCMSq5Zab3JMgGTwzYFcbk91gepj/eS6Kbs2mjHDLzHW2V2Is 0aviZzxS3uNQF2wiRry8q029XgXSXTYBwUCfNpzbcE8NlqwZQdpCWM2dxN8Ev+6u4nuXe6ngVdT meY29Q8YSbAdM22Ayr1xcakgwAbpwfOYukVVzsaVztYtNP66jiugHV7y43Y2+p1lDq8ISQuyrYt oGji+oZgAClcMajwSOqUrqCGMU+gfXKFhQdXt72KeAiILBHudIfQfeyubBUsxtCC0B+NJUTPtOl yL4EgvGg5N66jlL4X+R0aHY/x9eNGYLF7nwMeiAuQj1lEdM1heEVCrsLNob16sX006nG3XHO7NX zCrth4SIVmQcXFciVi0Z46fFHTQx/GJrXIGnF5ENPHeDtusvtHRzlasPhT4q7VOEcQAyZDlv8mm wn+ZHmJor3xqjiw2pjkd0R/J2v9SSAQ+KYS9I+62RW74MJ1rz4L4d+2E5yytkUiyZ18/gJNUxxF 639+fATD/BHM6cLdEleFM+SJIKbxt1DA7dqIPA= X-Received: by 2002:a17:903:384d:b0:2d0:3412:a3f0 with SMTP id d9443c01a7336-2d0ca962498mr46521685ad.19.1785908133352; Tue, 04 Aug 2026 22:35:33 -0700 (PDT) Received: from [127.0.1.1] (61-220-246-151.hinet-ip.hinet.net. [61.220.246.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d0aa4c0b1fsm14307245ad.64.2026.08.04.22.35.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Aug 2026 22:35:32 -0700 (PDT) From: Kyle Hsieh Date: Wed, 05 Aug 2026 13:38:21 +0800 Subject: [PATCH v3 2/2] iio: adc: ti-ads112c04: Add support for TI ADS112C04 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-ti-ads112c04-driver-v3-2-49f436829e01@gmail.com> References: <20260805-ti-ads112c04-driver-v3-0-49f436829e01@gmail.com> In-Reply-To: <20260805-ti-ads112c04-driver-v3-0-49f436829e01@gmail.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kyle Hsieh X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=13673; i=kylehsieh1995@gmail.com; h=from:subject:message-id; bh=mh9Vc4GD7cjIRTzPZeqOurJ6XGAGOWFO88DhFXJJq1M=; b=owEBbQGS/pANAwAKAaWDQrcJVsSBAcsmYgBqcsxN3hVT89cn0FB9dEsyFqPgVZAZmt7s63Rrc 4ZL7YkLSBiJATMEAAEKAB0WIQTJHsaNZOdY+THGqJelg0K3CVbEgQUCanLMTQAKCRClg0K3CVbE gXjHCACb+BnU4LZF5CbtwRiUAWS5iG8y0WBYZD2mHVTu7cZ8dvX8Nkn3uCJlq66+4bLBwr9nDhw AFpR94xoZfFdU5w11kGC29DMpHolcxGaSn+tYgCw6GkXOIpvcpn+qkr/yTMPS0G6UUW2w1SOAK9 yHztD0Bfw6L24QNE6VcEPB2kJAOW+vWjfJcrqHHvg852vIVvU9l8BSb5dXLLp5m+YNSBlsUxMZb eHiuBWeElfHOc7EmQ1F0WIJYicrq910GfgcpyANUC9tGHM1nQ8zttDVcD0BVQpDR7EQtqBu7VPK Xt8iwK2Z2g2Z1/HO4ZLuVCP5ts5CbusI7FRarNAr33oOn1C8 X-Developer-Key: i=kylehsieh1995@gmail.com; a=openpgp; fpr=C91EC68D64E758F931C6A897A58342B70956C481 Add IIO driver support for the Texas Instruments ADS112C04 (16-bit) delta-sigma ADCs. The driver implements: - Single-shot conversions using the IIO raw read interface. - Dynamic parsing of single-ended and differential channels from device tree child nodes. - Hardware interrupt support via the DRDY pin, falling back to software polling if no IRQ is provided. - Scale calculation based on the internal 2.048V reference. - Dynamic reference voltage scaling via the regulator subsystem (refp-supply/refn-supply), falling back to the internal 2.048V reference if not specified. - Hardware reset fallback using GPIO. Signed-off-by: Kyle Hsieh --- drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ti-ads112c04.c | 423 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 434 insertions(+) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 3755a81c1efd..402e841bc083 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1789,6 +1789,16 @@ config TI_ADS1119 This driver can also be built as a module. If so, the module will= be called ti-ads1119. =20 +config TI_ADS112C04 + tristate "Texas Instruments ADS112C04 ADC" + depends on I2C + help + If you say yes here you get support for Texas Instruments + ADS112C04 (16-bit) I2C analog to digital converters. + + This driver can also be built as a module. If so, the module will be + called ti-ads112c04. + config TI_ADS124S08 tristate "Texas Instruments ADS124S08" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 707dd708912f..ebf9d4047a5a 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -153,6 +153,7 @@ obj-$(CONFIG_TI_ADS1015) +=3D ti-ads1015.o obj-$(CONFIG_TI_ADS1018) +=3D ti-ads1018.o obj-$(CONFIG_TI_ADS1100) +=3D ti-ads1100.o obj-$(CONFIG_TI_ADS1119) +=3D ti-ads1119.o +obj-$(CONFIG_TI_ADS112C04) +=3D ti-ads112c04.o obj-$(CONFIG_TI_ADS124S08) +=3D ti-ads124s08.o obj-$(CONFIG_TI_ADS1298) +=3D ti-ads1298.o obj-$(CONFIG_TI_ADS131E08) +=3D ti-ads131e08.o diff --git a/drivers/iio/adc/ti-ads112c04.c b/drivers/iio/adc/ti-ads112c04.c new file mode 100644 index 000000000000..64af866f615d --- /dev/null +++ b/drivers/iio/adc/ti-ads112c04.c @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Texas Instruments ADS112C04 16-bit I2C ADC driver + * + * Copyright (c) 2026 Kyle Hsieh + * + * Datasheet: https://www.ti.com/lit/ds/symlink/ads112c04.pdf + * Based on TI Reference Code and standard Linux IIO framework. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define ADS112C04_CMD_RESET 0x06 +#define ADS112C04_CMD_START_SYNC 0x08 +#define ADS112C04_CMD_POWERDOWN 0x02 +#define ADS112C04_CMD_RDATA 0x10 +#define ADS112C04_CMD_RREG(reg) (0x20 | ((reg) << 2)) +#define ADS112C04_CMD_WREG(reg) (0x40 | ((reg) << 2)) + +#define ADS112C04_REG_CONFIG0 0x00 +#define ADS112C04_REG_CONFIG1 0x01 +#define ADS112C04_REG_CONFIG2 0x02 +#define ADS112C04_REG_CONFIG3 0x03 + +#define ADS112C04_CONFIG0_MUX GENMASK(7, 4) +#define ADS112C04_CONFIG0_PGA_BYPASS BIT(0) +#define ADS112C04_CONFIG2_DRDY BIT(7) + +struct ads112c04_state { + struct i2c_client *client; + /* Protects concurrent ADC reads and device configuration */ + struct mutex lock; + struct completion completion; + struct regulator *vref_reg; + int vref_mV; + u8 config0; + u8 config1; +}; + +static int ads112c04_write_cmd(struct i2c_client *client, u8 cmd) +{ + int ret; + + ret =3D i2c_smbus_write_byte(client, cmd); + + return ret < 0 ? ret : 0; +} + +static int ads112c04_read_reg(struct i2c_client *client, u8 reg, u8 *val) +{ + int ret; + + ret =3D i2c_smbus_read_byte_data(client, ADS112C04_CMD_RREG(reg)); + if (ret < 0) + return ret; + + *val =3D ret; + + return 0; +} + +static int ads112c04_write_reg(struct i2c_client *client, u8 reg, u8 val) +{ + int ret; + + ret =3D i2c_smbus_write_byte_data(client, ADS112C04_CMD_WREG(reg), val); + + return ret < 0 ? ret : 0; +} + +static int ads112c04_wait_for_data(struct ads112c04_state *st) +{ + int ret, err; + u8 val; + + if (st->client->irq > 0) { + /* Timeout is 100ms (slowest data rate is 20 SPS) */ + ret =3D wait_for_completion_timeout(&st->completion, + msecs_to_jiffies(100)); + if (!ret) + return -ETIMEDOUT; + return 0; + } + + err =3D read_poll_timeout(ads112c04_read_reg, ret, + (ret < 0 || (val & ADS112C04_CONFIG2_DRDY)), + 1000, 100 * USEC_PER_MSEC, false, + st->client, ADS112C04_REG_CONFIG2, &val); + + if (ret < 0) + return ret; + + return err; +} + +static int ads112c04_read_data(struct ads112c04_state *st, int *val) +{ + int ret; + + ret =3D i2c_smbus_read_word_data(st->client, ADS112C04_CMD_RDATA); + if (ret < 0) + return ret; + + *val =3D sign_extend32(be16_to_cpu(ret), 15); + + return 0; +} + +static int ads112c04_get_adc_result(struct ads112c04_state *st, + struct iio_chan_spec const *chan, + int *val) +{ + u8 new_config0; + int ret; + + new_config0 =3D st->config0 & ~ADS112C04_CONFIG0_MUX; + new_config0 |=3D FIELD_PREP(ADS112C04_CONFIG0_MUX, chan->address); + + if (st->config0 !=3D new_config0) { + ret =3D ads112c04_write_reg(st->client, ADS112C04_REG_CONFIG0, new_confi= g0); + if (ret < 0) + return ret; + st->config0 =3D new_config0; + } + + reinit_completion(&st->completion); + + ret =3D ads112c04_write_cmd(st->client, ADS112C04_CMD_START_SYNC); + if (ret < 0) + return ret; + + ret =3D ads112c04_wait_for_data(st); + if (ret < 0) + return ret; + + return ads112c04_read_data(st, val); +} + +static int ads112c04_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct ads112c04_state *st =3D iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + mutex_lock(&st->lock); + ret =3D ads112c04_get_adc_result(st, chan, val); + mutex_unlock(&st->lock); + + if (ret < 0) + return ret; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + *val =3D st->vref_mV; + *val2 =3D 15; + return IIO_VAL_FRACTIONAL_LOG2; + + default: + return -EINVAL; + } +} + +static irqreturn_t ads112c04_irq_handler(int irq, void *private) +{ + struct iio_dev *indio_dev =3D private; + struct ads112c04_state *st =3D iio_priv(indio_dev); + + complete(&st->completion); + + return IRQ_HANDLED; +} + +static const struct iio_info ads112c04_info =3D { + .read_raw =3D ads112c04_read_raw, +}; + +static void ads112c04_regulator_disable(void *data) +{ + regulator_disable(data); +} + +static int ads112c04_parse_channels(struct iio_dev *indio_dev) +{ + struct device *dev =3D indio_dev->dev.parent; + struct iio_chan_spec *channels; + u32 num_channels, pair[2]; + int ret, i =3D 0; + + num_channels =3D device_get_named_child_node_count(dev, "channel"); + if (!num_channels) + return -EINVAL; + + channels =3D devm_kcalloc(dev, num_channels, sizeof(*channels), GFP_KERNE= L); + if (!channels) + return -ENOMEM; + + device_for_each_named_child_node_scoped(dev, child, "channel") { + struct iio_chan_spec *spec =3D &channels[i]; + + if (fwnode_property_present(child, "excitation-channels") || + fwnode_property_present(child, "reference-sources")) + return dev_err_probe(dev, -EOPNOTSUPP, + "advanced channel properties are not supported yet\n"); + + spec->type =3D IIO_VOLTAGE; + spec->indexed =3D 1; + spec->info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_= SCALE); + + if (fwnode_property_present(child, "single-channel")) { + ret =3D fwnode_property_read_u32(child, "single-channel", &pair[0]); + if (ret) + return dev_err_probe(dev, ret, + "failed to read single-channel property\n"); + + if (pair[0] > 3) + return dev_err_probe(dev, -EINVAL, + "single-channel must be 0-3\n"); + + spec->channel =3D pair[0]; + spec->address =3D 0x08 + pair[0]; + } else if (fwnode_property_present(child, "diff-channels")) { + ret =3D fwnode_property_read_u32_array(child, "diff-channels", pair, 2); + if (ret) + return dev_err_probe(dev, ret, + "failed to read diff-channels property\n"); + + if (pair[0] > 3 || pair[1] > 3) + return dev_err_probe(dev, -EINVAL, + "diff-channels must be 0-3\n"); + + spec->channel =3D pair[0]; + spec->channel2 =3D pair[1]; + spec->differential =3D 1; + + if (pair[0] =3D=3D 0 && pair[1] =3D=3D 1) + spec->address =3D 0x00; + else if (pair[0] =3D=3D 0 && pair[1] =3D=3D 2) + spec->address =3D 0x01; + else if (pair[0] =3D=3D 0 && pair[1] =3D=3D 3) + spec->address =3D 0x02; + else if (pair[0] =3D=3D 1 && pair[1] =3D=3D 0) + spec->address =3D 0x03; + else if (pair[0] =3D=3D 1 && pair[1] =3D=3D 2) + spec->address =3D 0x04; + else if (pair[0] =3D=3D 1 && pair[1] =3D=3D 3) + spec->address =3D 0x05; + else if (pair[0] =3D=3D 2 && pair[1] =3D=3D 3) + spec->address =3D 0x06; + else if (pair[0] =3D=3D 3 && pair[1] =3D=3D 2) + spec->address =3D 0x07; + else + return dev_err_probe(dev, -EINVAL, + "invalid diff-channels combination\n"); + } else { + return dev_err_probe(dev, -EINVAL, + "channel node must have single-channel or diff-channels\n"); + } + i++; + } + + indio_dev->channels =3D channels; + indio_dev->num_channels =3D i; + + return 0; +} + +static int ads112c04_probe(struct i2c_client *client) +{ + struct device *dev =3D &client->dev; + struct iio_dev *indio_dev; + struct ads112c04_state *st; + struct gpio_desc *reset_gpio; + int ret, refp_mV =3D 2048; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->client =3D client; + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + init_completion(&st->completion); + + indio_dev->name =3D "ads112c04"; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->info =3D &ads112c04_info; + + /* Forward compatibility checks for unimplemented DT properties */ + if (device_property_present(dev, "refn-supply") || + device_property_present(dev, "ti,refp-refn-resistor-ohms")) + return dev_err_probe(dev, -EOPNOTSUPP, + "refn-supply and external resistors are not supported yet\n"); + + ret =3D ads112c04_parse_channels(indio_dev); + if (ret) + return ret; + + ret =3D devm_regulator_get_enable(dev, "avdd"); + if (ret) + return dev_err_probe(dev, ret, "failed to get avdd regulator\n"); + + ret =3D devm_regulator_get_enable(dev, "dvdd"); + if (ret) + return dev_err_probe(dev, ret, "failed to get dvdd regulator\n"); + + st->vref_reg =3D devm_regulator_get_optional(dev, "refp"); + if (IS_ERR(st->vref_reg)) { + ret =3D PTR_ERR(st->vref_reg); + if (ret =3D=3D -ENODEV) + st->config1 =3D 0x00; + else + return ret; + + } else { + ret =3D regulator_enable(st->vref_reg); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, ads112c04_regulator_disable, + st->vref_reg); + if (ret) + return ret; + + ret =3D regulator_get_voltage(st->vref_reg); + if (ret < 0) + return ret; + + refp_mV =3D ret / (MICRO / MILLI); + st->config1 =3D 0x02; + } + + st->vref_mV =3D refp_mV; + + /* Power-On Reset (POR) delay */ + fsleep(50000); + + /* Requesting OUT_HIGH asserts the active-low reset pin immediately */ + reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset_gpio)) + return PTR_ERR(reset_gpio); + + if (reset_gpio) { + fsleep(1000); + gpiod_set_value_cansleep(reset_gpio, 0); + } else { + ret =3D ads112c04_write_cmd(client, ADS112C04_CMD_RESET); + if (ret < 0) + return ret; + } + + fsleep(1000); + + /* Bypass PGA for now to allow full-scale single-ended measurements */ + st->config0 =3D ADS112C04_CONFIG0_PGA_BYPASS; + ret =3D ads112c04_write_reg(client, ADS112C04_REG_CONFIG0, st->config0); + if (ret) + return ret; + + ret =3D ads112c04_write_reg(client, ADS112C04_REG_CONFIG1, st->config1); + if (ret) + return ret; + + if (client->irq > 0) { + ret =3D devm_request_irq(dev, client->irq, + ads112c04_irq_handler, + 0, + indio_dev->name, indio_dev); + if (ret) + return ret; + } + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct i2c_device_id ads112c04_id[] =3D { + { .name =3D "ads112c04" }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ads112c04_id); + +static const struct of_device_id ads112c04_of_match[] =3D { + { .compatible =3D "ti,ads112c04" }, + { } +}; +MODULE_DEVICE_TABLE(of, ads112c04_of_match); + +static struct i2c_driver ads112c04_driver =3D { + .driver =3D { + .name =3D "ads112c04", + .of_match_table =3D ads112c04_of_match, + }, + .probe =3D ads112c04_probe, + .id_table =3D ads112c04_id, +}; +module_i2c_driver(ads112c04_driver); + +MODULE_AUTHOR("Kyle Hsieh "); +MODULE_DESCRIPTION("Texas Instruments ADS112C04 ADC driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1