From nobody Sat Oct 3 04:28:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB92E449EB6; Wed, 5 Aug 2026 11:57:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785931064; cv=none; b=EyTkWGQhAlS92V+De+HQh5NtPZHmV/xcfOmD4K2WNLI8Gt5Fk1cfwRSaebbr3+D4tHARlpMQVAIpYXk8d5cZlVEQ5gs7BXs5wHOn0Q7NLhAmzSOvI4SR4wzbnwCtdvlUeoPBxW0AUo6X2DulVBzMXpawuskwNAcGSwr5w9RrGN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785931064; c=relaxed/simple; bh=gW7yskx0hJe4wqbjC3Uh9uR5y58UvdjvlKeXqi7lhsE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E63Jni0Pak6K8I71BXA6KvxNd0SPocDxru/yurPFfamHP1wWLDu514qbvt04xUYDGTxdwRo6gRsgeouVsr8UW81CnUVS/C/vwyva84s/UBmsR3JQGYRu5xwfG/n+Zd6U8Gg9Gg3POjUIy8Pc6Cxv0k+YqTANeTFw3V8wd4OCzYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FxmrL3cY; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FxmrL3cY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 102D31F00A3A; Wed, 5 Aug 2026 11:57:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785931062; bh=d8keb7Vf5mcDOWQ8qaY4y+UDfw6ta0RP32gTRI58mxc=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=FxmrL3cYhcXS2AU1x2oNu1UgxwxhOeTmAIxwxROvSeW7QH+GAuWc1x5qkb6YoAGXm Dis/gZ/mSkJcO0sYZ5Pfje3iaGXJ7CgjE7evQ3sCDKmMPZaUOe/qq6jCspmNdyrUa2 NRgFSp7CVSzG/SLv2zyfOS8QeN1r40ogdwsllpdMi0fqrqUp0h+HIp54qabgRpgGtM cWW0W7JqGoV3nVQjRnEHCTDMaHiOWjSoZw61wRYLmmYqidY4Ex9flyewfE25m9kdte 4aNfhNom3xnwORHEZjuZTHMkjBHPY3IfzsQaRPV90kDjUf9ZjA+b5bfUX8sYLAPjqI I8gwFzDpf4dzw== From: Thierry Reding Date: Wed, 05 Aug 2026 13:57:20 +0200 Subject: [PATCH v9 1/5] dt-bindings: pci: tegra264: Strictly distinguish C0 from C1-C5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-tegra264-pcie-v9-1-fa2ed7350ae1@nvidia.com> References: <20260805-tegra264-pcie-v9-0-fa2ed7350ae1@nvidia.com> In-Reply-To: <20260805-tegra264-pcie-v9-0-fa2ed7350ae1@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5710; i=treding@nvidia.com; h=from:subject:message-id; bh=gA/SKuXPQwDidcW7rDgkqxu6NGKwUPEXWt8YBaFws+g=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqcyUwEi6uk7zQmOLW216Sa6tT+uLjpv/y5kXH5 LgmE8lC5j+JAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCanMlMAAKCRDdI6zXfz6z oXhPD/9Y8tFhN/MBE0rU5WC77uGbQ8I48w6SPGt6n46VFoX8P0pHU1cqTwS202QMBEM6J6xHmIF ThkEIUObK6XzkyFK/B47bWM5Y3zQCd5gWzCjzc2Ir/mVt+DCSoAnpjPbK+GdCFQDZZ2RKnBYHMi z+ZOsb4DL+nZLKfX5VnEdgoMcxrtGomki7NrRCsvsd2ZuijOX77guC37wQLWvB6cTxD46iziQxU xCZpIb7Lu/OT7UEJp9bvpayJiHGgYNPe4JJBoGKfr1k9bkvtNt5U4wyhVnXkx21bbqAPFVLFTi9 i32FXylAW/1jWHW/QNSOmI20tKmON1MZnxsip+BBqKxX+5OzHyiMCktoTuq38H34c8eBsCq+oGD OiCcnIxN4TSFd1NvEOGgjO/L8sDdWFin97AIZDaN9HfziDGcYxfMXZj+iIQuT7fbQZMhayWpqex oLlXn9Fh6EwfgvLyOqz+QhAQA+5M9okXOZWFPKHb8NMM85uMsD9blVtvmT/POcHvYzb1w3gNKhb Zi3NGSbpycDABzzn2AgCPAKJmUANCuhOgPpuD7JXCT3p8RWAq2StjeTN4L0n7CbAAK+evq8e4vO VxUICOcm7EhVOv4r/Sqx2XNl1QN4w99kTwC7kCBRZzVWJ99XV8RRZqX/cMwIwGrS6YhD+ORYxLx OLoJDkdjVnNUieQ== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Instead of using the ECAM registers as the first entry, strictly make a distinction between C0 and C1-C5. This is needed because otherwise the unit address doesn't match the first "reg" entry. We also cannot change the ordering of these nodes to follow the ECAM addresses because that would put them outside of their "control bus" hierarchy since the ECAM address space is a global one outside of any of the control busses. Reviewed-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- Changes in v7: - undo changes suggested by Sashiko, should've trust the dedicated tool rather than the AI Changes in v6: - add maxItems as suggested by Sashiko Changes in v5: - rebase on top of v7.1-rc1, make it into a fix Changes in v4: - ECAM is outside of the controller's region, so it cannot be the first reg entry, otherwise we get warnings because it doesn't match the unit-address, so revert back to oneOf construct Changes in v2: - move ECAM region first and unify C0 vs. C1-C5 - move unevaluatedProperties to right before the examples - add description to clarify the two types of controllers - add examples for C0 and C1-C5 --- .../bindings/pci/nvidia,tegra264-pcie.yaml | 75 ++++++++++++++----= ---- 1 file changed, 50 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yam= l b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml index dc4f8725c9f5..acb677d477fb 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml @@ -10,32 +10,23 @@ maintainers: - Thierry Reding - Jon Hunter =20 +description: | + Of the six PCIe controllers found on Tegra264, one (C0) is used for the + internal GPU and the other five (C1-C5) are routed to connectors such as + PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1 + through C5, but not for C0. + properties: compatible: const: nvidia,tegra264-pcie =20 reg: - description: | - Of the six PCIe controllers found on Tegra264, one (C0) is used for = the - internal GPU and the other five (C1-C5) are routed to connectors suc= h as - PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for = C1 - through C5, but not for C0. minItems: 4 - items: - - description: ECAM-compatible configuration space - - description: application layer registers - - description: transaction layer registers - - description: privileged transaction layer registers - - description: data link/physical layer registers (not available on = C0) + maxItems: 5 =20 reg-names: minItems: 4 - items: - - const: ecam - - const: xal - - const: xtl - - const: xtl-pri - - const: xpl + maxItems: 5 =20 interrupts: minItems: 1 @@ -70,6 +61,40 @@ required: =20 allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# + - oneOf: + - description: C0 controller (no UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: ecam + + - description: C1-C5 controllers (with UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: data link/physical layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: xpl + - const: ecam =20 unevaluatedProperties: false =20 @@ -81,11 +106,11 @@ examples: =20 pci@c000000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xd0 0xb0000000 0x0 0x10000000>, - <0x00 0x0c000000 0x0 0x00004000>, + reg =3D <0x00 0x0c000000 0x0 0x00004000>, <0x00 0x0c004000 0x0 0x00001000>, - <0x00 0x0c005000 0x0 0x00001000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri"; + <0x00 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -118,12 +143,12 @@ examples: =20 pci@8400000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xa8 0xb0000000 0x0 0x10000000>, - <0x00 0x08400000 0x0 0x00004000>, + reg =3D <0x00 0x08400000 0x0 0x00004000>, <0x00 0x08404000 0x0 0x00001000>, <0x00 0x08405000 0x0 0x00001000>, - <0x00 0x08410000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08410000 0x0 0x00010000>, + <0xa8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; 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a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Switch to using the PCIe root port bindings in preparation for using the standard WAKE# handling. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/nvidia,tegra264-pcie.yaml | 40 +++++++++++++++++-= ---- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yam= l b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml index acb677d477fb..f0114defc04e 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml @@ -52,12 +52,11 @@ properties: - description: PCIe controller ID maximum: 5 =20 -required: - - interrupt-map - - interrupt-map-mask - - iommu-map - - msi-map - - nvidia,bpmp +patternProperties: + '^pcie@': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + unevaluatedProperties: false =20 allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# @@ -96,6 +95,13 @@ allOf: - const: xpl - const: ecam =20 +required: + - interrupt-map + - interrupt-map-mask + - iommu-map + - msi-map + - nvidia,bpmp + unevaluatedProperties: false =20 examples: @@ -130,9 +136,18 @@ examples: ranges =3D <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x0020= 0000>, <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x080000= 00>, <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc00000= 00>; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CIrOujUk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 572691F000E9; Wed, 5 Aug 2026 11:57:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785931067; bh=awvJhnsJwxAymEIAnFPrGQKmsl2oXtGQSqpjwM+RqvU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=CIrOujUkFTWwiVbRjYP/Og+N0kvJPd00r0UXpc7QjYJjJs5bfk/wNjOv/cRpATVtl r9FZ52zBho4DG2m9mdCyw3zIxv/VjR8WkGLjXX/p0NILoGgxOYyuHpjH3yQGyhXnYX Kd+VwdcaixrpM0V5WOz60g/9sVVHV+yjlp4tJaQ/hkdb6z/ogWe2pHG5W/CrziMPQb ZwQSUiv3NDRznccgN03OdUeB37ppt4v7Jdwnm5I4Poq5b97jXNU9t6bQYKuk92Jbrq cFHDoNKJ2J3R3jnearIaJ3G91ZhIoOFgdZXfrUZm6wp8uhNAmLYJe6f44YGrqROQ7Y VGnISfBqRmCgw== From: Thierry Reding Date: Wed, 05 Aug 2026 13:57:22 +0200 Subject: [PATCH v9 3/5] PCI: tegra: Add Tegra264 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-tegra264-pcie-v9-3-fa2ed7350ae1@nvidia.com> References: <20260805-tegra264-pcie-v9-0-fa2ed7350ae1@nvidia.com> In-Reply-To: <20260805-tegra264-pcie-v9-0-fa2ed7350ae1@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding , Manikanta Maddireddy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=18025; i=treding@nvidia.com; h=from:subject:message-id; bh=I66f7Aff8CwDwYd7ORcI3MdP2SOyBSeKCXYyuLDUvIw=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqcyUx0Z2PFG2zlGfV9PB7240lGTACl+kw6P9RX IzxzY0lVH+JAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCanMlMQAKCRDdI6zXfz6z obYnD/0YhxTWvnp5Wf91hF5gLSOBYl63XcCjuSRPkY4YZgZm6cqiT08+UNamjZZzvr/5No66QSE 6HwOV7I365M70eaPC3IbmI18BygIlvYTfijWE5m5aJ0HKELS8oAeiPo5ZvHcYIh63/sZxXWoUDx dR5v5XvsTiHtNQBFmZeOfnYVufojwTpjopsZwT94UB5kt81dYN9rOGNs0IT3w4GcMoa9c+esLoq yF0raFN+ZwFLF6n4qzpG7Kc/lXtBxvnosHsHrBcLwNp+ItRIF+iB5jx/BVABCu6ni4L+1hBNxY4 IF4LTRsEBVMo4/alJe4C4hoHVvu2a1Od0LUEPJySdSi28IftGWxHcqNQ60TYu+VkrgTHtZh0dw/ ReqKSUIeRwksUQB5c2C1ubIkRFjmsnj3r5iKBV9bqP6dvGq27Hk0GstLhCVXNbdR5QNyw+a7+Wh h9WadSPBRREsJKG9ymP98Gfj1EwtaQOZImTYRBuPDKd2fC7/V8BQOxy4nTeCygRNI9Gn4H48Rur OOdzq/mO7UYSGURbc0cyCD/9SEbkH7tu2smBkQuF/s5e4Idj3EomXuRP3+K2FNURDrF5fbvnArS xv+E96ZfXdk+qOAeOw7Pab+3fzw5qd1norfS6qLjIoVnep9VIUFDiGlj1/tR9hQhokH7sM2SRiT s0Ht3RDqiAlOrCg== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Add a driver for the PCIe controller found on NVIDIA Tegra264 SoCs. The driver is very small, with its main purpose being to set up the address translation registers and then creating a standard PCI host using ECAM. Signed-off-by: Manikanta Maddireddy Signed-off-by: Thierry Reding --- Changes in v9: - remove suspend/resume support, it doesn't work on Tegra264 yet - use pm_runtime_resume_and_get() instead of pm_runtime_get_sync() - rename tegra264_pcie_check_ranges() for clarity - remove unused header includes Changes in v8: - remove controller deinitialization, firmware does this already - separately track hotplug support and link up state for clarity - select pinctrl sleep state on suspend for symmetry with resume - fail probe if the link is down and not hotplug-capable - remove WAKE# IRQ support - add err_ prefix to gotos Changes in v7: - select PCI_ECAM to satisfy the build dependency (Jonathan Hunter) - remove pre-silicon support patch to avoid extra build dependency Changes in v6: - remove unneeded pm_runtime_disable() call (Sashiko) - do not use noirq suspend/resume callbacks (Sashiko) - wrap PM ops in pm_ptr() macro (Sashiko) - use standard wait times with msleep() (Lukas Wunner) - properly check errors for wake IRQs - fix build failures /o\ Changes in v5: - make PCIE_TEGRA264 symbol tristate - drop dependency on PCI_MSI - reorganize tegra264_pcie struct - use standard wake-gpios property - rename tegra264_pcie_bpmp_set_rp_state() to tegra264_pcie_power_off() - use dev_err() instead of dev_info() for some error messages - add clarifying comment as to why bandwidth requests aren't fatal - address some compiler warnings on 32-bit physical address platforms - drop needless comments - explicitly deinitialize controller on suspend - use devm_pm_runtime_active_enabled() - rename "free" label to "free_ecam" - use dev_err_probe() in more places - reselect default pin state during resume, not probe - return early on absence of wake GPIO - simplify BW value calculation Changes in v2: - specify generations applicable for PCI_TEGRA driver to avoid confusion - drop SPDX-FileCopyrightText tag - rename link_state to link_up to clarify meaning - replace memset() by an empty initializer - sanity-check only enable BAR regions - bring PCI link out of reset in case firmware didn't - use common wait times instead of defining our own - use core helpers to parse and print PCI link speed - fix multi-line comment - use dev_err_probe() more ubiquitously - fix probe sequence and error cleanup - use DEFINE_NOIRQ_DEV_PM_OPS() to avoid warnings for !PM_SUSPEND - reuse more standard registers and remove unused register definitions - use %pe and ERR_PTR() to print symbolic errors - add signed-off-by from Manikanta as the original author - add myself as author after significantly modifying the driver fixups --- drivers/pci/controller/Kconfig | 10 +- drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-tegra264.c | 450 +++++++++++++++++++++++++++++= ++++ 3 files changed, 460 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 8a3a31b2bc12..b20d84290f7e 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -255,7 +255,15 @@ config PCI_TEGRA select IRQ_MSI_LIB help Say Y here if you want support for the PCIe host controller found - on NVIDIA Tegra SoCs. + on NVIDIA Tegra SoCs (Tegra20 through Tegra186). + +config PCIE_TEGRA264 + tristate "NVIDIA Tegra264 PCIe controller" + depends on ARCH_TEGRA || COMPILE_TEST + select PCI_ECAM + help + Say Y here if you want support for the PCIe host controller found + on NVIDIA Tegra264 SoCs. =20 config PCIE_RCAR_HOST bool "Renesas R-Car PCIe controller (host mode)" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makef= ile index ac8db283f0fe..d478743b5142 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_HYPERV_INTERFACE) +=3D pci-hyperv-intf.o obj-$(CONFIG_PCI_MVEBU) +=3D pci-mvebu.o obj-$(CONFIG_PCI_AARDVARK) +=3D pci-aardvark.o obj-$(CONFIG_PCI_TEGRA) +=3D pci-tegra.o +obj-$(CONFIG_PCIE_TEGRA264) +=3D pcie-tegra264.o obj-$(CONFIG_PCI_RCAR_GEN2) +=3D pci-rcar-gen2.o obj-$(CONFIG_PCIE_RCAR_HOST) +=3D pcie-rcar.o pcie-rcar-host.o obj-$(CONFIG_PCIE_RCAR_EP) +=3D pcie-rcar.o pcie-rcar-ep.o diff --git a/drivers/pci/controller/pcie-tegra264.c b/drivers/pci/controlle= r/pcie-tegra264.c new file mode 100644 index 000000000000..e0c5b9d0d20b --- /dev/null +++ b/drivers/pci/controller/pcie-tegra264.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe host controller driver for Tegra264 SoC + * + * Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../pci.h" + +/* XAL registers */ +#define XAL_RC_ECAM_BASE_HI 0x00 +#define XAL_RC_ECAM_BASE_LO 0x04 +#define XAL_RC_ECAM_BUSMASK 0x08 +#define XAL_RC_IO_BASE_HI 0x0c +#define XAL_RC_IO_BASE_LO 0x10 +#define XAL_RC_IO_LIMIT_HI 0x14 +#define XAL_RC_IO_LIMIT_LO 0x18 +#define XAL_RC_MEM_32BIT_BASE_HI 0x1c +#define XAL_RC_MEM_32BIT_BASE_LO 0x20 +#define XAL_RC_MEM_32BIT_LIMIT_HI 0x24 +#define XAL_RC_MEM_32BIT_LIMIT_LO 0x28 +#define XAL_RC_MEM_64BIT_BASE_HI 0x2c +#define XAL_RC_MEM_64BIT_BASE_LO 0x30 +#define XAL_RC_MEM_64BIT_LIMIT_HI 0x34 +#define XAL_RC_MEM_64BIT_LIMIT_LO 0x38 +#define XAL_RC_BAR_CNTL_STANDARD 0x40 +#define XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN BIT(0) +#define XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN BIT(1) +#define XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN BIT(2) + +/* XTL registers */ +#define XTL_RC_PCIE_CFG_LINK_STATUS 0x5a + +#define XTL_RC_MGMT_PERST_CONTROL 0x218 +#define XTL_RC_MGMT_PERST_CONTROL_PERST_O_N BIT(0) + +#define XTL_RC_MGMT_CLOCK_CONTROL 0x47c +#define XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT BIT= (9) + +struct tegra264_pcie { + struct device *dev; + + /* I/O memory */ + void __iomem *xal; + void __iomem *xtl; + void __iomem *ecam; + + /* bridge configuration */ + struct pci_config_window *cfg; + struct pci_host_bridge *bridge; + + /* BPMP and bandwidth management */ + struct icc_path *icc_path; + struct tegra_bpmp *bpmp; + u32 ctl_id; + + bool supports_hotplug; + bool link_up; +}; + +static void tegra264_pcie_power_off(struct tegra264_pcie *pcie) +{ + struct tegra_bpmp_message msg =3D {}; + struct mrq_pcie_request req =3D {}; + int err; + + req.cmd =3D CMD_PCIE_RP_CONTROLLER_OFF; + req.rp_ctrlr_off.rp_controller =3D pcie->ctl_id; + + msg.mrq =3D MRQ_PCIE; + msg.tx.data =3D &req; + msg.tx.size =3D sizeof(req); + + err =3D tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + dev_err(pcie->dev, "failed to turn off PCIe #%u: %pe\n", + pcie->ctl_id, ERR_PTR(err)); + + if (msg.rx.ret) + dev_err(pcie->dev, "failed to turn off PCIe #%u: %d\n", + pcie->ctl_id, msg.rx.ret); +} + +static void tegra264_pcie_icc_set(struct tegra264_pcie *pcie) +{ + u32 value, speed, width; + int err; + + value =3D readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); + speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, value); + width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, value); + + value =3D Mbps_to_icc(width * PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])); + + /* + * We don't want to error out here because a boot-critical device + * could be connected to this root port. Failure to set the bandwidth + * request may have an adverse impact on performance, but it is not + * generally fatal, so we opt to continue regardless so that users + * get a chance to fix things. + */ + err =3D icc_set_bw(pcie->icc_path, value, value); + if (err < 0) + dev_err(pcie->dev, + "failed to request bandwidth (%u kBps): %pe\n", + value, ERR_PTR(err)); +} + +/* + * The various memory regions used by the controller (I/O, memory, ECAM) a= re + * set up during early boot and have hardware-level protections in place. = If + * the DT ranges don't match what's been setup, the controller won't be ab= le + * to write the address endpoints properly, so make sure to validate that = DT + * and firmware programming agree on these ranges. + */ +static bool tegra264_pcie_valid_ranges(struct platform_device *pdev) +{ + struct tegra264_pcie *pcie =3D platform_get_drvdata(pdev); + struct device_node *np =3D pcie->dev->of_node; + struct of_pci_range_parser parser; + phys_addr_t phys, limit, hi, lo; + struct of_pci_range range; + struct resource *res; + bool status =3D true; + u32 value; + int err; + + err =3D of_pci_range_parser_init(&parser, np); + if (err < 0) + return false; + + for_each_of_pci_range(&parser, &range) { + unsigned int addr_hi, addr_lo, limit_hi, limit_lo, enable; + unsigned long type =3D range.flags & IORESOURCE_TYPE_BITS; + phys_addr_t start, end, mask; + const char *region =3D NULL; + + end =3D range.cpu_addr + range.size - 1; + start =3D range.cpu_addr; + + switch (type) { + case IORESOURCE_IO: + addr_hi =3D XAL_RC_IO_BASE_HI; + addr_lo =3D XAL_RC_IO_BASE_LO; + limit_hi =3D XAL_RC_IO_LIMIT_HI; + limit_lo =3D XAL_RC_IO_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN; + mask =3D SZ_64K - 1; + region =3D "I/O"; + break; + + case IORESOURCE_MEM: + if (range.flags & IORESOURCE_PREFETCH) { + addr_hi =3D XAL_RC_MEM_64BIT_BASE_HI; + addr_lo =3D XAL_RC_MEM_64BIT_BASE_LO; + limit_hi =3D XAL_RC_MEM_64BIT_LIMIT_HI; + limit_lo =3D XAL_RC_MEM_64BIT_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN; + region =3D "prefetchable memory"; + } else { + addr_hi =3D XAL_RC_MEM_32BIT_BASE_HI; + addr_lo =3D XAL_RC_MEM_32BIT_BASE_LO; + limit_hi =3D XAL_RC_MEM_32BIT_LIMIT_HI; + limit_lo =3D XAL_RC_MEM_32BIT_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN; + region =3D "memory"; + } + + mask =3D SZ_1M - 1; + break; + } + + /* not interested in anything that's not I/O or memory */ + if (!region) + continue; + + /* don't check regions that haven't been enabled */ + value =3D readl(pcie->xal + XAL_RC_BAR_CNTL_STANDARD); + if ((value & enable) =3D=3D 0) + continue; + + hi =3D readl(pcie->xal + addr_hi); + lo =3D readl(pcie->xal + addr_lo); + phys =3D ((hi << 16) << 16) | lo; + + hi =3D readl(pcie->xal + limit_hi); + lo =3D readl(pcie->xal + limit_lo); + limit =3D ((hi << 16) << 16) | lo | mask; + + if (phys !=3D start || limit !=3D end) { + dev_err(pcie->dev, + "%s region mismatch: %pap-%pap -> %pap-%pap\n", + region, &phys, &limit, &start, &end); + status =3D false; + } + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); + if (!res) + return false; + + hi =3D readl(pcie->xal + XAL_RC_ECAM_BASE_HI); + lo =3D readl(pcie->xal + XAL_RC_ECAM_BASE_LO); + phys =3D ((hi << 16) << 16) | lo; + + value =3D readl(pcie->xal + XAL_RC_ECAM_BUSMASK); + limit =3D phys + ((value + 1) << 20) - 1; + + if (phys !=3D res->start || limit !=3D res->end) { + dev_err(pcie->dev, + "ECAM region mismatch: %pap-%pap -> %pap-%pap\n", + &phys, &limit, &res->start, &res->end); + status =3D false; + } + + return status; +} + +static bool tegra264_pcie_supports_hotplug(struct tegra264_pcie *pcie) +{ + u32 value =3D readl(pcie->xtl + XTL_RC_MGMT_CLOCK_CONTROL); + + return (value & XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_= PRSNT) !=3D 0; +} + +static bool tegra264_pcie_link_up(struct tegra264_pcie *pcie, + enum pci_bus_speed *speed) +{ + u16 value =3D readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); + + if (value & PCI_EXP_LNKSTA_DLLLA) { + if (speed) + *speed =3D pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, + value)]; + + return true; + } + + return false; +} + +static void tegra264_pcie_init(struct tegra264_pcie *pcie) +{ + enum pci_bus_speed speed; + unsigned int i; + u32 value; + + /* bring the endpoint out of reset */ + value =3D readl(pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); + value |=3D XTL_RC_MGMT_PERST_CONTROL_PERST_O_N; + writel(value, pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); + + for (i =3D 0; i < PCIE_LINK_WAIT_MAX_RETRIES; i++) { + if (tegra264_pcie_link_up(pcie, NULL)) + break; + + msleep(PCIE_LINK_WAIT_SLEEP_MS); + } + + pcie->supports_hotplug =3D tegra264_pcie_supports_hotplug(pcie); + pcie->link_up =3D tegra264_pcie_link_up(pcie, &speed); + + if (pcie->link_up) { + msleep(PCIE_RESET_CONFIG_WAIT_MS); + dev_info(pcie->dev, "PCIe #%u link is up (speed: %s)\n", + pcie->ctl_id, pci_speed_string(speed)); + tegra264_pcie_icc_set(pcie); + } else { + dev_info(pcie->dev, "PCIe #%u link is down\n", pcie->ctl_id); + + /* + * Make sure to reset the bandwidth requirements if the link + * is down but hotplug-capable. + */ + if (pcie->supports_hotplug) + tegra264_pcie_icc_set(pcie); + } +} + +static int tegra264_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct tegra264_pcie *pcie; + struct resource_entry *bus; + struct resource *res; + int err; + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie)); + if (!bridge) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate host bridge\n"); + + pcie =3D pci_host_bridge_priv(bridge); + platform_set_drvdata(pdev, pcie); + pcie->bridge =3D bridge; + pcie->dev =3D dev; + + pcie->xal =3D devm_platform_ioremap_resource_byname(pdev, "xal"); + if (IS_ERR(pcie->xal)) + return dev_err_probe(dev, PTR_ERR(pcie->xal), + "failed to map XAL memory\n"); + + pcie->xtl =3D devm_platform_ioremap_resource_byname(pdev, "xtl-pri"); + if (IS_ERR(pcie->xtl)) + return dev_err_probe(dev, PTR_ERR(pcie->xtl), + "failed to map XTL-PRI memory\n"); + + bus =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!bus) + return dev_err_probe(dev, -ENODEV, + "failed to get bus resources\n"); + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); + if (!res) + return dev_err_probe(dev, -ENXIO, + "failed to get ECAM resource\n"); + + pcie->icc_path =3D devm_of_icc_get(dev, "write"); + if (IS_ERR(pcie->icc_path)) + return dev_err_probe(dev, PTR_ERR(pcie->icc_path), + "failed to get ICC\n"); + + pcie->bpmp =3D tegra_bpmp_get_with_id(dev, &pcie->ctl_id); + if (IS_ERR(pcie->bpmp)) + return dev_err_probe(dev, PTR_ERR(pcie->bpmp), + "failed to get BPMP\n"); + + err =3D devm_pm_runtime_set_active_enabled(dev); + if (err < 0) { + dev_err_probe(dev, err, "failed to enable runtime PM\n"); + goto err_put_bpmp; + } + + err =3D pm_runtime_resume_and_get(dev); + if (err < 0) { + dev_err_probe(dev, err, "failed to power on device\n"); + goto err_put_bpmp; + } + + /* sanity check that programmed ranges match what's in DT */ + if (!tegra264_pcie_valid_ranges(pdev)) { + err =3D -EINVAL; + goto err_put_pm; + } + + pcie->cfg =3D pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pcie->cfg)) { + err =3D dev_err_probe(dev, PTR_ERR(pcie->cfg), + "failed to create ECAM\n"); + goto err_put_pm; + } + + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + bridge->sysdata =3D pcie->cfg; + pcie->ecam =3D pcie->cfg->win; + + tegra264_pcie_init(pcie); + + /* + * Fail if the link isn't up and doesn't support hotplug, no device + * will ever be able to be added on this bus. + */ + if (!pcie->link_up && !pcie->supports_hotplug) { + err =3D dev_err_probe(pcie->dev, -ENODEV, + "PCIe #%u link is down and not hotplug-capable, turning off\n", + pcie->ctl_id); + tegra264_pcie_power_off(pcie); + goto err_free_ecam; + } + + err =3D pci_host_probe(bridge); + if (err < 0) { + dev_err_probe(dev, err, "failed to register host\n"); + goto err_free_ecam; + } + + return 0; + +err_free_ecam: + pci_ecam_free(pcie->cfg); +err_put_pm: + pm_runtime_put_sync(dev); +err_put_bpmp: + tegra_bpmp_put(pcie->bpmp); + + return err; +} + +static void tegra264_pcie_remove(struct platform_device *pdev) +{ + struct tegra264_pcie *pcie =3D platform_get_drvdata(pdev); + + /* + * If we undo tegra264_pcie_init() then link goes down and need + * controller reset to bring up the link again. Remove intention is + * to clean up the root bridge and re-enumerate during bind. + */ + pci_lock_rescan_remove(); + pci_stop_root_bus(pcie->bridge->bus); + pci_remove_root_bus(pcie->bridge->bus); + pci_unlock_rescan_remove(); + + pm_runtime_put_sync(&pdev->dev); + tegra_bpmp_put(pcie->bpmp); + pci_ecam_free(pcie->cfg); +} + +static const struct of_device_id tegra264_pcie_of_match[] =3D { + { + .compatible =3D "nvidia,tegra264-pcie", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tegra264_pcie_of_match); + +static struct platform_driver tegra264_pcie_driver =3D { + .probe =3D tegra264_pcie_probe, + .remove =3D tegra264_pcie_remove, + .driver =3D { + .name =3D "tegra264-pcie", + .of_match_table =3D tegra264_pcie_of_match, + }, +}; +module_platform_driver(tegra264_pcie_driver); + +MODULE_AUTHOR("Manikanta Maddireddy "); +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra264 PCIe host controller driver"); +MODULE_LICENSE("GPL"); --=20 2.54.0 From nobody Sat Oct 3 04:28:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C592E448D06; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-tegra264-pcie-v9-4-fa2ed7350ae1@nvidia.com> References: <20260805-tegra264-pcie-v9-0-fa2ed7350ae1@nvidia.com> In-Reply-To: <20260805-tegra264-pcie-v9-0-fa2ed7350ae1@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4866; i=treding@nvidia.com; h=from:subject:message-id; bh=OrgGTXlOuoQVPim35wrIFPmVCqFnYG2TBo2ZemOVWPs=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqcyUx5L5WWwyhv+hKsn8HRF3TbkAcELnjKXNr8 WUnRWw66IOJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCanMlMQAKCRDdI6zXfz6z ocdVD/42+qR+EZlcE/i7iygqCuaIcL8IkFPNsi5otcQ3w7bROiPpIRoXZSNBysxVr1NnsbVbrhA fkKpqejaOTXFysszCPZCzuPCUERyqVUbo12JTUkMmQDSiCAIDlZGH0GeruR2INL5L6/JC5f/00b LRCVuTVP8UTW6gPE7Tb3aEOpjAuZesg7m2ouny6AoPiPUkLO4WL2VRB36vwyAw1suCMniwJmi7w 38Ket3U+2lxSjFKCPfcCslT9KpaEV3+Dxws/69xoJMBE8au/moD9+SIeqzN1UBbCZN+ZCvtTaAx Qtsn6xOrvUpTaMSMdeWd049ysVgAJZEHX6gohRxCKxxp9TB3fOyi98gA2H3Go4nn3rNtgq+1k/z dWVHo6fpPzcpvGtMWI4AL4NwVxzEnL5PD/p8oPgbvQ4gvbRLAMMMON+ySBxYkw9BB8XvT2Q7Lg+ DspkHoHo2WxMmmdmKsyimQu3zzZvtmGQ1Jf6W7Ky7Oa4dhzoR/Pe6WttovYPEP4NSjvJ0zK0Ozm mnUl5PqV1z9nPmloZpXuVVp1DoQeJsiIU2uvFVPxmE2QnNemvZaiCkVs9Ck5wHC9gzgPo6k28VN 2bJrcys76okexfQl/o+PU/rjAqFMU47Y0IVu3RFJoMr1Spaad0QWEAEA39CGFz6Q2+cxtxMIMRJ HJYY2Y6BKibuHxg== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding The ECAM region cannot be the first entry in the "reg" property, because in that case the unit-address wouldn't match the first entry. The order of the nodes can also not be changed to match the ECAM entry because the ECAM region is global and outside of any of the control busses. Acked-by: Manivannan Sadhasivam Signed-off-by: Thierry Reding --- Changes in v8: - add Acked-by from Manivannan Changes in v5: - rebase onto v7.1-rc1 Changes in v4: - revert ECAM "reg" entry order Changes in v2: - order ECAM "reg" entry before others --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 48 ++++++++++++++++------------= ---- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index a1a86022d638..cf9760c681b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3538,11 +3538,11 @@ cmdqv4: cmdqv@b200000 { =20 pci@c000000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xd0 0xb0000000 0x0 0x10000000>, - <0x00 0x0c000000 0x0 0x00004000>, + reg =3D <0x00 0x0c000000 0x0 0x00004000>, <0x00 0x0c004000 0x0 0x00001000>, - <0x00 0x0c005000 0x0 0x00001000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri"; + <0x00 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -3991,12 +3991,12 @@ gpio_uphy: gpio@8300000 { =20 pci@8400000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xa8 0xb0000000 0x0 0x10000000>, - <0x00 0x08400000 0x0 0x00004000>, + reg =3D <0x00 0x08400000 0x0 0x00004000>, <0x00 0x08404000 0x0 0x00001000>, <0x00 0x08405000 0x0 0x00001000>, - <0x00 0x08410000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08410000 0x0 0x00010000>, + <0xa8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -4023,12 +4023,12 @@ pci@8400000 { =20 pci@8420000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xb0 0xb0000000 0x0 0x10000000>, - <0x00 0x08420000 0x0 0x00004000>, + reg =3D <0x00 0x08420000 0x0 0x00004000>, <0x00 0x08424000 0x0 0x00001000>, <0x00 0x08425000 0x0 0x00001000>, - <0x00 0x08430000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08430000 0x0 0x00010000>, + <0xb0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -4055,12 +4055,12 @@ pci@8420000 { =20 pci@8440000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xb8 0xb0000000 0x0 0x10000000>, - <0x00 0x08440000 0x0 0x00004000>, + reg =3D <0x00 0x08440000 0x0 0x00004000>, <0x00 0x08444000 0x0 0x00001000>, <0x00 0x08445000 0x0 0x00001000>, - <0x00 0x08450000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08450000 0x0 0x00010000>, + <0xb8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -4087,12 +4087,12 @@ pci@8440000 { =20 pci@8460000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xc0 0xb0000000 0x0 0x10000000>, - <0x00 0x08460000 0x0 0x00004000>, + reg =3D <0x00 0x08460000 0x0 0x00004000>, <0x00 0x08464000 0x0 0x00001000>, <0x00 0x08465000 0x0 0x00001000>, - <0x00 0x08470000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08470000 0x0 0x00010000>, + <0xc0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -4119,12 +4119,12 @@ pci@8460000 { =20 pci@8480000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xc8 0xb0000000 0x0 0x10000000>, - <0x00 0x08480000 0x0 0x00004000>, + reg =3D <0x00 0x08480000 0x0 0x00004000>, <0x00 0x08484000 0x0 0x00001000>, <0x00 0x08485000 0x0 0x00001000>, - <0x00 0x08490000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08490000 0x0 0x00010000>, + <0xc8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; --=20 2.54.0 From nobody Sat Oct 3 04:28:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A992F44AB61; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NCNoC0aB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C17631F00A3A; Wed, 5 Aug 2026 11:57:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785931073; bh=LzKqxd0i6BEVMJwOWsnwGsBW9qgV25TXeNg/x8DnPDI=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=NCNoC0aBwKQQ4vN1jcy8CSJYbeF5emUvI7D7KMQODwsxdznFfW2sNRbs56EC08hRA 0FrqVT/7JDrgUSqborixN+8H1wy3+LcOwziJJ8pWngUqyYsZkzD9qKJH6vWskesSgw 0VCT3xGB56JW8dLjCgGEjiV3x6iqm7U/zlLUQ/WE0LB/TVULuotrypFLTPK1HZO1BG wNHhhJRb6bYTDiNpa1OP30WYyrDh3ee3zHz/BxYYfheJ4+d1UDrUewDWT7+xAbLTjv UsITCXheGiBpecEsbr9z9ttbsv+Efp9KfePQVvTlsADvm+a4LkLPehilXx1syOM3gH 1OHHRimHBnGMw== From: Thierry Reding Date: Wed, 05 Aug 2026 13:57:24 +0200 Subject: [PATCH v9 5/5] arm64: tegra: Add PCIe root ports on Tegra264 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-tegra264-pcie-v9-5-fa2ed7350ae1@nvidia.com> References: <20260805-tegra264-pcie-v9-0-fa2ed7350ae1@nvidia.com> In-Reply-To: <20260805-tegra264-pcie-v9-0-fa2ed7350ae1@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4514; i=treding@nvidia.com; h=from:subject:message-id; bh=CsDyWrPyNdz/9ucBVAUZst7qSxttLozNfWGdkMV1Nvk=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqcyUx/fOa7PuCvc4YnEtGLgFX8D2EDNtACsG62 7YwhBRcZS+JAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCanMlMQAKCRDdI6zXfz6z oci7D/97rMzKXZpPGsIfO9xGVdFYBFFpZTHF4fJ2l6bgLRc0RBnj5YtxHpBQIsVjfL3FXAf90YA nrMDe1FS/Zee1qi9jA4OCvZ9/WEhA0OA52abu2Acs0FKGauSPn4PI3vKOkhkaOr9DjqTjTSdOFE XJLK2w4L6mitimmM/dIobY6EUelz7ZPWF0/WD1953mDOG9NMdkT8fo4pudFu5hZKgaRrfRjcssw QIBttqZhPBsagLmcvPYJeU9xGN9YvYJvFwLL0rLNtQ5SwffcGtnXp8GUSLeKo6gcDys5ul9hPR1 00lhKsgnl/+B/7AUs6ciQ3LpiQ9oMmOViddKZNCLaedfYYUtr2m4s8MBOd9dww7yZVs05mcmkIN VMu9oBmB5R0nuR1Wbl3iQF+pXIVdHkXk90m6UJY1IU4lW/YbuQcdhkSGO23PzKylimG3DoSqMRR 8MZ2iST0uM22HjuloglDSin3HBM/4rbKv+PNk7NON6VJwQDNP1XSNMZhefGiyA+/3U/mgJao2jv c+EEm9gJITHVZKrFps/XPRnSdW9WlPp4b3noAMdWojqn8Zl+6XknTlVTNaFClZMNdyrugnfynfM RtkgtjSBRiUKiyHNcvIAlp2lPOyLTeVXjze7Y23HINAMwsmzuWZrYfUhathqD3cHbh8d0Lyo64X 1ZVeuabydndalzw== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding The bindings have been updated to use the PCIe root port bindings, so the nodes for the root ports must be added. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 66 ++++++++++++++++++++++++++++= +--- 1 file changed, 60 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index cf9760c681b1..31bd29df8e46 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3562,10 +3562,19 @@ pci@c000000 { ranges =3D <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-= prefetchable memory (128 MiB) */ <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x0 0xff>; =20 nvidia,bpmp =3D <&bpmp 0>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pinmux_main: pinmux@c281000 { @@ -4015,10 +4024,19 @@ pci@8400000 { ranges =3D <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 1>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pci@8420000 { @@ -4047,10 +4065,19 @@ pci@8420000 { ranges =3D <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 2>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pci@8440000 { @@ -4079,10 +4106,19 @@ pci@8440000 { ranges =3D <0x81000000 0x00 0x84000000 0xb8 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xb8 0xc0000000 0xb8 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 3>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pci@8460000 { @@ -4111,10 +4147,19 @@ pci@8460000 { ranges =3D <0x81000000 0x00 0x84000000 0xc0 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xc0 0xc0000000 0xc0 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 4>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pci@8480000 { @@ -4143,10 +4188,19 @@ pci@8480000 { ranges =3D <0x81000000 0x00 0x84000000 0xc8 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x48000000 0x00 0x48000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xc8 0xc0000000 0xc8 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 5>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; }; =20 --=20 2.54.0