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[92.99.174.41]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a16577d59fsm1617670a12.10.2026.08.05.06.45.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 06:45:18 -0700 (PDT) From: Alexey Charkov Date: Wed, 05 Aug 2026 17:45:09 +0400 Subject: [PATCH] clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-rk3576-spi-clk-v1-1-2f040d0d163b@flipper.net> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/yXMQQqDMBBA0avIrB1IlZjYq4gLTUYdLVYyrQiSu xvb5Vv8f4JQYBJ4ZicE2ln4vSY88gzc1K0jIftkKFRRKas0hqXUpkLZGN1rwdJ4stYaM6gaUrQ FGvj4DZv2b/n2M7nPfYEYL9++TxRyAAAA X-Change-ID: 20260805-rk3576-spi-clk-37de88877f09 To: Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Elaine Zhang , Sugar Zhang , Liang Chen , YouMin Chen , Detlev Casanova Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , Alexey Charkov X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3497; i=alchark@flipper.net; h=from:subject:message-id; bh=O1dK7PbUelw/4/J1OKfbGHie7DYKMuZjlf933Pye7bY=; b=owGbwMvMwCW2adGNfoHIK0sZT6slMWQV22XfvvmuqP1RUldnq1nfdpZ5hndVIz79f7PVW/4mp 5fj5Tu1HRNZGMS4GCzFFFnmfltiO9WIb9YuD4+vMHNYmUCGSIs0MAABCwNfbmJeqZGOkZ6ptqGe oZGOsY4RAxenAEz1BSaG/85lXT8ibTi0Dv9zX5KQtMzq3YsFcfwX5U2Dg68fNH+meYPhDxf74pk Xn+Sl1rTNlldp2/O8b9pH/avLzB/EXXBV3n0kjBcA X-Developer-Key: i=alchark@flipper.net; a=openpgp; fpr=9DF6A43D95320E9ABA4848F5B2A2D88F1059D4A5 The TRM defines available source muxes for SPI0..SPI4 as - b00: clk_gpll_div6_src - b01: clk_gpll_div8_src - b10: clk_cpll_div10_src - b11: clk_xin_osc0_func Which doesn't match what the current clock driver implements, making it impossible to derive some SPI clock rates such as 37.125 MHz (which requires clk_gpll_div8_src as the source mux). Add a correct mux definition per TRM and point SPI0..SPI4 clocks at it. Fixes: cc40f5baa91b ("clk: rockchip: Add clock controller for the RK3576") Signed-off-by: Alexey Charkov --- Hitting the bug requires explicitly setting the clock parents for any of the SPI controllers, which no mainline users do currently. This is therefore a forward-looking correctness fix and probably doesn't qualify for backporting to stable. --- drivers/clk/rockchip/clk-rk3576.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-r= k3576.c index 63f229e73a45..2cdd667f4004 100644 --- a/drivers/clk/rockchip/clk-rk3576.c +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -315,6 +315,7 @@ PNAME(mux_100m_24m_lclk0_p) =3D { "clk_cpll_div10", "x= in24m", "lclk_asrc_src_0" } PNAME(mux_100m_24m_lclk1_p) =3D { "clk_cpll_div10", "xin24m", "lclk_asrc_= src_1" }; PNAME(mux_150m_100m_50m_24m_p) =3D { "clk_gpll_div8", "clk_cpll_div10", "= clk_cpll_div20", "xin24m" }; PNAME(mux_200m_100m_50m_24m_p) =3D { "clk_gpll_div6", "clk_cpll_div10", "= clk_cpll_div20", "xin24m" }; +PNAME(mux_200m_150m_100m_24m_p) =3D { "clk_gpll_div6", "clk_gpll_div8", "= clk_cpll_div10", "xin24m" }; PNAME(mux_400m_200m_100m_24m_p) =3D { "clk_gpll_div3", "clk_gpll_div6", "= clk_cpll_div10", "xin24m" }; PNAME(mux_500m_250m_100m_24m_p) =3D { "clk_cpll_div2", "clk_cpll_div4", "= clk_cpll_div10", "xin24m" }; PNAME(mux_600m_400m_300m_24m_p) =3D { "clk_gpll_div2", "clk_gpll_div3", "= clk_gpll_div4", "xin24m" }; @@ -706,19 +707,19 @@ static struct rockchip_clk_branch rk3576_clk_branches= [] __initdata =3D { RK3576_CLKGATE_CON(16), 0, GFLAGS), GATE(PCLK_SPI4, "pclk_spi4", "pclk_bus_root", 0, RK3576_CLKGATE_CON(16), 1, GFLAGS), - COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_100m_24m_p, 0, RK3576_CLKSEL_CON(70), 13, 2, MFLAGS, RK3576_CLKGATE_CON(16), 2, GFLAGS), - COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_100m_24m_p, 0, RK3576_CLKSEL_CON(71), 0, 2, MFLAGS, RK3576_CLKGATE_CON(16), 3, GFLAGS), - COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_24m_p, 0, + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_100m_24m_p, 0, RK3576_CLKSEL_CON(71), 2, 2, MFLAGS, RK3576_CLKGATE_CON(16), 4, GFLAGS), - COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_100m_50m_24m_p, 0, + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_100m_24m_p, 0, RK3576_CLKSEL_CON(71), 4, 2, MFLAGS, RK3576_CLKGATE_CON(16), 5, GFLAGS), - COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_100m_50m_24m_p, 0, + COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_100m_24m_p, 0, RK3576_CLKSEL_CON(71), 6, 2, MFLAGS, RK3576_CLKGATE_CON(16), 6, GFLAGS), GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0, --- base-commit: 0f6da28aab51b16762ed82e8fdeaa5042da45b08 change-id: 20260805-rk3576-spi-clk-37de88877f09 Best regards, -- =20 Alexey Charkov