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Signed-off-by: Imran Shaik --- include/dt-bindings/clock/qcom,qcs8300-gcc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/clock/qcom,qcs8300-gcc.h b/include/dt-bind= ings/clock/qcom,qcs8300-gcc.h index a0083b1d212692825251d6a49e15b9129c1eb1b0..3c674c7baaba91815b13450e647= b41053bd7330d 100644 --- a/include/dt-bindings/clock/qcom,qcs8300-gcc.h +++ b/include/dt-bindings/clock/qcom,qcs8300-gcc.h @@ -191,6 +191,11 @@ #define GCC_VIDEO_AXI0_CLK 181 #define GCC_VIDEO_AXI1_CLK 182 #define GCC_VIDEO_XO_CLK 183 +#define GCC_GPLL5 184 +#define GCC_TSCSS_AHB_CLK 185 +#define GCC_TSCSS_CNTR_CLK_SRC 186 +#define GCC_TSCSS_ETU_CLK 187 +#define GCC_TSCSS_GLOBAL_CNTR_CLK 188 =20 /* GCC power domains */ #define GCC_EMAC0_GDSC 0 @@ -230,5 +235,6 @@ #define GCC_VIDEO_BCR 26 #define GCC_VIDEO_AXI0_CLK_ARES 27 #define GCC_VIDEO_AXI1_CLK_ARES 28 +#define GCC_TSCSS_BCR 29 =20 #endif --=20 2.34.1 From nobody Fri Oct 2 02:36:28 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5171442A79A for ; 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Signed-off-by: Imran Shaik Reviewed-by: Taniya Das --- drivers/clk/qcom/gcc-qcs8300.c | 103 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 103 insertions(+) diff --git a/drivers/clk/qcom/gcc-qcs8300.c b/drivers/clk/qcom/gcc-qcs8300.c index 31fd870b10f7aee14b390fecb9e44b8d8a11a77e..146b3b5dfead31ab508fe3df62a= 44b559026e750 100644 --- a/drivers/clk/qcom/gcc-qcs8300.c +++ b/drivers/clk/qcom/gcc-qcs8300.c @@ -42,6 +42,7 @@ enum { P_GCC_GPLL0_OUT_MAIN, P_GCC_GPLL1_OUT_MAIN, P_GCC_GPLL4_OUT_MAIN, + P_GCC_GPLL5_OUT_MAIN, P_GCC_GPLL7_OUT_MAIN, P_GCC_GPLL9_OUT_MAIN, P_PCIE_0_PIPE_CLK, @@ -128,6 +129,23 @@ static struct clk_alpha_pll gcc_gpll4 =3D { }, }; =20 +static struct clk_alpha_pll gcc_gpll5 =3D { + .offset =3D 0x5000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .enable_reg =3D 0x4b028, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll5", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + static struct clk_alpha_pll gcc_gpll7 =3D { .offset =3D 0x7000, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -364,6 +382,22 @@ static const struct clk_parent_data gcc_parent_data_18= [] =3D { { .index =3D DT_BI_TCXO }, }; =20 +static const struct parent_map gcc_parent_map_19[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL7_OUT_MAIN, 2 }, + { P_GCC_GPLL5_OUT_MAIN, 3 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_19[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll7.clkr.hw }, + { .hw =3D &gcc_gpll5.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src =3D { .reg =3D 0xa9074, .shift =3D 0, @@ -1094,6 +1128,25 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = =3D { }, }; =20 +static const struct freq_tbl ftbl_gcc_tscss_cntr_clk_src[] =3D { + F(15625000, P_GCC_GPLL7_OUT_MAIN, 16, 1, 4), + { } +}; + +static struct clk_rcg2 gcc_tscss_cntr_clk_src =3D { + .cmd_rcgr =3D 0x21008, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_19, + .freq_tbl =3D ftbl_gcc_tscss_cntr_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_tscss_cntr_clk_src", + .parent_data =3D gcc_parent_data_19, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_19), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] =3D { F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), @@ -2899,6 +2952,50 @@ static struct clk_branch gcc_sgmi_clkref_en =3D { }, }; =20 +static struct clk_branch gcc_tscss_ahb_clk =3D { + .halt_reg =3D 0x21024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_tscss_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tscss_etu_clk =3D { + .halt_reg =3D 0x21020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_tscss_etu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tscss_global_cntr_clk =3D { + .halt_reg =3D 0x21004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x21004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_tscss_global_cntr_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_tscss_cntr_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_phy_ahb_clk =3D { .halt_reg =3D 0x83020, .halt_check =3D BRANCH_HALT_VOTED, @@ -3360,6 +3457,7 @@ static struct clk_regmap *gcc_qcs8300_clocks[] =3D { [GCC_GPLL0_OUT_EVEN] =3D &gcc_gpll0_out_even.clkr, [GCC_GPLL1] =3D &gcc_gpll1.clkr, [GCC_GPLL4] =3D &gcc_gpll4.clkr, + [GCC_GPLL5] =3D &gcc_gpll5.clkr, [GCC_GPLL7] =3D &gcc_gpll7.clkr, [GCC_GPLL9] =3D &gcc_gpll9.clkr, [GCC_GPU_GPLL0_CLK_SRC] =3D &gcc_gpu_gpll0_clk_src.clkr, @@ -3464,6 +3562,10 @@ static struct clk_regmap *gcc_qcs8300_clocks[] =3D { [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, [GCC_SGMI_CLKREF_EN] =3D &gcc_sgmi_clkref_en.clkr, + [GCC_TSCSS_AHB_CLK] =3D &gcc_tscss_ahb_clk.clkr, + [GCC_TSCSS_CNTR_CLK_SRC] =3D &gcc_tscss_cntr_clk_src.clkr, + [GCC_TSCSS_ETU_CLK] =3D &gcc_tscss_etu_clk.clkr, + [GCC_TSCSS_GLOBAL_CNTR_CLK] =3D &gcc_tscss_global_cntr_clk.clkr, [GCC_UFS_PHY_AHB_CLK] =3D &gcc_ufs_phy_ahb_clk.clkr, [GCC_UFS_PHY_AXI_CLK] =3D &gcc_ufs_phy_axi_clk.clkr, [GCC_UFS_PHY_AXI_CLK_SRC] =3D &gcc_ufs_phy_axi_clk_src.clkr, @@ -3523,6 +3625,7 @@ static const struct qcom_reset_map gcc_qcs8300_resets= [] =3D { [GCC_PCIE_1_PHY_BCR] =3D { 0xae08c }, [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] =3D { 0xae094 }, [GCC_SDCC1_BCR] =3D { 0x20000 }, + [GCC_TSCSS_BCR] =3D { 0x21000 }, [GCC_UFS_PHY_BCR] =3D { 0x83000 }, [GCC_USB20_PRIM_BCR] =3D { 0x1c000 }, [GCC_USB2_PHY_PRIM_BCR] =3D { 0x5c01c }, --=20 2.34.1